1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 /* 27 * Copyright 2019 Peter Tribble. 28 */ 29 30 #ifndef _SYS_MACHINTREG_H 31 #define _SYS_MACHINTREG_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* 38 * Interrupt Receive Data Registers 39 * ASI_SDB_INTR_R or ASI_INTR_RECEIVE; ASI 0x7F; VA 0x40, 0x50, 0x60 40 */ 41 #define IRDR_0 0x40 42 #define IRDR_1 0x50 43 #define IRDR_2 0x60 44 45 #define UIII_IRDR_0 0x40 46 #define UIII_IRDR_1 0x48 47 #define UIII_IRDR_2 0x50 48 #define UIII_IRDR_3 0x58 49 #define UIII_IRDR_4 0x60 50 #define UIII_IRDR_5 0x68 51 #define UIII_IRDR_6 0x80 52 #define UIII_IRDR_7 0x88 53 54 /* 55 * Interrupt Receive Status Register 56 * ASI_INTR_RECEIVE_STATUS; ASI 0x49; VA 0x0 57 * 58 * |---------------------------------------------------| 59 * | RESERVED (Read as 0) | BUSY | PORTID | 60 * |--------------------------------|------|-----------| 61 * 63 6 5 4 0 62 * 63 */ 64 #define IRSR_BUSY 0x20 /* set when there's a vector received */ 65 #define IRSR_PID_MASK 0x1F /* PORTID bit mask <4:0> */ 66 67 /* 68 * Interrupt Dispatch Data Register 69 * ASI_SDB_INTR_W or ASI_INTR_DISPATCH; ASI 0x77; VA 0x40, 0x50, 0x60 70 */ 71 #define IDDR_0 0x40 72 #define IDDR_1 0x50 73 #define IDDR_2 0x60 74 75 #define UIII_IDDR_0 0x40 76 #define UIII_IDDR_1 0x48 77 #define UIII_IDDR_2 0x50 78 #define UIII_IDDR_3 0x58 79 #define UIII_IDDR_4 0x60 80 #define UIII_IDDR_5 0x68 81 #define UIII_IDDR_6 0x80 82 #define UIII_IDDR_7 0x88 83 84 #if defined(JALAPENO) || defined(SERRANO) 85 /* 86 * Interrupt Dispatch Command Register 87 * ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70 88 * 89 * |------------------------------------------------| 90 * | 0 | PORTID & BUSY/NACK | 0x70 | 91 * |---------|-----------------------|--------------| 92 * 63 19 18 14 13 0 93 */ 94 #define IDCR_OFFSET 0x70 /* IDCR VA<13:0> */ 95 #define IDCR_PID_SHIFT 14 96 #define IDCR_BN_SHIFT 14 /* JBUS only */ 97 #define IDCR_BN_MASK 0x3 /* JBUS only */ 98 #else /* (JALAPENO || SERRANO) */ 99 /* 100 * Interrupt Dispatch Command Register 101 * ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70 102 * 103 * |------------------------------------------------| 104 * | 0 | BUSY/NACK | PORTID | 0x70 | 105 * |---------|-----------|-----------|--------------| 106 * 63 29 28 24 23 14 13 0 107 */ 108 #define IDCR_OFFSET 0x70 /* IDCR VA<13:0> */ 109 #define IDCR_PID_SHIFT 14 110 #define IDCR_BN_SHIFT 24 /* safari only */ 111 #endif /* (JALAPENO || SERRANO) */ 112 113 /* 114 * Interrupt Dispatch Status Register 115 * ASI_INTR_DISPATCH_STATUS; ASI 0x48; VA 0x0 116 * 117 * |---------------------------------------------------| 118 * | RESERVED (Read as 0) | NACK | BUSY | 119 * |-----------------------------------|-------|-------| 120 * 63 2 1 0 | 121 */ 122 #define IDSR_NACK 0x2 /* set if interrupt dispatch failed */ 123 #define IDSR_BUSY 0x1 /* set when there's a dispatch */ 124 125 /* 126 * Safari systems define IDSR as 32 busy/nack pairs 127 */ 128 #if defined(JALAPENO) || defined(SERRANO) 129 #define IDSR_BN_SETS 4 130 #define CPUID_TO_BN_PAIR(x) ((x) & (IDSR_BN_SETS-1)) 131 #else /* (JALAPENO || SERRANO) */ 132 #define IDSR_BN_SETS 32 133 #endif /* (JALAPENO || SERRANO) */ 134 #define IDSR_NACK_BIT(i) ((uint64_t)IDSR_NACK << (2 * (i))) 135 #define IDSR_BUSY_BIT(i) ((uint64_t)IDSR_BUSY << (2 * (i))) 136 #define IDSR_NACK_TO_BUSY(n) ((n) >> 1) 137 #define IDSR_BUSY_TO_NACK(n) ((n) << 1) 138 #define IDSR_NACK_IDX(bit) (((bit) - 1) / 2) 139 #define IDSR_BUSY_IDX(bit) ((bit) / 2) 140 141 /* 142 * Interrupt Number Register 143 * Every interrupt source has a register associated with it 144 * 145 * |---------------------------------------------------| 146 * |INT_EN | PORTID |RESERVED (Read as 0)| INT_NUMBER| 147 * | | | | IGN | INO | 148 * |-------|----------|--------------------|-----|-----| 149 * | 31 30 26 25 11 10 6 5 0 150 */ 151 #define INR_EN_SHIFT 31 152 #define INR_PID_SHIFT 26 153 #define INR_PID_MASK (IRSR_PID_MASK << (INR_PID_SHIFT)) 154 /* 155 * IGN_SIZE can be defined in a platform's makefile. If it is not defined, 156 * use a default of 5. 157 */ 158 #ifndef IGN_SIZE 159 #define IGN_SIZE 5 /* Interrupt Group Number bit size */ 160 #endif 161 #define UPAID_TO_IGN(upaid) (upaid) 162 163 #define IR_CPU_CLEAR 0x4 /* clear pending register for cpu */ 164 #define IR_MASK_OFFSET 0x4 165 #define IR_SET_ITR 0x10 166 #define IR_SOFT_INT(n) (0x000010000 << (n)) 167 #define IR_SOFT_INT4 IR_SOFT_INT(4) /* r/w - software level 4 interrupt */ 168 #define IR_CPU_SOFTINT 0x8 /* set soft interrupt for cpu */ 169 #define IR_CLEAR_OFFSET 0x8 170 171 172 #ifdef __cplusplus 173 } 174 #endif 175 176 #endif /* _SYS_MACHINTREG_H */ 177