1*29949e86Sstevel /* 2*29949e86Sstevel * CDDL HEADER START 3*29949e86Sstevel * 4*29949e86Sstevel * The contents of this file are subject to the terms of the 5*29949e86Sstevel * Common Development and Distribution License (the "License"). 6*29949e86Sstevel * You may not use this file except in compliance with the License. 7*29949e86Sstevel * 8*29949e86Sstevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*29949e86Sstevel * or http://www.opensolaris.org/os/licensing. 10*29949e86Sstevel * See the License for the specific language governing permissions 11*29949e86Sstevel * and limitations under the License. 12*29949e86Sstevel * 13*29949e86Sstevel * When distributing Covered Code, include this CDDL HEADER in each 14*29949e86Sstevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*29949e86Sstevel * If applicable, add the following below this CDDL HEADER, with the 16*29949e86Sstevel * fields enclosed by brackets "[]" replaced with your own identifying 17*29949e86Sstevel * information: Portions Copyright [yyyy] [name of copyright owner] 18*29949e86Sstevel * 19*29949e86Sstevel * CDDL HEADER END 20*29949e86Sstevel */ 21*29949e86Sstevel 22*29949e86Sstevel /* 23*29949e86Sstevel * Copyright 1998 Sun Microsystems, Inc. All rights reserved. 24*29949e86Sstevel * Use is subject to license terms. 25*29949e86Sstevel */ 26*29949e86Sstevel 27*29949e86Sstevel #ifndef _SYS_ENVCTRL_UE250_H 28*29949e86Sstevel #define _SYS_ENVCTRL_UE250_H 29*29949e86Sstevel 30*29949e86Sstevel #pragma ident "%Z%%M% %I% %E% SMI" 31*29949e86Sstevel 32*29949e86Sstevel #ifdef __cplusplus 33*29949e86Sstevel extern "C" { 34*29949e86Sstevel #endif 35*29949e86Sstevel 36*29949e86Sstevel /* 37*29949e86Sstevel * envctrl_ue250.h 38*29949e86Sstevel * 39*29949e86Sstevel * This header file contains environmental control definitions specific 40*29949e86Sstevel * to the UltraEnterprise-250 platform. 41*29949e86Sstevel */ 42*29949e86Sstevel 43*29949e86Sstevel #define ENVCTRL_UE250_OVERTEMP_TIMEOUT_USEC 60 * MICROSEC 44*29949e86Sstevel #define ENVCTRL_UE250_BLINK_TIMEOUT_USEC 500 * (MICROSEC / MILLISEC) 45*29949e86Sstevel 46*29949e86Sstevel /* Keyswitch Definitions */ 47*29949e86Sstevel #define ENVCTRL_UE250_FSP_KEYMASK 0xC0 48*29949e86Sstevel #define ENVCTRL_UE250_FSP_POMASK 0x20 49*29949e86Sstevel #define ENVCTRL_UE250_FSP_KEYLOCKED 0x00 50*29949e86Sstevel #define ENVCTRL_UE250_FSP_KEYOFF 0xC0 51*29949e86Sstevel #define ENVCTRL_UE250_FSP_KEYDIAG 0x80 52*29949e86Sstevel #define ENVCTRL_UE250_FSP_KEYON 0x40 53*29949e86Sstevel 54*29949e86Sstevel /* Front Status Panel Definitions */ 55*29949e86Sstevel #define ENVCTRL_UE250_FSP_DISK_ERR 0x01 56*29949e86Sstevel #define ENVCTRL_UE250_FSP_PS_ERR 0x02 57*29949e86Sstevel #define ENVCTRL_UE250_FSP_TEMP_ERR 0x04 58*29949e86Sstevel #define ENVCTRL_UE250_FSP_GEN_ERR 0x08 59*29949e86Sstevel #define ENVCTRL_UE250_FSP_ACTIVE 0x10 60*29949e86Sstevel #define ENVCTRL_UE250_FSP_POWER 0x20 61*29949e86Sstevel #define ENVCTRL_UE250_FSP_USRMASK \ 62*29949e86Sstevel (ENVCTRL_UE250_FSP_DISK_ERR | ENVCTRL_UE250_FSP_GEN_ERR) 63*29949e86Sstevel 64*29949e86Sstevel #define ENVCTRL_UE250_FSP_OFF 0x4F 65*29949e86Sstevel 66*29949e86Sstevel #define ENVCTRL_UE250_MAX_DISKS 6 67*29949e86Sstevel #define ENVCTRL_UE250_MAXPS 0x02 /* 0 based array */ 68*29949e86Sstevel 69*29949e86Sstevel #define ENVCTRL_UE250_PDB_TEMP_DEV 0x94 70*29949e86Sstevel #define ENVCTRL_UE250_CPU_TEMP_DEV 0x9E 71*29949e86Sstevel #define ENVCTRL_UE250_CPU0_PORT 0 72*29949e86Sstevel #define ENVCTRL_UE250_CPU1_PORT 1 73*29949e86Sstevel #define ENVCTRL_UE250_MB0_PORT 2 74*29949e86Sstevel #define ENVCTRL_UE250_MB1_PORT 3 75*29949e86Sstevel #define ENVCTRL_UE250_PDB_TEMP_PORT 0 76*29949e86Sstevel #define ENVCTRL_UE250_SCSI_TEMP_PORT 3 77*29949e86Sstevel 78*29949e86Sstevel #define ENVCTRL_UE250_CPU0_SENSOR 0 79*29949e86Sstevel #define ENVCTRL_UE250_CPU1_SENSOR 1 80*29949e86Sstevel #define ENVCTRL_UE250_MB0_SENSOR 2 81*29949e86Sstevel #define ENVCTRL_UE250_MB1_SENSOR 3 82*29949e86Sstevel #define ENVCTRL_UE250_PDB_SENSOR 4 83*29949e86Sstevel #define ENVCTRL_UE250_SCSI_SENSOR 5 84*29949e86Sstevel 85*29949e86Sstevel #define ENVCTRL_UE250_MAX_CPU_TEMP 80 86*29949e86Sstevel 87*29949e86Sstevel #define ENVCTRL_UE250_PCF8591_BASE_ADDR 0x90 88*29949e86Sstevel #define ENVCTRL_UE250_PCF8574A_BASE_ADDR 0x70 89*29949e86Sstevel #define ENVCTRL_UE250_PCF8574_BASE_ADDR 0x40 90*29949e86Sstevel 91*29949e86Sstevel #define ENVCTRL_UE250_DFLOP_INIT0 0x77 92*29949e86Sstevel #define ENVCTRL_UE250_DFLOP_INIT1 0x7F 93*29949e86Sstevel #define ENVCTRL_UE250_DEVINTR_INIT0 0xF7 94*29949e86Sstevel #define ENVCTRL_UE250_DEVINTR_INIT1 0xFF 95*29949e86Sstevel #define ENVCTRL_UE250_INTR_LATCH_CLR 0xFE 96*29949e86Sstevel 97*29949e86Sstevel #ifdef __cplusplus 98*29949e86Sstevel } 99*29949e86Sstevel #endif 100*29949e86Sstevel 101*29949e86Sstevel #endif /* _SYS_ENVCTRL_UE250_H */ 102