1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_FHC_H 28 #define _SYS_FHC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/types32.h> 35 #include <sys/dditypes.h> 36 37 /* useful debugging stuff */ 38 #define FHC_ATTACH_DEBUG 0x1 39 #define FHC_INTERRUPT_DEBUG 0x2 40 #define FHC_REGISTERS_DEBUG 0x4 41 #define FHC_CTLOPS_DEBUG 0x8 42 43 #define FHC_BOARDS 0 44 #define FHC_CLOCKS 1 45 46 /* 47 * OBP supplies us with 6 register sets for the FHC. The code for the fhc 48 * driver relies on these register sets being presented by the PROM in the 49 * order specified below. If this changes, the following comments must be 50 * revised and the code in fhc_init() must be changed to reflect these 51 * revisions. 52 * 53 * They are: 54 * 0 FHC internal registers 55 * 1 IGR Interrupt Group Number 56 * 2 FanFail IMR, ISMR 57 * 3 System IMR, ISMR 58 * 4 UART IMR, ISMR 59 * 5 TOD IMR, ISMR 60 */ 61 62 /* 63 * The offsets are defined as offsets from the base of the OBP register 64 * set which the register belongs to. 65 */ 66 67 /* Register set 0 */ 68 #define FHC_OFF_ID 0x0 /* FHC ID register */ 69 #define FHC_OFF_RCTRL 0x10 /* FHC Reset Control and Status */ 70 #define FHC_OFF_CTRL 0x20 /* FHC Control and Status */ 71 #define FHC_OFF_BSR 0x30 /* FHC Board Status Register */ 72 #define FHC_OFF_JTAG_CTRL 0xF0 /* JTAG Control Register */ 73 #define FHC_OFF_JTAG_CMD 0x100 /* JTAG Comamnd Register */ 74 75 /* Register sets 2-5, the ISMR offset is the same */ 76 #define FHC_OFF_ISMR 0x10 /* FHC Interrupt State Machine */ 77 78 /* Bit field defines for FHC Control and Status Register */ 79 #define FHC_CENTERDIS 0x00100000 80 81 /* NOTE: this bit is only used by firmware and must always be cleared by OS */ 82 #define FHC_CSR_SYNC 0x00010000 83 #define FHC_MOD_OFF 0x00008000 84 #define FHC_ACDC_OFF 0x00004000 85 #define FHC_FHC_OFF 0x00002000 86 #define FHC_EPDA_OFF 0x00001000 87 #define FHC_EPDB_OFF 0x00000800 88 #define FHC_PS_OFF 0x00000400 89 #define FHC_NOT_BRD_PRES 0x00000200 90 #define FHC_LED_LEFT 0x00000040 91 #define FHC_LED_MID 0x00000020 92 #define FHC_LED_RIGHT 0x00000010 93 94 /* Bit field defines for FHC Reset Control and Status Register */ 95 #define FHC_POR 0x80000000 96 #define FHC_SOFT_POR 0x40000000 97 #define FHC_SOFT_XIR 0x20000000 98 99 /* Bit field defines for the JTAG control register. */ 100 #define JTAG_MASTER_EN 0x80000000 101 #define JTAG_MASTER_NPRES 0x40000000 102 103 104 /* Macros for decoding UPA speed pins from the Board Status Register */ 105 #define CPU_0_PINS(bsr) (((bsr) >> 10) & 0x7) 106 #define CPU_1_PINS(bsr) (((bsr) >> 7) & 0x7) 107 108 #define CID_REV_MASK 0x0fffffff 109 #define ULTRAI_COMPID 0x0002502f 110 #define ULTRAII_COMPID 0x0003602f 111 112 /* Macro for extracting the "plus" bit from the Board Status Register */ 113 #define ISPLUSBRD(bsr) (((bsr) & 1) == 0) 114 115 /* Macros for physical access */ 116 #define FHC_OFFSET 0xf8000000ull 117 #define FHC_REGOFF 0x800000ull 118 #define FHC_OFF_IGN 0x2000ull 119 #define FHC_OFF_SIM 0x6000ull 120 #define FHC_OFF_SSM 0x6010ull 121 #define FHC_OFF_UIM 0x8000ull 122 #define FHC_OFF_USM 0x8010ull 123 #define FHC_CTRL(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 124 FHC_REGOFF + FHC_OFF_CTRL) 125 #define FHC_JTAG_CTRL(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 126 FHC_REGOFF + FHC_OFF_JTAG_CTRL) 127 #define FHC_IGN(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 128 FHC_REGOFF + FHC_OFF_IGN) 129 #define FHC_SIM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 130 FHC_REGOFF + FHC_OFF_SIM) 131 #define FHC_SSM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 132 FHC_REGOFF + FHC_OFF_SSM) 133 #define FHC_UIM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 134 FHC_REGOFF + FHC_OFF_UIM) 135 #define FHC_USM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \ 136 FHC_REGOFF + FHC_OFF_USM) 137 138 /* 139 * the foolowing defines are used for trans phy-addr to board number 140 */ 141 #define BOARD_PHYADDR_SHIFT 24 142 #define CLOCKBOARD_PHYADDR_BITS 0x1fff8 143 #define IO_BOARD_NUMBER_SHIFT 10 144 #define IO_BOARD_NUMBER_MASK 0xf 145 146 /* 147 * The following defines are used by the fhc driver to determine the 148 * difference between IO and CPU type boards. This will be replaced 149 * later by JTAG scan to determine board type. 150 */ 151 152 /* XXX */ 153 #define FHC_UPADATA64A 0x40000 154 #define FHC_UPADATA64B 0x20000 155 /* XXX */ 156 157 /* Bit field defines for Board Status Register */ 158 #define FHC_DIAG_MODE 0x40 159 160 /* Bit field defines for the FHC Board Status Register when on a disk board */ 161 #define FHC_FANFAIL 0x00000040 162 #define FHC_SCSI_VDD_OK 0x00000001 163 164 /* Size of temperature recording array */ 165 #define MAX_TEMP_HISTORY 16 166 167 /* Maximum number of boards in system */ 168 #define MAX_BOARDS 16 169 170 /* Maximum number of Board Power Supplies. */ 171 #define MAX_PS_COUNT 8 172 173 /* Use predefined strings to name the kstats from this driver. */ 174 #define FHC_KSTAT_NAME "fhc" 175 #define CSR_KSTAT_NAMED "csr" 176 #define BSR_KSTAT_NAMED "bsr" 177 178 /* 179 * The following defines are for the AC chip, but are needed to be global, 180 * so have been put in the fhc header file. 181 */ 182 183 /* 184 * Most Sunfire ASICs have the chip rev encoded into bits 31-28 of the 185 * component ID register. 186 */ 187 #define CHIP_REV(c) ((c) >> 28) 188 189 #ifndef _ASM 190 191 /* Use predefined strings to name the kstats from this driver. */ 192 193 /* Bit field defines for Interrupt Mapping registers */ 194 #define IMR_VALID ((uint_t)1 << INR_EN_SHIFT) /* Mondo valid bit */ 195 196 /* Bit defines for Interrupt State Machine Register */ 197 #define INT_PENDING 3 /* state of the interrupt dispatch */ 198 199 struct intr_regs { 200 volatile uint_t *mapping_reg; 201 volatile uint_t *clear_reg; 202 uint_t mapping_reg_cache; /* cache current value for CPR */ 203 }; 204 205 #define BD_IVINTR_SHFT 0x7 206 207 /* 208 * Convert the Board Number field in the FHC Board Status Register to 209 * a board number. The field in the register is bits 0,3-1 of the board 210 * number. Therefore a macro is necessary to extract the board number. 211 */ 212 #define FHC_BSR_TO_BD(bsr) ((((bsr) >> 16) & 0x1) | \ 213 (((bsr) >> 12) & 0xE)) 214 215 #define FHC_INO(ino) ((ino) & 0x7) 216 #define FHC_CPU2BOARD(cpuid) ((cpuid) >> 1) 217 #define FHC_CPU_IS_A(cpuid) (!((cpuid) & 1)) 218 #define FHC_CPU_IS_B(cpuid) ((cpuid) & 1) 219 #define FHC_BOARD2CPU_A(board) ((board) << 1) 220 #define FHC_BOARD2CPU_B(board) (((board) << 1) + 1) 221 #define FHC_PS2BOARD(ps) ((((ps) & 0x6) << 1) | ((ps) & 0x1)) 222 #define FHC_BOARD2PS(board) ((((board) & 0xc) >> 1) | ((board) & 0x1)) 223 #define FHC_OTHER_CPU_ID(cpuid) ((cpuid) ^ 1) 224 225 /* this base address is assumed to never map to real memory */ 226 #define FHC_BASE_NOMEM (1ull << 40) 227 #define FHC_MAX_ECACHE_SIZE (16 * 1024 * 1024) 228 229 #define FHC_BOARD_0 0x1c000000000ull 230 #define FHC_BOARD_SPAN 0x200000000ull 231 #define FHC_DTAG_OFFSET 0xfa000000ull 232 #define FHC_BOARD_BASE(cpuid) (FHC_BOARD_0 + (cpuid) * FHC_BOARD_SPAN) 233 #define FHC_DTAG_BASE(cpuid) (FHC_BOARD_BASE(cpuid) + FHC_DTAG_OFFSET) 234 #define FHC_DTAG_LOW 0x300000000ull 235 #define FHC_DTAG_HIGH 0x3ull 236 #define FHC_DTAG_SIZE (16 * 1024 * 1024) 237 #define FHC_DTAG_SKIP 64 238 239 /* 240 * Each Sunfire CPU Board has 32Kbytes of SRAM on the FireHose Bus. 241 * 242 * The SRAM is allocated as follows: 243 * 244 * 0x1ff.f020.0000 - 0x1ff.f020.5fff scratch/stacks 245 * 0x1ff.f020.6000 - 0x1ff.f020.67ff reset info (2K bytes) 246 * 0x1ff.f020.6800 - 0x1ff.f020.6fff POST private (2K bytes) 247 * 0x1ff.f020.7000 - 0x1ff.f020.77ff OS private (2K bytes) 248 * 0x1ff.f020.7800 - 0x1ff.f020.7fff OBP private (2K bytes) 249 */ 250 #define FHC_LOCAL_SRAM_BASE 0x1fff0200000ull 251 #define FHC_GLOBAL_SRAM_BASE 0x1c0f8200000ull 252 #define FHC_CPU2GLOBAL_SRAM(mid) \ 253 (FHC_GLOBAL_SRAM_BASE + (mid) * 0x200000000ull) 254 255 #define FHC_SRAM_OS_BASE 0x7000 256 #define FHC_LOCAL_OS_PAGEBASE ((FHC_LOCAL_SRAM_BASE + FHC_SRAM_OS_BASE) & \ 257 MMU_PAGEMASK) 258 #define FHC_SRAM_OS_OFFSET ((FHC_LOCAL_SRAM_BASE + FHC_SRAM_OS_BASE) & \ 259 MMU_PAGEOFFSET) 260 261 #define FHC_SHUTDOWN_WAIT_MSEC 1000 262 263 #define FHC_MAX_INO 4 264 265 #define FHC_SYS_INO 0x0 266 #define FHC_UART_INO 0x1 267 #define FHC_TOD_INO 0x2 268 #define FHC_FANFAIL_INO 0x3 269 270 /* 271 * Defines for the kstats created for passing temperature values and 272 * history out to user level programs. All temperatures passed out 273 * will be in degrees Centigrade, corrected for the board type the 274 * temperature was read from. Since each Board type has a different 275 * response curve for the A/D convertor, the temperatures are all 276 * calibrated inside the kernel. 277 */ 278 279 #define OVERTEMP_KSTAT_NAME "temperature" 280 281 /* 282 * This kstat is used for manually overriding temperatures. 283 */ 284 285 #define TEMP_OVERRIDE_KSTAT_NAME "temperature override" 286 287 /* 288 * Time averaging based method of recording temperature history. 289 * Higher level temperature arrays are composed of temperature averages 290 * of the array one level below. When the lower array completes a 291 * set of data, the data is averaged and placed into the higher 292 * level array. Then the lower level array is overwritten until 293 * it is once again complete, where the process repeats. 294 * 295 * This method gives a user a fine grained view of the last minute, 296 * and larger grained views of the temperature as one goes back in 297 * time. 298 * 299 * The time units for the longer samples are based on the value 300 * of the OVERTEMP_TIMEOUT_SEC and the number of elements in each 301 * of the arrays between level 1 and the higher level. 302 */ 303 304 #define OVERTEMP_TIMEOUT_SEC 2 305 306 /* definition of the clock board index */ 307 #define CLOCK_BOARD_INDEX 16 308 309 #define L1_SZ 30 /* # of OVERTEMP_TIMEOUT_SEC samples */ 310 #define L2_SZ 15 /* size of array for level 2 samples */ 311 #define L3_SZ 12 /* size of array for level 3 samples */ 312 #define L4_SZ 4 /* size of array for level 4 samples */ 313 #define L5_SZ 2 /* size of array for level 5 samples */ 314 315 /* 316 * Macros for determining when to do the temperature averaging of arrays. 317 */ 318 #define L2_INDEX(i) ((i) / L1_SZ) 319 #define L2_REM(i) ((i) % L1_SZ) 320 #define L3_INDEX(i) ((i) / (L1_SZ * L2_SZ)) 321 #define L3_REM(i) ((i) % (L1_SZ * L2_SZ)) 322 #define L4_INDEX(i) ((i) / (L1_SZ * L2_SZ * L3_SZ)) 323 #define L4_REM(i) ((i) % (L1_SZ * L2_SZ * L3_SZ)) 324 #define L5_INDEX(i) ((i) / (L1_SZ * L2_SZ * L3_SZ * L4_SZ)) 325 #define L5_REM(i) ((i) % (L1_SZ * L2_SZ * L3_SZ * L4_SZ)) 326 327 /* 328 * define for an illegal temperature. This temperature will never be seen 329 * in a real system, so it is used as an illegal value in the various 330 * functions processing the temperature data structure. 331 */ 332 #define NA_TEMP 0x7FFF 333 334 /* 335 * State variable for board temperature. Each board has its own 336 * temperature state. State transitions from OK -> bad direction 337 * happen instantaneously, but use a counter in the opposite 338 * direction, so that noise in the A/D counters does not cause 339 * a large number of messages to appear. 340 */ 341 enum temp_state { TEMP_OK = 0, /* normal board temperature */ 342 TEMP_WARN = 1, /* start warning operator */ 343 TEMP_DANGER = 2 }; /* get ready to shutdown */ 344 345 /* 346 * Number of temperature poll counts to wait before printing that the 347 * system has cooled down. 348 */ 349 #define TEMP_STATE_TIMEOUT_SEC 20 350 #define TEMP_STATE_COUNT ((TEMP_STATE_TIMEOUT_SEC) / \ 351 (OVERTEMP_TIMEOUT_SEC)) 352 353 /* 354 * Number of poll counts that a system temperature must be at or above danger 355 * temperature before system is halted and powers down. 356 */ 357 #define SHUTDOWN_TIMEOUT_SEC 20 358 #define SHUTDOWN_COUNT ((SHUTDOWN_TIMEOUT_SEC) / \ 359 (OVERTEMP_TIMEOUT_SEC)) 360 361 /* 362 * State variable for temperature trend. Each state represents the 363 * current temperature trend for a given device. 364 */ 365 enum temp_trend { TREND_UNKNOWN = 0, /* Unknown temperature trend */ 366 TREND_RAPID_FALL = 1, /* Rapidly falling temp. */ 367 TREND_FALL = 2, /* Falling temperature */ 368 TREND_STABLE = 3, /* Stable temperature */ 369 TREND_RISE = 4, /* Rising temperature */ 370 TREND_RAPID_RISE = 5, /* Rapidly rising temperature */ 371 TREND_NOISY = 6 }; /* Unknown trend (noisy) */ 372 373 /* Thresholds for temperature trend */ 374 #define NOISE_THRESH 2 375 #define RAPID_RISE_THRESH 4 376 #define RAPID_FALL_THRESH 4 377 378 /* 379 * Main structure for passing the calibrated and time averaged temperature 380 * values to user processes. This structure is copied out via the kstat 381 * mechanism. 382 */ 383 #define TEMP_KSTAT_VERSION 3 /* version of temp_stats structure */ 384 struct temp_stats { 385 uint_t index; /* index of current temperature */ 386 short l1[L1_SZ]; /* OVERTEMP_TIMEOUT_SEC samples */ 387 short l2[L2_SZ]; /* level 2 samples */ 388 short l3[L3_SZ]; /* level 3 samples */ 389 short l4[L4_SZ]; /* level 4 samples */ 390 short l5[L5_SZ]; /* level 5 samples */ 391 short max; /* maximum temperature recorded */ 392 short min; /* minimum temperature recorded */ 393 enum temp_state state; /* state of board temperature */ 394 int temp_cnt; /* counter for state changes */ 395 int shutdown_cnt; /* counter for overtemp shutdown */ 396 int version; /* version of this structure */ 397 enum temp_trend trend; /* temperature trend for board */ 398 short override; /* override temperature for testing */ 399 }; 400 401 /* The variable fhc_cpu_warning_temp_threshold is initialized to this value. */ 402 #define FHC_CPU_WARNING_TEMP_THRESHOLD 45 403 404 /* 405 * Fault list management. 406 * 407 * The following defines and enum definitions have been created to support 408 * the fault list (struct ft_list). These defines must match with the 409 * fault string table in fhc.c. If any faults are added, they must be 410 * added at the end of this list, and the table must be modified 411 * accordingly. 412 */ 413 enum ft_type { 414 FT_CORE_PS = 0, /* Core power supply */ 415 FT_OVERTEMP, /* Temperature */ 416 FT_AC_PWR, /* AC power Supply */ 417 FT_PPS, /* Peripheral Power Supply */ 418 FT_CLK_33, /* System 3.3 Volt Power */ 419 FT_CLK_50, /* System 5.0 Volt Power */ 420 FT_V5_P, /* Peripheral 5V Power */ 421 FT_V12_P, /* Peripheral 12V Power */ 422 FT_V5_AUX, /* Auxiliary 5V Power */ 423 FT_V5_P_PCH, /* Peripheral 5V Precharge */ 424 FT_V12_P_PCH, /* Peripheral 12V Precharge */ 425 FT_V3_PCH, /* System 3V Precharge */ 426 FT_V5_PCH, /* System 5V Precharge */ 427 FT_PPS_FAN, /* Peripheral Power Supply Fan */ 428 FT_RACK_EXH, /* Rack Exhaust Fan */ 429 FT_DSK_FAN, /* 4 (or 5) Slot Disk Fan */ 430 FT_AC_FAN, /* AC Box Fan */ 431 FT_KEYSW_FAN, /* Key Switch Fan */ 432 FT_INSUFFICIENT_POWER, /* System has insufficient power */ 433 FT_PROM, /* fault inherited from PROM */ 434 FT_HOT_PLUG, /* hot plug unavailable */ 435 FT_TODFAULT /* tod error detection */ 436 }; 437 438 enum ft_class { 439 FT_BOARD, 440 FT_SYSTEM 441 }; 442 443 /* 444 * This extern allows other drivers to use the ft_str_table if they 445 * have fhc specified as a depends_on driver. 446 */ 447 extern char *ft_str_table[]; 448 449 /* Maximum length of string table entries */ 450 #define MAX_FT_DESC 64 451 452 #define FT_LIST_KSTAT_NAME "fault_list" 453 454 /* 455 * The fault list structure is a structure for holding information on 456 * kernel detected faults. The fault list structures are linked into 457 * a list and the list is protected by the ftlist_mutex. There are 458 * also several routines for manipulating the fault list. 459 */ 460 struct ft_list { 461 int32_t unit; /* unit number of faulting device */ 462 enum ft_type type; /* type of faulting device */ 463 int32_t pad; /* padding to replace old next pointer */ 464 enum ft_class fclass; /* System or board class fault */ 465 time32_t create_time; /* Time stamp at fault detection */ 466 char msg[MAX_FT_DESC]; /* fault string */ 467 }; 468 469 /* 470 * Allow binary compatibility between ILP32 and LP64 by 471 * eliminating the next pointer and making ft_list a fixed size. 472 * The structure name "ft_list" remains unchanged for 473 * source compatibility of kstat applications. 474 */ 475 struct ft_link_list { 476 struct ft_list f; 477 struct ft_link_list *next; 478 }; 479 480 /* 481 * Board list management. 482 * 483 * Enumerated types for defining type of system and clock 484 * boards. It is used by both the kernel and user programs. 485 */ 486 enum board_type { 487 EMPTY_BOARD = -1, 488 UNINIT_BOARD = 0, /* Uninitialized board type */ 489 UNKNOWN_BOARD, /* Unknown board type */ 490 CPU_BOARD, /* System board CPU(s) */ 491 MEM_BOARD, /* System board no CPUs */ 492 IO_2SBUS_BOARD, /* 2 SBus & SOC IO Board */ 493 IO_SBUS_FFB_BOARD, /* SBus & FFB SOC IO Board */ 494 IO_PCI_BOARD, /* PCI IO Board */ 495 DISK_BOARD, /* Disk Drive Board */ 496 CLOCK_BOARD, /* System Clock board */ 497 IO_2SBUS_SOCPLUS_BOARD, /* 2 SBus & SOC+ IO board */ 498 IO_SBUS_FFB_SOCPLUS_BOARD /* SBus&FFB&SOC+ board */ 499 }; 500 501 /* 502 * Defined strings for comparing with OBP board-type property. If OBP ever 503 * changes the board-type properties, these string defines must be changed 504 * as well. 505 */ 506 #define CPU_BD_NAME "cpu" 507 #define MEM_BD_NAME "mem" 508 #define IO_2SBUS_BD_NAME "dual-sbus" 509 #define IO_SBUS_FFB_BD_NAME "upa-sbus" 510 #define IO_PCI_BD_NAME "dual-pci" 511 #define DISK_BD_NAME "disk" 512 #define IO_2SBUS_SOCPLUS_BD_NAME "dual-sbus-soc+" 513 #define IO_SBUS_FFB_SOCPLUS_BD_NAME "upa-sbus-soc+" 514 515 /* 516 * The following structures and union are needed because the bd_info 517 * structure describes all types of system boards. 518 * XXX - We cannot determine Spitfire rev from JTAG scan, so it is 519 * left blank for now. Future implementations might fill in this info. 520 */ 521 struct cpu_info { 522 int cpu_rev; /* CPU revision */ 523 int cpu_speed; /* rated speed of CPU in MHz */ 524 int cpu_compid; /* CPU component ID */ 525 int sdb0_compid; /* SDB component ID */ 526 int sdb1_compid; /* SDB component ID */ 527 int ec_compid; /* Ecache RAM ID, needed for cache size */ 528 int cache_size; /* Cache size in bytes */ 529 int cpu_sram_mode; /* module's sram mode */ 530 int cpu_detected; /* Something on the CPU JTAG ring. */ 531 }; 532 533 struct io1_info { 534 int sio0_compid; /* Sysio component ID */ 535 int sio1_compid; /* Sysio component ID */ 536 int hme_compid; /* several revs in existence */ 537 int soc_compid; /* SOC */ 538 }; 539 540 struct io1plus_info { 541 int sio0_compid; /* Sysio component ID */ 542 int sio1_compid; /* Sysio component ID */ 543 int hme_compid; /* several revs in existence */ 544 int socplus_compid; /* SOC+ */ 545 }; 546 547 /* Defines for the FFB size field */ 548 #define FFB_FAILED -1 549 #define FFB_NOT_FOUND 0 550 #define FFB_SINGLE 1 551 #define FFB_DOUBLE 2 552 553 struct io2_info { 554 int fbc_compid; /* FBC component ID */ 555 int ffb_size; /* not present, single or dbl buffered */ 556 int sio1_compid; /* Sysio component ID */ 557 int hme_compid; /* several revs in existence */ 558 int soc_compid; /* SOC component ID */ 559 }; 560 561 struct io2plus_info { 562 int fbc_compid; /* FBC component ID */ 563 int ffb_size; /* not present, single or dbl buffered */ 564 int sio1_compid; /* Sysio component ID */ 565 int hme_compid; /* several revs in existence */ 566 int socplus_compid; /* or SOC+ component ID */ 567 }; 568 569 struct io3_info { 570 int psyo0_compid; /* Psycho+ component ID */ 571 int psyo1_compid; /* Psycho+ component ID */ 572 int cheo_compid; /* Cheerio component ID */ 573 }; 574 575 struct dsk_info { 576 int disk_pres[2]; 577 int disk_id[2]; 578 }; 579 580 union bd_un { 581 struct cpu_info cpu[2]; 582 struct io1_info io1; 583 struct io2_info io2; 584 struct io3_info io3; 585 struct dsk_info dsk; 586 struct io1plus_info io1plus; 587 struct io2plus_info io2plus; 588 }; 589 590 /* 591 * board_state and bd_info are maintained for backward 592 * compatibility with prtdiag and others user programs that may rely 593 * on them. 594 */ 595 enum board_state { 596 UNKNOWN_STATE = 0, /* Unknown board */ 597 ACTIVE_STATE, /* active and working */ 598 HOTPLUG_STATE, /* Hot plugged board */ 599 LOWPOWER_STATE, /* Powered down board */ 600 DISABLED_STATE, /* Board disabled by PROM */ 601 FAILED_STATE /* Board failed by POST */ 602 }; 603 604 struct bd_info { 605 enum board_type type; /* Type of board */ 606 enum board_state state; /* current state of this board */ 607 int board; /* board number */ 608 int fhc_compid; /* fhc component id */ 609 int ac_compid; /* ac component id */ 610 char prom_rev[64]; /* best guess as to what is needed */ 611 union bd_un bd; 612 }; 613 614 /* 615 * Config admin interface. 616 * 617 * Receptacle states. 618 */ 619 typedef enum { 620 SYSC_CFGA_RSTATE_EMPTY = 0, /* Empty state */ 621 SYSC_CFGA_RSTATE_DISCONNECTED, /* DISCONNECTED state */ 622 SYSC_CFGA_RSTATE_CONNECTED /* CONNECTED state */ 623 } sysc_cfga_rstate_t; 624 625 /* 626 * Occupant states. 627 */ 628 typedef enum { 629 SYSC_CFGA_OSTATE_UNCONFIGURED = 0, /* UNCONFIGURED state */ 630 SYSC_CFGA_OSTATE_CONFIGURED /* CONFIGURED state */ 631 } sysc_cfga_ostate_t; 632 633 /* 634 * Receptacle/Occupant condition. 635 */ 636 typedef enum { 637 SYSC_CFGA_COND_UNKNOWN = 0, /* Unknown condition */ 638 SYSC_CFGA_COND_OK, /* Condition OK */ 639 SYSC_CFGA_COND_FAILING, /* Failing */ 640 SYSC_CFGA_COND_FAILED, /* Failed */ 641 SYSC_CFGA_COND_UNUSABLE /* Unusable */ 642 } sysc_cfga_cond_t; 643 644 /* 645 * Error definitions for CFGADM platform library 646 */ 647 typedef enum { 648 SYSC_ERR_DEFAULT = 0, /* generic errors */ 649 SYSC_ERR_INTRANS, /* hardware in transition */ 650 SYSC_ERR_UTHREAD, /* can't stop user thread */ 651 SYSC_ERR_KTHREAD, /* can't stop kernel thread */ 652 SYSC_ERR_SUSPEND, /* can't suspend a device */ 653 SYSC_ERR_RESUME, /* can't resume a device */ 654 SYSC_ERR_POWER, /* not enough power for slot */ 655 SYSC_ERR_COOLING, /* not enough cooling for slot */ 656 SYSC_ERR_PRECHARGE, /* not enough precharge for slot */ 657 SYSC_ERR_HOTPLUG, /* Hot Plug Unavailable */ 658 SYSC_ERR_HW_COMPAT, /* incompatible hardware found during dr */ 659 SYSC_ERR_NON_DR_PROM, /* prom not support Dynamic Reconfiguration */ 660 SYSC_ERR_CORE_RESOURCE, /* core resource cannot be removed */ 661 SYSC_ERR_PROM, /* error encountered in OBP/POST */ 662 SYSC_ERR_DR_INIT, /* error encountered in sysc_dr_init op */ 663 SYSC_ERR_NDI_ATTACH, /* error encountered in NDI attach operations */ 664 SYSC_ERR_NDI_DETACH, /* error encountered in NDI detach operations */ 665 SYSC_ERR_RSTATE, /* wrong receptacle state */ 666 SYSC_ERR_OSTATE, /* wrong occupant state */ 667 SYSC_ERR_COND /* invalid condition */ 668 } sysc_err_t; 669 670 /* 671 * Config admin structure. 672 */ 673 typedef struct sysc_cfga_stat { 674 /* generic representation of the attachment point below */ 675 sysc_cfga_rstate_t rstate; /* current receptacle state */ 676 sysc_cfga_ostate_t ostate; /* current occupant state */ 677 sysc_cfga_cond_t condition; /* current board condition */ 678 time32_t last_change; /* last state/condition change */ 679 uint_t in_transition:1; /* board is in_transition */ 680 681 /* platform specific below */ 682 enum board_type type; /* Type of board */ 683 int board; /* board number */ 684 int fhc_compid; /* fhc component id */ 685 int ac_compid; /* ac component id */ 686 char prom_rev[64]; /* best guess as to what is needed */ 687 union bd_un bd; 688 uint_t no_detach:1; /* board is non_detachable */ 689 uint_t plus_board:1; /* board is 98 MHz capable */ 690 } sysc_cfga_stat_t; 691 692 /* 693 * Config admin command structure for SYSC_CFGA ioctls. 694 */ 695 typedef struct sysc_cfga_cmd { 696 uint_t force:1; /* force this state transition */ 697 uint_t test:1; /* Need to test hardware */ 698 int arg; /* generic data for test */ 699 sysc_err_t errtype; /* error code returned */ 700 char *outputstr; /* output returned from ioctl */ 701 } sysc_cfga_cmd_t; 702 703 typedef struct sysc_cfga_cmd32 { 704 uint_t force:1; /* force this state transition */ 705 uint_t test:1; /* Need to test hardware */ 706 int arg; /* generic data for test */ 707 sysc_err_t errtype; /* error code returned */ 708 caddr32_t outputstr; /* output returned from ioctl */ 709 } sysc_cfga_cmd32_t; 710 711 typedef struct sysc_cfga_pkt { 712 sysc_cfga_cmd_t cmd_cfga; 713 char *errbuf; /* internal error buffer */ 714 } sysc_cfga_pkt_t; 715 716 /* 717 * Sysctrl DR sequencer interface. 718 */ 719 typedef struct sysc_dr_handle { 720 dev_info_t **dip_list; /* list of top dips for board */ 721 int dip_list_len; /* length devinfo list */ 722 int flags; /* dr specific flags */ 723 int error; /* dr operation error */ 724 char *errstr; /* dr config/unfig error message */ 725 } sysc_dr_handle_t; 726 727 #define SYSC_DR_MAX_NODE 32 728 #define SYSC_DR_FHC 0x1 /* connect phase init (fhc) */ 729 #define SYSC_DR_DEVS 0x2 /* config phase init (devices) */ 730 #define SYSC_DR_FORCE 0x4 /* force detach */ 731 #define SYSC_DR_REMOVE 0x8 /* remove dev_info */ 732 733 #define SYSC_DR_HANDLE_FHC 0x0 734 #define SYSC_DR_HANDLE_DEVS 0x1 735 736 /* 737 * Sysctrl event interface. 738 */ 739 typedef enum sysc_evt { 740 SYSC_EVT_BD_EMPTY = 0, 741 SYSC_EVT_BD_PRESENT, 742 SYSC_EVT_BD_DISABLED, 743 SYSC_EVT_BD_FAILED, 744 SYSC_EVT_BD_OVERTEMP, 745 SYSC_EVT_BD_TEMP_OK, 746 SYSC_EVT_BD_PS_CHANGE, 747 SYSC_EVT_BD_INS_FAILED, 748 SYSC_EVT_BD_INSERTED, 749 SYSC_EVT_BD_REMOVED, 750 SYSC_EVT_BD_HP_DISABLED, 751 SYSC_EVT_BD_CORE_RESOURCE_DISCONNECT 752 } sysc_evt_t; 753 754 /* 755 * sysctrl audit message events 756 */ 757 typedef enum sysc_audit_evt { 758 SYSC_AUDIT_RSTATE_EMPTY = 0, 759 SYSC_AUDIT_RSTATE_CONNECT, 760 SYSC_AUDIT_RSTATE_DISCONNECT, 761 SYSC_AUDIT_RSTATE_SUCCEEDED, 762 SYSC_AUDIT_RSTATE_EMPTY_FAILED, 763 SYSC_AUDIT_RSTATE_CONNECT_FAILED, 764 SYSC_AUDIT_RSTATE_DISCONNECT_FAILED, 765 SYSC_AUDIT_OSTATE_CONFIGURE, 766 SYSC_AUDIT_OSTATE_UNCONFIGURE, 767 SYSC_AUDIT_OSTATE_SUCCEEDED, 768 SYSC_AUDIT_OSTATE_CONFIGURE_FAILED, 769 SYSC_AUDIT_OSTATE_UNCONFIGURE_FAILED 770 } sysc_audit_evt_t; 771 772 typedef struct { 773 void (*update)(void *, sysc_cfga_stat_t *, sysc_evt_t); 774 void *soft; 775 } sysc_evt_handle_t; 776 777 void fhc_bd_sc_register(void f(void *, sysc_cfga_stat_t *, sysc_evt_t), void *); 778 779 /* 780 * The board list structure is the central storage for the kernel's 781 * knowledge of normally booted and hotplugged boards. 782 */ 783 typedef struct bd_list { 784 struct fhc_soft_state *softsp; /* handle for DDI soft state */ 785 sysc_cfga_stat_t sc; /* board info */ 786 sysc_dr_handle_t sh[2]; /* sysctrl dr interface */ 787 void *dev_softsp; /* opaque pointer to device state */ 788 void *ac_softsp; /* opaque pointer to our AC */ 789 struct kstat *ksp; /* pointer used in kstat destroy */ 790 int fault; /* failure on this board? */ 791 int flags; /* board state flags */ 792 } fhc_bd_t; 793 794 /* 795 * Fhc_bd.c holds 2 resizable arrays of boards. First for clock 796 * boards under central and second for normally booted and 797 * hotplugged boards. 798 */ 799 typedef struct resizable_bd_list { 800 fhc_bd_t **boards; 801 int size; 802 int last; 803 int sorted; 804 } fhc_bd_resizable_t; 805 806 #define BDF_VALID 0x1 /* board entry valid */ 807 #define BDF_DETACH 0x2 /* board detachable */ 808 #define BDF_DISABLED 0x4 /* board disabled */ 809 810 #define SYSC_OUTPUT_LEN MAXPATHLEN /* output str len */ 811 812 /* 813 * Board list management interface. 814 */ 815 int fhc_max_boards(void); 816 void fhc_bdlist_init(void); 817 void fhc_bdlist_fini(void); 818 void fhc_bdlist_prime(int, int, int); 819 fhc_bd_t *fhc_bdlist_lock(int); 820 void fhc_bdlist_unlock(void); 821 822 void fhc_bd_init(struct fhc_soft_state *, int, enum board_type); 823 fhc_bd_t *fhc_bd(int); 824 fhc_bd_t *fhc_bd_clock(void); 825 fhc_bd_t *fhc_bd_first(void); 826 fhc_bd_t *fhc_bd_next(fhc_bd_t *); 827 enum board_type fhc_bd_type(int); 828 char *fhc_bd_typestr(enum board_type); 829 int fhc_bd_valid(int); 830 int fhc_bd_detachable(int); 831 832 int fhc_bd_insert_scan(void); 833 int fhc_bd_remove_scan(void); 834 int fhc_bd_test(int, sysc_cfga_pkt_t *); 835 int fhc_bd_test_set_cond(int, sysc_cfga_pkt_t *); 836 void fhc_bd_update(int, sysc_evt_t); 837 void fhc_bd_env_set(int, void *); 838 839 int fhc_bdlist_locked(void); 840 int fhc_bd_busy(int); 841 int fhc_bd_is_jtag_master(int); 842 int fhc_bd_is_plus(int); 843 844 #if defined(_KERNEL) 845 846 /* 847 * In order to indicate that we are in an environmental chamber, or 848 * oven, the test people will set the 'mfg-mode' property in the 849 * options node to 'chamber'. Therefore we have the following define. 850 */ 851 #define CHAMBER_VALUE "chamber" 852 853 /* 854 * zs design for fhc has two zs' interrupting on same interrupt mondo 855 * This requires us to poll for zs and zs alone. The poll list has been 856 * defined as a fixed size for simplicity. 857 */ 858 #define MAX_ZS_CNT 2 859 860 /* FHC Interrupt routine wrapper structure */ 861 struct fhc_wrapper_arg { 862 struct fhc_soft_state *softsp; 863 volatile uint_t *clear_reg; 864 volatile uint_t *mapping_reg; 865 dev_info_t *child; 866 uint32_t inum; 867 uint_t (*funcp)(caddr_t, caddr_t); 868 caddr_t arg1; 869 caddr_t arg2; 870 }; 871 872 /* 873 * The JTAG master command structure. It contains the address of the 874 * the JTAG controller on this system board. The controller can only 875 * be used if this FHC holds the JTAG master signal. This is checked 876 * by reading the JTAG control register on this FHC. 877 */ 878 struct jt_mstr { 879 volatile uint_t *jtag_cmd; 880 int is_master; 881 kmutex_t lock; 882 }; 883 884 /* Functions exported to manage the fault list */ 885 void reg_fault(int, enum ft_type, enum ft_class); 886 void clear_fault(int, enum ft_type, enum ft_class); 887 int process_fault_list(void); 888 void create_ft_kstats(int); 889 890 /* memloc's are protected under the bdlist lock */ 891 struct fhc_memloc { 892 struct fhc_memloc *next; 893 int board; /* reference our board element */ 894 uint_t pa; /* base PA of this segment (in MB) */ 895 uint_t size; /* size of this segment (in MB) */ 896 }; 897 898 /* Functions used to manage memory 'segments' */ 899 #define FHC_MEMLOC_SHIFT 20 900 #define FHC_MEMLOC_MAX (0x10000000000ull >> FHC_MEMLOC_SHIFT) 901 void fhc_add_memloc(int board, uint64_t pa, uint_t size); 902 void fhc_del_memloc(int board); 903 uint64_t fhc_find_memloc_gap(uint_t size); 904 void fhc_program_memory(int board, uint64_t base); 905 906 /* Structures used in the driver to manage the hardware */ 907 struct fhc_soft_state { 908 dev_info_t *dip; /* dev info of myself */ 909 struct bd_list *list; /* pointer to board list entry */ 910 int is_central; /* A central space instance of FHC */ 911 volatile uint_t *id; /* FHC ID register */ 912 volatile uint_t *rctrl; /* FHC Reset Control and Status */ 913 volatile uint_t *bsr; /* FHC Board Status register */ 914 volatile uint_t *jtag_ctrl; /* JTAG Control register */ 915 volatile uint_t *igr; /* Interrupt Group Number */ 916 struct intr_regs intr_regs[FHC_MAX_INO]; 917 struct fhc_wrapper_arg poll_list[MAX_ZS_CNT]; 918 struct fhc_wrapper_arg *intr_list[FHC_MAX_INO]; 919 kmutex_t poll_list_lock; 920 uchar_t spurious_zs_cntr; /* Spurious counter for zs devices */ 921 kmutex_t pokefault_mutex; 922 int pokefault; 923 924 /* this lock protects the following data */ 925 /* ! non interrupt use only ! */ 926 kmutex_t ctrl_lock; /* lock for access to FHC CSR */ 927 volatile uint_t *ctrl; /* FHC Control and Status */ 928 929 /* The JTAG master structure has internal locking */ 930 struct jt_mstr jt_master; 931 932 /* the pointer to the kstat is stored for deletion upon detach */ 933 kstat_t *fhc_ksp; 934 }; 935 936 /* 937 * Function shared with child drivers which require fhc 938 * support. They gain access to this function through the use of the 939 * _depends_on variable. 940 */ 941 enum board_type get_board_type(int board); 942 void update_temp(dev_info_t *pdip, struct temp_stats *envstat, uchar_t value); 943 enum temp_trend temp_trend(struct temp_stats *); 944 void fhc_reboot(void); 945 int overtemp_kstat_update(kstat_t *ksp, int rw); 946 int temp_override_kstat_update(kstat_t *ksp, int rw); 947 void init_temp_arrays(struct temp_stats *envstat); 948 void update_board_leds(fhc_bd_t *, uint_t, uint_t); 949 struct jt_mstr *jtag_master_lock(void); 950 void jtag_master_unlock(struct jt_mstr *); 951 extern int fhc_board_poweroffcpus(int board, char *errbuf, int cpu_flags); 952 953 954 /* FHC interrupt specification */ 955 struct fhcintrspec { 956 uint_t mondo; 957 uint_t pil; 958 dev_info_t *child; 959 struct fhc_wrapper_arg *handler_arg; 960 }; 961 962 /* kstat structure used by fhc to pass data to user programs. */ 963 struct fhc_kstat { 964 struct kstat_named csr; /* FHC Control and Status Register */ 965 struct kstat_named bsr; /* FHC Board Status Register */ 966 }; 967 968 #endif /* _KERNEL */ 969 970 #endif /* _ASM */ 971 972 #ifdef __cplusplus 973 } 974 #endif 975 976 #endif /* _SYS_FHC_H */ 977