1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 1999 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/types.h> 28 #include <sys/param.h> 29 #include <sys/ddi.h> 30 #include <sys/sunddi.h> 31 #include <sys/ddi_impldefs.h> 32 #include <sys/obpdefs.h> 33 #include <sys/cmn_err.h> 34 #include <sys/errno.h> 35 #include <sys/debug.h> 36 #include <sys/fhc.h> 37 #include <sys/jtag.h> 38 #include <sys/ac.h> 39 #include <sys/machsystm.h> 40 #include <sys/cpu.h> 41 #include <sys/cpuvar.h> 42 43 /* 44 * Defines for data structures used only in this module. They will 45 * not be exported to external modules. 46 */ 47 48 /* 49 * Define the hardware structure of JTAG 50 */ 51 52 #define JTAG_CSR_BASE ((jtag_csr *)0xF0300000) 53 54 55 #define JTAG_CR 0x08000f0 56 #define JTAG_CMD 0x0800100 57 58 /* JTAG status flags */ 59 #define JTAG_BUSY_BIT 0x100 60 61 /* JTAG commands */ 62 #define JTAG_SEL_RING 0x6000 63 #define JTAG_SEL_DR 0x5050 64 #define JTAG_SEL_IR 0x5068 65 #define JTAG_SHIFT 0x00A0 66 #define JTAG_RUNIDLE 0x50C0 67 #define JTAG_IR_TO_DR 0x50E8 68 #define JTAG_DR_TO_IR 0x50F4 69 #define JTAG_TAP_RESET 0x50FF 70 71 72 /* 73 * Definitions of data types. 74 * 75 */ 76 77 /* 78 * Most routines in this interface return a negative value when 79 * an error occurs. In the normal case, the routines return a non-negative 80 * value, which may be of interest to the caller. The following enumeration 81 * provides the meaning of each error return code. 82 */ 83 84 /* 85 * When calling verify_jtag_chip, you must pass PRINT_ERR if you 86 * want the cmn_err call to occur. This is because sometimes 87 * when we verify rings, (checking for NPB's) we do not want to 88 * print error messages. 89 */ 90 #define PRINT_JTAG_ERR 5 91 92 /* 93 * You must pass in the proper chip masks when calling 94 * config board() 95 */ 96 #define AC_INIT 1 97 #define DCU1500_INIT 2 98 #define DCU1600_INIT 2 99 #define DCU1700_INIT 2 100 #define DCU1800_INIT 2 101 #define DCU1900_INIT 2 102 #define DCU2000_INIT 2 103 #define DCU2100_INIT 2 104 #define DCU2200_INIT 2 105 #define FHC_INIT 4 106 107 #define SYSIO_INIT 8 108 109 /* scan ring numbers */ 110 #define RING0 0 111 #define RING1 1 112 #define RING2 2 113 114 /* 115 * Scan ring 0 lengths. Boards are typed by their scan ring length. This 116 * is inherently flawed if a new board type has the same number of 117 * components as one of the original boards. 118 * 119 * The inherently flawed scenario now exists with the introduction 120 * of the soc+ versions of the 2-SBus and UPA/SBus boards. Argh... 121 */ 122 #define CPU_TYPE_LEN 12 /* CPU board ring length */ 123 #define IO_TYPE1_LEN 15 /* 2 sysio 1 HM */ 124 #define IO_TYPE2_LEN 14 /* 1 sysio 1 ffb */ 125 #define PCI_TYPE_LEN 16 /* PCI board ring length */ 126 #define PCI_TYPEA_LEN 110 /* PCI ISP off ring */ 127 #define PCI_TYPEB_LEN 104 /* PCI ISP in ring */ 128 #define DSK_TYPE_LEN 2 /* Disk board ring length */ 129 #define IO_TYPE4_LEN 126 /* 2 sysio soc+ */ 130 #define IO_TYPE5_LEN 110 /* 1 sysio 1 ffb soc+ */ 131 132 #define CPU_0_5_LEN 8 /* 0.5 Meg Module ring length */ 133 #define CPU_1_0_LEN 12 /* 1 Meg and 2 Meg ring length */ 134 #define FFB_SNG_LEN 6 /* Single bufferef FFB */ 135 #define FFB_DBL_LEN 18 /* Double buffered FFB */ 136 137 /* 138 * Component IDs of various SRAM chips. The only way to distinguish between 139 * 1M, 2M, and 4M Ecache is via the component IDs of the SRAMs. 140 */ 141 #define SRAM_256K 0x00000000 142 #define SRAM_128K 0x000090E3 143 #define SRAM_64K_1 0x000000E3 144 #define SRAM_64K_2 0x01901149 145 146 typedef enum { 147 JTAG_OK = 0, /* no error */ 148 JTAG_FAIL = -1, /* generic JTAG failure */ 149 TAP_TIMEOUT = -1, /* JTAG TAP state machine not responding */ 150 BAD_ARGS = -2, /* incorrect arguments passed by caller */ 151 BAD_CID = -3, /* JTAG component ID does not match */ 152 RING_BROKEN = -4, /* JTAG ring continuity test failed */ 153 INIT_MISMATCH = -5, /* State after initialization not expected */ 154 LENGTH_MISMATCH = -6 /* Ring length does not match expected */ 155 } jtag_error; 156 157 typedef u_short jtag_instruction; 158 typedef u_char jtag_ring; /* format is bbbb rrrr in binary */ 159 160 /* Internal macros */ 161 static int tap_issue_cmd(volatile u_int *, u_int); 162 163 /* TAP register access macros */ 164 165 /* NOTE the only status is the busy bit (8) */ 166 167 /* read the jtag data bits */ 168 #define jtag_data(reg, nbits) (*(reg) >> (32 - (nbits))) 169 170 #define JTAG_TIMEOUT 0x10000 171 172 #define TAP_DECLARE int timeout; 173 174 #define TAP_WAIT(reg) timeout = JTAG_TIMEOUT; \ 175 while ((*(reg) & JTAG_BUSY_BIT) != 0) \ 176 if ((--timeout) < 0) \ 177 return (TAP_TIMEOUT) 178 179 #define TAP_SHIFT(reg, data, nbits) \ 180 *(reg) = ((data<<16) | ((nbits-1)<<12) | JTAG_SHIFT); \ 181 TAP_WAIT(reg) 182 183 /* Error-checking macros to simplify the coding */ 184 185 #define TAP_ISSUE_CMD(reg, cmd, status) \ 186 status = tap_issue_cmd(reg, cmd); \ 187 if (status < 0) \ 188 return (status) 189 190 #define TAP_SHIFT_CONSTANT(reg, val, nbits, status) \ 191 status = tap_shift_constant(reg, val, nbits); \ 192 if (status < 0) \ 193 return (status) 194 195 #define TAP_SHIFT_SINGLE(reg, val, nbits, status) \ 196 status = tap_shift_single(reg, val, nbits); \ 197 if (status < 0) \ 198 return (status) 199 200 #define TAP_SHIFT_MULTIPLE(reg, in, nbits, out, status) \ 201 status = tap_shift_multiple(reg, in, nbits, out); \ 202 if (status < 0) \ 203 return (status) 204 205 /* 206 * A jtag_log_comp describes a component as seen by JTAG. 207 * 208 * Since there are multiple versions & revision for a single 209 * component, this can be a bit complicated... 210 * 211 * The implementation assumes that all components which can be used 212 * interchangeably have the exact same programming model regarding 213 * JTAG programming. Then, interchangeable components differ only by 214 * their component IDs. The field id points to a NULL-terminated list 215 * of component IDs. Allowable component IDs may differ only in the rev 216 * number, which must be higher than or equal to the one in the list. 217 * 218 * The init_pdesc field points to a byte string which describes how to 219 * initialize the component. The structure of this byte string is not 220 * exported (see the implementation of jtag_init_chip). 221 * 222 * The fmt_desc field points to a byte string which describes how to 223 * convert the scan-out format to the more usual DCSR format. The 224 * structure of this string is not exported (see the implementation 225 * of jtag_scanout_chip). 226 */ 227 228 typedef struct { 229 u_int *id; /* Pointer to component IDs, 0 if no CID */ 230 u_char ir_len; /* number of bits in instruction register */ 231 u_char dr_len; /* number of bits in DR for init/dump */ 232 jtag_instruction id_code; /* instruction to read component ID */ 233 jtag_instruction init_code; /* instruction to write parameters */ 234 jtag_instruction dump_code; /* instruction to read parameters */ 235 u_char *init_pdesc; /* initialization patch descriptors */ 236 u_char *fmt_desc; /* reformat descriptor */ 237 } jtag_log_comp; 238 239 240 /* A jtag_phys_comp describes a component position inside a ring */ 241 242 typedef struct { 243 jtag_log_comp *chip; /* pointer to chip descriptor */ 244 short ir_after; /* number of IR bits after chip in ring */ 245 short ir_before; /* number of IR bits before chip in ring */ 246 short by_after; /* number of bypass bits after chip in ring */ 247 short by_before; /* number of bypass bits before chip in ring */ 248 } jtag_phys_comp; 249 250 251 /* Board ring description */ 252 253 typedef struct { 254 int size; 255 jtag_phys_comp *components; 256 } jtag_ring_desc; 257 258 /* 259 * Initialization options 260 * 261 * These data types describe the options for each type of component 262 * internally to the jtag_init_*_ring routines. They can all be 263 * recast into arrays of unsigned integers. 264 * 265 * Note that these types DEPEND on the *_init_pdesc structures, which 266 * use indices to the components of the *_options types. As a result, 267 * the data structure & the type must be modified simultaneously, 268 * although this dependency is not immediately visible. This is ugly, 269 * but it makes the initialization routines much more readable. 270 */ 271 272 typedef struct { 273 u_int frozen; 274 u_int reset_a; 275 u_int reset_b; 276 u_int board_id; 277 u_int mask_hwerr; 278 u_int arb_fast; 279 u_int node_id; 280 u_int pcr_hi; 281 u_int pcr_lo; 282 u_int pcc_ctl1; 283 u_int pcc_ctl0; 284 u_int pcc_tctrl; 285 } ac_options; 286 287 struct ac_regs { 288 unsigned int bcsr; 289 unsigned int brscr; 290 unsigned int esr_hi; 291 unsigned int esr_lo; 292 unsigned int emr_hi; 293 unsigned int emr_lo; 294 unsigned int ccr; 295 unsigned int cntr_hi; 296 unsigned int cntr_lo; 297 }; 298 299 typedef struct { 300 u_int frozen; 301 u_int mask_pe; 302 u_int mask_oe; 303 } dc_options; 304 305 typedef struct { 306 u_int csr_hi; /* CSR 20:18 */ 307 u_int csr_mid; /* CSR 16:8 */ 308 u_int csr_midlo; /* CSR 6:4 */ 309 } fhc_options; 310 311 312 struct fhc_regs { 313 u_int por; 314 u_int csr; 315 u_int rcsr; 316 u_int bsr; 317 }; 318 319 /* Structure to capture the scan data from the bct8244's. */ 320 struct bct_fields { 321 u_int disk1_pres; 322 u_int disk0_pres; 323 u_int disk1_id; 324 u_int disk0_id; 325 }; 326 327 /* Collective type for *_options * */ 328 typedef u_int *jtag_opt; 329 330 /* 331 * The following definitions are the action flags used in the byte 332 * string which is used to describe component initialization. The 333 * only piece of code which understands those flags is jtag_init_chip. 334 * 335 * Initializing a component consists of scanning successive values 336 * into the component. The data for each pass is obtained by applying 337 * successive patches to a reference pattern. The patch descriptors 338 * are a byte string which form a succession of operations. The first 339 * byte of an operation is a set of flags defining the action: 340 */ 341 #define JTIN_INDEX 0x0F 342 #define JTIN_INSERT 0x10 343 #define JTIN_UPDATE 0x20 344 #define JTIN_COMPARE 0x40 345 #define JTIN_END 0x80 346 347 /* 348 * When JTIN_INSERT is specified, the flag byte is followed by 349 * two bytes indicating the lsb and msb of the field to be updated, and 350 * the JTIN_INDEX part of the flags indicate which value should be 351 * inserted: if JTIN_INDEX is zero, the value to insert is the next 352 * byte in the aray, extended to a 32-bit word; if JTIN_INDEX is 353 * non-zero, the value to insert is at word offset index in the patch 354 * array passed to jtag_init_chip. 355 */ 356 357 /* 358 * The fmt_desc field points to a reformat table which converts the 359 * scan-out format to the standard DSCR-style format. The format descriptor 360 * is a byte string, with special bytes indicating functional operations 361 * as indicated by bit fields in the following table: 362 */ 363 #define JTSO_END 0x80 /* end of table */ 364 #define JTSO_XTRACT 0x40 /* extract & merge [lsb, msb] */ 365 #define JTSO_ST 0x20 /* store & increment */ 366 #define JTSO_SHIFT 0x1F /* shift count for extract & merge */ 367 368 /* 369 * Function Declarations 370 */ 371 static void jtag_error_print(int, jtag_error); 372 static int jtag_get_comp_id(volatile u_int *, jtag_phys_comp *); 373 374 /* 375 * Bit-field manipulations 376 */ 377 static u_int jtag_bf_extract(u_char *s, int lsb, int msb); 378 static void jtag_bf_insert(u_char *s, int lsb, int msb, int value); 379 static void jtag_bf_zero(u_char *s, int nbits); 380 static int jtag_bf_cmp(u_char *s1, u_char *s2, int nbits); 381 382 /* 383 * Test-access port interface 384 */ 385 static int tap_wait(volatile u_int *); 386 static int tap_shift_single(volatile u_int *, int, int); 387 static int tap_shift_multiple(volatile u_int *, u_char *, int, u_char *); 388 389 /* 390 * Ring-level interface 391 */ 392 393 static int select_ring(volatile u_int *, jtag_ring, int); 394 static int jtag_rescan_IR_DR(volatile u_int *, jtag_phys_comp *, 395 jtag_instruction, u_char *, int, u_char *); 396 static int jtag_single_IR_DR(volatile u_int *, jtag_phys_comp *, 397 jtag_instruction, u_char *, int, u_char *); 398 static int jtag_ring_length(volatile u_int *, jtag_ring); 399 static int jtag_ring_ir_length(volatile u_int *, jtag_ring); 400 401 /* 402 * Component-level interface 403 */ 404 405 static int jtag_scanout_chip(volatile u_int *, jtag_ring, jtag_phys_comp *, 406 u_int *); 407 static int jtag_init_chip(volatile u_int *, jtag_ring, jtag_phys_comp *, 408 const u_int *, u_char *); 409 static jtag_phys_comp *find_chip(jtag_ring_desc *, jtag_log_comp *, int); 410 static void format_chip_data(u_char *, u_int *, u_char *); 411 static int jtag_init_ac(volatile u_int *, int, enum board_type); 412 413 /* 414 * Data tables. 415 * 416 * The JTAG implementation is data table driven. These tables describe 417 * the chip, ring, and board components. 418 */ 419 420 /* 421 * Data structures describing the scannable components 422 */ 423 424 static char jtag_err[] = "JTAG ERROR"; 425 426 /* Constants defining the IR lengths for each of the chips */ 427 428 #define IR_LEN 8 /* all sunfire asics, spitfire, and sdb are 8 bits */ 429 #define HM_LEN 4 /* happy meal is 4 bits */ 430 #define NDP_LEN 2 /* ndp83840 is 2 bits */ 431 #define SOC_LEN 4 /* SOC is 4 bits */ 432 #define SOCPLUS_LEN 8 /* SOC+ is 8 bits */ 433 #define SIO_LEN 16 /* sysio asic is 16 bits */ 434 #define PSYO_LEN 4 /* psycho asic is 4 bits */ 435 #define CHEO_LEN 4 /* cheerio asic is 4 bits */ 436 #define EC_LEN 3 /* ecache tag rams is 3 bits each */ 437 438 #define FFB_LEN 16 /* ffb module is 16 bits */ 439 #define THREED_LEN 4 /* IR length for three D rams */ 440 #define BT498_LEN 4 /* IR length for bt 498 chip (ramdac) */ 441 442 443 444 /* Standard instructions */ 445 #define IDCODE 0xFFFE 446 #define INITCODE 0xbe 447 #define DUMPCODE 0xbe 448 449 #define CID_TO_REV(cid) ((cid) >> 28) 450 451 /* ASIC Jag IDs */ 452 static u_int cid_sf[] = { 453 0x0002502f, 454 0 455 }; 456 457 static u_int cid_sdb[] = { 458 0x0002602f, 459 0 460 }; 461 462 static u_int cid_fbc[] = { 463 0x1241906d, 464 0 465 }; 466 467 static u_int cid_lvt[] = { 468 0x0001d02f, 469 0 470 }; 471 472 static u_int cid_3dram[] = { 473 0X0E9A103B, 474 0 475 }; 476 477 static u_int cid_bt498[] = { 478 0x0001d02f, 479 0 480 }; 481 482 static u_int cid_sio[] = { 483 0x0ef0703b, 484 0 485 }; 486 487 static u_int cid_hm[] = { 488 0x01792045, 489 0 490 }; 491 492 static u_int cid_ac[] = { 493 0x10f9e07d, 494 0 495 }; 496 497 static u_int cid_dc[] = { 498 0x10f9f07d, 499 0 500 }; 501 502 static u_int cid_fhc[] = { 503 0x10fa007d, 504 0 505 }; 506 507 static u_int cid_psyo[] = { 508 0x3195401d, 509 0 510 }; 511 512 static u_int cid_cheo[] = { 513 0x11791022, 514 0 515 }; 516 517 518 /* 519 * NOTE the following chips are ignored for the most part by the POST JTAG 520 * If if is later determined that scan data may be of interest then we need 521 * to fill in the blanks below. 522 */ 523 524 static u_char ec_init_pdesc[] = { 525 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 526 }; 527 528 static u_char ec_fmt[] = { 529 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 530 }; 531 532 static u_char sio_init_pdesc[] = { 533 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 534 }; 535 536 static u_char sio_fmt[] = { 537 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 538 }; 539 540 static u_char psyo_init_pdesc[] = { 541 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 542 }; 543 544 static u_char psyo_fmt[] = { 545 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 546 }; 547 548 static u_char hm_init_pdesc[] = { 549 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 550 }; 551 552 static u_char hm_fmt[] = { 553 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 554 }; 555 556 static u_char ndp_init_pdesc[] = { 557 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 558 }; 559 560 static u_char ndp_fmt[] = { 561 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 562 }; 563 564 static u_char cheo_init_pdesc[] = { 565 JTIN_END|JTIN_INSERT|0, 0, 0, 0x0 566 }; 567 568 static u_char cheo_fmt[] = { 569 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 570 }; 571 572 573 /* The main ASCIS of interest are the AC, DC and FHC */ 574 575 /* 576 * The initialization of DC is as follows: 577 * 578 * Do NOT change the following data structure without checking 579 * _options in jtag_private.h, which depends on it. 580 */ 581 static u_char dc_init_pdesc[] = { 582 JTIN_INSERT|1, 0, 0, /* NFZN */ 583 JTIN_INSERT|2, 4, 4, /* Mask PE */ 584 JTIN_INSERT|3, 3, 3, /* Mask OE */ 585 JTIN_INSERT|0, 1, 2, 3, /* W1C Errors */ 586 JTIN_END|JTIN_UPDATE, 587 }; 588 589 static u_char dc_fmt[] = { 590 JTSO_ST|JTSO_XTRACT|JTSO_END| 0, 0, 4 /* DC[4:0] */ 591 }; 592 593 /* 594 * The initialization of AC is as follows: 595 * 596 * Do NOT change the following data structure without checking 597 * _options in jtag_private.h, which depends on it. 598 */ 599 static u_char ac_init_pdesc[] = { 600 JTIN_INSERT|0, 161, 161, 1, /* BOARD ADDR 40 */ 601 JTIN_INSERT|7, 159, 160, /* BOARD ADDR 39:38, wfi node */ 602 JTIN_INSERT|4, 155, 158, /* BOARD ADDR 37:34 */ 603 JTIN_INSERT|4, 151, 154, /* BOARD ID */ 604 JTIN_INSERT|6, 146, 146, /* ARB_FAST */ 605 JTIN_INSERT|1, 134, 134, /* NFZN */ 606 JTIN_INSERT|0, 133, 133, 0, /* ENWAKPOR */ 607 JTIN_INSERT|2, 135, 135, /* Reset B */ 608 JTIN_INSERT|3, 136, 136, /* Reset A */ 609 JTIN_INSERT|0, 99, 106, 0xff, /* W1C Errors */ 610 JTIN_INSERT|0, 107, 114, 0xff, /* W1C Errors */ 611 JTIN_INSERT|0, 115, 122, 0xff, /* W1C Errors */ 612 JTIN_INSERT|0, 123, 130, 0xff, /* W1C Errors */ 613 JTIN_INSERT|0, 131, 132, 0xff, /* W1C Errors */ 614 JTIN_INSERT|5, 88, 98, /* Error Masks */ 615 JTIN_INSERT|12, 76, 87, /* CNT1_CTL_<27:16> */ 616 JTIN_INSERT|10, 70, 75, /* CNT1_CTL <13:8> */ 617 JTIN_INSERT|11, 64, 69, /* CNT0_CTL <5:0> */ 618 JTIN_INSERT|8, 32, 63, /* CNT1 */ 619 JTIN_INSERT|9, 0, 31, /* CNT0 */ 620 JTIN_END|JTIN_UPDATE, /* Clears counters */ 621 }; 622 623 static u_char ac_fmt[] = { 624 JTSO_XTRACT|17, 148, 162, /* BCSR[31:17] */ 625 JTSO_XTRACT|15, 147, 147, /* BSCR[15] */ 626 JTSO_XTRACT|5, 138, 146, /* BSCR[13:5] */ 627 JTSO_ST|JTSO_XTRACT|0, 134, 137, /* BSCR[3:0] */ 628 JTSO_ST|JTSO_XTRACT|22, 133, 133, /* BRSCR[22] */ 629 JTSO_XTRACT|16, 131, 132, /* ESR[49:48] */ 630 JTSO_XTRACT|8, 124, 130, /* ESR[46:40] */ 631 JTSO_XTRACT|4, 122, 123, /* ESR[37:36] */ 632 JTSO_ST|JTSO_XTRACT|0, 120, 121, /* ESR[33:32] */ 633 JTSO_XTRACT|28, 116, 119, /* ESR[31:28] */ 634 JTSO_XTRACT|24, 115, 115, /* ESR[24] */ 635 JTSO_XTRACT|20, 112, 114, /* ESR[22:20] */ 636 JTSO_XTRACT|12, 107, 111, /* ESR[16:12] */ 637 JTSO_XTRACT|4, 101, 106, /* ESR[9:4] */ 638 JTSO_ST|JTSO_XTRACT|0, 99, 100, /* ESR[1:0] */ 639 JTSO_XTRACT|16, 97, 98, /* EMR[49:48] */ 640 JTSO_XTRACT|8, 96, 96, /* EMR[40] */ 641 JTSO_ST|JTSO_XTRACT|4, 94, 95, /* EMR[37:36] */ 642 JTSO_XTRACT|28, 93, 93, /* EMR[28] */ 643 JTSO_XTRACT|24, 92, 92, /* EMR[24] */ 644 JTSO_XTRACT|20, 91, 91, /* EMR[20] */ 645 JTSO_XTRACT|12, 90, 90, /* EMR[12] */ 646 JTSO_XTRACT|8, 89, 89, /* EMR[8] */ 647 JTSO_ST|JTSO_XTRACT|4, 88, 88, /* EMR[4] */ 648 JTSO_XTRACT|16, 76, 87, /* CCR[27:16] */ 649 JTSO_XTRACT|8, 70, 75, /* CCR[13:8] */ 650 JTSO_ST|JTSO_XTRACT|0, 64, 69, /* CCR[5:0] */ 651 JTSO_ST|JTSO_XTRACT|0, 32, 63, /* CNT[63:32] */ 652 JTSO_ST|JTSO_XTRACT|JTSO_END|0, 0, 31 /* CNT[31:0] */ 653 }; 654 655 /* 656 */ 657 658 /* 659 * The following structure has three variable elements, as noted 660 * by the 1,2 and 3 digits or'ed in with the JTIN_INSERT flags. 661 * The number nad position of these elements must correspond with 662 * the fhc_ structure apssed into fhc_chip_init. 663 */ 664 static u_char fhc_init_pdesc[] = { 665 JTIN_INSERT|0, 41, 41, 0, /* POR */ 666 JTIN_INSERT|1, 38, 40, /* CSR[20:18] */ 667 JTIN_INSERT|2, 29, 37, /* CSR[16:8] */ 668 JTIN_INSERT|3, 26, 28, /* CSR[6:4] */ 669 JTIN_INSERT|0, 24, 25, 0x0, /* CSR[1:0] */ 670 JTIN_INSERT|0, 16, 23, 0x0, /* RCSR[31:24] */ 671 JTIN_INSERT|0, 2, 15, 0x0, /* BSR[18:5] */ 672 JTIN_INSERT|0, 0, 1, 0x0, /* BSR[1:0] */ 673 JTIN_END|JTIN_UPDATE, 674 }; 675 676 static u_char fhc_fmt[] = { 677 JTSO_ST|JTSO_XTRACT|0, 41, 41, /* POR State */ 678 JTSO_XTRACT|18, 38, 40, /* CSR[20:18] */ 679 JTSO_XTRACT|8, 29, 37, /* CSR[16:8] */ 680 JTSO_XTRACT|4, 26, 28, /* CSR[6:4] */ 681 JTSO_ST|JTSO_XTRACT|0, 24, 25, /* CSR[1:0] */ 682 JTSO_ST|JTSO_XTRACT|24, 16, 23, /* RCSR[31:24] */ 683 JTSO_XTRACT|5, 2, 15, /* BSR[18:5] */ 684 JTSO_ST|JTSO_XTRACT|JTSO_END|0, 0, 1, /* BSR[1:0] */ 685 }; 686 687 688 static u_char bct8244_fmt[] = { 689 JTSO_ST|JTSO_XTRACT|0, 17, 17, /* Disk 1 present */ 690 JTSO_ST|JTSO_XTRACT|0, 16, 16, /* Disk 0 present */ 691 JTSO_ST|JTSO_XTRACT|0, 12, 15, /* Disk 1 Target */ 692 JTSO_ST|JTSO_XTRACT|JTSO_END|0, 8, 11, /* Disk 0 Target */ 693 }; 694 695 /* A jtag_log_comp describes a component as seen by JTAG. */ 696 697 static jtag_log_comp chip_ac = { 698 cid_ac, 699 IR_LEN, 163, 700 IDCODE, INITCODE, DUMPCODE, 701 ac_init_pdesc, ac_fmt 702 }; 703 704 static jtag_log_comp chip_bct8244 = { 705 0, 706 IR_LEN, 18, 707 0x2, 0x2, 0x2, 708 NULL, bct8244_fmt 709 }; 710 711 static jtag_log_comp chip_dc = { 712 cid_dc, 713 IR_LEN, 5, 714 IDCODE, INITCODE, DUMPCODE, 715 dc_init_pdesc, dc_fmt 716 }; 717 718 static jtag_log_comp chip_fhc = { 719 cid_fhc, 720 IR_LEN, 42, 721 IDCODE, INITCODE, DUMPCODE, 722 fhc_init_pdesc, fhc_fmt 723 }; 724 725 static jtag_log_comp chip_ec = { 726 0, 727 EC_LEN, 42, 728 1, INITCODE, IDCODE, 729 ec_init_pdesc, ec_fmt 730 }; 731 732 static jtag_log_comp chip_fbc = { 733 cid_fbc, 734 FFB_LEN, 42, 735 0xb000, 0xb000, 0xb000, 736 NULL, NULL 737 }; 738 739 static jtag_log_comp chip_lvt = { 740 cid_lvt, 741 IR_LEN, 42, 742 IDCODE, INITCODE, DUMPCODE, 743 NULL, NULL 744 }; 745 746 static jtag_log_comp chip_3dram = { 747 cid_3dram, 748 THREED_LEN, 42, 749 IDCODE, INITCODE, DUMPCODE, 750 NULL, NULL 751 }; 752 753 static jtag_log_comp chip_bt498 = { 754 cid_bt498, 755 BT498_LEN, 42, 756 IDCODE, INITCODE, DUMPCODE, 757 NULL, NULL 758 }; 759 760 static jtag_log_comp chip_sio = { 761 cid_sio, 762 SIO_LEN, 42, 763 0xb000, 0xb000, 0xb000, 764 sio_init_pdesc, sio_fmt 765 }; 766 767 static jtag_log_comp chip_hm = { 768 cid_hm, 769 HM_LEN, 42, 770 0xe, 0xe, 0xe, 771 hm_init_pdesc, hm_fmt 772 }; 773 774 static jtag_log_comp chip_ndp = { 775 0, 776 NDP_LEN, 42, 777 2, 2, 2, 778 ndp_init_pdesc, ndp_fmt 779 }; 780 781 static jtag_log_comp chip_soc = { 782 0, 783 SOC_LEN, 42, 784 4, 4, 4, 785 NULL, NULL 786 }; 787 788 static jtag_log_comp chip_socplus = { 789 0, 790 SOCPLUS_LEN, 42, 791 0xfe, 4, 4, 792 NULL, NULL 793 }; 794 795 static jtag_log_comp chip_spitfire = { 796 cid_sf, 797 IR_LEN, 42, 798 0xfe, 0xfe, 0xfe, 799 NULL, NULL 800 }; 801 802 803 static jtag_log_comp chip_sdb = { 804 cid_sdb, 805 IR_LEN, 42, 806 0xfe, 0xfe, 0xfe, 807 NULL, NULL 808 }; 809 810 static jtag_log_comp chip_psyo = { 811 cid_psyo, 812 PSYO_LEN, 42, 813 0xb000, 0xb000, 0xb000, 814 psyo_init_pdesc, psyo_fmt 815 }; 816 817 static jtag_log_comp chip_cheo = { 818 cid_cheo, 819 CHEO_LEN, 42, 820 0xb000, 0xb000, 0xb000, 821 cheo_init_pdesc, cheo_fmt 822 }; 823 824 /* 825 * Ring descriptions for sunfire boards 826 * 827 * For each ring, there is a generic type descriptor which describes 828 * the order of chips in the static data structure describing the 829 * ring. 830 * 831 * Rings are described by an array of physical components, and are 832 * recast into the specific ring type by routines which use them, see 833 * for example the jtag_init_*_ring routines. 834 * 835 * Although the ring data structures are declared as jtag_phys_comp[], 836 * the components must be ordered as required by the corresponding 837 * *_*_ring type (in jtag_private.h). 838 */ 839 840 /* 841 * Data structures describing the system board rings 842 */ 843 844 static jtag_phys_comp cpu_sysbd_ring_components[] = { 845 { &chip_ac, 11*IR_LEN, 0, 11, 0 }, /* AC */ 846 { &chip_dc, 10*IR_LEN, 1*IR_LEN, 10, 1 }, /* DC 1 */ 847 { &chip_dc, 9*IR_LEN, 2*IR_LEN, 9, 2 }, /* DC 2 */ 848 { &chip_dc, 8*IR_LEN, 3*IR_LEN, 8, 3 }, /* DC 3 */ 849 { &chip_dc, 7*IR_LEN, 4*IR_LEN, 7, 4 }, /* DC 4 */ 850 { &chip_dc, 6*IR_LEN, 5*IR_LEN, 6, 5 }, /* DC 5 */ 851 { &chip_dc, 5*IR_LEN, 6*IR_LEN, 5, 6 }, /* DC 6 */ 852 { &chip_dc, 4*IR_LEN, 7*IR_LEN, 4, 7 }, /* DC 7 */ 853 { &chip_dc, 3*IR_LEN, 8*IR_LEN, 3, 8 }, /* DC 8 */ 854 { &chip_fhc, 2*IR_LEN, 9*IR_LEN, 2, 9 }, /* FHC */ 855 { &chip_ec, 1*IR_LEN, 10*IR_LEN, 1, 10 }, /* RAM 0 */ 856 { &chip_ec, 0*IR_LEN, 11*IR_LEN, 0, 11 }, /* RAM 1 */ 857 }; 858 859 static jtag_ring_desc cpu_sysbd_ring = { 860 12, cpu_sysbd_ring_components 861 }; 862 863 864 static jtag_phys_comp cpu_mod_1m_ring_components[] = { 865 { &chip_spitfire, 43, 0, 11, 0 }, /* Spitfire */ 866 { &chip_ec, 40, 8, 10, 1 }, /* Parity chip */ 867 { &chip_ec, 37, 11, 9, 2 }, /* Byte 0 */ 868 { &chip_ec, 34, 14, 8, 3 }, /* Byte 1 */ 869 { &chip_ec, 31, 17, 7, 4 }, /* Byte 2 */ 870 { &chip_ec, 28, 20, 6, 5 }, /* Byte 3 */ 871 { &chip_ec, 25, 23, 5, 6 }, /* Byte 4 */ 872 { &chip_ec, 22, 26, 4, 7 }, /* Byte 5 */ 873 { &chip_ec, 19, 29, 3, 8 }, /* Byte 6 */ 874 { &chip_ec, 16, 32, 2, 9 }, /* Byte 7 */ 875 { &chip_sdb, 8, 35, 1, 10 }, /* SDB */ 876 { &chip_sdb, 0, 43, 0, 11 }, /* SDB */ 877 }; 878 879 static jtag_ring_desc cpu_mod_1m_ring = { 880 12, cpu_mod_1m_ring_components 881 }; 882 883 static jtag_phys_comp cpu_mod_ring_components[] = { 884 { &chip_spitfire, 31, 0, 7, 0 }, /* Spitfire */ 885 { &chip_ec, 28, 8, 6, 1 }, /* Parity chip */ 886 { &chip_ec, 25, 11, 5, 2 }, /* Byte 0 */ 887 { &chip_ec, 22, 14, 4, 3 }, /* Byte 1 */ 888 { &chip_ec, 19, 17, 3, 4 }, /* Byte 2 */ 889 { &chip_ec, 16, 20, 2, 5 }, /* Byte 3 */ 890 { &chip_sdb, 8, 23, 1, 6 }, /* SDB */ 891 { &chip_sdb, 0, 31, 0, 7 }, /* SDB */ 892 }; 893 894 static jtag_ring_desc cpu_mod_ring = { 895 8, cpu_mod_ring_components 896 }; 897 898 static jtag_phys_comp io1_sysbd_ring_components[] = { 899 { &chip_ac, 114, 0, 14, 0 }, /* AC */ 900 { &chip_dc, 106, 8, 13, 1 }, /* DC 1 */ 901 { &chip_dc, 98, 16, 12, 2 }, /* DC 2 */ 902 { &chip_dc, 90, 24, 11, 3 }, /* DC 3 */ 903 { &chip_dc, 82, 32, 10, 4 }, /* DC 4 */ 904 { &chip_dc, 74, 40, 9, 5 }, /* DC 5 */ 905 { &chip_dc, 66, 48, 8, 6 }, /* DC 6 */ 906 { &chip_dc, 58, 56, 7, 7 }, /* DC 7 */ 907 { &chip_dc, 50, 64, 6, 8 }, /* DC 8 */ 908 { &chip_fhc, 42, 72, 5, 9 }, /* FHC */ 909 { &chip_sio, 26, 80, 4, 10 }, /* SIO 0 */ 910 { &chip_sio, 10, 96, 3, 11 }, /* SIO 1 */ 911 { &chip_hm, 6, 112, 2, 12 }, /* HM */ 912 { &chip_ndp, 4, 116, 1, 13 }, /* NDP */ 913 { &chip_soc, 0, 118, 0, 14 }, /* SOC */ 914 }; 915 916 static jtag_phys_comp io2_sysbd_ring_components[] = { 917 { &chip_ac, 98, 0, 13, 0 }, /* AC */ 918 { &chip_dc, 90, 8, 12, 1 }, /* DC 1 */ 919 { &chip_dc, 82, 16, 11, 2 }, /* DC 2 */ 920 { &chip_dc, 74, 24, 10, 3 }, /* DC 3 */ 921 { &chip_dc, 66, 32, 9, 4 }, /* DC 4 */ 922 { &chip_dc, 58, 40, 8, 5 }, /* DC 5 */ 923 { &chip_dc, 50, 48, 7, 6 }, /* DC 6 */ 924 { &chip_dc, 42, 56, 6, 7 }, /* DC 7 */ 925 { &chip_dc, 34, 64, 5, 8 }, /* DC 8 */ 926 { &chip_fhc, 26, 72, 4, 9 }, /* FHC */ 927 { &chip_sio, 10, 80, 3, 10 }, /* SIO */ 928 { &chip_hm, 6, 96, 2, 11 }, /* HM */ 929 { &chip_ndp, 4, 100, 1, 12 }, /* NDP */ 930 { &chip_soc, 0, 102, 0, 13 }, /* SOC */ 931 }; 932 933 static jtag_phys_comp io1plus_sysbd_ring_components[] = { 934 { &chip_ac, 118, 0, 14, 0 }, /* AC */ 935 { &chip_dc, 110, 8, 13, 1 }, /* DC 1 */ 936 { &chip_dc, 102, 16, 12, 2 }, /* DC 2 */ 937 { &chip_dc, 94, 24, 11, 3 }, /* DC 3 */ 938 { &chip_dc, 86, 32, 10, 4 }, /* DC 4 */ 939 { &chip_dc, 78, 40, 9, 5 }, /* DC 5 */ 940 { &chip_dc, 70, 48, 8, 6 }, /* DC 6 */ 941 { &chip_dc, 62, 56, 7, 7 }, /* DC 7 */ 942 { &chip_dc, 54, 64, 6, 8 }, /* DC 8 */ 943 { &chip_fhc, 46, 72, 5, 9 }, /* FHC */ 944 { &chip_sio, 30, 80, 4, 10 }, /* SIO 0 */ 945 { &chip_sio, 14, 96, 3, 11 }, /* SIO 1 */ 946 { &chip_hm, 10, 112, 2, 12 }, /* HM */ 947 { &chip_ndp, 8, 116, 1, 13 }, /* NDP */ 948 { &chip_socplus, 0, 118, 0, 14 }, /* SOC+ */ 949 }; 950 951 static jtag_phys_comp io2plus_sysbd_ring_components[] = { 952 { &chip_ac, 102, 0, 13, 0 }, /* AC */ 953 { &chip_dc, 94, 8, 12, 1 }, /* DC 1 */ 954 { &chip_dc, 86, 16, 11, 2 }, /* DC 2 */ 955 { &chip_dc, 78, 24, 10, 3 }, /* DC 3 */ 956 { &chip_dc, 70, 32, 9, 4 }, /* DC 4 */ 957 { &chip_dc, 62, 40, 8, 5 }, /* DC 5 */ 958 { &chip_dc, 54, 48, 7, 6 }, /* DC 6 */ 959 { &chip_dc, 46, 56, 6, 7 }, /* DC 7 */ 960 { &chip_dc, 38, 64, 5, 8 }, /* DC 8 */ 961 { &chip_fhc, 30, 72, 4, 9 }, /* FHC */ 962 { &chip_sio, 14, 80, 3, 10 }, /* SIO */ 963 { &chip_hm, 10, 96, 2, 11 }, /* HM */ 964 { &chip_ndp, 8, 100, 1, 12 }, /* NDP */ 965 { &chip_socplus, 0, 102, 0, 13 }, /* SOC+ */ 966 }; 967 968 static jtag_phys_comp io3_sysbd_ring_components[] = { 969 { &chip_ac, 102, 0, 15, 0 }, /* AC */ 970 { &chip_dc, 94, 8, 14, 1 }, /* DC 1 */ 971 { &chip_dc, 86, 16, 13, 2 }, /* DC 2 */ 972 { &chip_dc, 78, 24, 12, 3 }, /* DC 3 */ 973 { &chip_dc, 70, 32, 11, 4 }, /* DC 4 */ 974 { &chip_dc, 62, 40, 10, 5 }, /* DC 5 */ 975 { &chip_dc, 54, 48, 9, 6 }, /* DC 6 */ 976 { &chip_dc, 46, 56, 8, 7 }, /* DC 7 */ 977 { &chip_dc, 38, 64, 7, 8 }, /* DC 8 */ 978 { &chip_fhc, 30, 72, 6, 9 }, /* FHC */ 979 { &chip_psyo, 26, 80, 5, 10 }, /* PSYO 0 */ 980 { &chip_cheo, 22, 84, 4, 11 }, /* CHEO */ 981 { &chip_ndp, 20, 88, 3, 12 }, /* NDP */ 982 { &chip_psyo, 16, 90, 2, 13 }, /* PSYO 1 */ 983 { &chip_bct8244, 8, 94, 1, 14 }, /* BCT 8244 */ 984 { &chip_bct8244, 0, 102, 0, 15 }, /* BCT 8244 */ 985 }; 986 987 static jtag_phys_comp dsk_sysbd_ring_components[] = { 988 { &chip_bct8244, 8, 0, 1, 0 }, /* BCT 8244 */ 989 { &chip_fhc, 0, 8, 0, 1 }, /* FHC */ 990 }; 991 992 static jtag_ring_desc io1_sysbd_ring = { 993 15, io1_sysbd_ring_components 994 }; 995 996 static jtag_ring_desc io1plus_sysbd_ring = { 997 15, io1plus_sysbd_ring_components 998 }; 999 1000 static jtag_ring_desc io2_sysbd_ring = { 1001 14, io2_sysbd_ring_components 1002 }; 1003 1004 static jtag_ring_desc io2plus_sysbd_ring = { 1005 14, io2plus_sysbd_ring_components 1006 }; 1007 1008 static jtag_ring_desc io3_sysbd_ring = { 1009 16, io3_sysbd_ring_components 1010 }; 1011 1012 static jtag_ring_desc dsk_sysbd_ring = { 1013 2, dsk_sysbd_ring_components 1014 }; 1015 1016 /* 1017 * Ring descriptors for single and double buffered FFB boards. 1018 * Note - Only the FBC has a component ID register. None of the 1019 * other chips on the FFB board has one, so do not check them. 1020 */ 1021 static jtag_phys_comp ffb_sngl_ring_components[] = { 1022 { &chip_fbc, 20, 0, 5, 0 }, /* FBC */ 1023 { &chip_3dram, 16, 16, 4, 1 }, /* 3DRAM */ 1024 { &chip_3dram, 12, 20, 3, 2 }, /* 3DRAM */ 1025 { &chip_3dram, 8, 24, 2, 3 }, /* 3DRAM */ 1026 { &chip_3dram, 4, 28, 1, 4 }, /* 3DRAM */ 1027 { &chip_bt498, 0, 32, 0, 5 }, /* RAMDAC */ 1028 }; 1029 1030 static jtag_phys_comp ffb_dbl_ring_components[] = { 1031 { &chip_fbc, 84, 0, 17, 0 }, /* FBC */ 1032 { &chip_lvt, 76, 16, 16, 1 }, /* LVT */ 1033 { &chip_lvt, 68, 24, 15, 2 }, /* LVT */ 1034 { &chip_lvt, 60, 32, 14, 3 }, /* LVT */ 1035 { &chip_lvt, 52, 40, 13, 4 }, /* LVT */ 1036 { &chip_3dram, 48, 48, 12, 5 }, /* 3DRAM */ 1037 { &chip_3dram, 44, 52, 11, 6 }, /* 3DRAM */ 1038 { &chip_3dram, 40, 56, 10, 7 }, /* 3DRAM */ 1039 { &chip_3dram, 36, 60, 9, 8 }, /* 3DRAM */ 1040 { &chip_3dram, 32, 64, 8, 9 }, /* 3DRAM */ 1041 { &chip_3dram, 28, 68, 7, 10 }, /* 3DRAM */ 1042 { &chip_3dram, 24, 72, 6, 11 }, /* 3DRAM */ 1043 { &chip_3dram, 20, 76, 5, 12 }, /* 3DRAM */ 1044 { &chip_3dram, 16, 80, 4, 13 }, /* 3DRAM */ 1045 { &chip_3dram, 12, 84, 3, 14 }, /* 3DRAM */ 1046 { &chip_3dram, 8, 88, 2, 15 }, /* 3DRAM */ 1047 { &chip_3dram, 4, 92, 1, 16 }, /* 3DRAM */ 1048 { &chip_bt498, 0, 96, 0, 17 }, /* RAMDAC */ 1049 }; 1050 1051 static jtag_ring_desc ffb_sngl_ring = { 1052 6, ffb_sngl_ring_components 1053 }; 1054 1055 static jtag_ring_desc ffb_dbl_ring = { 1056 18, ffb_dbl_ring_components 1057 }; 1058 1059 /* 1060 * Board descriptions 1061 */ 1062 1063 static jtag_ring_desc *cpu_system_board[] = { 1064 &cpu_sysbd_ring, /* Ring 0 */ 1065 &cpu_mod_ring, /* Ring 1 */ 1066 &cpu_mod_ring, /* Ring 2 */ 1067 }; 1068 1069 static jtag_ring_desc *io1_system_board[] = { 1070 &io1_sysbd_ring, /* Ring 0 */ 1071 (jtag_ring_desc *) NULL, /* Ring 1 */ 1072 (jtag_ring_desc *) NULL, /* Ring 2 */ 1073 }; 1074 1075 static jtag_ring_desc *io1plus_system_board[] = { 1076 &io1plus_sysbd_ring, /* Ring 0 */ 1077 (jtag_ring_desc *) NULL, /* Ring 1 */ 1078 (jtag_ring_desc *) NULL, /* Ring 2 */ 1079 }; 1080 1081 static jtag_ring_desc *io2_system_board[] = { 1082 &io2_sysbd_ring, /* Ring 0 */ 1083 (jtag_ring_desc *) NULL, /* Ring 1 (ffb) */ 1084 (jtag_ring_desc *) NULL, /* Ring 2 */ 1085 }; 1086 1087 static jtag_ring_desc *io2plus_system_board[] = { 1088 &io2plus_sysbd_ring, /* Ring 0 */ 1089 (jtag_ring_desc *) NULL, /* Ring 1 (ffb) */ 1090 (jtag_ring_desc *) NULL, /* Ring 2 */ 1091 }; 1092 1093 static jtag_ring_desc *io3_system_board[] = { 1094 &io3_sysbd_ring, /* Ring 0 */ 1095 (jtag_ring_desc *) NULL, /* Ring 1 */ 1096 (jtag_ring_desc *) NULL, /* Ring 2 */ 1097 }; 1098 1099 static jtag_ring_desc *disk_system_board[] = { 1100 &dsk_sysbd_ring, /* Ring 0 */ 1101 (jtag_ring_desc *) NULL, /* Ring 1 */ 1102 (jtag_ring_desc *) NULL, /* Ring 2 */ 1103 }; 1104 1105 /* 1106 * Function Definitions: 1107 * --------------------- 1108 */ 1109 1110 /* For sunfire there will be a ring descriptor for each type of board */ 1111 static jtag_ring_desc * 1112 get_ring_descriptor_bytype(int ring, enum board_type type) 1113 { 1114 1115 switch (type) { 1116 case CPU_BOARD: 1117 return (cpu_system_board[ring & 0xf]); 1118 1119 case IO_2SBUS_BOARD: 1120 return (io1_system_board[ring & 0xf]); 1121 1122 case IO_2SBUS_SOCPLUS_BOARD: 1123 return (io1plus_system_board[ring & 0xf]); 1124 1125 case IO_SBUS_FFB_BOARD: 1126 return (io2_system_board[ring & 0xf]); 1127 1128 case IO_SBUS_FFB_SOCPLUS_BOARD: 1129 return (io2plus_system_board[ring & 0xf]); 1130 1131 case IO_PCI_BOARD: 1132 return (io3_system_board[ring & 0xf]); 1133 1134 case DISK_BOARD: 1135 return (disk_system_board[ring & 0xf]); 1136 1137 default: 1138 return (NULL); 1139 } 1140 } 1141 1142 static void 1143 jtag_check_plus_board( 1144 volatile u_int *jreg, 1145 jtag_ring ring, 1146 jtag_phys_comp *comp, 1147 sysc_cfga_stat_t *sc) 1148 { 1149 struct fhc_regs fhc_data; 1150 1151 /* 1152 * the FHC Board Status Register indicates whether 1153 * the board 100 Mhz capable or not. 1154 */ 1155 fhc_data.bsr = (u_int)0xffffffff; 1156 1157 if ((jtag_scanout_chip(jreg, ring, comp, (u_int *)&fhc_data) >= 0) && 1158 (FHC_BSR_TO_BD(fhc_data.bsr) == sc->board) && 1159 ISPLUSBRD(fhc_data.bsr)) 1160 sc->plus_board = 1; 1161 } 1162 1163 /* 1164 * Returns (positive) board type if something detected, including 1165 * UNKNOWN_BOARD. 1166 * Returns EMPTY_BOARD if nothing there. 1167 */ 1168 enum board_type 1169 jtag_get_board_type(volatile u_int *jreg, sysc_cfga_stat_t *sc) 1170 { 1171 int len; 1172 int ring; 1173 int result; 1174 int board; 1175 int status; 1176 1177 /* 1178 * Select Board Ring 0 to scan. This contains the AC, FHC, 1179 * and DC ASICs 1180 */ 1181 1182 /* 1183 * Ring number is JTAG Board (7:4) and ring number (3:0) 1184 */ 1185 board = sc->board; 1186 ring = (board << 4) | 0; 1187 1188 if ((status = select_ring(jreg, ring, 1)) < 0) { 1189 cmn_err(CE_WARN, "Select ring error %d\n", status); 1190 } 1191 1192 len = jtag_ring_length(jreg, ring); 1193 switch (len) { 1194 case CPU_TYPE_LEN: 1195 result = CPU_BOARD; 1196 1197 jtag_check_plus_board(jreg, ring, 1198 &cpu_sysbd_ring_components[9], sc); 1199 1200 break; 1201 1202 case IO_TYPE1_LEN: 1203 switch (jtag_ring_ir_length(jreg, ring)) { 1204 case RING_BROKEN: 1205 result = UNKNOWN_BOARD; 1206 break; 1207 case IO_TYPE4_LEN: 1208 result = IO_2SBUS_SOCPLUS_BOARD; 1209 jtag_check_plus_board(jreg, ring, 1210 &io1plus_sysbd_ring_components[9], sc); 1211 break; 1212 default: 1213 result = IO_2SBUS_BOARD; 1214 jtag_check_plus_board(jreg, ring, 1215 &io1_sysbd_ring_components[9], sc); 1216 break; 1217 } 1218 1219 break; 1220 1221 case IO_TYPE2_LEN: 1222 switch (jtag_ring_ir_length(jreg, ring)) { 1223 case RING_BROKEN: 1224 result = UNKNOWN_BOARD; 1225 break; 1226 case IO_TYPE5_LEN: 1227 result = IO_SBUS_FFB_SOCPLUS_BOARD; 1228 jtag_check_plus_board(jreg, ring, 1229 &io2plus_sysbd_ring_components[9], sc); 1230 break; 1231 default: 1232 result = IO_SBUS_FFB_BOARD; 1233 jtag_check_plus_board(jreg, ring, 1234 &io2_sysbd_ring_components[9], sc); 1235 break; 1236 } 1237 1238 break; 1239 1240 case PCI_TYPE_LEN: 1241 switch (jtag_ring_ir_length(jreg, ring)) { 1242 case RING_BROKEN: 1243 result = UNKNOWN_BOARD; 1244 break; 1245 case PCI_TYPEA_LEN: 1246 result = IO_PCI_BOARD; 1247 jtag_check_plus_board(jreg, ring, 1248 &io3_sysbd_ring_components[9], sc); 1249 break; 1250 case PCI_TYPEB_LEN: 1251 default: 1252 result = UNKNOWN_BOARD; 1253 break; 1254 } 1255 break; 1256 1257 case DSK_TYPE_LEN: 1258 result = DISK_BOARD; 1259 break; 1260 1261 case RING_BROKEN: 1262 result = EMPTY_BOARD; 1263 break; 1264 1265 default: 1266 result = UNKNOWN_BOARD; 1267 break; 1268 } 1269 1270 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 1271 1272 return (result); 1273 } 1274 1275 #ifndef RFE_4174486 1276 /* 1277 * Until the RFE is fully investigated the likelyhood is that the 1278 * CPU frequency may be incorrectly displayed. Coupled with the lack of 1279 * Ecache size information and no information at all unless the 1280 * CPU board is physically plugged in, the default is not to get any 1281 * CPU information. 1282 * This patchable flag is provided so that more testing can be done 1283 * without re-compilation. 1284 */ 1285 static int jtag_cpu_scan_enable = 0; 1286 #endif /* RFE_4174486 */ 1287 1288 int 1289 jtag_get_board_info(volatile u_int *jreg, sysc_cfga_stat_t *sc) 1290 { 1291 jtag_ring_desc *rd; 1292 jtag_phys_comp *rc; 1293 int status; 1294 int ring; 1295 int len; 1296 int i; 1297 struct cpu_info *cpu; 1298 struct bct_fields bct_data; 1299 1300 /* fill in the board info structure */ 1301 1302 ring = sc->board << 4; 1303 1304 if ((status = select_ring(jreg, ring, 1)) < 0) { 1305 return (status); 1306 } 1307 1308 rd = get_ring_descriptor_bytype(ring, sc->type); 1309 1310 if (rd == NULL) { 1311 return (JTAG_FAIL); 1312 } 1313 1314 /* scan in the generic data common to all board types. */ 1315 1316 /* get the AC component ID */ 1317 rc = find_chip(rd, &chip_ac, 0); 1318 if (rc != NULL) { 1319 sc->ac_compid = jtag_get_comp_id(jreg, rc); 1320 } 1321 1322 /* get the FHC component ID */ 1323 rc = find_chip(rd, &chip_fhc, 0); 1324 if (rc != NULL) { 1325 sc->fhc_compid = jtag_get_comp_id(jreg, rc); 1326 } 1327 1328 /* Now scan the board type dependent components */ 1329 switch (sc->type) { 1330 case CPU_BOARD: 1331 /* 1332 * first determine the cache size of each module, then 1333 * use that ring descriptor. 1334 */ 1335 1336 for (i = 0, cpu = &sc->bd.cpu[i]; i < 2; i++, cpu++) { 1337 bzero(cpu, sizeof (*cpu)); 1338 #ifndef RFE_4174486 1339 if (!jtag_cpu_scan_enable) 1340 continue; 1341 #endif /* RFE_4174486 */ 1342 if (select_ring(jreg, ring | (i + 1), 1) < 0) { 1343 continue; 1344 } 1345 1346 len = jtag_ring_length(jreg, ring | (i + 1)); 1347 1348 switch (len) { 1349 case CPU_0_5_LEN: 1350 rd = &cpu_mod_ring; 1351 cpu->cpu_detected = 1; 1352 break; 1353 1354 case CPU_1_0_LEN: 1355 rd = &cpu_mod_1m_ring; 1356 cpu->cpu_detected = 1; 1357 break; 1358 1359 case RING_BROKEN: 1360 default: 1361 rd = NULL; 1362 break; 1363 } 1364 1365 if (!cpu->cpu_detected) 1366 continue; 1367 1368 if (rd != NULL) { 1369 rc = find_chip(rd, &chip_spitfire, 0); 1370 if (rc != NULL) { 1371 cpu->cpu_compid = 1372 jtag_get_comp_id(jreg, rc); 1373 } 1374 1375 /* 1376 * Do not get the component ID from the 1377 * first E$ chip. This is the tag chip 1378 * and does not help determine cache size. 1379 */ 1380 rc = find_chip(rd, &chip_ec, 1); 1381 if (rc != NULL) { 1382 cpu->ec_compid = 1383 jtag_get_comp_id(jreg, rc); 1384 } 1385 1386 rc = find_chip(rd, &chip_sdb, 0); 1387 if (rc != NULL) { 1388 cpu->sdb0_compid = 1389 jtag_get_comp_id(jreg, rc); 1390 } 1391 1392 rc = find_chip(rd, &chip_sdb, 1); 1393 if (rc != NULL) { 1394 cpu->sdb1_compid = 1395 jtag_get_comp_id(jreg, rc); 1396 } 1397 } 1398 1399 #ifdef RFE_4174486 1400 /* Work out Ecache size. */ 1401 switch (len) { 1402 case CPU_0_5_LEN: 1403 cpu->cache_size = 0x80000; 1404 break; 1405 1406 case CPU_1_0_LEN: 1407 /* default cache size for 9 SRAM chips */ 1408 cpu->cache_size = 0x100000; 1409 break; 1410 1411 default: 1412 break; 1413 } 1414 #endif /* RFE_4174486 */ 1415 } 1416 1417 break; 1418 1419 case IO_2SBUS_BOARD: 1420 rc = find_chip(rd, &chip_sio, 0); 1421 if (rc != NULL) { 1422 sc->bd.io1.sio0_compid = 1423 jtag_get_comp_id(jreg, rc); 1424 } 1425 1426 rc = find_chip(rd, &chip_sio, 1); 1427 if (rc != NULL) { 1428 sc->bd.io1.sio1_compid = 1429 jtag_get_comp_id(jreg, rc); 1430 } 1431 1432 rc = find_chip(rd, &chip_hm, 0); 1433 if (rc != NULL) { 1434 sc->bd.io1.hme_compid = jtag_get_comp_id(jreg, rc); 1435 } 1436 1437 rc = find_chip(rd, &chip_soc, 0); 1438 if (rc != NULL) { 1439 sc->bd.io1.soc_compid = jtag_get_comp_id(jreg, rc); 1440 } 1441 1442 break; 1443 1444 case IO_2SBUS_SOCPLUS_BOARD: 1445 rc = find_chip(rd, &chip_sio, 0); 1446 if (rc != NULL) { 1447 sc->bd.io1.sio0_compid = 1448 jtag_get_comp_id(jreg, rc); 1449 } 1450 1451 rc = find_chip(rd, &chip_sio, 1); 1452 if (rc != NULL) { 1453 sc->bd.io1.sio1_compid = 1454 jtag_get_comp_id(jreg, rc); 1455 } 1456 1457 rc = find_chip(rd, &chip_hm, 0); 1458 if (rc != NULL) { 1459 sc->bd.io1.hme_compid = jtag_get_comp_id(jreg, rc); 1460 } 1461 1462 rc = find_chip(rd, &chip_socplus, 0); 1463 if (rc != NULL) { 1464 sc->bd.io1plus.socplus_compid = 1465 jtag_get_comp_id(jreg, rc); 1466 } 1467 1468 break; 1469 1470 case IO_SBUS_FFB_BOARD: 1471 rc = find_chip(rd, &chip_sio, 0); 1472 if (rc != NULL) { 1473 sc->bd.io2.sio1_compid = jtag_get_comp_id(jreg, rc); 1474 } 1475 1476 rc = find_chip(rd, &chip_hm, 0); 1477 if (rc != NULL) { 1478 sc->bd.io2.hme_compid = jtag_get_comp_id(jreg, rc); 1479 } 1480 1481 rc = find_chip(rd, &chip_soc, 0); 1482 if (rc != NULL) { 1483 sc->bd.io2.soc_compid = jtag_get_comp_id(jreg, rc); 1484 } 1485 1486 /* Now scan for an FFB board */ 1487 if (select_ring(jreg, ring | 1, 1) < 0) { 1488 len = RING_BROKEN; 1489 } else { 1490 len = jtag_ring_length(jreg, ring | 1); 1491 } 1492 1493 switch (len) { 1494 case FFB_SNG_LEN: 1495 rd = &ffb_sngl_ring; 1496 sc->bd.io2.ffb_size = FFB_SINGLE; 1497 break; 1498 1499 case FFB_DBL_LEN: 1500 rd = &ffb_dbl_ring; 1501 sc->bd.io2.ffb_size = FFB_DOUBLE; 1502 break; 1503 1504 case RING_BROKEN: 1505 rd = NULL; 1506 sc->bd.io2.ffb_size = FFB_NOT_FOUND; 1507 break; 1508 1509 default: 1510 rd = NULL; 1511 sc->bd.io2.ffb_size = FFB_FAILED; 1512 break; 1513 } 1514 1515 /* Now scan out the FBC component ID */ 1516 if (rd != NULL) { 1517 rc = find_chip(rd, &chip_fbc, 0); 1518 } 1519 1520 if (rc != NULL) { 1521 sc->bd.io2.fbc_compid = jtag_get_comp_id(jreg, rc); 1522 } 1523 break; 1524 1525 case IO_SBUS_FFB_SOCPLUS_BOARD: 1526 rc = find_chip(rd, &chip_sio, 0); 1527 if (rc != NULL) { 1528 sc->bd.io2.sio1_compid = jtag_get_comp_id(jreg, rc); 1529 } 1530 1531 rc = find_chip(rd, &chip_hm, 0); 1532 if (rc != NULL) { 1533 sc->bd.io2.hme_compid = jtag_get_comp_id(jreg, rc); 1534 } 1535 1536 rc = find_chip(rd, &chip_socplus, 0); 1537 if (rc != NULL) { 1538 sc->bd.io2plus.socplus_compid = 1539 jtag_get_comp_id(jreg, rc); 1540 } 1541 1542 /* Now scan for an FFB board */ 1543 if (select_ring(jreg, ring | 1, 1) < 0) { 1544 len = RING_BROKEN; 1545 } else { 1546 len = jtag_ring_length(jreg, ring | 1); 1547 } 1548 1549 switch (len) { 1550 case FFB_SNG_LEN: 1551 rd = &ffb_sngl_ring; 1552 sc->bd.io2.ffb_size = FFB_SINGLE; 1553 break; 1554 1555 case FFB_DBL_LEN: 1556 rd = &ffb_dbl_ring; 1557 sc->bd.io2.ffb_size = FFB_DOUBLE; 1558 break; 1559 1560 case RING_BROKEN: 1561 rd = NULL; 1562 sc->bd.io2.ffb_size = FFB_NOT_FOUND; 1563 break; 1564 1565 default: 1566 rd = NULL; 1567 sc->bd.io2.ffb_size = FFB_FAILED; 1568 break; 1569 } 1570 1571 /* Now scan out the FBC component ID */ 1572 if (rd != NULL) { 1573 rc = find_chip(rd, &chip_fbc, 0); 1574 } 1575 1576 if (rc != NULL) { 1577 sc->bd.io2.fbc_compid = jtag_get_comp_id(jreg, rc); 1578 } 1579 break; 1580 1581 case IO_PCI_BOARD: 1582 rc = find_chip(rd, &chip_psyo, 0); 1583 if (rc != NULL) { 1584 sc->bd.io3.psyo0_compid = 1585 jtag_get_comp_id(jreg, rc); 1586 } 1587 1588 rc = find_chip(rd, &chip_psyo, 1); 1589 if (rc != NULL) { 1590 sc->bd.io3.psyo1_compid = 1591 jtag_get_comp_id(jreg, rc); 1592 } 1593 1594 rc = find_chip(rd, &chip_cheo, 0); 1595 if (rc != NULL) { 1596 sc->bd.io3.cheo_compid = jtag_get_comp_id(jreg, rc); 1597 } 1598 1599 break; 1600 1601 case DISK_BOARD: 1602 /* 1603 * Scan the BCT8244 to get the disk drive info out of 1604 * the chip. 1605 */ 1606 if (jtag_scanout_chip(jreg, ring, 1607 &dsk_sysbd_ring_components[0], (u_int *)&bct_data) < 0) { 1608 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 1609 return (-1); 1610 } 1611 1612 if ((bct_data.disk0_pres && 0x1) == 0) { 1613 sc->bd.dsk.disk_pres[0] = 1; 1614 sc->bd.dsk.disk_id[0] = 0xf & ~bct_data.disk0_id; 1615 } else { 1616 sc->bd.dsk.disk_pres[0] = 0; 1617 } 1618 1619 if ((bct_data.disk1_pres && 0x1) == 0) { 1620 sc->bd.dsk.disk_pres[1] = 1; 1621 sc->bd.dsk.disk_id[1] = 0xf & ~bct_data.disk1_id; 1622 } else { 1623 sc->bd.dsk.disk_pres[1] = 0; 1624 } 1625 1626 break; 1627 1628 default: 1629 break; 1630 } 1631 1632 return (JTAG_OK); 1633 } 1634 1635 static jtag_phys_comp * 1636 find_chip(jtag_ring_desc *rd, jtag_log_comp *chip, int instance) 1637 { 1638 int i; 1639 int found = 0; 1640 jtag_phys_comp *rc; 1641 1642 for (i = rd->size, rc = rd->components; i != 0; rc++, i--) { 1643 if (rc->chip == chip) { 1644 if (found == instance) { 1645 return (rc); 1646 } else { 1647 found++; 1648 } 1649 } 1650 } 1651 return (NULL); 1652 } 1653 1654 /* 1655 * Function jtag_error() : 1656 * 1657 * This function centrailizes the use of the JTAG error strings. 1658 * It should be called with the JTAG error code anytime the programmer 1659 * wants to print the type of JTAG error encountered. Just call with the 1660 * error code returned by the JTAG function. If no error occurred, nothing 1661 * is printed. 1662 */ 1663 static void 1664 jtag_error_print(int ring, jtag_error code) 1665 { 1666 char *ring_str = "System Board"; 1667 1668 switch (code) { 1669 case JTAG_OK : 1670 break; 1671 1672 case TAP_TIMEOUT : 1673 cmn_err(CE_WARN, "%s : TAP controller timeout\n", jtag_err); 1674 break; 1675 1676 case BAD_ARGS : 1677 cmn_err(CE_WARN, 1678 "%s : routine reports bad args: Board %d, %s Ring\n", 1679 jtag_err, ring >> 4, ring_str); 1680 break; 1681 1682 case BAD_CID : 1683 cmn_err(CE_WARN, 1684 "%s : Bad component ID detected: Board %d, %s Ring\n", 1685 jtag_err, ring >> 4, ring_str); 1686 break; 1687 1688 case RING_BROKEN : 1689 cmn_err(CE_WARN, "%s : ring broken: Board %d, %s Ring\n", 1690 jtag_err, ring >> 4, ring_str); 1691 break; 1692 1693 case INIT_MISMATCH: 1694 cmn_err(CE_WARN, 1695 "%s : State after init not expected: Board %d, " 1696 "%s Ring\n", jtag_err, ring >> 4, ring_str); 1697 break; 1698 1699 case LENGTH_MISMATCH : 1700 cmn_err(CE_WARN, 1701 "%s : Scan Chain Length mismatch: Board %d," 1702 " %s Ring\n", 1703 jtag_err, ring >> 4, ring_str); 1704 break; 1705 1706 } /* end of switch on code */ 1707 } /* end of jtag_error_print() */ 1708 1709 1710 static int 1711 jtag_get_comp_id(volatile u_int *jreg, jtag_phys_comp *comp) 1712 { 1713 u_char b[4]; 1714 u_int id; 1715 int status; 1716 1717 status = jtag_single_IR_DR(jreg, comp, comp->chip->id_code, 1718 b, 32, b); 1719 1720 /* Reorder the bytes of the ID read out */ 1721 id = b[0] | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 1722 1723 if (status < 0) { 1724 return (0); 1725 } else { 1726 return (id); 1727 } 1728 } 1729 1730 /* 1731 * Bit-manipulation routines 1732 */ 1733 1734 /* 1735 * jtag_bf_extract() 1736 * 1737 * This routine extracts bit strings from JTAG data scanout strings. This 1738 * routine is used to decode data scanned out of chips via JTAG. 1739 */ 1740 static u_int 1741 jtag_bf_extract(u_char *s, int lsb, int msb) 1742 { 1743 u_int result = 0; 1744 1745 ASSERT(s); 1746 1747 /* 1748 * lsb and msb are assumed to be within string, 1749 * and to span 32 bits at most 1750 */ 1751 for (; msb >= lsb; msb--) { 1752 result = (result << 1) | ((s[msb>>3] >> (msb & 7)) & 1); 1753 } 1754 return (result); 1755 } 1756 1757 /* 1758 * jtag_bf_insert() 1759 * 1760 * This routine is used to build bit strings for scanning into the 1761 * shadow chains of ASICs. 1762 */ 1763 static void 1764 jtag_bf_insert(u_char *s, int lsb, int msb, int value) 1765 { 1766 ASSERT(s); 1767 1768 /* 1769 * lsb and msb are assumed to be within string, 1770 * and to span 32 bits at most 1771 */ 1772 1773 for (; msb >= lsb; lsb++) { 1774 s[lsb>>3] = (s[lsb>>3] & ~ (1 << (lsb & 7))) | 1775 ((value & 1) << (lsb & 7)); 1776 value = value >> 1; 1777 } 1778 } 1779 1780 /* 1781 * 1782 */ 1783 static void 1784 jtag_bf_zero(u_char *s, int nbits) 1785 { 1786 int nbytes = (nbits+7)>>3; 1787 1788 while (nbytes-- != 0) { 1789 *s++ = 0; 1790 } 1791 } 1792 1793 /* 1794 * Return 0 if equal, != 0 else 1795 */ 1796 static int 1797 jtag_bf_cmp(u_char *s1, u_char *s2, int nbits) 1798 { 1799 int mask; 1800 for (nbits -= 8; nbits > 0; nbits -= 8) { 1801 if (*s1++ != *s2++) { 1802 return (-1); 1803 } 1804 mask = 0xFF >> (-nbits); 1805 if ((*s1++ & mask) != (*s2++ & mask)) { 1806 return (-1); 1807 } 1808 } 1809 1810 return (0); 1811 } 1812 1813 1814 /* 1815 * Generic chip-level top routines 1816 */ 1817 static int 1818 jtag_init_chip( 1819 volatile u_int *jreg, 1820 jtag_ring ring, 1821 jtag_phys_comp *component, 1822 const u_int *pval, 1823 u_char scan_out[32]) 1824 { 1825 int status; 1826 jtag_log_comp *chip; 1827 u_char scan_in[32]; 1828 u_char *pdesc; 1829 1830 status = select_ring(jreg, ring, 1); 1831 if (status < 0) { 1832 return (status); 1833 } 1834 1835 pval = pval - 1; /* adjust pval since indices start at 1 */ 1836 chip = component->chip; 1837 pdesc = chip->init_pdesc; 1838 1839 /* Zero out the scan-in area */ 1840 jtag_bf_zero(scan_in, 8*32); 1841 jtag_bf_zero(scan_out, 8*32); 1842 1843 for (;;) { 1844 u_int flags, lsb, msb, patch; 1845 flags = *pdesc++; 1846 if ((flags & JTIN_INSERT) != 0) { 1847 lsb = *pdesc++; 1848 msb = *pdesc++; 1849 if ((flags & JTIN_INDEX) != 0) { 1850 patch = pval[flags & JTIN_INDEX]; 1851 } else { 1852 patch = *pdesc++; 1853 } 1854 jtag_bf_insert(scan_in, lsb, msb, patch); 1855 } 1856 1857 if ((flags & JTIN_UPDATE) != 0) { 1858 status = jtag_single_IR_DR(jreg, component, 1859 chip->init_code, scan_in, chip->dr_len, 1860 scan_out); 1861 1862 if (status < 0) { 1863 return (status); 1864 } 1865 1866 if ((status = select_ring(jreg, ring, 1)) < 0) { 1867 return (status); 1868 } 1869 } 1870 1871 if ((flags & JTIN_COMPARE) != 0) { 1872 if (jtag_bf_cmp(scan_in, scan_out, chip->dr_len) != 0) 1873 return (INIT_MISMATCH); 1874 } 1875 1876 if ((flags & JTIN_END) != 0) { 1877 break; 1878 } 1879 } 1880 1881 return (JTAG_OK); /* all is OK... */ 1882 } 1883 1884 /* 1885 * Dump the info from a chip. 1886 * Return the number of bytes used, or <0 if failed 1887 */ 1888 static int 1889 jtag_scanout_chip( 1890 volatile u_int *jreg, 1891 jtag_ring ring, 1892 jtag_phys_comp *component, 1893 u_int *result) 1894 { 1895 int status; 1896 jtag_log_comp *chip; 1897 u_char scan_in[32]; 1898 u_char scan_out[32]; 1899 u_char *p; 1900 u_int value; 1901 int bytes_used = 0; 1902 1903 if ((status = select_ring(jreg, ring, 1)) < 0) { 1904 return (status); 1905 } 1906 1907 chip = component->chip; 1908 1909 p = chip->fmt_desc; 1910 if (p == NULL) { 1911 return (bytes_used); 1912 } 1913 1914 status = jtag_rescan_IR_DR(jreg, component, chip->dump_code, scan_in, 1915 chip->dr_len, scan_out); 1916 1917 if (status < 0) { 1918 return (status); 1919 } 1920 1921 if ((status = select_ring(jreg, ring, 1)) < 0) { 1922 return (status); 1923 } 1924 1925 for (value = 0; ; ) { 1926 u_char cmd = *p++; 1927 1928 if ((cmd & JTSO_XTRACT) != 0) { 1929 u_int lsb, msb; 1930 lsb = *p++; 1931 msb = *p++; 1932 value |= jtag_bf_extract(scan_out, lsb, msb) << 1933 (cmd & JTSO_SHIFT); 1934 } 1935 1936 if ((cmd & JTSO_ST) != 0) { 1937 *result++ = value; 1938 bytes_used += 4; 1939 value = 0; 1940 } 1941 1942 if ((cmd & JTSO_END) != 0) { 1943 break; 1944 } 1945 } 1946 return (bytes_used); 1947 } 1948 1949 /* 1950 * Set the AC into hotplug mode upon insertion 1951 */ 1952 static int 1953 jtag_init_ac(volatile u_int *jreg, int bid, enum board_type brdtype) 1954 { 1955 int rc = JTAG_OK; 1956 int status; 1957 int ring = (bid << 4); 1958 ac_options ac_opt; 1959 u_char scan_out[64]; 1960 uint_t cs_value; 1961 1962 if (brdtype == UNKNOWN_BOARD) 1963 return (rc); 1964 1965 ac_opt.frozen = 0; /* 0 = frozen */ 1966 ac_opt.reset_a = 1; 1967 ac_opt.reset_b = 1; 1968 ac_opt.board_id = bid; 1969 ac_opt.mask_hwerr = (uint_t)-1; 1970 ac_opt.node_id = 3; 1971 1972 /* Get a good AC BCSR value from the board we are running on. */ 1973 cs_value = ldphysio(AC_BCSR(FHC_CPU2BOARD(CPU->cpu_id))); 1974 1975 ac_opt.arb_fast = (cs_value & AC_ARB_FAST) ? 1 : 0; 1976 ac_opt.pcr_hi = 0; 1977 ac_opt.pcr_lo = 0x80000000LL - 0x9ac4 - (bid << 3); 1978 ac_opt.pcc_ctl0 = 0x3f; 1979 ac_opt.pcc_ctl1 = 0x3f; 1980 ac_opt.pcc_tctrl = (1 << 11); /* TREN */ 1981 1982 if ((brdtype == CPU_BOARD) || (brdtype == MEM_BOARD)) { 1983 rc = jtag_init_chip(jreg, ring, &cpu_sysbd_ring_components[0], 1984 (jtag_opt)&ac_opt, scan_out); 1985 } else if (brdtype == IO_2SBUS_BOARD) { 1986 rc = jtag_init_chip(jreg, ring, &io1_sysbd_ring_components[0], 1987 (jtag_opt)&ac_opt, scan_out); 1988 } else if (brdtype == IO_2SBUS_SOCPLUS_BOARD) { 1989 rc = jtag_init_chip(jreg, ring, 1990 &io1plus_sysbd_ring_components[0], 1991 (jtag_opt)&ac_opt, scan_out); 1992 } else if (brdtype == IO_SBUS_FFB_BOARD) { 1993 rc = jtag_init_chip(jreg, ring, &io2_sysbd_ring_components[0], 1994 (jtag_opt)&ac_opt, scan_out); 1995 } else if (brdtype == IO_SBUS_FFB_SOCPLUS_BOARD) { 1996 rc = jtag_init_chip(jreg, ring, 1997 &io2plus_sysbd_ring_components[0], 1998 (jtag_opt)&ac_opt, scan_out); 1999 } else if (brdtype == IO_PCI_BOARD) { 2000 rc = jtag_init_chip(jreg, ring, &io3_sysbd_ring_components[0], 2001 (jtag_opt)&ac_opt, scan_out); 2002 } else { 2003 cmn_err(CE_NOTE, " jtag_init_ac() Board %d" 2004 " unsupported type %2X", bid, brdtype); 2005 } 2006 2007 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2008 2009 if (rc != JTAG_OK) { 2010 jtag_error_print(ring, rc); 2011 } 2012 2013 return (rc); 2014 } 2015 2016 #define EN_LOC_FATAL 0x02 2017 #define MOD_OFF 0x80 2018 #define ACDC_OFF 0x40 2019 #define EPDA_OFF 0x10 2020 #define EPDB_OFF 0x08 2021 #define NOT_BRD_PRESENT 0x02 2022 #define NOT_BRD_LED_LEFT 0x04 2023 #define BRD_LED_MID 0x02 2024 #define BRD_LED_RIGHT 0x01 2025 2026 /* 2027 * Each board has an FHC asic. 2028 */ 2029 int 2030 jtag_powerdown_board(volatile u_int *jreg, int board, enum board_type type, 2031 u_int *fhc_csr, u_int *fhc_bsr, int intr) 2032 { 2033 int rc = JTAG_OK; 2034 fhc_options fhc_opt; 2035 struct fhc_regs fhc_data; 2036 u_char scan_out[32]; 2037 int status; 2038 int ring; 2039 2040 if (type == UNKNOWN_BOARD) { 2041 sysc_cfga_stat_t asc; 2042 2043 bzero(&asc, sizeof (asc)); 2044 asc.board = board; 2045 type = jtag_get_board_type(jreg, &asc); 2046 } 2047 2048 if (!intr) 2049 (void) jtag_init_ac(jreg, board, type); 2050 2051 ring = board << 4; 2052 2053 fhc_opt.csr_hi = 0; 2054 fhc_opt.csr_mid = MOD_OFF | EPDA_OFF | EPDB_OFF | NOT_BRD_PRESENT; 2055 if (intr) { 2056 /* 2057 * by not setting NOT_BRD_PRESENT we can simulate a board 2058 * insertion 2059 */ 2060 fhc_opt.csr_mid &= ~NOT_BRD_PRESENT; 2061 } 2062 2063 fhc_opt.csr_midlo = NOT_BRD_LED_LEFT | BRD_LED_MID; 2064 2065 if ((type == CPU_BOARD) || (type == MEM_BOARD)) { 2066 rc = jtag_init_chip(jreg, ring, &cpu_sysbd_ring_components[9], 2067 (jtag_opt)&fhc_opt, scan_out); 2068 } else if (type == IO_2SBUS_BOARD) { 2069 rc = jtag_init_chip(jreg, ring, &io1_sysbd_ring_components[9], 2070 (jtag_opt)&fhc_opt, scan_out); 2071 } else if (type == IO_2SBUS_SOCPLUS_BOARD) { 2072 rc = jtag_init_chip(jreg, ring, 2073 &io1plus_sysbd_ring_components[9], 2074 (jtag_opt)&fhc_opt, scan_out); 2075 } else if (type == IO_SBUS_FFB_BOARD) { 2076 rc = jtag_init_chip(jreg, ring, &io2_sysbd_ring_components[9], 2077 (jtag_opt)&fhc_opt, scan_out); 2078 } else if (type == IO_SBUS_FFB_SOCPLUS_BOARD) { 2079 rc = jtag_init_chip(jreg, ring, 2080 &io2plus_sysbd_ring_components[9], 2081 (jtag_opt)&fhc_opt, scan_out); 2082 } else if (type == IO_PCI_BOARD) { 2083 rc = jtag_init_chip(jreg, ring, &io3_sysbd_ring_components[9], 2084 (jtag_opt)&fhc_opt, scan_out); 2085 } else if (type == UNKNOWN_BOARD) { 2086 rc = jtag_init_chip(jreg, ring, &cpu_sysbd_ring_components[9], 2087 (jtag_opt)&fhc_opt, scan_out); 2088 } else { 2089 cmn_err(CE_WARN, "Unsupported Board type %2X\n", 2090 fhc_bd_type(board)); 2091 } 2092 2093 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2094 2095 if (rc != JTAG_OK) { 2096 jtag_error_print(ring, rc); 2097 } 2098 2099 /* Reformat the FHC shadow chain scan data */ 2100 format_chip_data(chip_fhc.fmt_desc, (u_int *)&fhc_data, 2101 scan_out); 2102 2103 *fhc_csr = fhc_data.csr; 2104 *fhc_bsr = fhc_data.bsr; 2105 2106 2107 return (rc); 2108 } 2109 2110 /* 2111 * This function performs the fhc initialization for a disk board. The 2112 * hotplug variable tells the function whether to put the LED into low 2113 * power mode or not. 2114 */ 2115 int 2116 jtag_init_disk_board(volatile u_int *jreg, int board, 2117 u_int *fhc_csr, u_int *fhc_bsr) 2118 { 2119 int rc = JTAG_OK; 2120 fhc_options fhc_opt; 2121 struct fhc_regs fhc_data; 2122 u_char scan_out[32]; 2123 int status; 2124 int ring; 2125 2126 ring = board << 4; 2127 2128 fhc_opt.csr_hi = 0; 2129 fhc_opt.csr_mid = NOT_BRD_PRESENT; 2130 fhc_opt.csr_midlo = NOT_BRD_LED_LEFT | BRD_LED_MID; 2131 2132 rc = jtag_init_chip(jreg, ring, &dsk_sysbd_ring_components[1], 2133 (jtag_opt)&fhc_opt, scan_out); 2134 2135 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2136 2137 if (rc != JTAG_OK) { 2138 jtag_error_print(ring, rc); 2139 return (-1); 2140 } 2141 2142 /* Reformat the FHC shadow chain scan data */ 2143 format_chip_data(chip_fhc.fmt_desc, (u_int *)&fhc_data, 2144 scan_out); 2145 2146 *fhc_csr = fhc_data.csr; 2147 *fhc_bsr = fhc_data.bsr; 2148 2149 return (0); 2150 } 2151 2152 /* 2153 * NOTES: 2154 * 1. Scan data streams are little-endian sequences of bytes: byte 0 2155 * will provide the 8 lsb of the scan chain, and so on. If the last 2156 * byte is not full (count not a multiple of 8), the least significant 2157 * bits are used. 2158 * 2. All procedures assume that the JTAG control register 2159 * is non-busy on entry, and return with the control register 2160 * non-busy. It is a good idea to call tap_wait as part of the JTAG 2161 * sanity check sequence to verify there is no obvious malfunction. 2162 */ 2163 2164 2165 /* 2166 * Non-data TAP commands 2167 */ 2168 2169 /* 2170 * Wait for the TAP to be idle. 2171 * Return <0 if error, >=0 if OK. 2172 */ 2173 2174 int 2175 tap_wait(volatile u_int *jreg) 2176 { 2177 TAP_DECLARE; 2178 TAP_WAIT(jreg); 2179 return (JTAG_OK); 2180 } 2181 2182 /* 2183 * Send a TAP command, wait for completion. 2184 * Return <0 if error, >=0 if OK. 2185 */ 2186 2187 static int 2188 tap_issue_cmd(volatile u_int *jreg, u_int command) 2189 { 2190 TAP_DECLARE; 2191 2192 *jreg = command; 2193 TAP_WAIT(jreg); 2194 return (JTAG_OK); 2195 } 2196 2197 /* 2198 * Data TAP commands 2199 */ 2200 2201 /* 2202 * Shift 1 to 16 bits into the component. 2203 * Return <0 if error, the shifted out bits (always >=0) if OK. 2204 */ 2205 2206 int 2207 tap_shift_single(volatile u_int *jreg, int data, int nbits) 2208 { 2209 /* Return <0 if error, >0 (16-bit data) if OK */ 2210 TAP_DECLARE; 2211 TAP_SHIFT(jreg, data, nbits); 2212 return (jtag_data(jreg, nbits)); 2213 } 2214 2215 /* 2216 * Shift the required number of bits from in into the component, 2217 * retrieve the bits shifted out. 2218 * Return <0 if error, >=0 if OK. 2219 */ 2220 2221 int 2222 tap_shift_multiple( 2223 volatile u_int *jreg, 2224 u_char *data_in, 2225 int nbits, 2226 u_char *data_out) /* data_out may be NULL if not needed */ 2227 { 2228 TAP_DECLARE; 2229 2230 /* 2231 * The loop is done a byte at a time to avoid stepping out 2232 * of the caller's buffer 2233 */ 2234 for (; nbits > 0; nbits = nbits - 8) { 2235 int bits_this_pass = nbits > 8 ? 8 : nbits; 2236 TAP_SHIFT(jreg, *data_in++, bits_this_pass); 2237 if (data_out != NULL) { 2238 *data_out = jtag_data(jreg, bits_this_pass); 2239 data_out++; 2240 } 2241 } 2242 2243 return (JTAG_OK); 2244 } 2245 2246 /* 2247 * Shift the required number of bits of the specified 2248 * value into the selected register. Note that this routine makes 2249 * sense only for value = 0 and value = -1. 2250 * Return <0 if error, >=0 if OK. 2251 */ 2252 2253 static int 2254 tap_shift_constant(volatile u_int *jreg, int value, int nbits) 2255 { 2256 TAP_DECLARE; 2257 2258 TAP_WAIT(jreg); 2259 2260 /* 2261 * The loop is done a half-word at a time 2262 */ 2263 for (; nbits > 0; nbits = nbits - 16) { 2264 int bits_this_pass = nbits > 16 ? 16 : nbits; 2265 TAP_SHIFT(jreg, value, bits_this_pass); 2266 } 2267 2268 return (JTAG_OK); 2269 } 2270 2271 2272 /* 2273 * Ring-level commands 2274 */ 2275 2276 /* 2277 * Select the required ring. Reset it if required (reset != 0). 2278 * Return <0 if error, >=0 if OK. 2279 */ 2280 2281 static int 2282 select_ring(volatile u_int *jreg, jtag_ring ring, int reset) 2283 { 2284 int status; 2285 jtag_ring jring; 2286 2287 status = tap_wait(jreg); 2288 if (status < 0) { 2289 return (status); 2290 } 2291 2292 /* Translate a Physical Board number to a JTAG board number */ 2293 jring = ((u_int)(ring & 0x10) << 3) | ((u_int)(ring & 0xE0) >> 1) | 2294 (ring & 0xF); 2295 status = tap_issue_cmd(jreg, (jring << 16) | JTAG_SEL_RING); 2296 if (status < 0) { 2297 return (status); 2298 } 2299 2300 if (reset != 0) { 2301 status = tap_issue_cmd(jreg, JTAG_TAP_RESET); 2302 } 2303 2304 return (status); 2305 } 2306 2307 /* 2308 * Shift the specified instruction into the component, then 2309 * shift the required data in & retrieve the data out. 2310 * Return <0 if error, >=0 if OK. 2311 */ 2312 2313 static int 2314 jtag_single_IR_DR( 2315 volatile u_int *jreg, 2316 jtag_phys_comp *component, 2317 jtag_instruction instr, 2318 u_char *in, 2319 int nbits, 2320 u_char *out) 2321 { 2322 int status; 2323 2324 TAP_ISSUE_CMD(jreg, JTAG_SEL_IR, status); 2325 TAP_SHIFT_CONSTANT(jreg, -1, component->ir_after, status); 2326 TAP_SHIFT_SINGLE(jreg, instr, component->chip->ir_len, status); 2327 TAP_SHIFT_CONSTANT(jreg, -1, component->ir_before, status); 2328 TAP_ISSUE_CMD(jreg, JTAG_IR_TO_DR, status); 2329 TAP_SHIFT_CONSTANT(jreg, 0, component->by_after, status); 2330 TAP_SHIFT_MULTIPLE(jreg, in, nbits, out, status); 2331 TAP_SHIFT_CONSTANT(jreg, 0, component->by_before, status); 2332 TAP_ISSUE_CMD(jreg, JTAG_RUNIDLE, status); 2333 2334 return (status); 2335 } 2336 2337 /* 2338 * jtag_rescan_IR_DR() 2339 * 2340 * This function is used in order to rescan the DC ASICs when taking 2341 * them out of the frozen state. This is necessary because of a problem 2342 * when taking DCs out of the frozen state. Sometimes the operation must 2343 * be retryed. 2344 * 2345 * TODO - Eliminate the *in input parameter if able to. 2346 */ 2347 2348 /* ARGSUSED */ 2349 static int 2350 jtag_rescan_IR_DR( 2351 volatile u_int *jreg, 2352 jtag_phys_comp *component, 2353 jtag_instruction instr, 2354 u_char *in, 2355 int nbits, 2356 u_char *out) 2357 { 2358 int status, i; 2359 u_char tmp[32]; 2360 2361 for (i = 0; i < 32; i++) 2362 tmp[i] = 0; 2363 2364 TAP_ISSUE_CMD(jreg, JTAG_SEL_IR, status); 2365 TAP_SHIFT_CONSTANT(jreg, -1, component->ir_after, status); 2366 TAP_SHIFT_SINGLE(jreg, instr, component->chip->ir_len, status); 2367 TAP_SHIFT_CONSTANT(jreg, -1, component->ir_before, status); 2368 TAP_ISSUE_CMD(jreg, JTAG_IR_TO_DR, status); 2369 2370 /* scan the chip out */ 2371 TAP_SHIFT_CONSTANT(jreg, 0, component->by_after, status); 2372 TAP_SHIFT_MULTIPLE(jreg, tmp, nbits, out, status); 2373 TAP_SHIFT_CONSTANT(jreg, 0, component->by_before, status); 2374 2375 /* re scan the chip */ 2376 TAP_SHIFT_CONSTANT(jreg, 0, component->by_after, status); 2377 TAP_SHIFT_MULTIPLE(jreg, out, nbits, tmp, status); 2378 TAP_SHIFT_CONSTANT(jreg, 0, component->by_before, status); 2379 2380 TAP_ISSUE_CMD(jreg, JTAG_RUNIDLE, status); 2381 2382 return (status); 2383 } 2384 2385 /* 2386 * Return the number of components of the current ring, or <0 if failed 2387 */ 2388 static int 2389 jtag_ring_length(volatile u_int *jreg, jtag_ring ring) 2390 { 2391 int status, length; 2392 2393 /* 2394 * Reset the ring & check that there is a component 2395 * This is based on the fact that TAP reset forces the IDCODE, 2396 * or BYPASS (with 0 preloaded) if there is no ID 2397 */ 2398 2399 status = select_ring(jreg, ring, 1); 2400 if (status < 0) { 2401 cmn_err(CE_WARN, "select ring error jtag status %x\n", 2402 status); 2403 return (status); 2404 } 2405 2406 TAP_ISSUE_CMD(jreg, JTAG_SEL_DR, status); 2407 TAP_SHIFT_SINGLE(jreg, -1, 8, status); 2408 if (status == 0xFF) { 2409 return (RING_BROKEN); /* no CID detected */ 2410 } 2411 2412 /* 2413 * Put all components in BYPASS. This assumes the chain has 2414 * at most 32 components, and that each IR is at most 16-bits. 2415 * Note that the algorithm depends on the bypass FF to be cleared 2416 * on a tap reset! 2417 */ 2418 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2419 TAP_ISSUE_CMD(jreg, JTAG_SEL_IR, status); 2420 TAP_SHIFT_CONSTANT(jreg, -1, 32*16, status); 2421 TAP_ISSUE_CMD(jreg, JTAG_IR_TO_DR, status); 2422 TAP_SHIFT_CONSTANT(jreg, 0, 32, status); 2423 2424 for (length = 0; length <= 33; length++) { /* bit by bit */ 2425 TAP_SHIFT_SINGLE(jreg, -1, 1, status); 2426 2427 if (status != 0) { 2428 break; 2429 } 2430 } 2431 TAP_ISSUE_CMD(jreg, JTAG_RUNIDLE, status); 2432 /* more than 32 components ??? */ 2433 return ((length <= 32) ? length : RING_BROKEN); 2434 } 2435 2436 /* 2437 * Return the total number of instruction register bits in the 2438 * current ring, or < 0 if failed. 2439 */ 2440 int 2441 jtag_ring_ir_length(volatile u_int *jreg, jtag_ring ring) 2442 { 2443 int status, length; 2444 2445 /* 2446 * Reset the ring & check that there is a component 2447 * This is based on the fact that TAP reset forces the IDCODE, 2448 * or BYPASS (with 0 preloaded) if there is no ID 2449 */ 2450 status = select_ring(jreg, ring, 1); 2451 if (status < 0) { 2452 cmn_err(CE_WARN, "select error status %x", status); 2453 return (status); 2454 } 2455 2456 /* 2457 * Reset, Select IR, Shift in all 1's assuming the chain has 2458 * at most 32 components, and that each IR is at most 16-bits. 2459 * Then shift in 0's and count until a 0 comes out. 2460 * And cleanup by flushing with all 1's before reset or idle 2461 * --- FATAL's if you don't as you go through update-ir state 2462 */ 2463 TAP_ISSUE_CMD(jreg, JTAG_TAP_RESET, status); 2464 TAP_ISSUE_CMD(jreg, JTAG_SEL_IR, status); 2465 2466 /* 1 fill, look for 0 */ 2467 TAP_SHIFT_CONSTANT(jreg, -1, 32 * 16, status); 2468 for (length = 0; length <= 32 * 16; length++) { /* bit by bit */ 2469 TAP_SHIFT_SINGLE(jreg, 0, 1, status); 2470 if (status == 0) 2471 break; 2472 } 2473 2474 /* bypass should be safe */ 2475 TAP_SHIFT_CONSTANT(jreg, -1, 32 * 16, status); 2476 TAP_ISSUE_CMD(jreg, JTAG_RUNIDLE, status); 2477 /* more than 32*16 ir bits ??? */ 2478 return ((length <= 32 * 16) ? length : RING_BROKEN); 2479 } 2480 2481 /* 2482 * Format the jtag shadow scan data from scan_out bit string and store 2483 * in the array on u_ints. The datap represents the registers from 2484 * the chip under scan. 2485 * XXX - How to represent 64 bit registers here? 2486 */ 2487 static void 2488 format_chip_data(u_char *fmt, u_int *datap, u_char *scan_out) 2489 { 2490 u_int value; 2491 2492 for (value = 0; ; ) { 2493 u_char cmd = *fmt++; 2494 2495 if ((cmd & JTSO_XTRACT) != 0) { 2496 u_int lsb, msb; 2497 lsb = *fmt++; 2498 msb = *fmt++; 2499 value |= jtag_bf_extract(scan_out, lsb, msb) << 2500 (cmd & JTSO_SHIFT); 2501 } 2502 2503 if ((cmd & JTSO_ST) != 0) { 2504 *datap++ = value; 2505 value = 0; 2506 } 2507 2508 if ((cmd & JTSO_END) != 0) { 2509 break; 2510 } 2511 } 2512 } 2513