1*5d9d9091SRichard Lowe/* 2*5d9d9091SRichard Lowe * CDDL HEADER START 3*5d9d9091SRichard Lowe * 4*5d9d9091SRichard Lowe * The contents of this file are subject to the terms of the 5*5d9d9091SRichard Lowe * Common Development and Distribution License (the "License"). 6*5d9d9091SRichard Lowe * You may not use this file except in compliance with the License. 7*5d9d9091SRichard Lowe * 8*5d9d9091SRichard Lowe * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*5d9d9091SRichard Lowe * or http://www.opensolaris.org/os/licensing. 10*5d9d9091SRichard Lowe * See the License for the specific language governing permissions 11*5d9d9091SRichard Lowe * and limitations under the License. 12*5d9d9091SRichard Lowe * 13*5d9d9091SRichard Lowe * When distributing Covered Code, include this CDDL HEADER in each 14*5d9d9091SRichard Lowe * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*5d9d9091SRichard Lowe * If applicable, add the following below this CDDL HEADER, with the 16*5d9d9091SRichard Lowe * fields enclosed by brackets "[]" replaced with your own identifying 17*5d9d9091SRichard Lowe * information: Portions Copyright [yyyy] [name of copyright owner] 18*5d9d9091SRichard Lowe * 19*5d9d9091SRichard Lowe * CDDL HEADER END 20*5d9d9091SRichard Lowe */ 21*5d9d9091SRichard Lowe/* 22*5d9d9091SRichard Lowe * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23*5d9d9091SRichard Lowe * Use is subject to license terms. 24*5d9d9091SRichard Lowe */ 25*5d9d9091SRichard Lowe 26*5d9d9091SRichard Lowe/* 27*5d9d9091SRichard Lowe * General machine architecture & implementation specific 28*5d9d9091SRichard Lowe * assembly language routines. 29*5d9d9091SRichard Lowe */ 30*5d9d9091SRichard Lowe#include "assym.h" 31*5d9d9091SRichard Lowe 32*5d9d9091SRichard Lowe#include <sys/asm_linkage.h> 33*5d9d9091SRichard Lowe#include <sys/machsystm.h> 34*5d9d9091SRichard Lowe#include <sys/machthread.h> 35*5d9d9091SRichard Lowe#include <sys/privregs.h> 36*5d9d9091SRichard Lowe#include <sys/cmpregs.h> 37*5d9d9091SRichard Lowe#include <sys/clock.h> 38*5d9d9091SRichard Lowe#include <sys/fpras.h> 39*5d9d9091SRichard Lowe 40*5d9d9091SRichard Lowe/* 41*5d9d9091SRichard Lowe * This isn't the routine you're looking for. 42*5d9d9091SRichard Lowe * 43*5d9d9091SRichard Lowe * The routine simply returns the value of %tick on the *current* processor. 44*5d9d9091SRichard Lowe * Most of the time, gettick() [which in turn maps to %stick on platforms 45*5d9d9091SRichard Lowe * that have different CPU %tick rates] is what you want. 46*5d9d9091SRichard Lowe */ 47*5d9d9091SRichard Lowe 48*5d9d9091SRichard Lowe ENTRY(ultra_gettick) 49*5d9d9091SRichard Lowe retl 50*5d9d9091SRichard Lowe rdpr %tick, %o0 51*5d9d9091SRichard Lowe SET_SIZE(ultra_gettick) 52*5d9d9091SRichard Lowe 53*5d9d9091SRichard Lowe/* 54*5d9d9091SRichard Lowe * Get the processor ID. 55*5d9d9091SRichard Lowe * === MID reg as specified in 15dec89 sun4u spec, sec 5.4.3 56*5d9d9091SRichard Lowe */ 57*5d9d9091SRichard Lowe 58*5d9d9091SRichard Lowe ENTRY(getprocessorid) 59*5d9d9091SRichard Lowe CPU_INDEX(%o0, %o1) 60*5d9d9091SRichard Lowe retl 61*5d9d9091SRichard Lowe nop 62*5d9d9091SRichard Lowe SET_SIZE(getprocessorid) 63*5d9d9091SRichard Lowe 64*5d9d9091SRichard Lowe ENTRY(set_error_enable_tl1) 65*5d9d9091SRichard Lowe cmp %g2, EER_SET_ABSOLUTE 66*5d9d9091SRichard Lowe be %xcc, 1f 67*5d9d9091SRichard Lowe nop 68*5d9d9091SRichard Lowe ldxa [%g0]ASI_ESTATE_ERR, %g3 69*5d9d9091SRichard Lowe membar #Sync 70*5d9d9091SRichard Lowe cmp %g2, EER_SET_SETBITS 71*5d9d9091SRichard Lowe be,a %xcc, 1f 72*5d9d9091SRichard Lowe or %g3, %g1, %g1 73*5d9d9091SRichard Lowe andn %g3, %g1, %g1 /* EER_SET_CLRBITS */ 74*5d9d9091SRichard Lowe1: 75*5d9d9091SRichard Lowe stxa %g1, [%g0]ASI_ESTATE_ERR /* ecache error enable reg */ 76*5d9d9091SRichard Lowe membar #Sync 77*5d9d9091SRichard Lowe retry 78*5d9d9091SRichard Lowe SET_SIZE(set_error_enable_tl1) 79*5d9d9091SRichard Lowe 80*5d9d9091SRichard Lowe ENTRY(set_error_enable) 81*5d9d9091SRichard Lowe stxa %o0, [%g0]ASI_ESTATE_ERR /* ecache error enable reg */ 82*5d9d9091SRichard Lowe membar #Sync 83*5d9d9091SRichard Lowe retl 84*5d9d9091SRichard Lowe nop 85*5d9d9091SRichard Lowe SET_SIZE(set_error_enable) 86*5d9d9091SRichard Lowe 87*5d9d9091SRichard Lowe ENTRY(get_error_enable) 88*5d9d9091SRichard Lowe retl 89*5d9d9091SRichard Lowe ldxa [%g0]ASI_ESTATE_ERR, %o0 /* ecache error enable reg */ 90*5d9d9091SRichard Lowe SET_SIZE(get_error_enable) 91*5d9d9091SRichard Lowe 92*5d9d9091SRichard Lowe ENTRY(get_asyncflt) 93*5d9d9091SRichard Lowe ldxa [%g0]ASI_AFSR, %o1 ! afsr reg 94*5d9d9091SRichard Lowe retl 95*5d9d9091SRichard Lowe stx %o1, [%o0] 96*5d9d9091SRichard Lowe SET_SIZE(get_asyncflt) 97*5d9d9091SRichard Lowe 98*5d9d9091SRichard Lowe ENTRY(set_asyncflt) 99*5d9d9091SRichard Lowe stxa %o0, [%g0]ASI_AFSR ! afsr reg 100*5d9d9091SRichard Lowe membar #Sync 101*5d9d9091SRichard Lowe retl 102*5d9d9091SRichard Lowe nop 103*5d9d9091SRichard Lowe SET_SIZE(set_asyncflt) 104*5d9d9091SRichard Lowe 105*5d9d9091SRichard Lowe ENTRY(get_asyncaddr) 106*5d9d9091SRichard Lowe ldxa [%g0]ASI_AFAR, %o1 ! afar reg 107*5d9d9091SRichard Lowe retl 108*5d9d9091SRichard Lowe stx %o1, [%o0] 109*5d9d9091SRichard Lowe SET_SIZE(get_asyncaddr) 110*5d9d9091SRichard Lowe 111*5d9d9091SRichard Lowe ENTRY_NP(tick2ns) 112*5d9d9091SRichard Lowe sethi %hi(cpunodes), %o4 113*5d9d9091SRichard Lowe or %o4, %lo(cpunodes), %o4 ! %o4 = &cpunodes 114*5d9d9091SRichard Lowe ! Register usage: 115*5d9d9091SRichard Lowe ! 116*5d9d9091SRichard Lowe ! o0 = timestamp 117*5d9d9091SRichard Lowe ! o2 = byte offset into cpunodes for tick_nsec_scale of this CPU 118*5d9d9091SRichard Lowe ! o4 = &cpunodes 119*5d9d9091SRichard Lowe ! 120*5d9d9091SRichard Lowe mulx %o1, CPU_NODE_SIZE, %o2 ! %o2 = byte offset into cpunodes 121*5d9d9091SRichard Lowe add %o2, TICK_NSEC_SCALE, %o2 122*5d9d9091SRichard Lowe ld [%o4 + %o2], %o2 ! %o2 = cpunodes[cpuid].tick_nsec_scale 123*5d9d9091SRichard Lowe NATIVE_TIME_TO_NSEC_SCALE(%o0, %o2, %o3, TICK_NSEC_SHIFT) 124*5d9d9091SRichard Lowe retl 125*5d9d9091SRichard Lowe nop 126*5d9d9091SRichard Lowe SET_SIZE(tick2ns) 127*5d9d9091SRichard Lowe 128*5d9d9091SRichard Lowe ENTRY(set_cmp_error_steering) 129*5d9d9091SRichard Lowe membar #Sync 130*5d9d9091SRichard Lowe set ASI_CORE_ID, %o0 ! %o0 = ASI_CORE_ID 131*5d9d9091SRichard Lowe ldxa [%o0]ASI_CMP_PER_CORE, %o0 ! get ASI_CORE_ID 132*5d9d9091SRichard Lowe and %o0, COREID_MASK, %o0 133*5d9d9091SRichard Lowe set ASI_CMP_ERROR_STEERING, %o1 ! %o1 = ERROR_STEERING_REG 134*5d9d9091SRichard Lowe stxa %o0, [%o1]ASI_CMP_SHARED ! this core now hadles 135*5d9d9091SRichard Lowe membar #Sync ! non-core specific errors 136*5d9d9091SRichard Lowe retl 137*5d9d9091SRichard Lowe nop 138*5d9d9091SRichard Lowe SET_SIZE(set_cmp_error_steering) 139*5d9d9091SRichard Lowe 140*5d9d9091SRichard Lowe ENTRY(ultra_getver) 141*5d9d9091SRichard Lowe retl 142*5d9d9091SRichard Lowe rdpr %ver, %o0 143*5d9d9091SRichard Lowe SET_SIZE(ultra_getver) 144*5d9d9091SRichard Lowe 145*5d9d9091SRichard Lowe /* 146*5d9d9091SRichard Lowe * Check instructions using just the AX pipelines, designed by 147*5d9d9091SRichard Lowe * C.B. Liaw of PNP. 148*5d9d9091SRichard Lowe * 149*5d9d9091SRichard Lowe * This function must match a struct fpras_chkfn and must be 150*5d9d9091SRichard Lowe * block aligned. A zero return means all was well. These 151*5d9d9091SRichard Lowe * instructions are chosen to be sensitive to bit corruptions 152*5d9d9091SRichard Lowe * on the fpras rewrite, so if a bit corruption still produces 153*5d9d9091SRichard Lowe * a valid instruction we should still get an incorrect result 154*5d9d9091SRichard Lowe * here. This function is never called directly - it is copied 155*5d9d9091SRichard Lowe * into per-cpu and per-operation buffers; it must therefore 156*5d9d9091SRichard Lowe * be absolutely position independent. If an illegal instruction 157*5d9d9091SRichard Lowe * is encountered then the trap handler trampolines to the final 158*5d9d9091SRichard Lowe * three instructions of this function. 159*5d9d9091SRichard Lowe * 160*5d9d9091SRichard Lowe * We want two instructions that are complements of one another, 161*5d9d9091SRichard Lowe * and which can perform a calculation with a known result. 162*5d9d9091SRichard Lowe * 163*5d9d9091SRichard Lowe * SETHI: 164*5d9d9091SRichard Lowe * 165*5d9d9091SRichard Lowe * | 0 0 | rd | 1 0 0 | imm22 | 166*5d9d9091SRichard Lowe * 31 30 29 25 24 22 21 0 167*5d9d9091SRichard Lowe * 168*5d9d9091SRichard Lowe * ADDCCC with two source registers: 169*5d9d9091SRichard Lowe * 170*5d9d9091SRichard Lowe * | 1 0 | rd | 0 1 1 0 0 0 | rs1 | 0 | - | rs2 | 171*5d9d9091SRichard Lowe * 31 30 29 25 24 19 18 14 13 12 5 4 0 172*5d9d9091SRichard Lowe * 173*5d9d9091SRichard Lowe * We can choose rd and imm2 of the SETHI and rd, rs1 and rs2 of 174*5d9d9091SRichard Lowe * the ADDCCC to obtain instructions that are complements in all but 175*5d9d9091SRichard Lowe * bit 30. 176*5d9d9091SRichard Lowe * 177*5d9d9091SRichard Lowe * Registers are numbered as follows: 178*5d9d9091SRichard Lowe * 179*5d9d9091SRichard Lowe * r[31] %i7 180*5d9d9091SRichard Lowe * r[30] %i6 181*5d9d9091SRichard Lowe * r[29] %i5 182*5d9d9091SRichard Lowe * r[28] %i4 183*5d9d9091SRichard Lowe * r[27] %i3 184*5d9d9091SRichard Lowe * r[26] %i2 185*5d9d9091SRichard Lowe * r[25] %i1 186*5d9d9091SRichard Lowe * r[24] %i0 187*5d9d9091SRichard Lowe * r[23] %l7 188*5d9d9091SRichard Lowe * r[22] %l6 189*5d9d9091SRichard Lowe * r[21] %l5 190*5d9d9091SRichard Lowe * r[20] %l4 191*5d9d9091SRichard Lowe * r[19] %l3 192*5d9d9091SRichard Lowe * r[18] %l2 193*5d9d9091SRichard Lowe * r[17] %l1 194*5d9d9091SRichard Lowe * r[16] %l0 195*5d9d9091SRichard Lowe * r[15] %o7 196*5d9d9091SRichard Lowe * r[14] %o6 197*5d9d9091SRichard Lowe * r[13] %o5 198*5d9d9091SRichard Lowe * r[12] %o4 199*5d9d9091SRichard Lowe * r[11] %o3 200*5d9d9091SRichard Lowe * r[10] %o2 201*5d9d9091SRichard Lowe * r[9] %o1 202*5d9d9091SRichard Lowe * r[8] %o0 203*5d9d9091SRichard Lowe * r[7] %g7 204*5d9d9091SRichard Lowe * r[6] %g6 205*5d9d9091SRichard Lowe * r[5] %g5 206*5d9d9091SRichard Lowe * r[4] %g4 207*5d9d9091SRichard Lowe * r[3] %g3 208*5d9d9091SRichard Lowe * r[2] %g2 209*5d9d9091SRichard Lowe * r[1] %g1 210*5d9d9091SRichard Lowe * r[0] %g0 211*5d9d9091SRichard Lowe * 212*5d9d9091SRichard Lowe * For register r[n], register r[31-n] is the complement. We must 213*5d9d9091SRichard Lowe * avoid use of %i6/%i7 and %o6/%o7 as well as %g7. Clearly we need 214*5d9d9091SRichard Lowe * to use a local or input register as one half of the pair, which 215*5d9d9091SRichard Lowe * requires us to obtain our own register window or take steps 216*5d9d9091SRichard Lowe * to preserve any local or input we choose to use. We choose 217*5d9d9091SRichard Lowe * %o1 as rd for the SETHI, so rd of the ADDCCC must be %l6. 218*5d9d9091SRichard Lowe * We'll use %o1 as rs1 and %l6 as rs2 of the ADDCCC, which then 219*5d9d9091SRichard Lowe * requires that imm22 be 0b111 10110 1 11111111 01001 or 0x3dbfe9, 220*5d9d9091SRichard Lowe * or %hi(0xf6ffa400). This determines the value of the constant 221*5d9d9091SRichard Lowe * CBV2 below. 222*5d9d9091SRichard Lowe * 223*5d9d9091SRichard Lowe * The constant CBV1 is chosen such that an initial subcc %g0, CBV1 224*5d9d9091SRichard Lowe * will set the carry bit and every addccc thereafter will continue 225*5d9d9091SRichard Lowe * to generate a carry. Other values are possible for CBV1 - this 226*5d9d9091SRichard Lowe * is just one that works this way. 227*5d9d9091SRichard Lowe * 228*5d9d9091SRichard Lowe * Finally CBV3 is the expected answer when we perform our repeated 229*5d9d9091SRichard Lowe * calculations on CBV1 and CBV2 - it is not otherwise specially 230*5d9d9091SRichard Lowe * derived. If this result is not obtained then a corruption has 231*5d9d9091SRichard Lowe * occured during the FPRAS_REWRITE of one of the two blocks of 232*5d9d9091SRichard Lowe * 16 instructions. A corruption could also result in an illegal 233*5d9d9091SRichard Lowe * instruction or other unexpected trap - we catch illegal 234*5d9d9091SRichard Lowe * instruction traps in the PC range and trampoline to the 235*5d9d9091SRichard Lowe * last instructions of the function to return a failure indication. 236*5d9d9091SRichard Lowe * 237*5d9d9091SRichard Lowe */ 238*5d9d9091SRichard Lowe 239*5d9d9091SRichard Lowe#define CBV1 0xc11 240*5d9d9091SRichard Lowe#define CBV2 0xf6ffa400 241*5d9d9091SRichard Lowe#define CBV3 0x66f9d800 242*5d9d9091SRichard Lowe#define CBR1 %o1 243*5d9d9091SRichard Lowe#define CBR2 %l6 244*5d9d9091SRichard Lowe#define CBO2 %o2 245*5d9d9091SRichard Lowe#define SETHI_CBV2_CBR1 sethi %hi(CBV2), CBR1 246*5d9d9091SRichard Lowe#define ADDCCC_CBR1_CBR2_CBR2 addccc CBR1, CBR2, CBR2 247*5d9d9091SRichard Lowe 248*5d9d9091SRichard Lowe .align 64 249*5d9d9091SRichard Lowe ENTRY_NP(fpras_chkfn_type1) 250*5d9d9091SRichard Lowe mov CBR2, CBO2 ! 1, preserve CBR2 of (callers) window 251*5d9d9091SRichard Lowe mov FPRAS_OK, %o0 ! 2, default return value 252*5d9d9091SRichard Lowe ba,pt %icc, 1f ! 3 253*5d9d9091SRichard Lowe subcc %g0, CBV1, CBR2 ! 4 254*5d9d9091SRichard Lowe ! 5 - 16 255*5d9d9091SRichard Lowe .align 64 256*5d9d9091SRichard Lowe1: SETHI_CBV2_CBR1 ! 1 257*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 2 258*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 3 259*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 4 260*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 5 261*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 6 262*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 7 263*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 8 264*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 9 265*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 10 266*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 11 267*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 12 268*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 13 269*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 14 270*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 15 271*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 16 272*5d9d9091SRichard Lowe 273*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 1 274*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 2 275*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 3 276*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 4 277*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 5 278*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 6 279*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 7 280*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 8 281*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 9 282*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 10 283*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 11 284*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 12 285*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 13 286*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 14 287*5d9d9091SRichard Lowe ADDCCC_CBR1_CBR2_CBR2 ! 15 288*5d9d9091SRichard Lowe SETHI_CBV2_CBR1 ! 16 289*5d9d9091SRichard Lowe 290*5d9d9091SRichard Lowe addc CBR1, CBR2, CBR2 ! 1 291*5d9d9091SRichard Lowe sethi %hi(CBV3), CBR1 ! 2 292*5d9d9091SRichard Lowe cmp CBR1, CBR2 ! 3 293*5d9d9091SRichard Lowe movnz %icc, FPRAS_BADCALC, %o0! 4, how detected 294*5d9d9091SRichard Lowe retl ! 5 295*5d9d9091SRichard Lowe mov CBO2, CBR2 ! 6, restore borrowed register 296*5d9d9091SRichard Lowe .skip 4*(13-7+1) ! 7 - 13 297*5d9d9091SRichard Lowe ! 298*5d9d9091SRichard Lowe ! illegal instr'n trap comes here 299*5d9d9091SRichard Lowe ! 300*5d9d9091SRichard Lowe mov CBO2, CBR2 ! 14, restore borrowed register 301*5d9d9091SRichard Lowe retl ! 15 302*5d9d9091SRichard Lowe mov FPRAS_BADTRAP, %o0 ! 16, how detected 303*5d9d9091SRichard Lowe SET_SIZE(fpras_chkfn_type1) 304*5d9d9091SRichard Lowe 305*5d9d9091SRichard Lowe/* 306*5d9d9091SRichard Lowe * fp_zero() - clear all fp data registers and the fsr 307*5d9d9091SRichard Lowe */ 308*5d9d9091SRichard Lowe 309*5d9d9091SRichard Lowe ENTRY_NP(fp_zero) 310*5d9d9091SRichard Lowe std %g0, [%sp + ARGPUSH + STACK_BIAS] 311*5d9d9091SRichard Lowe fzero %f0 312*5d9d9091SRichard Lowe fzero %f2 313*5d9d9091SRichard Lowe ldd [%sp + ARGPUSH + STACK_BIAS], %fsr 314*5d9d9091SRichard Lowe faddd %f0, %f2, %f4 315*5d9d9091SRichard Lowe fmuld %f0, %f2, %f6 316*5d9d9091SRichard Lowe faddd %f0, %f2, %f8 317*5d9d9091SRichard Lowe fmuld %f0, %f2, %f10 318*5d9d9091SRichard Lowe faddd %f0, %f2, %f12 319*5d9d9091SRichard Lowe fmuld %f0, %f2, %f14 320*5d9d9091SRichard Lowe faddd %f0, %f2, %f16 321*5d9d9091SRichard Lowe fmuld %f0, %f2, %f18 322*5d9d9091SRichard Lowe faddd %f0, %f2, %f20 323*5d9d9091SRichard Lowe fmuld %f0, %f2, %f22 324*5d9d9091SRichard Lowe faddd %f0, %f2, %f24 325*5d9d9091SRichard Lowe fmuld %f0, %f2, %f26 326*5d9d9091SRichard Lowe faddd %f0, %f2, %f28 327*5d9d9091SRichard Lowe fmuld %f0, %f2, %f30 328*5d9d9091SRichard Lowe faddd %f0, %f2, %f32 329*5d9d9091SRichard Lowe fmuld %f0, %f2, %f34 330*5d9d9091SRichard Lowe faddd %f0, %f2, %f36 331*5d9d9091SRichard Lowe fmuld %f0, %f2, %f38 332*5d9d9091SRichard Lowe faddd %f0, %f2, %f40 333*5d9d9091SRichard Lowe fmuld %f0, %f2, %f42 334*5d9d9091SRichard Lowe faddd %f0, %f2, %f44 335*5d9d9091SRichard Lowe fmuld %f0, %f2, %f46 336*5d9d9091SRichard Lowe faddd %f0, %f2, %f48 337*5d9d9091SRichard Lowe fmuld %f0, %f2, %f50 338*5d9d9091SRichard Lowe faddd %f0, %f2, %f52 339*5d9d9091SRichard Lowe fmuld %f0, %f2, %f54 340*5d9d9091SRichard Lowe faddd %f0, %f2, %f56 341*5d9d9091SRichard Lowe fmuld %f0, %f2, %f58 342*5d9d9091SRichard Lowe faddd %f0, %f2, %f60 343*5d9d9091SRichard Lowe retl 344*5d9d9091SRichard Lowe fmuld %f0, %f2, %f62 345*5d9d9091SRichard Lowe SET_SIZE(fp_zero) 346*5d9d9091SRichard Lowe 347