1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/kmem.h> 30 #include <sys/conf.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/fm/protocol.h> 34 #include <sys/fm/util.h> 35 #include <sys/modctl.h> 36 #include <sys/disp.h> 37 #include <sys/stat.h> 38 #include <sys/ddi_impldefs.h> 39 #include <sys/vmem.h> 40 #include <sys/iommutsb.h> 41 #include <sys/cpuvar.h> 42 #include <sys/ivintr.h> 43 #include <sys/byteorder.h> 44 #include <sys/hotplug/pci/pciehpc.h> 45 #include <px_obj.h> 46 #include <pcie_pwr.h> 47 #include "px_tools_var.h" 48 #include <px_regs.h> 49 #include <px_csr.h> 50 #include <sys/machsystm.h> 51 #include "px_lib4u.h" 52 #include "px_err.h" 53 #include "oberon_regs.h" 54 55 #pragma weak jbus_stst_order 56 57 extern void jbus_stst_order(); 58 59 ulong_t px_mmu_dvma_end = 0xfffffffful; 60 uint_t px_ranges_phi_mask = 0xfffffffful; 61 uint64_t *px_oberon_ubc_scratch_regs; 62 uint64_t px_paddr_mask; 63 64 static int px_goto_l23ready(px_t *px_p); 65 static int px_goto_l0(px_t *px_p); 66 static int px_pre_pwron_check(px_t *px_p); 67 static uint32_t px_identity_init(px_t *px_p); 68 static boolean_t px_cpr_callb(void *arg, int code); 69 static uint_t px_cb_intr(caddr_t arg); 70 71 /* 72 * px_lib_map_registers 73 * 74 * This function is called from the attach routine to map the registers 75 * accessed by this driver. 76 * 77 * used by: px_attach() 78 * 79 * return value: DDI_FAILURE on failure 80 */ 81 int 82 px_lib_map_regs(pxu_t *pxu_p, dev_info_t *dip) 83 { 84 ddi_device_acc_attr_t attr; 85 px_reg_bank_t reg_bank = PX_REG_CSR; 86 87 DBG(DBG_ATTACH, dip, "px_lib_map_regs: pxu_p:0x%p, dip 0x%p\n", 88 pxu_p, dip); 89 90 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 91 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 92 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 93 94 /* 95 * PCI CSR Base 96 */ 97 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], 98 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { 99 goto fail; 100 } 101 102 reg_bank++; 103 104 /* 105 * XBUS CSR Base 106 */ 107 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], 108 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { 109 goto fail; 110 } 111 112 pxu_p->px_address[reg_bank] -= FIRE_CONTROL_STATUS; 113 114 done: 115 for (; reg_bank >= PX_REG_CSR; reg_bank--) { 116 DBG(DBG_ATTACH, dip, "reg_bank 0x%x address 0x%p\n", 117 reg_bank, pxu_p->px_address[reg_bank]); 118 } 119 120 return (DDI_SUCCESS); 121 122 fail: 123 cmn_err(CE_WARN, "%s%d: unable to map reg entry %d\n", 124 ddi_driver_name(dip), ddi_get_instance(dip), reg_bank); 125 126 for (reg_bank--; reg_bank >= PX_REG_CSR; reg_bank--) { 127 pxu_p->px_address[reg_bank] = NULL; 128 ddi_regs_map_free(&pxu_p->px_ac[reg_bank]); 129 } 130 131 return (DDI_FAILURE); 132 } 133 134 /* 135 * px_lib_unmap_regs: 136 * 137 * This routine unmaps the registers mapped by map_px_registers. 138 * 139 * used by: px_detach(), and error conditions in px_attach() 140 * 141 * return value: none 142 */ 143 void 144 px_lib_unmap_regs(pxu_t *pxu_p) 145 { 146 int i; 147 148 for (i = 0; i < PX_REG_MAX; i++) { 149 if (pxu_p->px_ac[i]) 150 ddi_regs_map_free(&pxu_p->px_ac[i]); 151 } 152 } 153 154 int 155 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 156 { 157 158 caddr_t xbc_csr_base, csr_base; 159 px_dvma_range_prop_t px_dvma_range; 160 pxu_t *pxu_p; 161 uint8_t chip_mask; 162 px_t *px_p = DIP_TO_STATE(dip); 163 px_chip_type_t chip_type = px_identity_init(px_p); 164 165 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p", dip); 166 167 if (chip_type == PX_CHIP_UNIDENTIFIED) { 168 cmn_err(CE_WARN, "%s%d: Unrecognized Hardware Version\n", 169 NAMEINST(dip)); 170 return (DDI_FAILURE); 171 } 172 173 chip_mask = BITMASK(chip_type); 174 px_paddr_mask = (chip_type == PX_CHIP_FIRE) ? MMU_FIRE_PADDR_MASK : 175 MMU_OBERON_PADDR_MASK; 176 177 /* 178 * Allocate platform specific structure and link it to 179 * the px state structure. 180 */ 181 pxu_p = kmem_zalloc(sizeof (pxu_t), KM_SLEEP); 182 pxu_p->chip_type = chip_type; 183 pxu_p->portid = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 184 "portid", -1); 185 186 /* Map in the registers */ 187 if (px_lib_map_regs(pxu_p, dip) == DDI_FAILURE) { 188 kmem_free(pxu_p, sizeof (pxu_t)); 189 190 return (DDI_FAILURE); 191 } 192 193 xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 194 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 195 196 pxu_p->tsb_cookie = iommu_tsb_alloc(pxu_p->portid); 197 pxu_p->tsb_size = iommu_tsb_cookie_to_size(pxu_p->tsb_cookie); 198 pxu_p->tsb_vaddr = iommu_tsb_cookie_to_va(pxu_p->tsb_cookie); 199 200 pxu_p->tsb_paddr = va_to_pa(pxu_p->tsb_vaddr); 201 202 /* 203 * Create "virtual-dma" property to support child devices 204 * needing to know DVMA range. 205 */ 206 px_dvma_range.dvma_base = (uint32_t)px_mmu_dvma_end + 1 207 - ((pxu_p->tsb_size >> 3) << MMU_PAGE_SHIFT); 208 px_dvma_range.dvma_len = (uint32_t) 209 px_mmu_dvma_end - px_dvma_range.dvma_base + 1; 210 211 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 212 "virtual-dma", (caddr_t)&px_dvma_range, 213 sizeof (px_dvma_range_prop_t)); 214 /* 215 * Initilize all fire hardware specific blocks. 216 */ 217 hvio_cb_init(xbc_csr_base, pxu_p); 218 hvio_ib_init(csr_base, pxu_p); 219 hvio_pec_init(csr_base, pxu_p); 220 hvio_mmu_init(csr_base, pxu_p); 221 222 px_p->px_plat_p = (void *)pxu_p; 223 224 /* 225 * Initialize all the interrupt handlers 226 */ 227 switch (PX_CHIP_TYPE(pxu_p)) { 228 case PX_CHIP_OBERON: 229 /* 230 * Oberon hotplug uses SPARE3 field in ILU Error Log Enable 231 * register to indicate the status of leaf reset, 232 * we need to preserve the value of this bit, and keep it in 233 * px_ilu_log_mask to reflect the state of the bit 234 */ 235 if (CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3)) 236 px_ilu_log_mask |= (1ull << 237 ILU_ERROR_LOG_ENABLE_SPARE3); 238 else 239 px_ilu_log_mask &= ~(1ull << 240 ILU_ERROR_LOG_ENABLE_SPARE3); 241 242 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 243 px_fabric_die_rc_ue |= PCIE_AER_UCE_UC; 244 break; 245 246 case PX_CHIP_FIRE: 247 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 248 break; 249 250 default: 251 cmn_err(CE_WARN, "%s%d: PX primary bus Unknown\n", 252 ddi_driver_name(dip), ddi_get_instance(dip)); 253 return (DDI_FAILURE); 254 } 255 256 /* Initilize device handle */ 257 *dev_hdl = (devhandle_t)csr_base; 258 259 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 260 261 return (DDI_SUCCESS); 262 } 263 264 int 265 px_lib_dev_fini(dev_info_t *dip) 266 { 267 caddr_t csr_base; 268 uint8_t chip_mask; 269 px_t *px_p = DIP_TO_STATE(dip); 270 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 271 272 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 273 274 /* 275 * Deinitialize all the interrupt handlers 276 */ 277 switch (PX_CHIP_TYPE(pxu_p)) { 278 case PX_CHIP_OBERON: 279 case PX_CHIP_FIRE: 280 chip_mask = BITMASK(PX_CHIP_TYPE(pxu_p)); 281 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 282 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_DISABLE); 283 break; 284 285 default: 286 cmn_err(CE_WARN, "%s%d: PX primary bus Unknown\n", 287 ddi_driver_name(dip), ddi_get_instance(dip)); 288 return (DDI_FAILURE); 289 } 290 291 iommu_tsb_free(pxu_p->tsb_cookie); 292 293 px_lib_unmap_regs((pxu_t *)px_p->px_plat_p); 294 kmem_free(px_p->px_plat_p, sizeof (pxu_t)); 295 px_p->px_plat_p = NULL; 296 297 return (DDI_SUCCESS); 298 } 299 300 /*ARGSUSED*/ 301 int 302 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 303 sysino_t *sysino) 304 { 305 px_t *px_p = DIP_TO_STATE(dip); 306 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 307 uint64_t ret; 308 309 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 310 "devino 0x%x\n", dip, devino); 311 312 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 313 pxu_p, devino, sysino)) != H_EOK) { 314 DBG(DBG_LIB_INT, dip, 315 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 316 return (DDI_FAILURE); 317 } 318 319 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 320 *sysino); 321 322 return (DDI_SUCCESS); 323 } 324 325 /*ARGSUSED*/ 326 int 327 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 328 intr_valid_state_t *intr_valid_state) 329 { 330 uint64_t ret; 331 332 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 333 dip, sysino); 334 335 if ((ret = hvio_intr_getvalid(DIP_TO_HANDLE(dip), 336 sysino, intr_valid_state)) != H_EOK) { 337 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 338 ret); 339 return (DDI_FAILURE); 340 } 341 342 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 343 *intr_valid_state); 344 345 return (DDI_SUCCESS); 346 } 347 348 /*ARGSUSED*/ 349 int 350 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 351 intr_valid_state_t intr_valid_state) 352 { 353 uint64_t ret; 354 355 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 356 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 357 358 if ((ret = hvio_intr_setvalid(DIP_TO_HANDLE(dip), 359 sysino, intr_valid_state)) != H_EOK) { 360 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 361 ret); 362 return (DDI_FAILURE); 363 } 364 365 return (DDI_SUCCESS); 366 } 367 368 /*ARGSUSED*/ 369 int 370 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 371 intr_state_t *intr_state) 372 { 373 uint64_t ret; 374 375 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 376 dip, sysino); 377 378 if ((ret = hvio_intr_getstate(DIP_TO_HANDLE(dip), 379 sysino, intr_state)) != H_EOK) { 380 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 381 ret); 382 return (DDI_FAILURE); 383 } 384 385 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 386 *intr_state); 387 388 return (DDI_SUCCESS); 389 } 390 391 /*ARGSUSED*/ 392 int 393 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 394 intr_state_t intr_state) 395 { 396 uint64_t ret; 397 398 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 399 "intr_state 0x%x\n", dip, sysino, intr_state); 400 401 if ((ret = hvio_intr_setstate(DIP_TO_HANDLE(dip), 402 sysino, intr_state)) != H_EOK) { 403 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 404 ret); 405 return (DDI_FAILURE); 406 } 407 408 return (DDI_SUCCESS); 409 } 410 411 /*ARGSUSED*/ 412 int 413 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 414 { 415 px_t *px_p = DIP_TO_STATE(dip); 416 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 417 uint64_t ret; 418 419 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 420 dip, sysino); 421 422 if ((ret = hvio_intr_gettarget(DIP_TO_HANDLE(dip), pxu_p, 423 sysino, cpuid)) != H_EOK) { 424 DBG(DBG_LIB_INT, dip, "hvio_intr_gettarget failed, ret 0x%lx\n", 425 ret); 426 return (DDI_FAILURE); 427 } 428 429 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 430 431 return (DDI_SUCCESS); 432 } 433 434 /*ARGSUSED*/ 435 int 436 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 437 { 438 px_t *px_p = DIP_TO_STATE(dip); 439 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 440 uint64_t ret; 441 442 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 443 "cpuid 0x%x\n", dip, sysino, cpuid); 444 445 if ((ret = hvio_intr_settarget(DIP_TO_HANDLE(dip), pxu_p, 446 sysino, cpuid)) != H_EOK) { 447 DBG(DBG_LIB_INT, dip, "hvio_intr_settarget failed, ret 0x%lx\n", 448 ret); 449 return (DDI_FAILURE); 450 } 451 452 return (DDI_SUCCESS); 453 } 454 455 /*ARGSUSED*/ 456 int 457 px_lib_intr_reset(dev_info_t *dip) 458 { 459 devino_t ino; 460 sysino_t sysino; 461 462 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 463 464 /* Reset all Interrupts */ 465 for (ino = 0; ino < INTERRUPT_MAPPING_ENTRIES; ino++) { 466 if (px_lib_intr_devino_to_sysino(dip, ino, 467 &sysino) != DDI_SUCCESS) 468 return (BF_FATAL); 469 470 if (px_lib_intr_setstate(dip, sysino, 471 INTR_IDLE_STATE) != DDI_SUCCESS) 472 return (BF_FATAL); 473 } 474 475 return (BF_NONE); 476 } 477 478 /*ARGSUSED*/ 479 int 480 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 481 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 482 { 483 px_t *px_p = DIP_TO_STATE(dip); 484 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 485 uint64_t ret; 486 487 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 488 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 489 dip, tsbid, pages, attr, addr, pfn_index, flags); 490 491 if ((ret = hvio_iommu_map(px_p->px_dev_hdl, pxu_p, tsbid, pages, 492 attr, addr, pfn_index, flags)) != H_EOK) { 493 DBG(DBG_LIB_DMA, dip, 494 "px_lib_iommu_map failed, ret 0x%lx\n", ret); 495 return (DDI_FAILURE); 496 } 497 498 return (DDI_SUCCESS); 499 } 500 501 /*ARGSUSED*/ 502 int 503 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 504 { 505 px_t *px_p = DIP_TO_STATE(dip); 506 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 507 uint64_t ret; 508 509 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 510 "pages 0x%x\n", dip, tsbid, pages); 511 512 if ((ret = hvio_iommu_demap(px_p->px_dev_hdl, pxu_p, tsbid, pages)) 513 != H_EOK) { 514 DBG(DBG_LIB_DMA, dip, 515 "px_lib_iommu_demap failed, ret 0x%lx\n", ret); 516 517 return (DDI_FAILURE); 518 } 519 520 return (DDI_SUCCESS); 521 } 522 523 /*ARGSUSED*/ 524 int 525 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 526 r_addr_t *r_addr_p) 527 { 528 px_t *px_p = DIP_TO_STATE(dip); 529 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 530 uint64_t ret; 531 532 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 533 dip, tsbid); 534 535 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), pxu_p, tsbid, 536 attr_p, r_addr_p)) != H_EOK) { 537 DBG(DBG_LIB_DMA, dip, 538 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 539 540 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 541 } 542 543 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 544 *attr_p, *r_addr_p); 545 546 return (DDI_SUCCESS); 547 } 548 549 550 /* 551 * Checks dma attributes against system bypass ranges 552 * The bypass range is determined by the hardware. Return them so the 553 * common code can do generic checking against them. 554 */ 555 /*ARGSUSED*/ 556 int 557 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 558 uint64_t *lo_p, uint64_t *hi_p) 559 { 560 px_t *px_p = DIP_TO_STATE(dip); 561 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 562 563 *lo_p = hvio_get_bypass_base(pxu_p); 564 *hi_p = hvio_get_bypass_end(pxu_p); 565 566 return (DDI_SUCCESS); 567 } 568 569 570 /*ARGSUSED*/ 571 int 572 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 573 io_addr_t *io_addr_p) 574 { 575 uint64_t ret; 576 px_t *px_p = DIP_TO_STATE(dip); 577 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 578 579 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 580 "attr 0x%x\n", dip, ra, attr); 581 582 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), pxu_p, ra, 583 attr, io_addr_p)) != H_EOK) { 584 DBG(DBG_LIB_DMA, dip, 585 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 586 return (DDI_FAILURE); 587 } 588 589 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 590 *io_addr_p); 591 592 return (DDI_SUCCESS); 593 } 594 595 /* 596 * bus dma sync entry point. 597 */ 598 /*ARGSUSED*/ 599 int 600 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 601 off_t off, size_t len, uint_t cache_flags) 602 { 603 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 604 px_t *px_p = DIP_TO_STATE(dip); 605 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 606 607 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 608 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 609 dip, rdip, handle, off, len, cache_flags); 610 611 /* 612 * No flush needed for Oberon 613 */ 614 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 615 return (DDI_SUCCESS); 616 617 /* 618 * jbus_stst_order is found only in certain cpu modules. 619 * Just return success if not present. 620 */ 621 if (&jbus_stst_order == NULL) 622 return (DDI_SUCCESS); 623 624 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 625 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 626 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 627 628 return (DDI_FAILURE); 629 } 630 631 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 632 return (DDI_SUCCESS); 633 634 /* 635 * No flush needed when sending data from memory to device. 636 * Nothing to do to "sync" memory to what device would already see. 637 */ 638 if (!(mp->dmai_rflags & DDI_DMA_READ) || 639 ((cache_flags & PX_DMA_SYNC_DDI_FLAGS) == DDI_DMA_SYNC_FORDEV)) 640 return (DDI_SUCCESS); 641 642 /* 643 * Perform necessary cpu workaround to ensure jbus ordering. 644 * CPU's internal "invalidate FIFOs" are flushed. 645 */ 646 647 #if !defined(lint) 648 kpreempt_disable(); 649 #endif 650 jbus_stst_order(); 651 #if !defined(lint) 652 kpreempt_enable(); 653 #endif 654 return (DDI_SUCCESS); 655 } 656 657 /* 658 * MSIQ Functions: 659 */ 660 /*ARGSUSED*/ 661 int 662 px_lib_msiq_init(dev_info_t *dip) 663 { 664 px_t *px_p = DIP_TO_STATE(dip); 665 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 666 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 667 caddr_t msiq_addr; 668 px_dvma_addr_t pg_index; 669 size_t size; 670 int ret; 671 672 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 673 674 /* 675 * Map the EQ memory into the Fire MMU (has to be 512KB aligned) 676 * and then initialize the base address register. 677 * 678 * Allocate entries from Fire IOMMU so that the resulting address 679 * is properly aligned. Calculate the index of the first allocated 680 * entry. Note: The size of the mapping is assumed to be a multiple 681 * of the page size. 682 */ 683 msiq_addr = (caddr_t)(((uint64_t)msiq_state_p->msiq_buf_p + 684 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 685 686 size = msiq_state_p->msiq_cnt * 687 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 688 689 pxu_p->msiq_mapped_p = vmem_xalloc(px_p->px_mmu_p->mmu_dvma_map, 690 size, (512 * 1024), 0, 0, NULL, NULL, VM_NOSLEEP | VM_BESTFIT); 691 692 if (pxu_p->msiq_mapped_p == NULL) 693 return (DDI_FAILURE); 694 695 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 696 MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 697 698 if ((ret = px_lib_iommu_map(px_p->px_dip, PCI_TSBID(0, pg_index), 699 MMU_BTOP(size), PCI_MAP_ATTR_WRITE, (void *)msiq_addr, 0, 700 MMU_MAP_BUF)) != DDI_SUCCESS) { 701 DBG(DBG_LIB_MSIQ, dip, 702 "hvio_msiq_init failed, ret 0x%lx\n", ret); 703 704 (void) px_lib_msiq_fini(dip); 705 return (DDI_FAILURE); 706 } 707 708 (void) hvio_msiq_init(DIP_TO_HANDLE(dip), pxu_p); 709 710 return (DDI_SUCCESS); 711 } 712 713 /*ARGSUSED*/ 714 int 715 px_lib_msiq_fini(dev_info_t *dip) 716 { 717 px_t *px_p = DIP_TO_STATE(dip); 718 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 719 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 720 px_dvma_addr_t pg_index; 721 size_t size; 722 723 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 724 725 /* 726 * Unmap and free the EQ memory that had been mapped 727 * into the Fire IOMMU. 728 */ 729 size = msiq_state_p->msiq_cnt * 730 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 731 732 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 733 MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 734 735 (void) px_lib_iommu_demap(px_p->px_dip, 736 PCI_TSBID(0, pg_index), MMU_BTOP(size)); 737 738 /* Free the entries from the Fire MMU */ 739 vmem_xfree(px_p->px_mmu_p->mmu_dvma_map, 740 (void *)pxu_p->msiq_mapped_p, size); 741 742 return (DDI_SUCCESS); 743 } 744 745 /*ARGSUSED*/ 746 int 747 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 748 uint_t *msiq_rec_cnt_p) 749 { 750 px_t *px_p = DIP_TO_STATE(dip); 751 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 752 uint64_t *msiq_addr; 753 size_t msiq_size; 754 755 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 756 dip, msiq_id); 757 758 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 759 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 760 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 761 ra_p = (r_addr_t *)((caddr_t)msiq_addr + (msiq_id * msiq_size)); 762 763 *msiq_rec_cnt_p = msiq_state_p->msiq_rec_cnt; 764 765 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 766 ra_p, *msiq_rec_cnt_p); 767 768 return (DDI_SUCCESS); 769 } 770 771 /*ARGSUSED*/ 772 int 773 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 774 pci_msiq_valid_state_t *msiq_valid_state) 775 { 776 uint64_t ret; 777 778 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 779 dip, msiq_id); 780 781 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 782 msiq_id, msiq_valid_state)) != H_EOK) { 783 DBG(DBG_LIB_MSIQ, dip, 784 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 785 return (DDI_FAILURE); 786 } 787 788 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 789 *msiq_valid_state); 790 791 return (DDI_SUCCESS); 792 } 793 794 /*ARGSUSED*/ 795 int 796 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 797 pci_msiq_valid_state_t msiq_valid_state) 798 { 799 uint64_t ret; 800 801 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 802 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 803 804 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 805 msiq_id, msiq_valid_state)) != H_EOK) { 806 DBG(DBG_LIB_MSIQ, dip, 807 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 808 return (DDI_FAILURE); 809 } 810 811 return (DDI_SUCCESS); 812 } 813 814 /*ARGSUSED*/ 815 int 816 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 817 pci_msiq_state_t *msiq_state) 818 { 819 uint64_t ret; 820 821 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 822 dip, msiq_id); 823 824 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 825 msiq_id, msiq_state)) != H_EOK) { 826 DBG(DBG_LIB_MSIQ, dip, 827 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 828 return (DDI_FAILURE); 829 } 830 831 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 832 *msiq_state); 833 834 return (DDI_SUCCESS); 835 } 836 837 /*ARGSUSED*/ 838 int 839 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 840 pci_msiq_state_t msiq_state) 841 { 842 uint64_t ret; 843 844 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 845 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 846 847 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 848 msiq_id, msiq_state)) != H_EOK) { 849 DBG(DBG_LIB_MSIQ, dip, 850 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 851 return (DDI_FAILURE); 852 } 853 854 return (DDI_SUCCESS); 855 } 856 857 /*ARGSUSED*/ 858 int 859 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 860 msiqhead_t *msiq_head) 861 { 862 uint64_t ret; 863 864 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 865 dip, msiq_id); 866 867 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 868 msiq_id, msiq_head)) != H_EOK) { 869 DBG(DBG_LIB_MSIQ, dip, 870 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 871 return (DDI_FAILURE); 872 } 873 874 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: msiq_head 0x%x\n", 875 *msiq_head); 876 877 return (DDI_SUCCESS); 878 } 879 880 /*ARGSUSED*/ 881 int 882 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 883 msiqhead_t msiq_head) 884 { 885 uint64_t ret; 886 887 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 888 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 889 890 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 891 msiq_id, msiq_head)) != H_EOK) { 892 DBG(DBG_LIB_MSIQ, dip, 893 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 894 return (DDI_FAILURE); 895 } 896 897 return (DDI_SUCCESS); 898 } 899 900 /*ARGSUSED*/ 901 int 902 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 903 msiqtail_t *msiq_tail) 904 { 905 uint64_t ret; 906 907 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 908 dip, msiq_id); 909 910 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 911 msiq_id, msiq_tail)) != H_EOK) { 912 DBG(DBG_LIB_MSIQ, dip, 913 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 914 return (DDI_FAILURE); 915 } 916 917 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 918 *msiq_tail); 919 920 return (DDI_SUCCESS); 921 } 922 923 /*ARGSUSED*/ 924 void 925 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 926 { 927 eq_rec_t *eq_rec_p = (eq_rec_t *)msiq_p->msiq_curr; 928 929 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p eq_rec_p 0x%p\n", 930 dip, eq_rec_p); 931 932 if (!eq_rec_p->eq_rec_fmt_type) { 933 /* Set msiq_rec_type to zero */ 934 msiq_rec_p->msiq_rec_type = 0; 935 936 return; 937 } 938 939 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: EQ RECORD, " 940 "eq_rec_rid 0x%llx eq_rec_fmt_type 0x%llx " 941 "eq_rec_len 0x%llx eq_rec_addr0 0x%llx " 942 "eq_rec_addr1 0x%llx eq_rec_data0 0x%llx " 943 "eq_rec_data1 0x%llx\n", eq_rec_p->eq_rec_rid, 944 eq_rec_p->eq_rec_fmt_type, eq_rec_p->eq_rec_len, 945 eq_rec_p->eq_rec_addr0, eq_rec_p->eq_rec_addr1, 946 eq_rec_p->eq_rec_data0, eq_rec_p->eq_rec_data1); 947 948 /* 949 * Only upper 4 bits of eq_rec_fmt_type is used 950 * to identify the EQ record type. 951 */ 952 switch (eq_rec_p->eq_rec_fmt_type >> 3) { 953 case EQ_REC_MSI32: 954 msiq_rec_p->msiq_rec_type = MSI32_REC; 955 956 msiq_rec_p->msiq_rec_data.msi.msi_data = 957 eq_rec_p->eq_rec_data0; 958 break; 959 case EQ_REC_MSI64: 960 msiq_rec_p->msiq_rec_type = MSI64_REC; 961 962 msiq_rec_p->msiq_rec_data.msi.msi_data = 963 eq_rec_p->eq_rec_data0; 964 break; 965 case EQ_REC_MSG: 966 msiq_rec_p->msiq_rec_type = MSG_REC; 967 968 msiq_rec_p->msiq_rec_data.msg.msg_route = 969 eq_rec_p->eq_rec_fmt_type & 7; 970 msiq_rec_p->msiq_rec_data.msg.msg_targ = eq_rec_p->eq_rec_rid; 971 msiq_rec_p->msiq_rec_data.msg.msg_code = eq_rec_p->eq_rec_data0; 972 break; 973 default: 974 cmn_err(CE_WARN, "%s%d: px_lib_get_msiq_rec: " 975 "0x%x is an unknown EQ record type", 976 ddi_driver_name(dip), ddi_get_instance(dip), 977 (int)eq_rec_p->eq_rec_fmt_type); 978 break; 979 } 980 981 msiq_rec_p->msiq_rec_rid = eq_rec_p->eq_rec_rid; 982 msiq_rec_p->msiq_rec_msi_addr = ((eq_rec_p->eq_rec_addr1 << 16) | 983 (eq_rec_p->eq_rec_addr0 << 2)); 984 985 /* Zero out eq_rec_fmt_type field */ 986 eq_rec_p->eq_rec_fmt_type = 0; 987 } 988 989 /* 990 * MSI Functions: 991 */ 992 /*ARGSUSED*/ 993 int 994 px_lib_msi_init(dev_info_t *dip) 995 { 996 px_t *px_p = DIP_TO_STATE(dip); 997 px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 998 uint64_t ret; 999 1000 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 1001 1002 if ((ret = hvio_msi_init(DIP_TO_HANDLE(dip), 1003 msi_state_p->msi_addr32, msi_state_p->msi_addr64)) != H_EOK) { 1004 DBG(DBG_LIB_MSIQ, dip, "px_lib_msi_init failed, ret 0x%lx\n", 1005 ret); 1006 return (DDI_FAILURE); 1007 } 1008 1009 return (DDI_SUCCESS); 1010 } 1011 1012 /*ARGSUSED*/ 1013 int 1014 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 1015 msiqid_t *msiq_id) 1016 { 1017 uint64_t ret; 1018 1019 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 1020 dip, msi_num); 1021 1022 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 1023 msi_num, msiq_id)) != H_EOK) { 1024 DBG(DBG_LIB_MSI, dip, 1025 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 1026 return (DDI_FAILURE); 1027 } 1028 1029 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 1030 *msiq_id); 1031 1032 return (DDI_SUCCESS); 1033 } 1034 1035 /*ARGSUSED*/ 1036 int 1037 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 1038 msiqid_t msiq_id, msi_type_t msitype) 1039 { 1040 uint64_t ret; 1041 1042 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 1043 "msq_id 0x%x\n", dip, msi_num, msiq_id); 1044 1045 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 1046 msi_num, msiq_id)) != H_EOK) { 1047 DBG(DBG_LIB_MSI, dip, 1048 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 1049 return (DDI_FAILURE); 1050 } 1051 1052 return (DDI_SUCCESS); 1053 } 1054 1055 /*ARGSUSED*/ 1056 int 1057 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 1058 pci_msi_valid_state_t *msi_valid_state) 1059 { 1060 uint64_t ret; 1061 1062 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 1063 dip, msi_num); 1064 1065 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 1066 msi_num, msi_valid_state)) != H_EOK) { 1067 DBG(DBG_LIB_MSI, dip, 1068 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 1069 return (DDI_FAILURE); 1070 } 1071 1072 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 1073 *msi_valid_state); 1074 1075 return (DDI_SUCCESS); 1076 } 1077 1078 /*ARGSUSED*/ 1079 int 1080 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 1081 pci_msi_valid_state_t msi_valid_state) 1082 { 1083 uint64_t ret; 1084 1085 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 1086 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 1087 1088 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 1089 msi_num, msi_valid_state)) != H_EOK) { 1090 DBG(DBG_LIB_MSI, dip, 1091 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 1092 return (DDI_FAILURE); 1093 } 1094 1095 return (DDI_SUCCESS); 1096 } 1097 1098 /*ARGSUSED*/ 1099 int 1100 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 1101 pci_msi_state_t *msi_state) 1102 { 1103 uint64_t ret; 1104 1105 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 1106 dip, msi_num); 1107 1108 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 1109 msi_num, msi_state)) != H_EOK) { 1110 DBG(DBG_LIB_MSI, dip, 1111 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 1112 return (DDI_FAILURE); 1113 } 1114 1115 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 1116 *msi_state); 1117 1118 return (DDI_SUCCESS); 1119 } 1120 1121 /*ARGSUSED*/ 1122 int 1123 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 1124 pci_msi_state_t msi_state) 1125 { 1126 uint64_t ret; 1127 1128 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 1129 "msi_state 0x%x\n", dip, msi_num, msi_state); 1130 1131 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 1132 msi_num, msi_state)) != H_EOK) { 1133 DBG(DBG_LIB_MSI, dip, 1134 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 1135 return (DDI_FAILURE); 1136 } 1137 1138 return (DDI_SUCCESS); 1139 } 1140 1141 /* 1142 * MSG Functions: 1143 */ 1144 /*ARGSUSED*/ 1145 int 1146 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1147 msiqid_t *msiq_id) 1148 { 1149 uint64_t ret; 1150 1151 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 1152 dip, msg_type); 1153 1154 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 1155 msg_type, msiq_id)) != H_EOK) { 1156 DBG(DBG_LIB_MSG, dip, 1157 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 1158 return (DDI_FAILURE); 1159 } 1160 1161 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1162 *msiq_id); 1163 1164 return (DDI_SUCCESS); 1165 } 1166 1167 /*ARGSUSED*/ 1168 int 1169 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1170 msiqid_t msiq_id) 1171 { 1172 uint64_t ret; 1173 1174 DBG(DBG_LIB_MSG, dip, "px_lib_msi_setstate: dip 0x%p msg_type 0x%x " 1175 "msiq_id 0x%x\n", dip, msg_type, msiq_id); 1176 1177 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1178 msg_type, msiq_id)) != H_EOK) { 1179 DBG(DBG_LIB_MSG, dip, 1180 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1181 return (DDI_FAILURE); 1182 } 1183 1184 return (DDI_SUCCESS); 1185 } 1186 1187 /*ARGSUSED*/ 1188 int 1189 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1190 pcie_msg_valid_state_t *msg_valid_state) 1191 { 1192 uint64_t ret; 1193 1194 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1195 dip, msg_type); 1196 1197 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1198 msg_valid_state)) != H_EOK) { 1199 DBG(DBG_LIB_MSG, dip, 1200 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1201 return (DDI_FAILURE); 1202 } 1203 1204 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1205 *msg_valid_state); 1206 1207 return (DDI_SUCCESS); 1208 } 1209 1210 /*ARGSUSED*/ 1211 int 1212 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1213 pcie_msg_valid_state_t msg_valid_state) 1214 { 1215 uint64_t ret; 1216 1217 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1218 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1219 1220 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1221 msg_valid_state)) != H_EOK) { 1222 DBG(DBG_LIB_MSG, dip, 1223 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1224 return (DDI_FAILURE); 1225 } 1226 1227 return (DDI_SUCCESS); 1228 } 1229 1230 /* 1231 * Suspend/Resume Functions: 1232 * Currently unsupported by hypervisor 1233 */ 1234 int 1235 px_lib_suspend(dev_info_t *dip) 1236 { 1237 px_t *px_p = DIP_TO_STATE(dip); 1238 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1239 px_cb_t *cb_p = PX2CB(px_p); 1240 devhandle_t dev_hdl, xbus_dev_hdl; 1241 uint64_t ret = H_EOK; 1242 1243 DBG(DBG_DETACH, dip, "px_lib_suspend: dip 0x%p\n", dip); 1244 1245 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; 1246 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; 1247 1248 if ((ret = hvio_suspend(dev_hdl, pxu_p)) != H_EOK) 1249 goto fail; 1250 1251 if (--cb_p->attachcnt == 0) { 1252 ret = hvio_cb_suspend(xbus_dev_hdl, pxu_p); 1253 if (ret != H_EOK) 1254 cb_p->attachcnt++; 1255 } 1256 1257 fail: 1258 return ((ret != H_EOK) ? DDI_FAILURE: DDI_SUCCESS); 1259 } 1260 1261 void 1262 px_lib_resume(dev_info_t *dip) 1263 { 1264 px_t *px_p = DIP_TO_STATE(dip); 1265 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1266 px_cb_t *cb_p = PX2CB(px_p); 1267 devhandle_t dev_hdl, xbus_dev_hdl; 1268 devino_t pec_ino = px_p->px_inos[PX_INTR_PEC]; 1269 devino_t xbc_ino = px_p->px_inos[PX_INTR_XBC]; 1270 1271 DBG(DBG_ATTACH, dip, "px_lib_resume: dip 0x%p\n", dip); 1272 1273 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; 1274 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; 1275 1276 if (++cb_p->attachcnt == 1) 1277 hvio_cb_resume(dev_hdl, xbus_dev_hdl, xbc_ino, pxu_p); 1278 1279 hvio_resume(dev_hdl, pec_ino, pxu_p); 1280 } 1281 1282 /* 1283 * Generate a unique Oberon UBC ID based on the Logicial System Board and 1284 * the IO Channel from the portid property field. 1285 */ 1286 static uint64_t 1287 oberon_get_ubc_id(dev_info_t *dip) 1288 { 1289 px_t *px_p = DIP_TO_STATE(dip); 1290 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1291 uint64_t ubc_id; 1292 1293 /* 1294 * Generate a unique 6 bit UBC ID using the 2 IO_Channel#[1:0] bits and 1295 * the 4 LSB_ID[3:0] bits from the Oberon's portid property. 1296 */ 1297 ubc_id = (((pxu_p->portid >> OBERON_PORT_ID_IOC) & 1298 OBERON_PORT_ID_IOC_MASK) | (((pxu_p->portid >> 1299 OBERON_PORT_ID_LSB) & OBERON_PORT_ID_LSB_MASK) 1300 << OBERON_UBC_ID_LSB)); 1301 1302 return (ubc_id); 1303 } 1304 1305 /* 1306 * Oberon does not have a UBC scratch register, so alloc an array of scratch 1307 * registers when needed and use a unique UBC ID as an index. This code 1308 * can be simplified if we use a pre-allocated array. They are currently 1309 * being dynamically allocated because it's only needed by the Oberon. 1310 */ 1311 static void 1312 oberon_set_cb(dev_info_t *dip, uint64_t val) 1313 { 1314 uint64_t ubc_id; 1315 1316 if (px_oberon_ubc_scratch_regs == NULL) 1317 px_oberon_ubc_scratch_regs = 1318 (uint64_t *)kmem_zalloc(sizeof (uint64_t)* 1319 OBERON_UBC_ID_MAX, KM_SLEEP); 1320 1321 ubc_id = oberon_get_ubc_id(dip); 1322 1323 px_oberon_ubc_scratch_regs[ubc_id] = val; 1324 1325 /* 1326 * Check if any scratch registers are still in use. If all scratch 1327 * registers are currently set to zero, then deallocate the scratch 1328 * register array. 1329 */ 1330 for (ubc_id = 0; ubc_id < OBERON_UBC_ID_MAX; ubc_id++) { 1331 if (px_oberon_ubc_scratch_regs[ubc_id] != NULL) 1332 return; 1333 } 1334 1335 /* 1336 * All scratch registers are set to zero so deallocate the scratch 1337 * register array and set the pointer to NULL. 1338 */ 1339 kmem_free(px_oberon_ubc_scratch_regs, 1340 (sizeof (uint64_t)*OBERON_UBC_ID_MAX)); 1341 1342 px_oberon_ubc_scratch_regs = NULL; 1343 } 1344 1345 /* 1346 * Oberon does not have a UBC scratch register, so use an allocated array of 1347 * scratch registers and use the unique UBC ID as an index into that array. 1348 */ 1349 static uint64_t 1350 oberon_get_cb(dev_info_t *dip) 1351 { 1352 uint64_t ubc_id; 1353 1354 if (px_oberon_ubc_scratch_regs == NULL) 1355 return (0); 1356 1357 ubc_id = oberon_get_ubc_id(dip); 1358 1359 return (px_oberon_ubc_scratch_regs[ubc_id]); 1360 } 1361 1362 /* 1363 * Misc Functions: 1364 * Currently unsupported by hypervisor 1365 */ 1366 static uint64_t 1367 px_get_cb(dev_info_t *dip) 1368 { 1369 px_t *px_p = DIP_TO_STATE(dip); 1370 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1371 1372 /* 1373 * Oberon does not currently have Scratchpad registers. 1374 */ 1375 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 1376 return (oberon_get_cb(dip)); 1377 1378 return (CSR_XR((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1)); 1379 } 1380 1381 static void 1382 px_set_cb(dev_info_t *dip, uint64_t val) 1383 { 1384 px_t *px_p = DIP_TO_STATE(dip); 1385 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1386 1387 /* 1388 * Oberon does not currently have Scratchpad registers. 1389 */ 1390 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1391 oberon_set_cb(dip, val); 1392 return; 1393 } 1394 1395 CSR_XS((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1, val); 1396 } 1397 1398 /*ARGSUSED*/ 1399 int 1400 px_lib_map_vconfig(dev_info_t *dip, 1401 ddi_map_req_t *mp, pci_config_offset_t off, 1402 pci_regspec_t *rp, caddr_t *addrp) 1403 { 1404 /* 1405 * No special config space access services in this layer. 1406 */ 1407 return (DDI_FAILURE); 1408 } 1409 1410 void 1411 px_lib_map_attr_check(ddi_map_req_t *mp) 1412 { 1413 ddi_acc_hdl_t *hp = mp->map_handlep; 1414 1415 /* fire does not accept byte masks from PIO store merge */ 1416 if (hp->ah_acc.devacc_attr_dataorder == DDI_STORECACHING_OK_ACC) 1417 hp->ah_acc.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1418 } 1419 1420 void 1421 px_lib_clr_errs(px_t *px_p) 1422 { 1423 px_pec_t *pec_p = px_p->px_pec_p; 1424 dev_info_t *rpdip = px_p->px_dip; 1425 int err = PX_OK, ret; 1426 int acctype = pec_p->pec_safeacc_type; 1427 ddi_fm_error_t derr; 1428 1429 /* Create the derr */ 1430 bzero(&derr, sizeof (ddi_fm_error_t)); 1431 derr.fme_version = DDI_FME_VERSION; 1432 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1433 derr.fme_flag = acctype; 1434 1435 if (acctype == DDI_FM_ERR_EXPECTED) { 1436 derr.fme_status = DDI_FM_NONFATAL; 1437 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, &derr); 1438 } 1439 1440 mutex_enter(&px_p->px_fm_mutex); 1441 1442 /* send ereport/handle/clear fire registers */ 1443 err = px_err_handle(px_p, &derr, PX_LIB_CALL, B_TRUE); 1444 1445 /* Check all child devices for errors */ 1446 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 1447 1448 mutex_exit(&px_p->px_fm_mutex); 1449 1450 /* 1451 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 1452 * therefore it does not cause panic. 1453 */ 1454 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 1455 PX_FM_PANIC("Fatal System Port Error has occurred\n"); 1456 } 1457 1458 #ifdef DEBUG 1459 int px_peekfault_cnt = 0; 1460 int px_pokefault_cnt = 0; 1461 #endif /* DEBUG */ 1462 1463 /*ARGSUSED*/ 1464 static int 1465 px_lib_do_poke(dev_info_t *dip, dev_info_t *rdip, 1466 peekpoke_ctlops_t *in_args) 1467 { 1468 px_t *px_p = DIP_TO_STATE(dip); 1469 px_pec_t *pec_p = px_p->px_pec_p; 1470 int err = DDI_SUCCESS; 1471 on_trap_data_t otd; 1472 1473 mutex_enter(&pec_p->pec_pokefault_mutex); 1474 pec_p->pec_ontrap_data = &otd; 1475 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1476 1477 /* Set up protected environment. */ 1478 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1479 uintptr_t tramp = otd.ot_trampoline; 1480 1481 otd.ot_trampoline = (uintptr_t)&poke_fault; 1482 err = do_poke(in_args->size, (void *)in_args->dev_addr, 1483 (void *)in_args->host_addr); 1484 otd.ot_trampoline = tramp; 1485 } else 1486 err = DDI_FAILURE; 1487 1488 px_lib_clr_errs(px_p); 1489 1490 if (otd.ot_trap & OT_DATA_ACCESS) 1491 err = DDI_FAILURE; 1492 1493 /* Take down protected environment. */ 1494 no_trap(); 1495 1496 pec_p->pec_ontrap_data = NULL; 1497 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1498 mutex_exit(&pec_p->pec_pokefault_mutex); 1499 1500 #ifdef DEBUG 1501 if (err == DDI_FAILURE) 1502 px_pokefault_cnt++; 1503 #endif 1504 return (err); 1505 } 1506 1507 /*ARGSUSED*/ 1508 static int 1509 px_lib_do_caut_put(dev_info_t *dip, dev_info_t *rdip, 1510 peekpoke_ctlops_t *cautacc_ctlops_arg) 1511 { 1512 size_t size = cautacc_ctlops_arg->size; 1513 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1514 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1515 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1516 size_t repcount = cautacc_ctlops_arg->repcount; 1517 uint_t flags = cautacc_ctlops_arg->flags; 1518 1519 px_t *px_p = DIP_TO_STATE(dip); 1520 px_pec_t *pec_p = px_p->px_pec_p; 1521 int err = DDI_SUCCESS; 1522 1523 /* 1524 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1525 * mutex. 1526 */ 1527 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1528 1529 pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1530 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1531 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1532 1533 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1534 for (; repcount; repcount--) { 1535 switch (size) { 1536 1537 case sizeof (uint8_t): 1538 i_ddi_put8(hp, (uint8_t *)dev_addr, 1539 *(uint8_t *)host_addr); 1540 break; 1541 1542 case sizeof (uint16_t): 1543 i_ddi_put16(hp, (uint16_t *)dev_addr, 1544 *(uint16_t *)host_addr); 1545 break; 1546 1547 case sizeof (uint32_t): 1548 i_ddi_put32(hp, (uint32_t *)dev_addr, 1549 *(uint32_t *)host_addr); 1550 break; 1551 1552 case sizeof (uint64_t): 1553 i_ddi_put64(hp, (uint64_t *)dev_addr, 1554 *(uint64_t *)host_addr); 1555 break; 1556 } 1557 1558 host_addr += size; 1559 1560 if (flags == DDI_DEV_AUTOINCR) 1561 dev_addr += size; 1562 1563 px_lib_clr_errs(px_p); 1564 1565 if (pec_p->pec_ontrap_data->ot_trap & OT_DATA_ACCESS) { 1566 err = DDI_FAILURE; 1567 #ifdef DEBUG 1568 px_pokefault_cnt++; 1569 #endif 1570 break; 1571 } 1572 } 1573 } 1574 1575 i_ddi_notrap((ddi_acc_handle_t)hp); 1576 pec_p->pec_ontrap_data = NULL; 1577 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1578 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1579 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1580 1581 return (err); 1582 } 1583 1584 1585 int 1586 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1587 peekpoke_ctlops_t *in_args) 1588 { 1589 return (in_args->handle ? px_lib_do_caut_put(dip, rdip, in_args) : 1590 px_lib_do_poke(dip, rdip, in_args)); 1591 } 1592 1593 1594 /*ARGSUSED*/ 1595 static int 1596 px_lib_do_peek(dev_info_t *dip, peekpoke_ctlops_t *in_args) 1597 { 1598 px_t *px_p = DIP_TO_STATE(dip); 1599 px_pec_t *pec_p = px_p->px_pec_p; 1600 int err = DDI_SUCCESS; 1601 on_trap_data_t otd; 1602 1603 mutex_enter(&pec_p->pec_pokefault_mutex); 1604 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1605 1606 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1607 uintptr_t tramp = otd.ot_trampoline; 1608 1609 otd.ot_trampoline = (uintptr_t)&peek_fault; 1610 err = do_peek(in_args->size, (void *)in_args->dev_addr, 1611 (void *)in_args->host_addr); 1612 otd.ot_trampoline = tramp; 1613 } else 1614 err = DDI_FAILURE; 1615 1616 no_trap(); 1617 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1618 mutex_exit(&pec_p->pec_pokefault_mutex); 1619 1620 #ifdef DEBUG 1621 if (err == DDI_FAILURE) 1622 px_peekfault_cnt++; 1623 #endif 1624 return (err); 1625 } 1626 1627 1628 static int 1629 px_lib_do_caut_get(dev_info_t *dip, peekpoke_ctlops_t *cautacc_ctlops_arg) 1630 { 1631 size_t size = cautacc_ctlops_arg->size; 1632 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1633 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1634 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1635 size_t repcount = cautacc_ctlops_arg->repcount; 1636 uint_t flags = cautacc_ctlops_arg->flags; 1637 1638 px_t *px_p = DIP_TO_STATE(dip); 1639 px_pec_t *pec_p = px_p->px_pec_p; 1640 int err = DDI_SUCCESS; 1641 1642 /* 1643 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1644 * mutex. 1645 */ 1646 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1647 1648 pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1649 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1650 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1651 1652 if (repcount == 1) { 1653 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1654 i_ddi_caut_get(size, (void *)dev_addr, 1655 (void *)host_addr); 1656 } else { 1657 int i; 1658 uint8_t *ff_addr = (uint8_t *)host_addr; 1659 for (i = 0; i < size; i++) 1660 *ff_addr++ = 0xff; 1661 1662 err = DDI_FAILURE; 1663 #ifdef DEBUG 1664 px_peekfault_cnt++; 1665 #endif 1666 } 1667 } else { 1668 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1669 for (; repcount; repcount--) { 1670 i_ddi_caut_get(size, (void *)dev_addr, 1671 (void *)host_addr); 1672 1673 host_addr += size; 1674 1675 if (flags == DDI_DEV_AUTOINCR) 1676 dev_addr += size; 1677 } 1678 } else { 1679 err = DDI_FAILURE; 1680 #ifdef DEBUG 1681 px_peekfault_cnt++; 1682 #endif 1683 } 1684 } 1685 1686 i_ddi_notrap((ddi_acc_handle_t)hp); 1687 pec_p->pec_ontrap_data = NULL; 1688 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1689 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1690 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1691 1692 return (err); 1693 } 1694 1695 /*ARGSUSED*/ 1696 int 1697 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1698 peekpoke_ctlops_t *in_args, void *result) 1699 { 1700 result = (void *)in_args->host_addr; 1701 return (in_args->handle ? px_lib_do_caut_get(dip, in_args) : 1702 px_lib_do_peek(dip, in_args)); 1703 } 1704 1705 /* 1706 * implements PPM interface 1707 */ 1708 int 1709 px_lib_pmctl(int cmd, px_t *px_p) 1710 { 1711 ASSERT((cmd & ~PPMREQ_MASK) == PPMREQ); 1712 switch (cmd) { 1713 case PPMREQ_PRE_PWR_OFF: 1714 /* 1715 * Currently there is no device power management for 1716 * the root complex (fire). When there is we need to make 1717 * sure that it is at full power before trying to send the 1718 * PME_Turn_Off message. 1719 */ 1720 DBG(DBG_PWR, px_p->px_dip, 1721 "ioctl: request to send PME_Turn_Off\n"); 1722 return (px_goto_l23ready(px_p)); 1723 1724 case PPMREQ_PRE_PWR_ON: 1725 DBG(DBG_PWR, px_p->px_dip, "ioctl: PRE_PWR_ON request\n"); 1726 return (px_pre_pwron_check(px_p)); 1727 1728 case PPMREQ_POST_PWR_ON: 1729 DBG(DBG_PWR, px_p->px_dip, "ioctl: POST_PWR_ON request\n"); 1730 return (px_goto_l0(px_p)); 1731 1732 default: 1733 return (DDI_FAILURE); 1734 } 1735 } 1736 1737 /* 1738 * sends PME_Turn_Off message to put the link in L2/L3 ready state. 1739 * called by px_ioctl. 1740 * returns DDI_SUCCESS or DDI_FAILURE 1741 * 1. Wait for link to be in L1 state (link status reg) 1742 * 2. write to PME_Turn_off reg to boradcast 1743 * 3. set timeout 1744 * 4. If timeout, return failure. 1745 * 5. If PM_TO_Ack, wait till link is in L2/L3 ready 1746 */ 1747 static int 1748 px_goto_l23ready(px_t *px_p) 1749 { 1750 pcie_pwr_t *pwr_p; 1751 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1752 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 1753 int ret = DDI_SUCCESS; 1754 clock_t end, timeleft; 1755 int mutex_held = 1; 1756 1757 /* If no PM info, return failure */ 1758 if (!PCIE_PMINFO(px_p->px_dip) || 1759 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1760 return (DDI_FAILURE); 1761 1762 mutex_enter(&pwr_p->pwr_lock); 1763 mutex_enter(&px_p->px_l23ready_lock); 1764 /* Clear the PME_To_ACK receieved flag */ 1765 px_p->px_pm_flags &= ~PX_PMETOACK_RECVD; 1766 /* 1767 * When P25 is the downstream device, after receiving 1768 * PME_To_ACK, fire will go to Detect state, which causes 1769 * the link down event. Inform FMA that this is expected. 1770 * In case of all other cards complaint with the pci express 1771 * spec, this will happen when the power is re-applied. FMA 1772 * code will clear this flag after one instance of LDN. Since 1773 * there will not be a LDN event for the spec compliant cards, 1774 * we need to clear the flag after receiving PME_To_ACK. 1775 */ 1776 px_p->px_pm_flags |= PX_LDN_EXPECTED; 1777 if (px_send_pme_turnoff(csr_base) != DDI_SUCCESS) { 1778 ret = DDI_FAILURE; 1779 goto l23ready_done; 1780 } 1781 px_p->px_pm_flags |= PX_PME_TURNOFF_PENDING; 1782 1783 end = ddi_get_lbolt() + drv_usectohz(px_pme_to_ack_timeout); 1784 while (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1785 timeleft = cv_timedwait(&px_p->px_l23ready_cv, 1786 &px_p->px_l23ready_lock, end); 1787 /* 1788 * if cv_timedwait returns -1, it is either 1789 * 1) timed out or 1790 * 2) there was a pre-mature wakeup but by the time 1791 * cv_timedwait is called again end < lbolt i.e. 1792 * end is in the past. 1793 * 3) By the time we make first cv_timedwait call, 1794 * end < lbolt is true. 1795 */ 1796 if (timeleft == -1) 1797 break; 1798 } 1799 if (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1800 /* 1801 * Either timedout or interrupt didn't get a 1802 * chance to grab the mutex and set the flag. 1803 * release the mutex and delay for sometime. 1804 * This will 1) give a chance for interrupt to 1805 * set the flag 2) creates a delay between two 1806 * consequetive requests. 1807 */ 1808 mutex_exit(&px_p->px_l23ready_lock); 1809 delay(drv_usectohz(50 * PX_MSEC_TO_USEC)); 1810 mutex_held = 0; 1811 if (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1812 ret = DDI_FAILURE; 1813 DBG(DBG_PWR, px_p->px_dip, " Timed out while waiting" 1814 " for PME_TO_ACK\n"); 1815 } 1816 } 1817 px_p->px_pm_flags &= 1818 ~(PX_PME_TURNOFF_PENDING | PX_PMETOACK_RECVD | PX_LDN_EXPECTED); 1819 1820 l23ready_done: 1821 if (mutex_held) 1822 mutex_exit(&px_p->px_l23ready_lock); 1823 /* 1824 * Wait till link is in L1 idle, if sending PME_Turn_Off 1825 * was succesful. 1826 */ 1827 if (ret == DDI_SUCCESS) { 1828 if (px_link_wait4l1idle(csr_base) != DDI_SUCCESS) { 1829 DBG(DBG_PWR, px_p->px_dip, " Link is not at L1" 1830 " even though we received PME_To_ACK.\n"); 1831 /* 1832 * Workaround for hardware bug with P25. 1833 * Due to a hardware bug with P25, link state 1834 * will be Detect state rather than L1 after 1835 * link is transitioned to L23Ready state. Since 1836 * we don't know whether link is L23ready state 1837 * without Fire's state being L1_idle, we delay 1838 * here just to make sure that we wait till link 1839 * is transitioned to L23Ready state. 1840 */ 1841 delay(drv_usectohz(100 * PX_MSEC_TO_USEC)); 1842 } 1843 pwr_p->pwr_link_lvl = PM_LEVEL_L3; 1844 1845 } 1846 mutex_exit(&pwr_p->pwr_lock); 1847 return (ret); 1848 } 1849 1850 /* 1851 * Message interrupt handler intended to be shared for both 1852 * PME and PME_TO_ACK msg handling, currently only handles 1853 * PME_To_ACK message. 1854 */ 1855 uint_t 1856 px_pmeq_intr(caddr_t arg) 1857 { 1858 px_t *px_p = (px_t *)arg; 1859 1860 DBG(DBG_PWR, px_p->px_dip, " PME_To_ACK received \n"); 1861 mutex_enter(&px_p->px_l23ready_lock); 1862 cv_broadcast(&px_p->px_l23ready_cv); 1863 if (px_p->px_pm_flags & PX_PME_TURNOFF_PENDING) { 1864 px_p->px_pm_flags |= PX_PMETOACK_RECVD; 1865 } else { 1866 /* 1867 * This maybe the second ack received. If so then, 1868 * we should be receiving it during wait4L1 stage. 1869 */ 1870 px_p->px_pmetoack_ignored++; 1871 } 1872 mutex_exit(&px_p->px_l23ready_lock); 1873 return (DDI_INTR_CLAIMED); 1874 } 1875 1876 static int 1877 px_pre_pwron_check(px_t *px_p) 1878 { 1879 pcie_pwr_t *pwr_p; 1880 1881 /* If no PM info, return failure */ 1882 if (!PCIE_PMINFO(px_p->px_dip) || 1883 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1884 return (DDI_FAILURE); 1885 1886 /* 1887 * For the spec compliant downstream cards link down 1888 * is expected when the device is powered on. 1889 */ 1890 px_p->px_pm_flags |= PX_LDN_EXPECTED; 1891 return (pwr_p->pwr_link_lvl == PM_LEVEL_L3 ? DDI_SUCCESS : DDI_FAILURE); 1892 } 1893 1894 static int 1895 px_goto_l0(px_t *px_p) 1896 { 1897 pcie_pwr_t *pwr_p; 1898 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1899 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 1900 int ret = DDI_SUCCESS; 1901 uint64_t time_spent = 0; 1902 1903 /* If no PM info, return failure */ 1904 if (!PCIE_PMINFO(px_p->px_dip) || 1905 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1906 return (DDI_FAILURE); 1907 1908 mutex_enter(&pwr_p->pwr_lock); 1909 /* 1910 * The following link retrain activity will cause LDN and LUP event. 1911 * Receiving LDN prior to receiving LUP is expected, not an error in 1912 * this case. Receiving LUP indicates link is fully up to support 1913 * powering up down stream device, and of course any further LDN and 1914 * LUP outside this context will be error. 1915 */ 1916 px_p->px_lup_pending = 1; 1917 if (px_link_retrain(csr_base) != DDI_SUCCESS) { 1918 ret = DDI_FAILURE; 1919 goto l0_done; 1920 } 1921 1922 /* LUP event takes the order of 15ms amount of time to occur */ 1923 for (; px_p->px_lup_pending && (time_spent < px_lup_poll_to); 1924 time_spent += px_lup_poll_interval) 1925 drv_usecwait(px_lup_poll_interval); 1926 if (px_p->px_lup_pending) 1927 ret = DDI_FAILURE; 1928 l0_done: 1929 px_enable_detect_quiet(csr_base); 1930 if (ret == DDI_SUCCESS) 1931 pwr_p->pwr_link_lvl = PM_LEVEL_L0; 1932 mutex_exit(&pwr_p->pwr_lock); 1933 return (ret); 1934 } 1935 1936 /* 1937 * Extract the drivers binding name to identify which chip we're binding to. 1938 * Whenever a new bus bridge is created, the driver alias entry should be 1939 * added here to identify the device if needed. If a device isn't added, 1940 * the identity defaults to PX_CHIP_UNIDENTIFIED. 1941 */ 1942 static uint32_t 1943 px_identity_init(px_t *px_p) 1944 { 1945 dev_info_t *dip = px_p->px_dip; 1946 char *name = ddi_binding_name(dip); 1947 uint32_t revision = 0; 1948 1949 revision = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1950 "module-revision#", 0); 1951 1952 /* Check for Fire driver binding name */ 1953 if (strcmp(name, "pciex108e,80f0") == 0) { 1954 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 1955 "(FIRE), module-revision %d\n", NAMEINST(dip), 1956 revision); 1957 1958 return ((revision >= FIRE_MOD_REV_20) ? 1959 PX_CHIP_FIRE : PX_CHIP_UNIDENTIFIED); 1960 } 1961 1962 /* Check for Oberon driver binding name */ 1963 if (strcmp(name, "pciex108e,80f8") == 0) { 1964 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 1965 "(OBERON), module-revision %d\n", NAMEINST(dip), 1966 revision); 1967 1968 return (PX_CHIP_OBERON); 1969 } 1970 1971 DBG(DBG_ATTACH, dip, "%s%d: Unknown PCI Express Host bridge %s %x\n", 1972 ddi_driver_name(dip), ddi_get_instance(dip), name, revision); 1973 1974 return (PX_CHIP_UNIDENTIFIED); 1975 } 1976 1977 int 1978 px_err_add_intr(px_fault_t *px_fault_p) 1979 { 1980 dev_info_t *dip = px_fault_p->px_fh_dip; 1981 px_t *px_p = DIP_TO_STATE(dip); 1982 1983 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1984 px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL) == 0); 1985 1986 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1987 1988 return (DDI_SUCCESS); 1989 } 1990 1991 void 1992 px_err_rem_intr(px_fault_t *px_fault_p) 1993 { 1994 dev_info_t *dip = px_fault_p->px_fh_dip; 1995 px_t *px_p = DIP_TO_STATE(dip); 1996 1997 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1998 IB_INTR_WAIT); 1999 2000 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 2001 } 2002 2003 /* 2004 * px_cb_add_intr() - Called from attach(9E) to create CB if not yet 2005 * created, to add CB interrupt vector always, but enable only once. 2006 */ 2007 int 2008 px_cb_add_intr(px_fault_t *fault_p) 2009 { 2010 px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip); 2011 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2012 px_cb_t *cb_p = (px_cb_t *)px_get_cb(fault_p->px_fh_dip); 2013 px_cb_list_t *pxl, *pxl_new; 2014 cpuid_t cpuid; 2015 2016 2017 if (cb_p == NULL) { 2018 cb_p = kmem_zalloc(sizeof (px_cb_t), KM_SLEEP); 2019 mutex_init(&cb_p->cb_mutex, NULL, MUTEX_DRIVER, NULL); 2020 cb_p->px_cb_func = px_cb_intr; 2021 pxu_p->px_cb_p = cb_p; 2022 px_set_cb(fault_p->px_fh_dip, (uint64_t)cb_p); 2023 2024 /* px_lib_dev_init allows only FIRE and OBERON */ 2025 px_err_reg_enable( 2026 (pxu_p->chip_type == PX_CHIP_FIRE) ? 2027 PX_ERR_JBC : PX_ERR_UBC, 2028 pxu_p->px_address[PX_REG_XBC]); 2029 } else 2030 pxu_p->px_cb_p = cb_p; 2031 2032 mutex_enter(&cb_p->cb_mutex); 2033 2034 VERIFY(add_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL, 2035 cb_p->px_cb_func, (caddr_t)cb_p, NULL) == 0); 2036 2037 if (cb_p->pxl == NULL) { 2038 2039 cpuid = intr_dist_cpuid(), 2040 px_ib_intr_enable(px_p, cpuid, fault_p->px_intr_ino); 2041 2042 pxl = kmem_zalloc(sizeof (px_cb_list_t), KM_SLEEP); 2043 pxl->pxp = px_p; 2044 2045 cb_p->pxl = pxl; 2046 cb_p->sysino = fault_p->px_fh_sysino; 2047 cb_p->cpuid = cpuid; 2048 2049 } else { 2050 /* 2051 * Find the last pxl or 2052 * stop short at encoutering a redundent, or 2053 * both. 2054 */ 2055 pxl = cb_p->pxl; 2056 for (; !(pxl->pxp == px_p) && pxl->next; pxl = pxl->next); 2057 if (pxl->pxp == px_p) { 2058 cmn_err(CE_WARN, "px_cb_add_intr: reregister sysino " 2059 "%lx by px_p 0x%p\n", cb_p->sysino, (void *)px_p); 2060 return (DDI_FAILURE); 2061 } 2062 2063 /* add to linked list */ 2064 pxl_new = kmem_zalloc(sizeof (px_cb_list_t), KM_SLEEP); 2065 pxl_new->pxp = px_p; 2066 pxl->next = pxl_new; 2067 } 2068 cb_p->attachcnt++; 2069 2070 mutex_exit(&cb_p->cb_mutex); 2071 2072 return (DDI_SUCCESS); 2073 } 2074 2075 /* 2076 * px_cb_rem_intr() - Called from detach(9E) to remove its CB 2077 * interrupt vector, to shift proxy to the next available px, 2078 * or disable CB interrupt when itself is the last. 2079 */ 2080 void 2081 px_cb_rem_intr(px_fault_t *fault_p) 2082 { 2083 px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip), *pxp; 2084 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2085 px_cb_t *cb_p = PX2CB(px_p); 2086 px_cb_list_t *pxl, *prev; 2087 px_fault_t *f_p; 2088 2089 ASSERT(cb_p->pxl); 2090 2091 /* De-list the target px, move the next px up */ 2092 2093 mutex_enter(&cb_p->cb_mutex); 2094 2095 pxl = cb_p->pxl; 2096 if (pxl->pxp == px_p) { 2097 cb_p->pxl = pxl->next; 2098 } else { 2099 prev = pxl; 2100 pxl = pxl->next; 2101 for (; pxl && (pxl->pxp != px_p); prev = pxl, pxl = pxl->next); 2102 if (!pxl) { 2103 cmn_err(CE_WARN, "px_cb_rem_intr: can't find px_p 0x%p " 2104 "in registered CB list.", (void *)px_p); 2105 return; 2106 } 2107 prev->next = pxl->next; 2108 } 2109 kmem_free(pxl, sizeof (px_cb_list_t)); 2110 2111 if (fault_p->px_fh_sysino == cb_p->sysino) { 2112 px_ib_intr_disable(px_p->px_ib_p, fault_p->px_intr_ino, 2113 IB_INTR_WAIT); 2114 2115 if (cb_p->pxl) { 2116 pxp = cb_p->pxl->pxp; 2117 f_p = &pxp->px_cb_fault; 2118 cb_p->sysino = f_p->px_fh_sysino; 2119 2120 PX_INTR_ENABLE(pxp->px_dip, cb_p->sysino, cb_p->cpuid); 2121 (void) px_lib_intr_setstate(pxp->px_dip, cb_p->sysino, 2122 INTR_IDLE_STATE); 2123 } 2124 } 2125 2126 rem_ivintr(fault_p->px_fh_sysino, NULL); 2127 pxu_p->px_cb_p = NULL; 2128 cb_p->attachcnt--; 2129 if (cb_p->pxl) { 2130 mutex_exit(&cb_p->cb_mutex); 2131 return; 2132 } 2133 mutex_exit(&cb_p->cb_mutex); 2134 2135 /* px_lib_dev_init allows only FIRE and OBERON */ 2136 px_err_reg_disable( 2137 (pxu_p->chip_type == PX_CHIP_FIRE) ? PX_ERR_JBC : PX_ERR_UBC, 2138 pxu_p->px_address[PX_REG_XBC]); 2139 2140 mutex_destroy(&cb_p->cb_mutex); 2141 px_set_cb(fault_p->px_fh_dip, 0ull); 2142 kmem_free(cb_p, sizeof (px_cb_t)); 2143 } 2144 2145 /* 2146 * px_cb_intr() - sun4u only, CB interrupt dispatcher 2147 */ 2148 uint_t 2149 px_cb_intr(caddr_t arg) 2150 { 2151 px_cb_t *cb_p = (px_cb_t *)arg; 2152 px_cb_list_t *pxl = cb_p->pxl; 2153 px_t *pxp = pxl ? pxl->pxp : NULL; 2154 px_fault_t *fault_p; 2155 2156 while (pxl && pxp && (pxp->px_state != PX_ATTACHED)) { 2157 pxl = pxl->next; 2158 pxp = (pxl) ? pxl->pxp : NULL; 2159 } 2160 2161 if (pxp) { 2162 fault_p = &pxp->px_cb_fault; 2163 return (fault_p->px_err_func((caddr_t)fault_p)); 2164 } else 2165 return (DDI_INTR_UNCLAIMED); 2166 } 2167 2168 /* 2169 * px_cb_intr_redist() - sun4u only, CB interrupt redistribution 2170 */ 2171 void 2172 px_cb_intr_redist(px_t *px_p) 2173 { 2174 px_fault_t *f_p = &px_p->px_cb_fault; 2175 px_cb_t *cb_p = PX2CB(px_p); 2176 devino_t ino = px_p->px_inos[PX_INTR_XBC]; 2177 cpuid_t cpuid; 2178 2179 mutex_enter(&cb_p->cb_mutex); 2180 2181 if (cb_p->sysino != f_p->px_fh_sysino) { 2182 mutex_exit(&cb_p->cb_mutex); 2183 return; 2184 } 2185 2186 cb_p->cpuid = cpuid = intr_dist_cpuid(); 2187 px_ib_intr_dist_en(px_p->px_dip, cpuid, ino, B_FALSE); 2188 2189 mutex_exit(&cb_p->cb_mutex); 2190 } 2191 2192 #ifdef FMA 2193 void 2194 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 2195 { 2196 /* populate the rc_status by reading the registers - TBD */ 2197 } 2198 #endif /* FMA */ 2199 2200 /* 2201 * Unprotected raw reads/writes of fabric device's config space. 2202 * Only used for temporary PCI-E Fabric Error Handling. 2203 */ 2204 uint32_t 2205 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) 2206 { 2207 px_ranges_t *rp = px_p->px_ranges_p; 2208 uint64_t range_prop, base_addr; 2209 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 2210 uint32_t val; 2211 2212 /* Get Fire's Physical Base Address */ 2213 range_prop = px_get_range_prop(px_p, rp, bank); 2214 2215 /* Get config space first. */ 2216 base_addr = range_prop + PX_BDF_TO_CFGADDR(bdf, offset); 2217 2218 val = ldphysio(base_addr); 2219 2220 return (LE_32(val)); 2221 } 2222 2223 void 2224 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 2225 uint32_t val) { 2226 px_ranges_t *rp = px_p->px_ranges_p; 2227 uint64_t range_prop, base_addr; 2228 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 2229 2230 /* Get Fire's Physical Base Address */ 2231 range_prop = px_get_range_prop(px_p, rp, bank); 2232 2233 /* Get config space first. */ 2234 base_addr = range_prop + PX_BDF_TO_CFGADDR(bdf, offset); 2235 2236 stphysio(base_addr, LE_32(val)); 2237 } 2238 2239 /* 2240 * cpr callback 2241 * 2242 * disable fabric error msg interrupt prior to suspending 2243 * all device drivers; re-enable fabric error msg interrupt 2244 * after all devices are resumed. 2245 */ 2246 static boolean_t 2247 px_cpr_callb(void *arg, int code) 2248 { 2249 px_t *px_p = (px_t *)arg; 2250 px_ib_t *ib_p = px_p->px_ib_p; 2251 px_pec_t *pec_p = px_p->px_pec_p; 2252 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2253 caddr_t csr_base; 2254 devino_t ce_ino, nf_ino, f_ino; 2255 px_ib_ino_info_t *ce_ino_p, *nf_ino_p, *f_ino_p; 2256 uint64_t imu_log_enable, imu_intr_enable; 2257 uint64_t imu_log_mask, imu_intr_mask; 2258 2259 ce_ino = px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id); 2260 nf_ino = px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id); 2261 f_ino = px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id); 2262 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2263 2264 imu_log_enable = CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE); 2265 imu_intr_enable = CSR_XR(csr_base, IMU_INTERRUPT_ENABLE); 2266 2267 imu_log_mask = BITMASK(IMU_ERROR_LOG_ENABLE_FATAL_MES_NOT_EN_LOG_EN) | 2268 BITMASK(IMU_ERROR_LOG_ENABLE_NONFATAL_MES_NOT_EN_LOG_EN) | 2269 BITMASK(IMU_ERROR_LOG_ENABLE_COR_MES_NOT_EN_LOG_EN); 2270 2271 imu_intr_mask = 2272 BITMASK(IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_S_INT_EN) | 2273 BITMASK(IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_S_INT_EN) | 2274 BITMASK(IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_S_INT_EN) | 2275 BITMASK(IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_P_INT_EN) | 2276 BITMASK(IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_P_INT_EN) | 2277 BITMASK(IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_P_INT_EN); 2278 2279 switch (code) { 2280 case CB_CODE_CPR_CHKPT: 2281 /* disable imu rbne on corr/nonfatal/fatal errors */ 2282 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, 2283 imu_log_enable & (~imu_log_mask)); 2284 2285 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, 2286 imu_intr_enable & (~imu_intr_mask)); 2287 2288 /* disable CORR intr mapping */ 2289 px_ib_intr_disable(ib_p, ce_ino, IB_INTR_NOWAIT); 2290 2291 /* disable NON FATAL intr mapping */ 2292 px_ib_intr_disable(ib_p, nf_ino, IB_INTR_NOWAIT); 2293 2294 /* disable FATAL intr mapping */ 2295 px_ib_intr_disable(ib_p, f_ino, IB_INTR_NOWAIT); 2296 2297 break; 2298 2299 case CB_CODE_CPR_RESUME: 2300 mutex_enter(&ib_p->ib_ino_lst_mutex); 2301 2302 ce_ino_p = px_ib_locate_ino(ib_p, ce_ino); 2303 nf_ino_p = px_ib_locate_ino(ib_p, nf_ino); 2304 f_ino_p = px_ib_locate_ino(ib_p, f_ino); 2305 2306 /* enable CORR intr mapping */ 2307 if (ce_ino_p) 2308 px_ib_intr_enable(px_p, ce_ino_p->ino_cpuid, ce_ino); 2309 else 2310 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2311 "reenable PCIe Correctable msg intr.\n"); 2312 2313 /* enable NON FATAL intr mapping */ 2314 if (nf_ino_p) 2315 px_ib_intr_enable(px_p, nf_ino_p->ino_cpuid, nf_ino); 2316 else 2317 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2318 "reenable PCIe Non Fatal msg intr.\n"); 2319 2320 /* enable FATAL intr mapping */ 2321 if (f_ino_p) 2322 px_ib_intr_enable(px_p, f_ino_p->ino_cpuid, f_ino); 2323 else 2324 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2325 "reenable PCIe Fatal msg intr.\n"); 2326 2327 mutex_exit(&ib_p->ib_ino_lst_mutex); 2328 2329 /* enable corr/nonfatal/fatal not enable error */ 2330 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, (imu_log_enable | 2331 (imu_log_mask & px_imu_log_mask))); 2332 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, (imu_intr_enable | 2333 (imu_intr_mask & px_imu_intr_mask))); 2334 2335 break; 2336 } 2337 2338 return (B_TRUE); 2339 } 2340 2341 uint64_t 2342 px_get_rng_parent_hi_mask(px_t *px_p) 2343 { 2344 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2345 uint64_t mask; 2346 2347 switch (PX_CHIP_TYPE(pxu_p)) { 2348 case PX_CHIP_OBERON: 2349 mask = OBERON_RANGE_PROP_MASK; 2350 break; 2351 case PX_CHIP_FIRE: 2352 mask = PX_RANGE_PROP_MASK; 2353 break; 2354 default: 2355 mask = PX_RANGE_PROP_MASK; 2356 } 2357 2358 return (mask); 2359 } 2360 2361 /* 2362 * fetch chip's range propery's value 2363 */ 2364 uint64_t 2365 px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank) 2366 { 2367 uint64_t mask, range_prop; 2368 2369 mask = px_get_rng_parent_hi_mask(px_p); 2370 range_prop = (((uint64_t)(rp[bank].parent_high & mask)) << 32) | 2371 rp[bank].parent_low; 2372 2373 return (range_prop); 2374 } 2375 2376 /* 2377 * add cpr callback 2378 */ 2379 void 2380 px_cpr_add_callb(px_t *px_p) 2381 { 2382 px_p->px_cprcb_id = callb_add(px_cpr_callb, (void *)px_p, 2383 CB_CL_CPR_POST_USER, "px_cpr"); 2384 } 2385 2386 /* 2387 * remove cpr callback 2388 */ 2389 void 2390 px_cpr_rem_callb(px_t *px_p) 2391 { 2392 (void) callb_delete(px_p->px_cprcb_id); 2393 } 2394 2395 /*ARGSUSED*/ 2396 static uint_t 2397 px_hp_intr(caddr_t arg1, caddr_t arg2) 2398 { 2399 px_t *px_p = (px_t *)arg1; 2400 int rval; 2401 2402 rval = pciehpc_intr(px_p->px_dip); 2403 2404 #ifdef DEBUG 2405 if (rval == DDI_INTR_UNCLAIMED) 2406 cmn_err(CE_WARN, "%s%d: UNCLAIMED intr\n", 2407 ddi_driver_name(px_p->px_dip), 2408 ddi_get_instance(px_p->px_dip)); 2409 #endif 2410 2411 return (rval); 2412 } 2413 2414 int 2415 px_lib_hotplug_init(dev_info_t *dip, void *arg) 2416 { 2417 px_t *px_p = DIP_TO_STATE(dip); 2418 uint64_t ret; 2419 2420 if ((ret = hvio_hotplug_init(dip, arg)) == DDI_SUCCESS) { 2421 sysino_t sysino; 2422 2423 if (px_lib_intr_devino_to_sysino(px_p->px_dip, 2424 px_p->px_inos[PX_INTR_HOTPLUG], &sysino) != 2425 DDI_SUCCESS) { 2426 #ifdef DEBUG 2427 cmn_err(CE_WARN, "%s%d: devino_to_sysino fails\n", 2428 ddi_driver_name(px_p->px_dip), 2429 ddi_get_instance(px_p->px_dip)); 2430 #endif 2431 return (DDI_FAILURE); 2432 } 2433 2434 VERIFY(add_ivintr(sysino, PX_PCIEHP_PIL, 2435 (intrfunc)px_hp_intr, (caddr_t)px_p, NULL) == 0); 2436 } 2437 2438 return (ret); 2439 } 2440 2441 void 2442 px_lib_hotplug_uninit(dev_info_t *dip) 2443 { 2444 if (hvio_hotplug_uninit(dip) == DDI_SUCCESS) { 2445 px_t *px_p = DIP_TO_STATE(dip); 2446 sysino_t sysino; 2447 2448 if (px_lib_intr_devino_to_sysino(px_p->px_dip, 2449 px_p->px_inos[PX_INTR_HOTPLUG], &sysino) != 2450 DDI_SUCCESS) { 2451 #ifdef DEBUG 2452 cmn_err(CE_WARN, "%s%d: devino_to_sysino fails\n", 2453 ddi_driver_name(px_p->px_dip), 2454 ddi_get_instance(px_p->px_dip)); 2455 #endif 2456 return; 2457 } 2458 2459 rem_ivintr(sysino, NULL); 2460 } 2461 } 2462 2463 boolean_t 2464 px_lib_is_in_drain_state(px_t *px_p) 2465 { 2466 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2467 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2468 uint64_t drain_status; 2469 2470 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 2471 drain_status = CSR_BR(csr_base, DRAIN_CONTROL_STATUS, DRAIN); 2472 } else { 2473 drain_status = CSR_BR(csr_base, TLU_STATUS, DRAIN); 2474 } 2475 2476 return (drain_status); 2477 } 2478