1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * sun4u Fire Error Handling 31 */ 32 33 #include <sys/types.h> 34 #include <sys/ddi.h> 35 #include <sys/sunddi.h> 36 #include <sys/fm/protocol.h> 37 #include <sys/fm/util.h> 38 #include <sys/pcie.h> 39 #include <sys/pcie_impl.h> 40 #include "px_obj.h" 41 #include <px_regs.h> 42 #include <px_csr.h> 43 #include <sys/membar.h> 44 #include "pcie_pwr.h" 45 #include "px_lib4u.h" 46 #include "px_err.h" 47 #include "px_err_impl.h" 48 49 /* 50 * JBC error bit table 51 */ 52 #define JBC_BIT_DESC(bit, hdl, erpt) \ 53 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 54 0, \ 55 PX_ERR_BIT_HANDLE(hdl), \ 56 PX_ERPT_SEND(erpt), \ 57 PX_ERR_JBC_CLASS(bit) }, \ 58 { JBC_INTERRUPT_STATUS_ ## bit ## _S, \ 59 0, \ 60 PX_ERR_BIT_HANDLE(hdl), \ 61 PX_ERPT_SEND(erpt), \ 62 PX_ERR_JBC_CLASS(bit) 63 px_err_bit_desc_t px_err_cb_tbl[] = { 64 /* JBC FATAL - see io erpt doc, section 1.1 */ 65 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 66 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 67 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 68 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 69 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 70 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 71 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 72 73 /* JBC MERGE - see io erpt doc, section 1.2 */ 74 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 75 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 76 77 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 78 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 79 { JBC_BIT_DESC(CE_ASYN, jbc_jbusint_in, jbc_in) }, 80 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 81 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 82 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 83 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 84 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 85 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 86 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 87 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 88 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 89 90 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 91 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 92 93 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 94 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_dmcint_odcd, jbc_odcd) }, 95 { JBC_BIT_DESC(ILL_ACC_RD, jbc_dmcint_odcd, jbc_odcd) }, 96 { JBC_BIT_DESC(PIO_UNMAP, jbc_dmcint_odcd, jbc_odcd) }, 97 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 98 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 99 { JBC_BIT_DESC(ILL_ACC, jbc_dmcint_odcd, jbc_odcd) }, 100 101 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 102 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 103 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 104 105 /* JBC CSR - see io erpt doc, section 1.7 */ 106 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 107 }; 108 109 #define px_err_cb_keys \ 110 (sizeof (px_err_cb_tbl)) / (sizeof (px_err_bit_desc_t)) 111 112 /* 113 * DMC error bit tables 114 */ 115 #define IMU_BIT_DESC(bit, hdl, erpt) \ 116 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 117 0, \ 118 PX_ERR_BIT_HANDLE(hdl), \ 119 PX_ERPT_SEND(erpt), \ 120 PX_ERR_DMC_CLASS(bit) }, \ 121 { IMU_INTERRUPT_STATUS_ ## bit ## _S, \ 122 0, \ 123 PX_ERR_BIT_HANDLE(hdl), \ 124 PX_ERPT_SEND(erpt), \ 125 PX_ERR_DMC_CLASS(bit) 126 px_err_bit_desc_t px_err_imu_tbl[] = { 127 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 128 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 129 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 130 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 131 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_pme, imu_rds) }, 132 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 133 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 134 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 135 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 136 137 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 138 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 139 140 /* DMC IMU - see io erpt doc, section 2.3 */ 141 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 142 }; 143 144 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 145 146 /* mmu errors */ 147 #define MMU_BIT_DESC(bit, hdl, erpt) \ 148 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 149 0, \ 150 PX_ERR_BIT_HANDLE(hdl), \ 151 PX_ERPT_SEND(erpt), \ 152 PX_ERR_DMC_CLASS(bit) }, \ 153 { MMU_INTERRUPT_STATUS_ ## bit ## _S, \ 154 0, \ 155 PX_ERR_BIT_HANDLE(hdl), \ 156 PX_ERPT_SEND(erpt), \ 157 PX_ERR_DMC_CLASS(bit) 158 px_err_bit_desc_t px_err_mmu_tbl[] = { 159 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 160 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 161 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 162 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 163 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 164 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 165 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 166 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 167 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 168 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 169 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 170 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 171 172 /* DMC MMU - see io erpt doc, section 2.5 */ 173 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 174 }; 175 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 176 177 /* 178 * PEC error bit tables 179 */ 180 #define ILU_BIT_DESC(bit, hdl, erpt) \ 181 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 182 0, \ 183 PX_ERR_BIT_HANDLE(hdl), \ 184 PX_ERPT_SEND(erpt), \ 185 PX_ERR_PEC_CLASS(bit) }, \ 186 { ILU_INTERRUPT_STATUS_ ## bit ## _S, \ 187 0, \ 188 PX_ERR_BIT_HANDLE(hdl), \ 189 PX_ERPT_SEND(erpt), \ 190 PX_ERR_PEC_CLASS(bit) 191 px_err_bit_desc_t px_err_ilu_tbl[] = { 192 /* PEC ILU none - see io erpt doc, section 3.1 */ 193 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 194 }; 195 #define px_err_ilu_keys \ 196 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 197 198 /* 199 * PEC UE errors implementation is incomplete pending PCIE generic 200 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 201 */ 202 /* pec ue errors */ 203 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 204 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 205 0, \ 206 PX_ERR_BIT_HANDLE(hdl), \ 207 PX_ERPT_SEND(erpt), \ 208 PX_ERR_PEC_CLASS(bit) }, \ 209 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 210 0, \ 211 PX_ERR_BIT_HANDLE(hdl), \ 212 PX_ERPT_SEND(erpt), \ 213 PX_ERR_PEC_CLASS(bit) 214 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 215 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 216 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 217 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 218 219 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 220 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 221 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 222 223 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 224 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 225 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 226 227 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 228 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 229 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 230 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 231 232 /* Not used */ 233 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 234 }; 235 #define px_err_tlu_ue_keys \ 236 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 237 238 /* 239 * PEC CE errors implementation is incomplete pending PCIE generic 240 * fabric rules. 241 */ 242 /* pec ce errors */ 243 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 244 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 245 0, \ 246 PX_ERR_BIT_HANDLE(hdl), \ 247 PX_ERPT_SEND(erpt), \ 248 PX_ERR_PEC_CLASS(bit) }, \ 249 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 250 0, \ 251 PX_ERR_BIT_HANDLE(hdl), \ 252 PX_ERPT_SEND(erpt), \ 253 PX_ERR_PEC_CLASS(bit) 254 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 255 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 256 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 257 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 258 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 259 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 260 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 261 }; 262 #define px_err_tlu_ce_keys \ 263 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 264 265 /* pec oe errors */ 266 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 267 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 268 0, \ 269 PX_ERR_BIT_HANDLE(hdl), \ 270 PX_ERPT_SEND(erpt), \ 271 PX_ERR_PEC_CLASS(bit) }, \ 272 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 273 0, \ 274 PX_ERR_BIT_HANDLE(hdl), \ 275 PX_ERPT_SEND(erpt), \ 276 PX_ERR_PEC_CLASS(bit) 277 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 278 /* 279 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 280 */ 281 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 282 283 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 284 { TLU_OE_BIT_DESC(WUC, non_fatal, pciex_rx_tx_oe) }, 285 { TLU_OE_BIT_DESC(RUC, non_fatal, pciex_rx_tx_oe) }, 286 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 287 288 /* TLU Other Event - see io erpt doc, section 3.9 */ 289 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 290 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 291 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 292 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 293 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 294 { TLU_OE_BIT_DESC(LDN, non_fatal, pciex_ldn) }, 295 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_lup) }, 296 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 297 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 298 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 299 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 300 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 301 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 302 }; 303 304 #define px_err_tlu_oe_keys \ 305 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 306 307 /* 308 * All the following tables below are for LPU Interrupts. These interrupts 309 * are *NOT* error interrupts, but event status interrupts. 310 * 311 * These events are probably of most interest to: 312 * o Hotplug 313 * o Power Management 314 * o etc... 315 * 316 * There are also a few events that would be interresting for FMA. 317 * Again none of the regiseters below state that an error has occured 318 * or that data has been lost. If anything, they give status that an 319 * error is *about* to occur. examples 320 * o INT_SKP_ERR - indicates clock between fire and child is too far 321 * off and is most unlikely able to compensate 322 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 323 * HW recoverable, but will like end up as a future 324 * fabric error as well. 325 * 326 * For now, we don't care about any of these errors and should be ignore, 327 * but cleared. 328 */ 329 330 /* LPU Link Interrupt Table */ 331 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 332 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 333 0, \ 334 NULL, \ 335 NULL, \ 336 "" 337 px_err_bit_desc_t px_err_lpul_tbl[] = { 338 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 339 }; 340 #define px_err_lpul_keys \ 341 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 342 343 /* LPU Physical Interrupt Table */ 344 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 345 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 346 0, \ 347 NULL, \ 348 NULL, \ 349 "" 350 px_err_bit_desc_t px_err_lpup_tbl[] = { 351 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 352 }; 353 #define px_err_lpup_keys \ 354 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 355 356 /* LPU Receive Interrupt Table */ 357 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 358 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 359 0, \ 360 NULL, \ 361 NULL, \ 362 "" 363 px_err_bit_desc_t px_err_lpur_tbl[] = { 364 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 365 }; 366 #define px_err_lpur_keys \ 367 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 368 369 /* LPU Transmit Interrupt Table */ 370 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 371 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 372 0, \ 373 NULL, \ 374 NULL, \ 375 "" 376 px_err_bit_desc_t px_err_lpux_tbl[] = { 377 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 378 }; 379 #define px_err_lpux_keys \ 380 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 381 382 /* LPU LTSSM Interrupt Table */ 383 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 384 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 385 0, \ 386 NULL, \ 387 NULL, \ 388 "" 389 px_err_bit_desc_t px_err_lpus_tbl[] = { 390 { LPUS_BIT_DESC(ANY, NULL, NULL) } 391 }; 392 #define px_err_lpus_keys \ 393 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 394 395 /* LPU Gigablaze Glue Interrupt Table */ 396 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 397 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 398 0, \ 399 NULL, \ 400 NULL, \ 401 "" 402 px_err_bit_desc_t px_err_lpug_tbl[] = { 403 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 404 }; 405 #define px_err_lpug_keys \ 406 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 407 408 409 /* Mask and Tables */ 410 #define MnT6(pre) \ 411 B_FALSE, \ 412 &px_ ## pre ## _intr_mask, \ 413 &px_ ## pre ## _log_mask, \ 414 &px_ ## pre ## _count_mask, \ 415 px_err_ ## pre ## _tbl, \ 416 px_err_ ## pre ## _keys, \ 417 0 418 419 /* LPU Registers Addresses */ 420 #define LR4(pre) \ 421 NULL, \ 422 LPU_ ## pre ## _INTERRUPT_MASK, \ 423 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 424 LPU_ ## pre ## _INTERRUPT_AND_STATUS 425 426 /* LPU Registers Addresses with Irregularities */ 427 #define LR4_FIXME(pre) \ 428 NULL, \ 429 LPU_ ## pre ## _INTERRUPT_MASK, \ 430 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 431 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 432 433 /* TLU Registers Addresses */ 434 #define TR4(pre) \ 435 TLU_ ## pre ## _LOG_ENABLE, \ 436 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 437 TLU_ ## pre ## _INTERRUPT_STATUS, \ 438 TLU_ ## pre ## _STATUS_CLEAR 439 440 /* Registers Addresses for JBC, MMU, IMU and ILU */ 441 #define R4(pre) \ 442 pre ## _ERROR_LOG_ENABLE, \ 443 pre ## _INTERRUPT_ENABLE, \ 444 pre ## _INTERRUPT_STATUS, \ 445 pre ## _ERROR_STATUS_CLEAR 446 447 /* 448 * Register error handling tables. 449 * The ID Field (first field) is identified by an enum px_err_id_t. 450 * It is located in px_err.h 451 */ 452 px_err_reg_desc_t px_err_reg_tbl[] = { 453 { MnT6(cb), R4(JBC), "JBC Error"}, 454 { MnT6(mmu), R4(MMU), "MMU Error"}, 455 { MnT6(imu), R4(IMU), "IMU Error"}, 456 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 457 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 458 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 459 { MnT6(ilu), R4(ILU), "ILU Error"}, 460 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 461 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 462 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 463 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 464 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 465 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"} 466 }; 467 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 468 469 typedef struct px_err_ss { 470 uint64_t err_status[PX_ERR_REG_KEYS]; 471 } px_err_ss_t; 472 473 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc); 474 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 475 px_err_ss_t *ss); 476 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 477 int err, int caller); 478 479 /* 480 * px_err_cb_intr: 481 * Interrupt handler for the JBC block. 482 * o lock 483 * o create derr 484 * o px_err_handle(leaf1, with jbc) 485 * o px_err_handle(leaf2, without jbc) 486 * o dispatch (leaf1) 487 * o dispatch (leaf2) 488 * o unlock 489 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 490 */ 491 uint_t 492 px_err_cb_intr(caddr_t arg) 493 { 494 px_fault_t *px_fault_p = (px_fault_t *)arg; 495 dev_info_t *rpdip = px_fault_p->px_fh_dip; 496 dev_info_t *leafdip; 497 px_t *px_p = DIP_TO_STATE(rpdip); 498 px_cb_t *cb_p = px_p->px_cb_p; 499 int err = PX_OK; 500 int ret = DDI_FM_OK; 501 int fatal = 0; 502 int nonfatal = 0; 503 int unknown = 0; 504 int i; 505 boolean_t chkjbc = B_TRUE; 506 ddi_fm_error_t derr; 507 508 /* Create the derr */ 509 bzero(&derr, sizeof (ddi_fm_error_t)); 510 derr.fme_version = DDI_FME_VERSION; 511 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 512 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 513 514 mutex_enter(&cb_p->xbc_fm_mutex); 515 516 /* send ereport/handle/clear for ALL fire leaves */ 517 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 518 if ((px_p = cb_p->xbc_px_list[i]) == NULL) 519 continue; 520 521 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, chkjbc); 522 chkjbc = B_FALSE; 523 } 524 525 /* Check all child devices for errors on ALL fire leaves */ 526 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 527 if ((px_p = cb_p->xbc_px_list[i]) != NULL) { 528 leafdip = px_p->px_dip; 529 ret = ndi_fm_handler_dispatch(leafdip, NULL, &derr); 530 switch (ret) { 531 case DDI_FM_FATAL: 532 fatal++; 533 break; 534 case DDI_FM_NONFATAL: 535 nonfatal++; 536 break; 537 case DDI_FM_UNKNOWN: 538 unknown++; 539 break; 540 default: 541 break; 542 } 543 } 544 } 545 546 /* Set the intr state to idle for the leaf that received the mondo */ 547 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 548 INTR_IDLE_STATE); 549 550 mutex_exit(&cb_p->xbc_fm_mutex); 551 552 /* 553 * PX_FATAL_HW error is diagnosed after system recovered from 554 * HW initiated reset, therefore no furthur handling is required. 555 */ 556 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 557 PX_FM_PANIC("Fatal System Bus Error has occurred\n"); 558 559 return (DDI_INTR_CLAIMED); 560 } 561 562 /* 563 * px_err_dmc_pec_intr: 564 * Interrupt handler for the DMC/PEC block. 565 * o lock 566 * o create derr 567 * o px_err_handle(leaf, with jbc) 568 * o dispatch (leaf) 569 * o unlock 570 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 571 */ 572 uint_t 573 px_err_dmc_pec_intr(caddr_t arg) 574 { 575 px_fault_t *px_fault_p = (px_fault_t *)arg; 576 dev_info_t *rpdip = px_fault_p->px_fh_dip; 577 px_t *px_p = DIP_TO_STATE(rpdip); 578 px_cb_t *cb_p = px_p->px_cb_p; 579 int err = PX_OK; 580 int ret = DDI_FM_OK; 581 ddi_fm_error_t derr; 582 583 /* Create the derr */ 584 bzero(&derr, sizeof (ddi_fm_error_t)); 585 derr.fme_version = DDI_FME_VERSION; 586 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 587 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 588 589 mutex_enter(&cb_p->xbc_fm_mutex); 590 591 /* send ereport/handle/clear fire registers */ 592 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 593 594 /* Check all child devices for errors */ 595 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 596 597 /* Set the interrupt state to idle */ 598 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 599 INTR_IDLE_STATE); 600 601 mutex_exit(&cb_p->xbc_fm_mutex); 602 603 /* 604 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 605 * therefore it does not cause panic. 606 */ 607 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 608 PX_FM_PANIC("Fatal System Port Error has occurred\n"); 609 610 return (DDI_INTR_CLAIMED); 611 } 612 613 /* 614 * Error register are being handled by px_hlib xxx_init functions. 615 * They are also called again by px_err_add_intr for mondo62 and 63 616 * from px_cb_attach and px_attach 617 */ 618 void 619 px_err_reg_enable(px_t *px_p, px_err_id_t id) 620 { 621 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 622 uint64_t intr_mask = *reg_desc->intr_mask_p; 623 uint64_t log_mask = *reg_desc->log_mask_p; 624 caddr_t csr_base; 625 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 626 627 if (id == PX_ERR_JBC) 628 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 629 else 630 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 631 632 reg_desc->enabled = B_TRUE; 633 634 /* Enable logs if it exists */ 635 if (reg_desc->log_addr != NULL) 636 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 637 638 /* 639 * For readability you in code you set 1 to enable an interrupt. 640 * But in Fire it's backwards. You set 1 to *disable* an intr. 641 * Reverse the user tunable intr mask field. 642 * 643 * Disable All Errors 644 * Clear All Errors 645 * Enable Errors 646 */ 647 CSR_XS(csr_base, reg_desc->enable_addr, 0); 648 CSR_XS(csr_base, reg_desc->clear_addr, -1); 649 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 650 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 651 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 652 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 653 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 654 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 655 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 656 if (reg_desc->log_addr != NULL) { 657 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 658 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 659 } 660 } 661 662 void 663 px_err_reg_disable(px_t *px_p, px_err_id_t id) 664 { 665 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 666 caddr_t csr_base; 667 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 668 669 if (id == PX_ERR_JBC) 670 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_XBC]; 671 else 672 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_CSR]; 673 674 reg_desc->enabled = B_FALSE; 675 676 switch (id) { 677 case PX_ERR_JBC: 678 case PX_ERR_MMU: 679 case PX_ERR_IMU: 680 case PX_ERR_TLU_UE: 681 case PX_ERR_TLU_CE: 682 case PX_ERR_TLU_OE: 683 case PX_ERR_ILU: 684 if (reg_desc->log_addr != NULL) { 685 CSR_XS(csr_base, reg_desc->log_addr, 0); 686 } 687 CSR_XS(csr_base, reg_desc->enable_addr, 0); 688 break; 689 case PX_ERR_LPU_LINK: 690 case PX_ERR_LPU_PHY: 691 case PX_ERR_LPU_RX: 692 case PX_ERR_LPU_TX: 693 case PX_ERR_LPU_LTSSM: 694 case PX_ERR_LPU_GIGABLZ: 695 if (reg_desc->log_addr != NULL) { 696 CSR_XS(csr_base, reg_desc->log_addr, -1); 697 } 698 CSR_XS(csr_base, reg_desc->enable_addr, -1); 699 break; 700 } 701 } 702 703 /* 704 * px_err_handle: 705 * Common function called by trap, mondo and fabric intr. 706 * o Snap shot current fire registers 707 * o check for safe access 708 * o send ereport and clear snap shot registers 709 * o check severity of snap shot registers 710 * 711 * @param px_p leaf in which to check access 712 * @param derr fm err data structure to be updated 713 * @param caller PX_TRAP_CALL | PX_INTR_CALL 714 * @param chkjbc whether to handle jbc registers 715 * @return err PX_OK | PX_NONFATAL | 716 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 717 */ 718 int 719 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 720 boolean_t chkjbc) 721 { 722 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 723 px_err_ss_t ss; 724 int err = PX_OK; 725 726 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 727 728 /* snap shot the current fire registers */ 729 px_err_snapshot(px_p, &ss, chkjbc); 730 731 /* check for safe access */ 732 px_err_safeacc_check(px_p, derr); 733 734 /* send ereports/handle/clear registers */ 735 err = px_err_erpt_and_clr(px_p, derr, &ss); 736 737 /* check for error severity */ 738 err = px_err_check_severity(px_p, derr, err, caller); 739 740 /* Mark the On Trap Handle if an error occured */ 741 if (err != PX_OK) { 742 px_pec_t *pec_p = px_p->px_pec_p; 743 on_trap_data_t *otd = pec_p->pec_ontrap_data; 744 745 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 746 otd->ot_trap |= OT_DATA_ACCESS; 747 } 748 749 return (err); 750 } 751 752 /* 753 * Static function 754 */ 755 756 /* 757 * px_err_snapshot: 758 * Take a current snap shot of all the fire error registers. This includes 759 * JBC, DMC, and PEC, unless chkjbc == false; 760 * 761 * @param px_p leaf in which to take the snap shot. 762 * @param ss pre-allocated memory to store the snap shot. 763 * @param chkjbc boolean on whether to store jbc register. 764 */ 765 static void 766 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc) 767 { 768 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 769 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 770 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 771 px_err_reg_desc_t *reg_desc; 772 int reg_id; 773 774 /* snapshot JBC interrupt status */ 775 reg_id = PX_ERR_JBC; 776 if (chkjbc == B_TRUE) { 777 reg_desc = &px_err_reg_tbl[reg_id]; 778 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 779 reg_desc->status_addr); 780 } else { 781 ss->err_status[reg_id] = 0; 782 } 783 784 /* snapshot DMC/PEC interrupt status */ 785 for (reg_id = 1; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 786 reg_desc = &px_err_reg_tbl[reg_id]; 787 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 788 reg_desc->status_addr); 789 } 790 } 791 792 /* 793 * px_err_erpt_and_clr: 794 * This function does the following thing to all the fire registers based 795 * on an earlier snap shot. 796 * o Send ereport 797 * o Handle the error 798 * o Clear the error 799 * 800 * @param px_p leaf in which to take the snap shot. 801 * @param derr fm err in which the ereport is to be based on 802 * @param ss pre-allocated memory to store the snap shot. 803 */ 804 static int 805 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 806 { 807 dev_info_t *rpdip = px_p->px_dip; 808 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 809 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 810 caddr_t csr_base; 811 px_err_reg_desc_t *err_reg_tbl; 812 px_err_bit_desc_t *err_bit_tbl; 813 px_err_bit_desc_t *err_bit_desc; 814 815 uint64_t *log_mask, *count_mask; 816 uint64_t status_addr, clear_addr; 817 uint64_t ss_reg; 818 819 int (*err_handler)(); 820 int (*erpt_handler)(); 821 int reg_id, key; 822 int err = PX_OK; 823 824 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 825 826 /* send erport/handle/clear JBC errors */ 827 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 828 /* Get the correct register description table */ 829 err_reg_tbl = &px_err_reg_tbl[reg_id]; 830 831 /* Get the correct CSR BASE */ 832 if (reg_id == PX_ERR_JBC) { 833 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 834 } else { 835 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 836 } 837 838 /* Get pointers to masks and register addresses */ 839 log_mask = err_reg_tbl->log_mask_p; 840 count_mask = err_reg_tbl->count_mask_p; 841 status_addr = err_reg_tbl->status_addr; 842 clear_addr = err_reg_tbl->clear_addr; 843 ss_reg = ss->err_status[reg_id]; 844 845 /* Get the register BIT description table */ 846 err_bit_tbl = err_reg_tbl->err_bit_tbl; 847 848 /* For each known bit in the register send erpt and handle */ 849 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 850 /* Get the bit description table for this register */ 851 err_bit_desc = &err_bit_tbl[key]; 852 853 /* 854 * If the ss_reg is set for this bit, 855 * send ereport and handle 856 */ 857 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 858 /* Increment the counter if necessary */ 859 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 860 err_bit_desc->counter++; 861 } 862 863 /* Error Handle for this bit */ 864 err_handler = err_bit_desc->err_handler; 865 if (err_handler) 866 err |= err_handler(rpdip, 867 csr_base, 868 derr, 869 err_reg_tbl, 870 err_bit_desc); 871 872 /* Send the ereport if it's an UNEXPECTED err */ 873 erpt_handler = err_bit_desc->erpt_handler; 874 if (derr->fme_flag == DDI_FM_ERR_UNEXPECTED) { 875 if (erpt_handler) 876 (void) erpt_handler(rpdip, 877 csr_base, 878 ss_reg, 879 derr, 880 err_bit_desc->bit, 881 err_bit_desc->class_name); 882 } 883 } 884 885 } 886 887 /* Print register status */ 888 if (ss_reg & *log_mask) 889 DBG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 890 status_addr, ss_reg, err_reg_tbl->msg); 891 892 /* Clear the register and error */ 893 CSR_XS(csr_base, clear_addr, ss_reg); 894 } 895 896 return (err); 897 } 898 899 /* 900 * px_err_check_severity: 901 * Check the severity of the fire error based on an earlier snapshot 902 * 903 * @param px_p leaf in which to take the snap shot. 904 * @param derr fm err in which the ereport is to be based on 905 * @param ss pre-allocated memory to store the snap shot. 906 */ 907 static int 908 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 909 { 910 px_pec_t *pec_p = px_p->px_pec_p; 911 boolean_t is_safeacc = B_FALSE; 912 913 /* nothing to do if called with no error */ 914 if (err == PX_OK) 915 return (err); 916 917 /* Cautious access error handling */ 918 switch (derr->fme_flag) { 919 case DDI_FM_ERR_EXPECTED: 920 if (caller == PX_TRAP_CALL) { 921 /* 922 * for ddi_caut_get treat all events as nonfatal 923 * The trampoline will set err_ena = 0, 924 * err_status = NONFATAL. 925 */ 926 derr->fme_status = DDI_FM_NONFATAL; 927 is_safeacc = B_TRUE; 928 } else { 929 /* 930 * For ddi_caut_put treat all events as nonfatal. Here 931 * we have the handle and can call ndi_fm_acc_err_set(). 932 */ 933 derr->fme_status = DDI_FM_NONFATAL; 934 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 935 is_safeacc = B_TRUE; 936 } 937 break; 938 case DDI_FM_ERR_PEEK: 939 case DDI_FM_ERR_POKE: 940 /* 941 * For ddi_peek/poke treat all events as nonfatal. 942 */ 943 is_safeacc = B_TRUE; 944 break; 945 default: 946 is_safeacc = B_FALSE; 947 } 948 949 /* 950 * The third argument "err" is passed in as error status from checking 951 * Fire register, re-adjust error status from safe access. 952 */ 953 if (is_safeacc && !(err & PX_FATAL_GOS)) 954 return (PX_NONFATAL); 955 956 return (err); 957 } 958 959 /* predefined convenience functions */ 960 /* ARGSUSED */ 961 int 962 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 963 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 964 px_err_bit_desc_t *err_bit_descr) 965 { 966 return (PX_FATAL_HW); 967 } 968 969 /* ARGSUSED */ 970 int 971 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 972 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 973 px_err_bit_desc_t *err_bit_descr) 974 { 975 return (PX_FATAL_GOS); 976 } 977 978 /* ARGSUSED */ 979 int 980 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 981 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 982 px_err_bit_desc_t *err_bit_descr) 983 { 984 return (PX_STUCK_FATAL); 985 } 986 987 /* ARGSUSED */ 988 int 989 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 990 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 991 px_err_bit_desc_t *err_bit_descr) 992 { 993 return (PX_FATAL_SW); 994 } 995 996 /* ARGSUSED */ 997 int 998 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 999 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1000 px_err_bit_desc_t *err_bit_descr) 1001 { 1002 return (PX_NONFATAL); 1003 } 1004 1005 /* ARGSUSED */ 1006 int 1007 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1008 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1009 { 1010 return (PX_OK); 1011 } 1012 1013 /* ARGSUSED */ 1014 int 1015 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1016 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1017 { 1018 return (PX_ERR_UNKNOWN); 1019 } 1020 1021 /* ARGSUSED */ 1022 PX_ERPT_SEND_DEC(do_not) 1023 { 1024 return (PX_OK); 1025 } 1026 1027 1028 /* JBC FATAL - see io erpt doc, section 1.1 */ 1029 PX_ERPT_SEND_DEC(jbc_fatal) 1030 { 1031 char buf[FM_MAX_CLASS]; 1032 boolean_t pri = PX_ERR_IS_PRI(bit); 1033 1034 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1035 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1036 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1037 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1038 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1039 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1040 FIRE_JBC_IE, DATA_TYPE_UINT64, 1041 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1042 FIRE_JBC_IS, DATA_TYPE_UINT64, 1043 ss_reg, 1044 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1045 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1046 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1047 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1048 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1049 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1050 NULL); 1051 1052 return (PX_OK); 1053 } 1054 1055 /* JBC MERGE - see io erpt doc, section 1.2 */ 1056 PX_ERPT_SEND_DEC(jbc_merge) 1057 { 1058 char buf[FM_MAX_CLASS]; 1059 boolean_t pri = PX_ERR_IS_PRI(bit); 1060 1061 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1062 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1063 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1064 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1065 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1066 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1067 FIRE_JBC_IE, DATA_TYPE_UINT64, 1068 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1069 FIRE_JBC_IS, DATA_TYPE_UINT64, 1070 ss_reg, 1071 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1072 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1073 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1074 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1075 NULL); 1076 1077 return (PX_OK); 1078 } 1079 1080 /* 1081 * JBC Merge buffer nonfatal errors: 1082 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1083 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1084 */ 1085 /* ARGSUSED */ 1086 int 1087 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1088 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1089 px_err_bit_desc_t *err_bit_descr) 1090 { 1091 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1092 uint64_t paddr; 1093 int ret; 1094 1095 if (!pri) 1096 return (PX_FATAL_GOS); 1097 1098 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1099 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1100 1101 ret = px_handle_lookup( 1102 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1103 1104 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1105 } 1106 1107 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1108 PX_ERPT_SEND_DEC(jbc_in) 1109 { 1110 char buf[FM_MAX_CLASS]; 1111 boolean_t pri = PX_ERR_IS_PRI(bit); 1112 1113 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1114 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1115 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1116 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1117 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1118 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1119 FIRE_JBC_IE, DATA_TYPE_UINT64, 1120 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1121 FIRE_JBC_IS, DATA_TYPE_UINT64, 1122 ss_reg, 1123 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1124 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1125 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1126 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1127 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1128 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1129 NULL); 1130 1131 return (PX_OK); 1132 } 1133 1134 /* 1135 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1136 * Log Reg[42:0]. 1137 * CE async fault error: nonfatal 1138 * Jbus bus error: dma::nonfatal 1139 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1140 * Write data parity error: pio/write:M:nonfatal 1141 * Read data parity error: pio/read:M:nonfatal 1142 * Illegal NCWR bytemask: pio:write:M:nonfatal 1143 * Illegal NCRD bytemask: pio:write:M:nonfatal 1144 * Invalid jbus transaction: nonfatal 1145 */ 1146 /* ARGSUSED */ 1147 int 1148 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1149 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1150 px_err_bit_desc_t *err_bit_descr) 1151 { 1152 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1153 uint64_t paddr; 1154 int ret; 1155 1156 if (!pri) 1157 return (PX_FATAL_GOS); 1158 1159 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1160 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1161 1162 ret = px_handle_lookup( 1163 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1164 1165 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1166 } 1167 1168 1169 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1170 PX_ERPT_SEND_DEC(jbc_out) 1171 { 1172 char buf[FM_MAX_CLASS]; 1173 boolean_t pri = PX_ERR_IS_PRI(bit); 1174 1175 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1176 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1177 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1178 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1179 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1180 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1181 FIRE_JBC_IE, DATA_TYPE_UINT64, 1182 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1183 FIRE_JBC_IS, DATA_TYPE_UINT64, 1184 ss_reg, 1185 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1186 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1187 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1188 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1189 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1190 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1191 NULL); 1192 1193 return (PX_OK); 1194 } 1195 1196 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1197 PX_ERPT_SEND_DEC(jbc_odcd) 1198 { 1199 char buf[FM_MAX_CLASS]; 1200 boolean_t pri = PX_ERR_IS_PRI(bit); 1201 1202 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1203 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1204 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1205 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1206 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1207 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1208 FIRE_JBC_IE, DATA_TYPE_UINT64, 1209 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1210 FIRE_JBC_IS, DATA_TYPE_UINT64, 1211 ss_reg, 1212 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1213 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1214 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1215 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1216 NULL); 1217 1218 return (PX_OK); 1219 } 1220 1221 /* 1222 * JBC Dmcint ODCO nonfatal errer handling - 1223 * Unmapped PIO read error: pio:read:M:nonfatal 1224 * Unmapped PIO write error: pio:write:M:nonfatal 1225 * PIO data parity error: pio:write:M:nonfatal 1226 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1227 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1228 */ 1229 /* ARGSUSED */ 1230 int 1231 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1232 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1233 px_err_bit_desc_t *err_bit_descr) 1234 { 1235 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1236 uint64_t paddr; 1237 int ret; 1238 1239 if (!pri) 1240 return (PX_FATAL_GOS); 1241 1242 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1243 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1244 1245 ret = px_handle_lookup( 1246 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1247 1248 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1249 } 1250 1251 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1252 PX_ERPT_SEND_DEC(jbc_idc) 1253 { 1254 char buf[FM_MAX_CLASS]; 1255 boolean_t pri = PX_ERR_IS_PRI(bit); 1256 1257 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1258 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1259 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1260 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1261 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1262 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1263 FIRE_JBC_IE, DATA_TYPE_UINT64, 1264 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1265 FIRE_JBC_IS, DATA_TYPE_UINT64, 1266 ss_reg, 1267 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1268 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1269 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1270 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1271 NULL); 1272 1273 return (PX_OK); 1274 } 1275 1276 /* JBC CSR - see io erpt doc, section 1.7 */ 1277 PX_ERPT_SEND_DEC(jbc_csr) 1278 { 1279 char buf[FM_MAX_CLASS]; 1280 boolean_t pri = PX_ERR_IS_PRI(bit); 1281 1282 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1283 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1284 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1285 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1286 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1287 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1288 FIRE_JBC_IE, DATA_TYPE_UINT64, 1289 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1290 FIRE_JBC_IS, DATA_TYPE_UINT64, 1291 ss_reg, 1292 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1293 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1294 "jbc-error-reg", DATA_TYPE_UINT64, 1295 CSR_XR(csr_base, CSR_ERROR_LOG), 1296 NULL); 1297 1298 return (PX_OK); 1299 } 1300 1301 /* 1302 * JBC CSR errer handling - 1303 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1304 */ 1305 /* ARGSUSED */ 1306 int 1307 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1308 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1309 px_err_bit_desc_t *err_bit_descr) 1310 { 1311 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1312 uint64_t paddr; 1313 int ret; 1314 1315 if (!pri) 1316 return (PX_FATAL_GOS); 1317 1318 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1319 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1320 1321 ret = px_handle_lookup( 1322 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1323 1324 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1325 } 1326 1327 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1328 1329 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1330 PX_ERPT_SEND_DEC(imu_rds) 1331 { 1332 char buf[FM_MAX_CLASS]; 1333 boolean_t pri = PX_ERR_IS_PRI(bit); 1334 1335 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1336 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1337 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1338 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1339 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1340 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1341 FIRE_IMU_IE, DATA_TYPE_UINT64, 1342 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1343 FIRE_IMU_IS, DATA_TYPE_UINT64, 1344 ss_reg, 1345 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1346 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1347 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1348 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1349 NULL); 1350 1351 return (PX_OK); 1352 } 1353 1354 /* imu function to handle all Received but Not Enabled errors */ 1355 /* ARGSUSED */ 1356 int 1357 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1358 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1359 px_err_bit_desc_t *err_bit_descr) 1360 { 1361 uint64_t imu_log_enable, imu_intr_enable; 1362 int mask = BITMASK(err_bit_descr->bit); 1363 int err = PX_NONFATAL; 1364 1365 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1366 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1367 1368 /* 1369 * If matching bit is not set, meaning corresponding rbne not 1370 * enabled, then receiving it indicates some sort of malfunction 1371 * possibly in hardware. 1372 * 1373 * Other wise, software may have intentionally disabled certain 1374 * errors for a period of time within which the occuring of the 1375 * disabled errors become rbne, that is non fatal. 1376 */ 1377 if (!(imu_log_enable & imu_intr_enable & mask)) 1378 err = PX_FATAL_SW; 1379 1380 return (err); 1381 } 1382 1383 /* 1384 * No platforms uses PME. Any PME received is simply logged 1385 * for analysis. 1386 */ 1387 /* ARGSUSED */ 1388 int 1389 px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 1390 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1391 px_err_bit_desc_t *err_bit_descr) 1392 { 1393 px_t *px_p = DIP_TO_STATE(rpdip); 1394 1395 px_p->px_pme_ignored++; 1396 return (PX_NONFATAL); 1397 } 1398 1399 /* handle EQ overflow */ 1400 /* ARGSUSED */ 1401 int 1402 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1403 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1404 px_err_bit_desc_t *err_bit_descr) 1405 { 1406 px_t *px_p = DIP_TO_STATE(rpdip); 1407 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1408 msiqid_t eqno; 1409 pci_msiq_state_t msiq_state; 1410 int err = PX_NONFATAL; 1411 int i; 1412 1413 eqno = msiq_state_p->msiq_1st_msiq_id; 1414 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1415 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1416 DDI_SUCCESS) { 1417 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1418 err = PX_FATAL_SW; 1419 } 1420 } 1421 } 1422 1423 return (err); 1424 } 1425 1426 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1427 PX_ERPT_SEND_DEC(imu_scs) 1428 { 1429 char buf[FM_MAX_CLASS]; 1430 boolean_t pri = PX_ERR_IS_PRI(bit); 1431 1432 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1433 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1434 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1435 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1436 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1437 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1438 FIRE_IMU_IE, DATA_TYPE_UINT64, 1439 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1440 FIRE_IMU_IS, DATA_TYPE_UINT64, 1441 ss_reg, 1442 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1443 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1444 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1445 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1446 NULL); 1447 1448 return (PX_OK); 1449 } 1450 1451 /* DMC IMU - see io erpt doc, section 2.3 */ 1452 PX_ERPT_SEND_DEC(imu) 1453 { 1454 char buf[FM_MAX_CLASS]; 1455 boolean_t pri = PX_ERR_IS_PRI(bit); 1456 1457 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1458 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1459 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1460 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1461 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1462 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1463 FIRE_IMU_IE, DATA_TYPE_UINT64, 1464 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1465 FIRE_IMU_IS, DATA_TYPE_UINT64, 1466 ss_reg, 1467 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1468 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1469 NULL); 1470 1471 return (PX_OK); 1472 } 1473 1474 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1475 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1476 { 1477 char buf[FM_MAX_CLASS]; 1478 boolean_t pri = PX_ERR_IS_PRI(bit); 1479 1480 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1481 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1482 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1483 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1484 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1485 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1486 FIRE_MMU_IE, DATA_TYPE_UINT64, 1487 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1488 FIRE_MMU_IS, DATA_TYPE_UINT64, 1489 ss_reg, 1490 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1491 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1492 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1493 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1494 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1495 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1496 NULL); 1497 1498 return (PX_OK); 1499 } 1500 1501 /* DMC MMU - see io erpt doc, section 2.5 */ 1502 PX_ERPT_SEND_DEC(mmu) 1503 { 1504 char buf[FM_MAX_CLASS]; 1505 boolean_t pri = PX_ERR_IS_PRI(bit); 1506 1507 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1508 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1509 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1510 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1511 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1512 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1513 FIRE_MMU_IE, DATA_TYPE_UINT64, 1514 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1515 FIRE_MMU_IS, DATA_TYPE_UINT64, 1516 ss_reg, 1517 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1518 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1519 NULL); 1520 1521 return (PX_OK); 1522 } 1523 1524 /* imu function to handle all Received but Not Enabled errors */ 1525 int 1526 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1527 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1528 px_err_bit_desc_t *err_bit_descr) 1529 { 1530 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1531 uint64_t mmu_log_enable, mmu_intr_enable; 1532 uint64_t mask = BITMASK(err_bit_descr->bit); 1533 uint64_t mmu_tfa, mmu_ctrl; 1534 uint64_t mmu_enable_bit = 0; 1535 int err = PX_NONFATAL; 1536 int ret; 1537 1538 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1539 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1540 1541 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1542 mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1543 1544 switch (err_bit_descr->bit) { 1545 case MMU_INTERRUPT_STATUS_BYP_ERR_P: 1546 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); 1547 break; 1548 case MMU_INTERRUPT_STATUS_TRN_ERR_P: 1549 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); 1550 break; 1551 default: 1552 mmu_enable_bit = 0; 1553 break; 1554 } 1555 1556 /* 1557 * If the interrupts are enabled and Translation/Bypass Enable bit 1558 * was set, then panic. This error should not have occured. 1559 */ 1560 if (mmu_log_enable & mmu_intr_enable & 1561 (mmu_ctrl & mmu_enable_bit)) { 1562 err = PX_FATAL_SW; 1563 } else { 1564 if (!pri) 1565 return (PX_FATAL_GOS); 1566 1567 ret = px_handle_lookup( 1568 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1569 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1570 1571 /* 1572 * S/W bug - this error should always be enabled 1573 */ 1574 1575 /* enable error & intr reporting for this bit */ 1576 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1577 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1578 1579 /* enable translation access/bypass enable */ 1580 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, 1581 mmu_ctrl | mmu_enable_bit); 1582 } 1583 1584 return (err); 1585 } 1586 1587 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1588 /* ARGSUSED */ 1589 int 1590 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1591 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1592 px_err_bit_desc_t *err_bit_descr) 1593 { 1594 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1595 uint64_t mmu_tfa; 1596 uint_t ret; 1597 1598 if (!pri) 1599 return (PX_FATAL_GOS); 1600 1601 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1602 ret = px_handle_lookup( 1603 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1604 1605 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1606 } 1607 1608 /* MMU Table walk errors */ 1609 /* ARGSUSED */ 1610 int 1611 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1612 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1613 px_err_bit_desc_t *err_bit_descr) 1614 { 1615 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1616 uint64_t mmu_tfa; 1617 uint_t ret; 1618 1619 if (!pri) 1620 return (PX_FATAL_GOS); 1621 1622 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1623 ret = px_handle_lookup( 1624 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1625 1626 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1627 } 1628 1629 /* 1630 * TLU LUP event - power management code is interested in this event. 1631 */ 1632 /* ARGSUSED */ 1633 int 1634 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1635 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1636 px_err_bit_desc_t *err_bit_descr) 1637 { 1638 px_t *px_p = DIP_TO_STATE(rpdip); 1639 1640 /* 1641 * Existense of pm info indicates the power management 1642 * is interested in this event. 1643 */ 1644 if (!PCIE_PMINFO(rpdip) || !PCIE_NEXUS_PMINFO(rpdip)) 1645 return (PX_OK); 1646 1647 mutex_enter(&px_p->px_lup_lock); 1648 px_p->px_lupsoft_pending++; 1649 mutex_exit(&px_p->px_lup_lock); 1650 1651 /* 1652 * Post a soft interrupt to wake up threads waiting for this. 1653 */ 1654 ddi_trigger_softintr(px_p->px_lupsoft_id); 1655 1656 return (PX_OK); 1657 } 1658 1659 /* PEC ILU none - see io erpt doc, section 3.1 */ 1660 PX_ERPT_SEND_DEC(pec_ilu) 1661 { 1662 char buf[FM_MAX_CLASS]; 1663 boolean_t pri = PX_ERR_IS_PRI(bit); 1664 1665 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1666 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1667 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1668 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1669 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1670 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1671 FIRE_ILU_IE, DATA_TYPE_UINT64, 1672 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1673 FIRE_ILU_IS, DATA_TYPE_UINT64, 1674 ss_reg, 1675 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1676 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1677 NULL); 1678 1679 return (PX_OK); 1680 } 1681 1682 /* PCIEX UE Errors */ 1683 /* ARGSUSED */ 1684 int 1685 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 1686 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1687 px_err_bit_desc_t *err_bit_descr) 1688 { 1689 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1690 1691 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ue_gos) ? 1692 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ue, 1693 px_fabric_die_rc_ue_gos)); 1694 } 1695 1696 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.2 */ 1697 PX_ERPT_SEND_DEC(pciex_rx_ue) 1698 { 1699 char buf[FM_MAX_CLASS]; 1700 boolean_t pri = PX_ERR_IS_PRI(bit); 1701 1702 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1703 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1704 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1705 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1706 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1707 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1708 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1709 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1710 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1711 ss_reg, 1712 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1713 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1714 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1715 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1716 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1717 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1718 NULL); 1719 1720 return (PX_OK); 1721 } 1722 1723 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.3 */ 1724 PX_ERPT_SEND_DEC(pciex_tx_ue) 1725 { 1726 char buf[FM_MAX_CLASS]; 1727 boolean_t pri = PX_ERR_IS_PRI(bit); 1728 1729 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1730 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1731 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1732 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1733 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1734 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1735 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1736 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1737 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1738 ss_reg, 1739 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1740 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1741 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 1742 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 1743 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 1744 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 1745 NULL); 1746 1747 return (PX_OK); 1748 } 1749 1750 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.4 */ 1751 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 1752 { 1753 char buf[FM_MAX_CLASS]; 1754 boolean_t pri = PX_ERR_IS_PRI(bit); 1755 1756 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1757 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1758 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1759 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1760 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1761 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1762 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1763 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1764 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1765 ss_reg, 1766 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1767 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1768 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1769 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1770 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1771 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1772 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 1773 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 1774 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 1775 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 1776 NULL); 1777 1778 return (PX_OK); 1779 } 1780 1781 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 1782 PX_ERPT_SEND_DEC(pciex_ue) 1783 { 1784 char buf[FM_MAX_CLASS]; 1785 boolean_t pri = PX_ERR_IS_PRI(bit); 1786 1787 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1788 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1789 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1790 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1791 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1792 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1793 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1794 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1795 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1796 ss_reg, 1797 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1798 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1799 NULL); 1800 1801 return (PX_OK); 1802 } 1803 1804 /* PCIEX UE Errors */ 1805 /* ARGSUSED */ 1806 int 1807 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 1808 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1809 px_err_bit_desc_t *err_bit_descr) 1810 { 1811 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1812 1813 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ce_gos) ? 1814 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ce, 1815 px_fabric_die_rc_ce_gos)); 1816 } 1817 1818 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 1819 PX_ERPT_SEND_DEC(pciex_ce) 1820 { 1821 char buf[FM_MAX_CLASS]; 1822 boolean_t pri = PX_ERR_IS_PRI(bit); 1823 1824 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1825 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1826 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1827 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1828 FIRE_TLU_CELE, DATA_TYPE_UINT64, 1829 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 1830 FIRE_TLU_CIE, DATA_TYPE_UINT64, 1831 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 1832 FIRE_TLU_CIS, DATA_TYPE_UINT64, 1833 ss_reg, 1834 FIRE_TLU_CESS, DATA_TYPE_UINT64, 1835 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 1836 NULL); 1837 1838 return (PX_OK); 1839 } 1840 1841 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 1842 PX_ERPT_SEND_DEC(pciex_rx_oe) 1843 { 1844 char buf[FM_MAX_CLASS]; 1845 boolean_t pri = PX_ERR_IS_PRI(bit); 1846 1847 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1848 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1849 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1850 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1851 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1852 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1853 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1854 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1855 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1856 ss_reg, 1857 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1858 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1859 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1860 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1861 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1862 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1863 NULL); 1864 1865 return (PX_OK); 1866 } 1867 1868 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 1869 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 1870 { 1871 char buf[FM_MAX_CLASS]; 1872 boolean_t pri = PX_ERR_IS_PRI(bit); 1873 1874 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1875 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1876 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1877 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1878 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1879 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1880 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1881 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1882 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1883 ss_reg, 1884 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1885 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1886 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 1887 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1888 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 1889 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1890 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 1891 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 1892 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, 1893 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 1894 NULL); 1895 1896 return (PX_OK); 1897 } 1898 1899 /* TLU Other Event - see io erpt doc, section 3.9 */ 1900 PX_ERPT_SEND_DEC(pciex_oe) 1901 { 1902 char buf[FM_MAX_CLASS]; 1903 boolean_t pri = PX_ERR_IS_PRI(bit); 1904 1905 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1906 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1907 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1908 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1909 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1910 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1911 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1912 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1913 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1914 ss_reg, 1915 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1916 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1917 NULL); 1918 1919 return (PX_OK); 1920 } 1921 1922 /* TLU Other Event - Link Down see io erpt doc, section 3.9 */ 1923 PX_ERPT_SEND_DEC(pciex_ldn) 1924 { 1925 px_t *px_p = DIP_TO_STATE(rpdip); 1926 1927 /* 1928 * Don't post ereport, if ldn event is due to 1929 * power management. 1930 */ 1931 if (px_p->px_pm_flags & PX_LDN_EXPECTED) { 1932 px_p->px_pm_flags &= ~PX_LDN_EXPECTED; 1933 return (PX_OK); 1934 } 1935 return (PX_ERPT_SEND(pciex_oe)(rpdip, csr_base, ss_reg, derr, 1936 bit, class_name)); 1937 1938 } 1939 1940 /* TLU Other Event - Link Up see io erpt doc, section 3.9 */ 1941 PX_ERPT_SEND_DEC(pciex_lup) 1942 { 1943 px_t *px_p = DIP_TO_STATE(rpdip); 1944 1945 /* 1946 * Don't post ereport, if lup event is due to 1947 * power management. 1948 */ 1949 if (px_p->px_pm_flags & PX_LUP_EXPECTED) { 1950 px_p->px_pm_flags &= ~PX_LUP_EXPECTED; 1951 return (PX_OK); 1952 } 1953 1954 return (PX_ERPT_SEND(pciex_oe)(rpdip, csr_base, ss_reg, derr, 1955 bit, class_name)); 1956 } 1957