1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * sun4u Fire Error Handling 31 */ 32 33 #include <sys/types.h> 34 #include <sys/ddi.h> 35 #include <sys/sunddi.h> 36 #include <sys/fm/protocol.h> 37 #include <sys/fm/util.h> 38 #include <sys/pcie.h> 39 #include <sys/pcie_impl.h> 40 #include "px_obj.h" 41 #include <px_regs.h> 42 #include <px_csr.h> 43 #include <sys/membar.h> 44 #include "pcie_pwr.h" 45 #include "px_lib4u.h" 46 #include "px_err.h" 47 #include "px_err_impl.h" 48 49 /* 50 * JBC error bit table 51 */ 52 #define JBC_BIT_DESC(bit, hdl, erpt) \ 53 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 54 0, \ 55 PX_ERR_BIT_HANDLE(hdl), \ 56 PX_ERPT_SEND(erpt), \ 57 PX_ERR_JBC_CLASS(bit) }, \ 58 { JBC_INTERRUPT_STATUS_ ## bit ## _S, \ 59 0, \ 60 PX_ERR_BIT_HANDLE(hdl), \ 61 PX_ERPT_SEND(erpt), \ 62 PX_ERR_JBC_CLASS(bit) 63 px_err_bit_desc_t px_err_cb_tbl[] = { 64 /* JBC FATAL - see io erpt doc, section 1.1 */ 65 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 66 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 67 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 68 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 69 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 70 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 71 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 72 73 /* JBC MERGE - see io erpt doc, section 1.2 */ 74 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 75 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 76 77 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 78 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 79 { JBC_BIT_DESC(CE_ASYN, jbc_jbusint_in, jbc_in) }, 80 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 81 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 82 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 83 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 84 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 85 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 86 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 87 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 88 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 89 90 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 91 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 92 93 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 94 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_dmcint_odcd, jbc_odcd) }, 95 { JBC_BIT_DESC(ILL_ACC_RD, jbc_dmcint_odcd, jbc_odcd) }, 96 { JBC_BIT_DESC(PIO_UNMAP, jbc_dmcint_odcd, jbc_odcd) }, 97 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 98 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 99 { JBC_BIT_DESC(ILL_ACC, jbc_dmcint_odcd, jbc_odcd) }, 100 101 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 102 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 103 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 104 105 /* JBC CSR - see io erpt doc, section 1.7 */ 106 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 107 }; 108 109 #define px_err_cb_keys \ 110 (sizeof (px_err_cb_tbl)) / (sizeof (px_err_bit_desc_t)) 111 112 /* 113 * DMC error bit tables 114 */ 115 #define IMU_BIT_DESC(bit, hdl, erpt) \ 116 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 117 0, \ 118 PX_ERR_BIT_HANDLE(hdl), \ 119 PX_ERPT_SEND(erpt), \ 120 PX_ERR_DMC_CLASS(bit) }, \ 121 { IMU_INTERRUPT_STATUS_ ## bit ## _S, \ 122 0, \ 123 PX_ERR_BIT_HANDLE(hdl), \ 124 PX_ERPT_SEND(erpt), \ 125 PX_ERR_DMC_CLASS(bit) 126 px_err_bit_desc_t px_err_imu_tbl[] = { 127 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 128 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 129 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 130 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 131 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_pme, imu_rds) }, 132 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 133 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 134 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 135 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 136 137 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 138 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 139 140 /* DMC IMU - see io erpt doc, section 2.3 */ 141 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 142 }; 143 144 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 145 146 /* mmu errors */ 147 #define MMU_BIT_DESC(bit, hdl, erpt) \ 148 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 149 0, \ 150 PX_ERR_BIT_HANDLE(hdl), \ 151 PX_ERPT_SEND(erpt), \ 152 PX_ERR_DMC_CLASS(bit) }, \ 153 { MMU_INTERRUPT_STATUS_ ## bit ## _S, \ 154 0, \ 155 PX_ERR_BIT_HANDLE(hdl), \ 156 PX_ERPT_SEND(erpt), \ 157 PX_ERR_DMC_CLASS(bit) 158 px_err_bit_desc_t px_err_mmu_tbl[] = { 159 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 160 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 161 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 162 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 163 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 164 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 165 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 166 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 167 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 168 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 169 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 170 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 171 172 /* DMC MMU - see io erpt doc, section 2.5 */ 173 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 174 }; 175 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 176 177 /* 178 * PEC error bit tables 179 */ 180 #define ILU_BIT_DESC(bit, hdl, erpt) \ 181 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 182 0, \ 183 PX_ERR_BIT_HANDLE(hdl), \ 184 PX_ERPT_SEND(erpt), \ 185 PX_ERR_PEC_CLASS(bit) }, \ 186 { ILU_INTERRUPT_STATUS_ ## bit ## _S, \ 187 0, \ 188 PX_ERR_BIT_HANDLE(hdl), \ 189 PX_ERPT_SEND(erpt), \ 190 PX_ERR_PEC_CLASS(bit) 191 px_err_bit_desc_t px_err_ilu_tbl[] = { 192 /* PEC ILU none - see io erpt doc, section 3.1 */ 193 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 194 }; 195 #define px_err_ilu_keys \ 196 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 197 198 /* 199 * PEC UE errors implementation is incomplete pending PCIE generic 200 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 201 */ 202 /* pec ue errors */ 203 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 204 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 205 0, \ 206 PX_ERR_BIT_HANDLE(hdl), \ 207 PX_ERPT_SEND(erpt), \ 208 PX_ERR_PEC_CLASS(bit) }, \ 209 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 210 0, \ 211 PX_ERR_BIT_HANDLE(hdl), \ 212 PX_ERPT_SEND(erpt), \ 213 PX_ERR_PEC_CLASS(bit) 214 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 215 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 216 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 217 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 218 219 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 220 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 221 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 222 223 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 224 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 225 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 226 227 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 228 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 229 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 230 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 231 232 /* Not used */ 233 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 234 }; 235 #define px_err_tlu_ue_keys \ 236 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 237 238 /* 239 * PEC CE errors implementation is incomplete pending PCIE generic 240 * fabric rules. 241 */ 242 /* pec ce errors */ 243 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 244 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 245 0, \ 246 PX_ERR_BIT_HANDLE(hdl), \ 247 PX_ERPT_SEND(erpt), \ 248 PX_ERR_PEC_CLASS(bit) }, \ 249 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 250 0, \ 251 PX_ERR_BIT_HANDLE(hdl), \ 252 PX_ERPT_SEND(erpt), \ 253 PX_ERR_PEC_CLASS(bit) 254 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 255 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 256 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 257 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 258 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 259 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 260 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 261 }; 262 #define px_err_tlu_ce_keys \ 263 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 264 265 /* pec oe errors */ 266 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 267 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 268 0, \ 269 PX_ERR_BIT_HANDLE(hdl), \ 270 PX_ERPT_SEND(erpt), \ 271 PX_ERR_PEC_CLASS(bit) }, \ 272 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 273 0, \ 274 PX_ERR_BIT_HANDLE(hdl), \ 275 PX_ERPT_SEND(erpt), \ 276 PX_ERR_PEC_CLASS(bit) 277 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 278 /* 279 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 280 */ 281 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 282 283 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 284 { TLU_OE_BIT_DESC(WUC, non_fatal, pciex_rx_tx_oe) }, 285 { TLU_OE_BIT_DESC(RUC, non_fatal, pciex_rx_tx_oe) }, 286 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 287 288 /* TLU Other Event - see io erpt doc, section 3.9 */ 289 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 290 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 291 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 292 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 293 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 294 { TLU_OE_BIT_DESC(LDN, tlu_ldn, pciex_oe) }, 295 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_oe) }, 296 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 297 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 298 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 299 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 300 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 301 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 302 }; 303 304 #define px_err_tlu_oe_keys \ 305 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 306 307 /* 308 * All the following tables below are for LPU Interrupts. These interrupts 309 * are *NOT* error interrupts, but event status interrupts. 310 * 311 * These events are probably of most interest to: 312 * o Hotplug 313 * o Power Management 314 * o etc... 315 * 316 * There are also a few events that would be interresting for FMA. 317 * Again none of the regiseters below state that an error has occured 318 * or that data has been lost. If anything, they give status that an 319 * error is *about* to occur. examples 320 * o INT_SKP_ERR - indicates clock between fire and child is too far 321 * off and is most unlikely able to compensate 322 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 323 * HW recoverable, but will like end up as a future 324 * fabric error as well. 325 * 326 * For now, we don't care about any of these errors and should be ignore, 327 * but cleared. 328 */ 329 330 /* LPU Link Interrupt Table */ 331 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 332 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 333 0, \ 334 NULL, \ 335 NULL, \ 336 "" 337 px_err_bit_desc_t px_err_lpul_tbl[] = { 338 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 339 }; 340 #define px_err_lpul_keys \ 341 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 342 343 /* LPU Physical Interrupt Table */ 344 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 345 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 346 0, \ 347 NULL, \ 348 NULL, \ 349 "" 350 px_err_bit_desc_t px_err_lpup_tbl[] = { 351 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 352 }; 353 #define px_err_lpup_keys \ 354 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 355 356 /* LPU Receive Interrupt Table */ 357 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 358 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 359 0, \ 360 NULL, \ 361 NULL, \ 362 "" 363 px_err_bit_desc_t px_err_lpur_tbl[] = { 364 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 365 }; 366 #define px_err_lpur_keys \ 367 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 368 369 /* LPU Transmit Interrupt Table */ 370 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 371 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 372 0, \ 373 NULL, \ 374 NULL, \ 375 "" 376 px_err_bit_desc_t px_err_lpux_tbl[] = { 377 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 378 }; 379 #define px_err_lpux_keys \ 380 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 381 382 /* LPU LTSSM Interrupt Table */ 383 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 384 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 385 0, \ 386 NULL, \ 387 NULL, \ 388 "" 389 px_err_bit_desc_t px_err_lpus_tbl[] = { 390 { LPUS_BIT_DESC(ANY, NULL, NULL) } 391 }; 392 #define px_err_lpus_keys \ 393 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 394 395 /* LPU Gigablaze Glue Interrupt Table */ 396 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 397 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 398 0, \ 399 NULL, \ 400 NULL, \ 401 "" 402 px_err_bit_desc_t px_err_lpug_tbl[] = { 403 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 404 }; 405 #define px_err_lpug_keys \ 406 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 407 408 409 /* Mask and Tables */ 410 #define MnT6(pre) \ 411 B_FALSE, \ 412 &px_ ## pre ## _intr_mask, \ 413 &px_ ## pre ## _log_mask, \ 414 &px_ ## pre ## _count_mask, \ 415 px_err_ ## pre ## _tbl, \ 416 px_err_ ## pre ## _keys, \ 417 0 418 419 /* LPU Registers Addresses */ 420 #define LR4(pre) \ 421 NULL, \ 422 LPU_ ## pre ## _INTERRUPT_MASK, \ 423 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 424 LPU_ ## pre ## _INTERRUPT_AND_STATUS 425 426 /* LPU Registers Addresses with Irregularities */ 427 #define LR4_FIXME(pre) \ 428 NULL, \ 429 LPU_ ## pre ## _INTERRUPT_MASK, \ 430 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 431 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 432 433 /* TLU Registers Addresses */ 434 #define TR4(pre) \ 435 TLU_ ## pre ## _LOG_ENABLE, \ 436 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 437 TLU_ ## pre ## _INTERRUPT_STATUS, \ 438 TLU_ ## pre ## _STATUS_CLEAR 439 440 /* Registers Addresses for JBC, MMU, IMU and ILU */ 441 #define R4(pre) \ 442 pre ## _ERROR_LOG_ENABLE, \ 443 pre ## _INTERRUPT_ENABLE, \ 444 pre ## _INTERRUPT_STATUS, \ 445 pre ## _ERROR_STATUS_CLEAR 446 447 /* 448 * Register error handling tables. 449 * The ID Field (first field) is identified by an enum px_err_id_t. 450 * It is located in px_err.h 451 */ 452 px_err_reg_desc_t px_err_reg_tbl[] = { 453 { MnT6(cb), R4(JBC), "JBC Error"}, 454 { MnT6(mmu), R4(MMU), "MMU Error"}, 455 { MnT6(imu), R4(IMU), "IMU Error"}, 456 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 457 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 458 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 459 { MnT6(ilu), R4(ILU), "ILU Error"}, 460 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 461 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 462 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 463 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 464 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 465 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"} 466 }; 467 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 468 469 typedef struct px_err_ss { 470 uint64_t err_status[PX_ERR_REG_KEYS]; 471 } px_err_ss_t; 472 473 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc); 474 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 475 px_err_ss_t *ss); 476 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 477 int err, int caller); 478 479 /* 480 * px_err_cb_intr: 481 * Interrupt handler for the JBC block. 482 * o lock 483 * o create derr 484 * o px_err_handle(leaf1, with jbc) 485 * o px_err_handle(leaf2, without jbc) 486 * o dispatch (leaf1) 487 * o dispatch (leaf2) 488 * o unlock 489 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 490 */ 491 uint_t 492 px_err_cb_intr(caddr_t arg) 493 { 494 px_fault_t *px_fault_p = (px_fault_t *)arg; 495 dev_info_t *rpdip = px_fault_p->px_fh_dip; 496 dev_info_t *leafdip; 497 px_t *px_p = DIP_TO_STATE(rpdip); 498 px_cb_t *cb_p = px_p->px_cb_p; 499 int err = PX_OK; 500 int ret = DDI_FM_OK; 501 int fatal = 0; 502 int nonfatal = 0; 503 int unknown = 0; 504 int i; 505 boolean_t chkjbc = B_TRUE; 506 ddi_fm_error_t derr; 507 508 /* Create the derr */ 509 bzero(&derr, sizeof (ddi_fm_error_t)); 510 derr.fme_version = DDI_FME_VERSION; 511 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 512 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 513 514 mutex_enter(&cb_p->xbc_fm_mutex); 515 516 /* send ereport/handle/clear for ALL fire leaves */ 517 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 518 if ((px_p = cb_p->xbc_px_list[i]) == NULL) 519 continue; 520 521 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, chkjbc); 522 chkjbc = B_FALSE; 523 } 524 525 /* Check all child devices for errors on ALL fire leaves */ 526 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 527 if ((px_p = cb_p->xbc_px_list[i]) != NULL) { 528 leafdip = px_p->px_dip; 529 ret = ndi_fm_handler_dispatch(leafdip, NULL, &derr); 530 switch (ret) { 531 case DDI_FM_FATAL: 532 fatal++; 533 break; 534 case DDI_FM_NONFATAL: 535 nonfatal++; 536 break; 537 case DDI_FM_UNKNOWN: 538 unknown++; 539 break; 540 default: 541 break; 542 } 543 } 544 } 545 546 /* Set the intr state to idle for the leaf that received the mondo */ 547 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 548 INTR_IDLE_STATE); 549 550 mutex_exit(&cb_p->xbc_fm_mutex); 551 552 /* 553 * PX_FATAL_HW error is diagnosed after system recovered from 554 * HW initiated reset, therefore no furthur handling is required. 555 */ 556 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 557 PX_FM_PANIC("Fatal System Bus Error has occurred\n"); 558 559 return (DDI_INTR_CLAIMED); 560 } 561 562 /* 563 * px_err_dmc_pec_intr: 564 * Interrupt handler for the DMC/PEC block. 565 * o lock 566 * o create derr 567 * o px_err_handle(leaf, with jbc) 568 * o dispatch (leaf) 569 * o unlock 570 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 571 */ 572 uint_t 573 px_err_dmc_pec_intr(caddr_t arg) 574 { 575 px_fault_t *px_fault_p = (px_fault_t *)arg; 576 dev_info_t *rpdip = px_fault_p->px_fh_dip; 577 px_t *px_p = DIP_TO_STATE(rpdip); 578 px_cb_t *cb_p = px_p->px_cb_p; 579 int err = PX_OK; 580 int ret = DDI_FM_OK; 581 ddi_fm_error_t derr; 582 583 /* Create the derr */ 584 bzero(&derr, sizeof (ddi_fm_error_t)); 585 derr.fme_version = DDI_FME_VERSION; 586 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 587 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 588 589 mutex_enter(&cb_p->xbc_fm_mutex); 590 591 /* send ereport/handle/clear fire registers */ 592 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 593 594 /* Check all child devices for errors */ 595 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 596 597 /* Set the interrupt state to idle */ 598 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 599 INTR_IDLE_STATE); 600 601 mutex_exit(&cb_p->xbc_fm_mutex); 602 603 /* 604 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 605 * therefore it does not cause panic. 606 */ 607 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 608 PX_FM_PANIC("Fatal System Port Error has occurred\n"); 609 610 return (DDI_INTR_CLAIMED); 611 } 612 613 /* 614 * Error register are being handled by px_hlib xxx_init functions. 615 * They are also called again by px_err_add_intr for mondo62 and 63 616 * from px_cb_attach and px_attach 617 */ 618 void 619 px_err_reg_enable(px_t *px_p, px_err_id_t id) 620 { 621 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 622 uint64_t intr_mask = *reg_desc->intr_mask_p; 623 uint64_t log_mask = *reg_desc->log_mask_p; 624 caddr_t csr_base; 625 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 626 627 if (id == PX_ERR_JBC) 628 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 629 else 630 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 631 632 reg_desc->enabled = B_TRUE; 633 634 /* Enable logs if it exists */ 635 if (reg_desc->log_addr != NULL) 636 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 637 638 /* 639 * For readability you in code you set 1 to enable an interrupt. 640 * But in Fire it's backwards. You set 1 to *disable* an intr. 641 * Reverse the user tunable intr mask field. 642 * 643 * Disable All Errors 644 * Clear All Errors 645 * Enable Errors 646 */ 647 CSR_XS(csr_base, reg_desc->enable_addr, 0); 648 CSR_XS(csr_base, reg_desc->clear_addr, -1); 649 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 650 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 651 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 652 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 653 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 654 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 655 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 656 if (reg_desc->log_addr != NULL) { 657 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 658 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 659 } 660 } 661 662 void 663 px_err_reg_disable(px_t *px_p, px_err_id_t id) 664 { 665 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 666 caddr_t csr_base; 667 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 668 669 if (id == PX_ERR_JBC) 670 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_XBC]; 671 else 672 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_CSR]; 673 674 reg_desc->enabled = B_FALSE; 675 676 switch (id) { 677 case PX_ERR_JBC: 678 case PX_ERR_MMU: 679 case PX_ERR_IMU: 680 case PX_ERR_TLU_UE: 681 case PX_ERR_TLU_CE: 682 case PX_ERR_TLU_OE: 683 case PX_ERR_ILU: 684 if (reg_desc->log_addr != NULL) { 685 CSR_XS(csr_base, reg_desc->log_addr, 0); 686 } 687 CSR_XS(csr_base, reg_desc->enable_addr, 0); 688 break; 689 case PX_ERR_LPU_LINK: 690 case PX_ERR_LPU_PHY: 691 case PX_ERR_LPU_RX: 692 case PX_ERR_LPU_TX: 693 case PX_ERR_LPU_LTSSM: 694 case PX_ERR_LPU_GIGABLZ: 695 if (reg_desc->log_addr != NULL) { 696 CSR_XS(csr_base, reg_desc->log_addr, -1); 697 } 698 CSR_XS(csr_base, reg_desc->enable_addr, -1); 699 break; 700 } 701 } 702 703 /* 704 * px_err_handle: 705 * Common function called by trap, mondo and fabric intr. 706 * o Snap shot current fire registers 707 * o check for safe access 708 * o send ereport and clear snap shot registers 709 * o check severity of snap shot registers 710 * 711 * @param px_p leaf in which to check access 712 * @param derr fm err data structure to be updated 713 * @param caller PX_TRAP_CALL | PX_INTR_CALL 714 * @param chkjbc whether to handle jbc registers 715 * @return err PX_OK | PX_NONFATAL | 716 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 717 */ 718 int 719 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 720 boolean_t chkjbc) 721 { 722 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 723 px_err_ss_t ss; 724 int err = PX_OK; 725 726 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 727 728 /* snap shot the current fire registers */ 729 px_err_snapshot(px_p, &ss, chkjbc); 730 731 /* check for safe access */ 732 px_err_safeacc_check(px_p, derr); 733 734 /* send ereports/handle/clear registers */ 735 err = px_err_erpt_and_clr(px_p, derr, &ss); 736 737 /* check for error severity */ 738 err = px_err_check_severity(px_p, derr, err, caller); 739 740 /* Mark the On Trap Handle if an error occured */ 741 if (err != PX_OK) { 742 px_pec_t *pec_p = px_p->px_pec_p; 743 on_trap_data_t *otd = pec_p->pec_ontrap_data; 744 745 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 746 otd->ot_trap |= OT_DATA_ACCESS; 747 } 748 749 return (err); 750 } 751 752 /* 753 * Static function 754 */ 755 756 /* 757 * px_err_snapshot: 758 * Take a current snap shot of all the fire error registers. This includes 759 * JBC, DMC, and PEC, unless chkjbc == false; 760 * 761 * @param px_p leaf in which to take the snap shot. 762 * @param ss pre-allocated memory to store the snap shot. 763 * @param chkjbc boolean on whether to store jbc register. 764 */ 765 static void 766 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc) 767 { 768 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 769 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 770 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 771 px_err_reg_desc_t *reg_desc; 772 int reg_id; 773 774 /* snapshot JBC interrupt status */ 775 reg_id = PX_ERR_JBC; 776 if (chkjbc == B_TRUE) { 777 reg_desc = &px_err_reg_tbl[reg_id]; 778 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 779 reg_desc->status_addr); 780 } else { 781 ss->err_status[reg_id] = 0; 782 } 783 784 /* snapshot DMC/PEC interrupt status */ 785 for (reg_id = 1; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 786 reg_desc = &px_err_reg_tbl[reg_id]; 787 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 788 reg_desc->status_addr); 789 } 790 } 791 792 /* 793 * px_err_erpt_and_clr: 794 * This function does the following thing to all the fire registers based 795 * on an earlier snap shot. 796 * o Send ereport 797 * o Handle the error 798 * o Clear the error 799 * 800 * @param px_p leaf in which to take the snap shot. 801 * @param derr fm err in which the ereport is to be based on 802 * @param ss pre-allocated memory to store the snap shot. 803 */ 804 static int 805 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 806 { 807 dev_info_t *rpdip = px_p->px_dip; 808 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 809 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 810 caddr_t csr_base; 811 px_err_reg_desc_t *err_reg_tbl; 812 px_err_bit_desc_t *err_bit_tbl; 813 px_err_bit_desc_t *err_bit_desc; 814 815 uint64_t *log_mask, *count_mask; 816 uint64_t status_addr, clear_addr; 817 uint64_t ss_reg; 818 819 int (*err_handler)(); 820 int (*erpt_handler)(); 821 int reg_id, key; 822 int err = PX_OK; 823 int biterr; 824 825 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 826 827 /* send erport/handle/clear JBC errors */ 828 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 829 /* Get the correct register description table */ 830 err_reg_tbl = &px_err_reg_tbl[reg_id]; 831 832 /* Get the correct CSR BASE */ 833 if (reg_id == PX_ERR_JBC) { 834 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 835 } else { 836 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 837 } 838 839 /* Get pointers to masks and register addresses */ 840 log_mask = err_reg_tbl->log_mask_p; 841 count_mask = err_reg_tbl->count_mask_p; 842 status_addr = err_reg_tbl->status_addr; 843 clear_addr = err_reg_tbl->clear_addr; 844 ss_reg = ss->err_status[reg_id]; 845 846 /* Get the register BIT description table */ 847 err_bit_tbl = err_reg_tbl->err_bit_tbl; 848 849 /* For each known bit in the register send erpt and handle */ 850 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 851 /* Get the bit description table for this register */ 852 err_bit_desc = &err_bit_tbl[key]; 853 854 /* 855 * If the ss_reg is set for this bit, 856 * send ereport and handle 857 */ 858 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 859 /* Increment the counter if necessary */ 860 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 861 err_bit_desc->counter++; 862 } 863 864 /* Error Handle for this bit */ 865 err_handler = err_bit_desc->err_handler; 866 if (err_handler) { 867 biterr = err_handler(rpdip, 868 csr_base, 869 derr, 870 err_reg_tbl, 871 err_bit_desc); 872 err |= biterr; 873 } 874 875 /* Send the ereport if it's an UNEXPECTED err */ 876 erpt_handler = err_bit_desc->erpt_handler; 877 if ((derr->fme_flag == DDI_FM_ERR_UNEXPECTED) && 878 (biterr != PX_OK)) { 879 if (erpt_handler) 880 (void) erpt_handler(rpdip, 881 csr_base, 882 ss_reg, 883 derr, 884 err_bit_desc->bit, 885 err_bit_desc->class_name); 886 } 887 } 888 889 } 890 891 /* Print register status */ 892 if (ss_reg & *log_mask) 893 DBG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 894 status_addr, ss_reg, err_reg_tbl->msg); 895 896 /* Clear the register and error */ 897 CSR_XS(csr_base, clear_addr, ss_reg); 898 } 899 900 return (err); 901 } 902 903 /* 904 * px_err_check_severity: 905 * Check the severity of the fire error based on an earlier snapshot 906 * 907 * @param px_p leaf in which to take the snap shot. 908 * @param derr fm err in which the ereport is to be based on 909 * @param ss pre-allocated memory to store the snap shot. 910 */ 911 static int 912 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 913 { 914 px_pec_t *pec_p = px_p->px_pec_p; 915 boolean_t is_safeacc = B_FALSE; 916 917 /* nothing to do if called with no error */ 918 if (err == PX_OK) 919 return (err); 920 921 /* Cautious access error handling */ 922 switch (derr->fme_flag) { 923 case DDI_FM_ERR_EXPECTED: 924 if (caller == PX_TRAP_CALL) { 925 /* 926 * for ddi_caut_get treat all events as nonfatal 927 * The trampoline will set err_ena = 0, 928 * err_status = NONFATAL. 929 */ 930 derr->fme_status = DDI_FM_NONFATAL; 931 is_safeacc = B_TRUE; 932 } else { 933 /* 934 * For ddi_caut_put treat all events as nonfatal. Here 935 * we have the handle and can call ndi_fm_acc_err_set(). 936 */ 937 derr->fme_status = DDI_FM_NONFATAL; 938 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 939 is_safeacc = B_TRUE; 940 } 941 break; 942 case DDI_FM_ERR_PEEK: 943 case DDI_FM_ERR_POKE: 944 /* 945 * For ddi_peek/poke treat all events as nonfatal. 946 */ 947 is_safeacc = B_TRUE; 948 break; 949 default: 950 is_safeacc = B_FALSE; 951 } 952 953 /* 954 * The third argument "err" is passed in as error status from checking 955 * Fire register, re-adjust error status from safe access. 956 */ 957 if (is_safeacc && !(err & PX_FATAL_GOS)) 958 return (PX_NONFATAL); 959 960 return (err); 961 } 962 963 /* predefined convenience functions */ 964 /* ARGSUSED */ 965 int 966 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 967 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 968 px_err_bit_desc_t *err_bit_descr) 969 { 970 return (PX_FATAL_HW); 971 } 972 973 /* ARGSUSED */ 974 int 975 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 976 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 977 px_err_bit_desc_t *err_bit_descr) 978 { 979 return (PX_FATAL_GOS); 980 } 981 982 /* ARGSUSED */ 983 int 984 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 985 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 986 px_err_bit_desc_t *err_bit_descr) 987 { 988 return (PX_STUCK_FATAL); 989 } 990 991 /* ARGSUSED */ 992 int 993 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 994 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 995 px_err_bit_desc_t *err_bit_descr) 996 { 997 return (PX_FATAL_SW); 998 } 999 1000 /* ARGSUSED */ 1001 int 1002 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 1003 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1004 px_err_bit_desc_t *err_bit_descr) 1005 { 1006 return (PX_NONFATAL); 1007 } 1008 1009 /* ARGSUSED */ 1010 int 1011 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1012 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1013 { 1014 return (PX_OK); 1015 } 1016 1017 /* ARGSUSED */ 1018 int 1019 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1020 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1021 { 1022 return (PX_ERR_UNKNOWN); 1023 } 1024 1025 /* ARGSUSED */ 1026 PX_ERPT_SEND_DEC(do_not) 1027 { 1028 return (PX_OK); 1029 } 1030 1031 1032 /* JBC FATAL - see io erpt doc, section 1.1 */ 1033 PX_ERPT_SEND_DEC(jbc_fatal) 1034 { 1035 char buf[FM_MAX_CLASS]; 1036 boolean_t pri = PX_ERR_IS_PRI(bit); 1037 1038 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1039 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1040 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1041 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1042 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1043 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1044 FIRE_JBC_IE, DATA_TYPE_UINT64, 1045 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1046 FIRE_JBC_IS, DATA_TYPE_UINT64, 1047 ss_reg, 1048 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1049 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1050 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1051 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1052 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1053 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1054 NULL); 1055 1056 return (PX_OK); 1057 } 1058 1059 /* JBC MERGE - see io erpt doc, section 1.2 */ 1060 PX_ERPT_SEND_DEC(jbc_merge) 1061 { 1062 char buf[FM_MAX_CLASS]; 1063 boolean_t pri = PX_ERR_IS_PRI(bit); 1064 1065 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1066 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1067 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1068 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1069 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1070 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1071 FIRE_JBC_IE, DATA_TYPE_UINT64, 1072 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1073 FIRE_JBC_IS, DATA_TYPE_UINT64, 1074 ss_reg, 1075 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1076 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1077 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1078 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1079 NULL); 1080 1081 return (PX_OK); 1082 } 1083 1084 /* 1085 * JBC Merge buffer nonfatal errors: 1086 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1087 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1088 */ 1089 /* ARGSUSED */ 1090 int 1091 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1092 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1093 px_err_bit_desc_t *err_bit_descr) 1094 { 1095 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1096 uint64_t paddr; 1097 int ret; 1098 1099 if (!pri) 1100 return (PX_FATAL_GOS); 1101 1102 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1103 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1104 1105 ret = px_handle_lookup( 1106 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1107 1108 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1109 } 1110 1111 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1112 PX_ERPT_SEND_DEC(jbc_in) 1113 { 1114 char buf[FM_MAX_CLASS]; 1115 boolean_t pri = PX_ERR_IS_PRI(bit); 1116 1117 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1118 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1119 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1120 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1121 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1122 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1123 FIRE_JBC_IE, DATA_TYPE_UINT64, 1124 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1125 FIRE_JBC_IS, DATA_TYPE_UINT64, 1126 ss_reg, 1127 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1128 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1129 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1130 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1131 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1132 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1133 NULL); 1134 1135 return (PX_OK); 1136 } 1137 1138 /* 1139 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1140 * Log Reg[42:0]. 1141 * CE async fault error: nonfatal 1142 * Jbus bus error: dma::nonfatal 1143 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1144 * Write data parity error: pio/write:M:nonfatal 1145 * Read data parity error: pio/read:M:nonfatal 1146 * Illegal NCWR bytemask: pio:write:M:nonfatal 1147 * Illegal NCRD bytemask: pio:write:M:nonfatal 1148 * Invalid jbus transaction: nonfatal 1149 */ 1150 /* ARGSUSED */ 1151 int 1152 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1153 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1154 px_err_bit_desc_t *err_bit_descr) 1155 { 1156 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1157 uint64_t paddr; 1158 int ret; 1159 1160 if (!pri) 1161 return (PX_FATAL_GOS); 1162 1163 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1164 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1165 1166 ret = px_handle_lookup( 1167 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1168 1169 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1170 } 1171 1172 1173 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1174 PX_ERPT_SEND_DEC(jbc_out) 1175 { 1176 char buf[FM_MAX_CLASS]; 1177 boolean_t pri = PX_ERR_IS_PRI(bit); 1178 1179 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1180 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1181 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1182 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1183 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1184 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1185 FIRE_JBC_IE, DATA_TYPE_UINT64, 1186 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1187 FIRE_JBC_IS, DATA_TYPE_UINT64, 1188 ss_reg, 1189 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1190 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1191 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1192 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1193 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1194 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1195 NULL); 1196 1197 return (PX_OK); 1198 } 1199 1200 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1201 PX_ERPT_SEND_DEC(jbc_odcd) 1202 { 1203 char buf[FM_MAX_CLASS]; 1204 boolean_t pri = PX_ERR_IS_PRI(bit); 1205 1206 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1207 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1208 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1209 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1210 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1211 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1212 FIRE_JBC_IE, DATA_TYPE_UINT64, 1213 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1214 FIRE_JBC_IS, DATA_TYPE_UINT64, 1215 ss_reg, 1216 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1217 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1218 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1219 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1220 NULL); 1221 1222 return (PX_OK); 1223 } 1224 1225 /* 1226 * JBC Dmcint ODCO nonfatal errer handling - 1227 * Unmapped PIO read error: pio:read:M:nonfatal 1228 * Unmapped PIO write error: pio:write:M:nonfatal 1229 * PIO data parity error: pio:write:M:nonfatal 1230 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1231 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1232 */ 1233 /* ARGSUSED */ 1234 int 1235 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1236 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1237 px_err_bit_desc_t *err_bit_descr) 1238 { 1239 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1240 uint64_t paddr; 1241 int ret; 1242 1243 if (!pri) 1244 return (PX_FATAL_GOS); 1245 1246 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1247 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1248 1249 ret = px_handle_lookup( 1250 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1251 1252 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1253 } 1254 1255 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1256 PX_ERPT_SEND_DEC(jbc_idc) 1257 { 1258 char buf[FM_MAX_CLASS]; 1259 boolean_t pri = PX_ERR_IS_PRI(bit); 1260 1261 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1262 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1263 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1264 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1265 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1266 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1267 FIRE_JBC_IE, DATA_TYPE_UINT64, 1268 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1269 FIRE_JBC_IS, DATA_TYPE_UINT64, 1270 ss_reg, 1271 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1272 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1273 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1274 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1275 NULL); 1276 1277 return (PX_OK); 1278 } 1279 1280 /* JBC CSR - see io erpt doc, section 1.7 */ 1281 PX_ERPT_SEND_DEC(jbc_csr) 1282 { 1283 char buf[FM_MAX_CLASS]; 1284 boolean_t pri = PX_ERR_IS_PRI(bit); 1285 1286 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1287 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1288 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1289 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1290 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1291 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1292 FIRE_JBC_IE, DATA_TYPE_UINT64, 1293 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1294 FIRE_JBC_IS, DATA_TYPE_UINT64, 1295 ss_reg, 1296 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1297 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1298 "jbc-error-reg", DATA_TYPE_UINT64, 1299 CSR_XR(csr_base, CSR_ERROR_LOG), 1300 NULL); 1301 1302 return (PX_OK); 1303 } 1304 1305 /* 1306 * JBC CSR errer handling - 1307 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1308 */ 1309 /* ARGSUSED */ 1310 int 1311 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1312 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1313 px_err_bit_desc_t *err_bit_descr) 1314 { 1315 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1316 uint64_t paddr; 1317 int ret; 1318 1319 if (!pri) 1320 return (PX_FATAL_GOS); 1321 1322 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1323 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1324 1325 ret = px_handle_lookup( 1326 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1327 1328 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1329 } 1330 1331 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1332 1333 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1334 PX_ERPT_SEND_DEC(imu_rds) 1335 { 1336 char buf[FM_MAX_CLASS]; 1337 boolean_t pri = PX_ERR_IS_PRI(bit); 1338 1339 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1340 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1341 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1342 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1343 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1344 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1345 FIRE_IMU_IE, DATA_TYPE_UINT64, 1346 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1347 FIRE_IMU_IS, DATA_TYPE_UINT64, 1348 ss_reg, 1349 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1350 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1351 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1352 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1353 NULL); 1354 1355 return (PX_OK); 1356 } 1357 1358 /* imu function to handle all Received but Not Enabled errors */ 1359 /* ARGSUSED */ 1360 int 1361 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1362 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1363 px_err_bit_desc_t *err_bit_descr) 1364 { 1365 uint64_t imu_log_enable, imu_intr_enable; 1366 int mask = BITMASK(err_bit_descr->bit); 1367 int err = PX_NONFATAL; 1368 1369 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1370 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1371 1372 /* 1373 * If matching bit is not set, meaning corresponding rbne not 1374 * enabled, then receiving it indicates some sort of malfunction 1375 * possibly in hardware. 1376 * 1377 * Other wise, software may have intentionally disabled certain 1378 * errors for a period of time within which the occuring of the 1379 * disabled errors become rbne, that is non fatal. 1380 */ 1381 if (!(imu_log_enable & imu_intr_enable & mask)) 1382 err = PX_FATAL_SW; 1383 1384 return (err); 1385 } 1386 1387 /* 1388 * No platforms uses PME. Any PME received is simply logged 1389 * for analysis. 1390 */ 1391 /* ARGSUSED */ 1392 int 1393 px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 1394 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1395 px_err_bit_desc_t *err_bit_descr) 1396 { 1397 px_t *px_p = DIP_TO_STATE(rpdip); 1398 1399 px_p->px_pme_ignored++; 1400 return (PX_NONFATAL); 1401 } 1402 1403 /* handle EQ overflow */ 1404 /* ARGSUSED */ 1405 int 1406 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1407 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1408 px_err_bit_desc_t *err_bit_descr) 1409 { 1410 px_t *px_p = DIP_TO_STATE(rpdip); 1411 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1412 msiqid_t eqno; 1413 pci_msiq_state_t msiq_state; 1414 int err = PX_NONFATAL; 1415 int i; 1416 1417 eqno = msiq_state_p->msiq_1st_msiq_id; 1418 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1419 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1420 DDI_SUCCESS) { 1421 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1422 err = PX_FATAL_SW; 1423 } 1424 } 1425 } 1426 1427 return (err); 1428 } 1429 1430 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1431 PX_ERPT_SEND_DEC(imu_scs) 1432 { 1433 char buf[FM_MAX_CLASS]; 1434 boolean_t pri = PX_ERR_IS_PRI(bit); 1435 1436 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1437 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1438 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1439 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1440 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1441 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1442 FIRE_IMU_IE, DATA_TYPE_UINT64, 1443 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1444 FIRE_IMU_IS, DATA_TYPE_UINT64, 1445 ss_reg, 1446 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1447 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1448 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1449 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1450 NULL); 1451 1452 return (PX_OK); 1453 } 1454 1455 /* DMC IMU - see io erpt doc, section 2.3 */ 1456 PX_ERPT_SEND_DEC(imu) 1457 { 1458 char buf[FM_MAX_CLASS]; 1459 boolean_t pri = PX_ERR_IS_PRI(bit); 1460 1461 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1462 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1463 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1464 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1465 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1466 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1467 FIRE_IMU_IE, DATA_TYPE_UINT64, 1468 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1469 FIRE_IMU_IS, DATA_TYPE_UINT64, 1470 ss_reg, 1471 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1472 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1473 NULL); 1474 1475 return (PX_OK); 1476 } 1477 1478 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1479 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1480 { 1481 char buf[FM_MAX_CLASS]; 1482 boolean_t pri = PX_ERR_IS_PRI(bit); 1483 1484 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1485 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1486 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1487 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1488 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1489 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1490 FIRE_MMU_IE, DATA_TYPE_UINT64, 1491 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1492 FIRE_MMU_IS, DATA_TYPE_UINT64, 1493 ss_reg, 1494 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1495 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1496 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1497 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1498 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1499 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1500 NULL); 1501 1502 return (PX_OK); 1503 } 1504 1505 /* DMC MMU - see io erpt doc, section 2.5 */ 1506 PX_ERPT_SEND_DEC(mmu) 1507 { 1508 char buf[FM_MAX_CLASS]; 1509 boolean_t pri = PX_ERR_IS_PRI(bit); 1510 1511 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1512 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1513 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1514 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1515 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1516 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1517 FIRE_MMU_IE, DATA_TYPE_UINT64, 1518 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1519 FIRE_MMU_IS, DATA_TYPE_UINT64, 1520 ss_reg, 1521 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1522 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1523 NULL); 1524 1525 return (PX_OK); 1526 } 1527 1528 /* imu function to handle all Received but Not Enabled errors */ 1529 int 1530 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1531 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1532 px_err_bit_desc_t *err_bit_descr) 1533 { 1534 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1535 uint64_t mmu_log_enable, mmu_intr_enable; 1536 uint64_t mask = BITMASK(err_bit_descr->bit); 1537 uint64_t mmu_tfa, mmu_ctrl; 1538 uint64_t mmu_enable_bit = 0; 1539 int err = PX_NONFATAL; 1540 int ret; 1541 1542 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1543 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1544 1545 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1546 mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1547 1548 switch (err_bit_descr->bit) { 1549 case MMU_INTERRUPT_STATUS_BYP_ERR_P: 1550 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); 1551 break; 1552 case MMU_INTERRUPT_STATUS_TRN_ERR_P: 1553 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); 1554 break; 1555 default: 1556 mmu_enable_bit = 0; 1557 break; 1558 } 1559 1560 /* 1561 * If the interrupts are enabled and Translation/Bypass Enable bit 1562 * was set, then panic. This error should not have occured. 1563 */ 1564 if (mmu_log_enable & mmu_intr_enable & 1565 (mmu_ctrl & mmu_enable_bit)) { 1566 err = PX_FATAL_SW; 1567 } else { 1568 if (!pri) 1569 return (PX_FATAL_GOS); 1570 1571 ret = px_handle_lookup( 1572 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1573 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1574 1575 /* 1576 * S/W bug - this error should always be enabled 1577 */ 1578 1579 /* enable error & intr reporting for this bit */ 1580 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1581 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1582 1583 /* enable translation access/bypass enable */ 1584 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, 1585 mmu_ctrl | mmu_enable_bit); 1586 } 1587 1588 return (err); 1589 } 1590 1591 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1592 /* ARGSUSED */ 1593 int 1594 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1595 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1596 px_err_bit_desc_t *err_bit_descr) 1597 { 1598 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1599 uint64_t mmu_tfa; 1600 uint_t ret; 1601 1602 if (!pri) 1603 return (PX_FATAL_GOS); 1604 1605 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1606 ret = px_handle_lookup( 1607 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1608 1609 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1610 } 1611 1612 /* MMU Table walk errors */ 1613 /* ARGSUSED */ 1614 int 1615 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1616 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1617 px_err_bit_desc_t *err_bit_descr) 1618 { 1619 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1620 uint64_t mmu_tfa; 1621 uint_t ret; 1622 1623 if (!pri) 1624 return (PX_FATAL_GOS); 1625 1626 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1627 ret = px_handle_lookup( 1628 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1629 1630 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1631 } 1632 1633 /* 1634 * TLU LUP event - if caused by power management activity, then it is expected. 1635 * In all other cases, it is an error. 1636 */ 1637 /* ARGSUSED */ 1638 int 1639 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1640 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1641 px_err_bit_desc_t *err_bit_descr) 1642 { 1643 px_t *px_p = DIP_TO_STATE(rpdip); 1644 1645 /* 1646 * power management code is currently the only segment that sets 1647 * px_lup_pending to indicate its expectation for a healthy LUP 1648 * event. For all other occasions, LUP event should be flaged as 1649 * error condition. 1650 */ 1651 return ((atomic_cas_32(&px_p->px_lup_pending, 1, 0) == 0) ? 1652 PX_NONFATAL : PX_OK); 1653 } 1654 1655 /* 1656 * TLU LDN event - if caused by power management activity, then it is expected. 1657 * In all other cases, it is an error. 1658 */ 1659 /* ARGSUSED */ 1660 int 1661 px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 1662 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1663 px_err_bit_desc_t *err_bit_descr) 1664 { 1665 px_t *px_p = DIP_TO_STATE(rpdip); 1666 return ((px_p->px_pm_flags & PX_LDN_EXPECTED) ? PX_OK : PX_NONFATAL); 1667 } 1668 1669 /* PEC ILU none - see io erpt doc, section 3.1 */ 1670 PX_ERPT_SEND_DEC(pec_ilu) 1671 { 1672 char buf[FM_MAX_CLASS]; 1673 boolean_t pri = PX_ERR_IS_PRI(bit); 1674 1675 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1676 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1677 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1678 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1679 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1680 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1681 FIRE_ILU_IE, DATA_TYPE_UINT64, 1682 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1683 FIRE_ILU_IS, DATA_TYPE_UINT64, 1684 ss_reg, 1685 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1686 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1687 NULL); 1688 1689 return (PX_OK); 1690 } 1691 1692 /* PCIEX UE Errors */ 1693 /* ARGSUSED */ 1694 int 1695 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 1696 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1697 px_err_bit_desc_t *err_bit_descr) 1698 { 1699 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1700 1701 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ue_gos) ? 1702 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ue, 1703 px_fabric_die_rc_ue_gos)); 1704 } 1705 1706 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.2 */ 1707 PX_ERPT_SEND_DEC(pciex_rx_ue) 1708 { 1709 char buf[FM_MAX_CLASS]; 1710 boolean_t pri = PX_ERR_IS_PRI(bit); 1711 1712 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1713 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1714 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1715 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1716 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1717 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1718 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1719 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1720 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1721 ss_reg, 1722 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1723 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1724 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1725 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1726 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1727 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1728 NULL); 1729 1730 return (PX_OK); 1731 } 1732 1733 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.3 */ 1734 PX_ERPT_SEND_DEC(pciex_tx_ue) 1735 { 1736 char buf[FM_MAX_CLASS]; 1737 boolean_t pri = PX_ERR_IS_PRI(bit); 1738 1739 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1740 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1741 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1742 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1743 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1744 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1745 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1746 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1747 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1748 ss_reg, 1749 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1750 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1751 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 1752 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 1753 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 1754 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 1755 NULL); 1756 1757 return (PX_OK); 1758 } 1759 1760 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.4 */ 1761 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 1762 { 1763 char buf[FM_MAX_CLASS]; 1764 boolean_t pri = PX_ERR_IS_PRI(bit); 1765 1766 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1767 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1768 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1769 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1770 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1771 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1772 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1773 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1774 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1775 ss_reg, 1776 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1777 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1778 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1779 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1780 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1781 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1782 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 1783 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 1784 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 1785 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 1786 NULL); 1787 1788 return (PX_OK); 1789 } 1790 1791 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 1792 PX_ERPT_SEND_DEC(pciex_ue) 1793 { 1794 char buf[FM_MAX_CLASS]; 1795 boolean_t pri = PX_ERR_IS_PRI(bit); 1796 1797 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1798 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1799 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1800 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1801 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1802 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1803 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1804 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1805 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1806 ss_reg, 1807 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1808 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1809 NULL); 1810 1811 return (PX_OK); 1812 } 1813 1814 /* PCIEX UE Errors */ 1815 /* ARGSUSED */ 1816 int 1817 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 1818 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1819 px_err_bit_desc_t *err_bit_descr) 1820 { 1821 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1822 1823 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ce_gos) ? 1824 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ce, 1825 px_fabric_die_rc_ce_gos)); 1826 } 1827 1828 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 1829 PX_ERPT_SEND_DEC(pciex_ce) 1830 { 1831 char buf[FM_MAX_CLASS]; 1832 boolean_t pri = PX_ERR_IS_PRI(bit); 1833 1834 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1835 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1836 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1837 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1838 FIRE_TLU_CELE, DATA_TYPE_UINT64, 1839 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 1840 FIRE_TLU_CIE, DATA_TYPE_UINT64, 1841 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 1842 FIRE_TLU_CIS, DATA_TYPE_UINT64, 1843 ss_reg, 1844 FIRE_TLU_CESS, DATA_TYPE_UINT64, 1845 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 1846 NULL); 1847 1848 return (PX_OK); 1849 } 1850 1851 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 1852 PX_ERPT_SEND_DEC(pciex_rx_oe) 1853 { 1854 char buf[FM_MAX_CLASS]; 1855 boolean_t pri = PX_ERR_IS_PRI(bit); 1856 1857 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1858 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1859 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1860 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1861 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1862 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1863 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1864 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1865 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1866 ss_reg, 1867 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1868 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1869 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1870 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1871 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1872 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1873 NULL); 1874 1875 return (PX_OK); 1876 } 1877 1878 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 1879 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 1880 { 1881 char buf[FM_MAX_CLASS]; 1882 boolean_t pri = PX_ERR_IS_PRI(bit); 1883 1884 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1885 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1886 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1887 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1888 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1889 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1890 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1891 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1892 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1893 ss_reg, 1894 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1895 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1896 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 1897 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1898 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 1899 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1900 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 1901 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 1902 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, 1903 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 1904 NULL); 1905 1906 return (PX_OK); 1907 } 1908 1909 /* TLU Other Event - see io erpt doc, section 3.9 */ 1910 PX_ERPT_SEND_DEC(pciex_oe) 1911 { 1912 char buf[FM_MAX_CLASS]; 1913 boolean_t pri = PX_ERR_IS_PRI(bit); 1914 1915 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1916 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1917 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1918 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1919 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1920 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1921 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1922 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1923 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1924 ss_reg, 1925 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1926 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1927 NULL); 1928 1929 return (PX_OK); 1930 } 1931