1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Schizo specifics implementation: 30 * interrupt mapping register 31 * PBM configuration 32 * ECC and PBM error handling 33 * Iommu mapping handling 34 * Streaming Cache flushing 35 */ 36 37 #include <sys/types.h> 38 #include <sys/kmem.h> 39 #include <sys/sysmacros.h> 40 #include <sys/async.h> 41 #include <sys/ivintr.h> 42 #include <sys/systm.h> 43 #include <sys/intr.h> 44 #include <sys/machsystm.h> /* lddphys() */ 45 #include <sys/machsystm.h> /* lddphys, intr_dist_add */ 46 #include <sys/iommutsb.h> 47 #include <sys/promif.h> /* prom_printf */ 48 #include <sys/map.h> 49 #include <sys/ddi.h> 50 #include <sys/sunddi.h> 51 #include <sys/sunndi.h> 52 #include <sys/spl.h> 53 #include <sys/fm/util.h> 54 #include <sys/ddi_impldefs.h> 55 #include <sys/fm/protocol.h> 56 #include <sys/fm/io/sun4upci.h> 57 #include <sys/fm/io/ddi.h> 58 #include <sys/fm/io/pci.h> 59 #include <sys/pci/pci_obj.h> 60 #include <sys/pci/pcisch.h> 61 #include <sys/pci/pcisch_asm.h> 62 #include <sys/x_call.h> /* XCALL_PIL */ 63 64 /*LINTLIBRARY*/ 65 66 extern uint8_t ldstub(uint8_t *); 67 68 #define IOMMU_CTX_BITMAP_SIZE (1 << (12 - 3)) 69 static void iommu_ctx_free(iommu_t *); 70 static int iommu_tlb_scrub(iommu_t *, int); 71 static uint32_t pci_identity_init(pci_t *); 72 73 static void pci_cb_clear_error(cb_t *, cb_errstate_t *); 74 static void pci_clear_error(pci_t *, pbm_errstate_t *); 75 static uint32_t pci_identity_init(pci_t *pci_p); 76 static int pci_intr_setup(pci_t *pci_p); 77 static void iommu_ereport_post(dev_info_t *, uint64_t, pbm_errstate_t *); 78 static void cb_ereport_post(dev_info_t *, uint64_t, cb_errstate_t *); 79 static void pcix_ereport_post(dev_info_t *, uint64_t, pbm_errstate_t *); 80 static void pci_format_ecc_addr(dev_info_t *dip, uint64_t *afar, 81 ecc_region_t region); 82 static void pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p); 83 static void tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, 84 dvma_addr_t dvma_pg, int npages); 85 86 static int pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p); 87 88 static pci_ksinfo_t *pci_name_kstat; 89 static pci_ksinfo_t *saf_name_kstat; 90 91 extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value); 92 93 /* called by pci_attach() DDI_ATTACH to initialize pci objects */ 94 int 95 pci_obj_setup(pci_t *pci_p) 96 { 97 pci_common_t *cmn_p; 98 uint32_t chip_id = pci_identity_init(pci_p); 99 uint32_t cmn_id = PCI_CMN_ID(ID_CHIP_TYPE(chip_id), pci_p->pci_id); 100 int ret; 101 102 /* Perform allocations first to avoid delicate unwinding. */ 103 if (pci_alloc_tsb(pci_p) != DDI_SUCCESS) 104 return (DDI_FAILURE); 105 106 mutex_enter(&pci_global_mutex); 107 cmn_p = get_pci_common_soft_state(cmn_id); 108 if (cmn_p == NULL) { 109 if (alloc_pci_common_soft_state(cmn_id) != DDI_SUCCESS) { 110 mutex_exit(&pci_global_mutex); 111 pci_free_tsb(pci_p); 112 return (DDI_FAILURE); 113 } 114 cmn_p = get_pci_common_soft_state(cmn_id); 115 cmn_p->pci_common_id = cmn_id; 116 cmn_p->pci_common_tsb_cookie = IOMMU_TSB_COOKIE_NONE; 117 } 118 119 ASSERT((pci_p->pci_side == 0) || (pci_p->pci_side == 1)); 120 if (cmn_p->pci_p[pci_p->pci_side]) { 121 /* second side attach */ 122 pci_p->pci_side = PCI_OTHER_SIDE(pci_p->pci_side); 123 ASSERT(cmn_p->pci_p[pci_p->pci_side] == NULL); 124 } 125 126 cmn_p->pci_p[pci_p->pci_side] = pci_p; 127 pci_p->pci_common_p = cmn_p; 128 129 if (cmn_p->pci_common_refcnt == 0) 130 cmn_p->pci_chip_id = chip_id; 131 132 ib_create(pci_p); 133 134 /* 135 * The initialization of cb internal interrupts depends on ib 136 */ 137 if (cmn_p->pci_common_refcnt == 0) { 138 cb_create(pci_p); 139 cmn_p->pci_common_cb_p = pci_p->pci_cb_p; 140 } else 141 pci_p->pci_cb_p = cmn_p->pci_common_cb_p; 142 143 iommu_create(pci_p); 144 145 if (cmn_p->pci_common_refcnt == 0) { 146 ecc_create(pci_p); 147 cmn_p->pci_common_ecc_p = pci_p->pci_ecc_p; 148 } else 149 pci_p->pci_ecc_p = cmn_p->pci_common_ecc_p; 150 151 pbm_create(pci_p); 152 sc_create(pci_p); 153 154 pci_fm_create(pci_p); 155 156 if ((ret = pci_intr_setup(pci_p)) != DDI_SUCCESS) 157 goto done; 158 159 pci_kstat_create(pci_p); 160 161 cmn_p->pci_common_attachcnt++; 162 cmn_p->pci_common_refcnt++; 163 done: 164 mutex_exit(&pci_global_mutex); 165 if (ret != DDI_SUCCESS) 166 cmn_err(CE_WARN, "pci_obj_setup failed %x", ret); 167 return (ret); 168 } 169 170 /* called by pci_detach() DDI_DETACH to destroy pci objects */ 171 void 172 pci_obj_destroy(pci_t *pci_p) 173 { 174 pci_common_t *cmn_p; 175 mutex_enter(&pci_global_mutex); 176 177 cmn_p = pci_p->pci_common_p; 178 cmn_p->pci_common_refcnt--; 179 cmn_p->pci_common_attachcnt--; 180 181 pci_kstat_destroy(pci_p); 182 183 /* schizo non-shared objects */ 184 pci_fm_destroy(pci_p); 185 186 sc_destroy(pci_p); 187 pbm_destroy(pci_p); 188 iommu_destroy(pci_p); 189 ib_destroy(pci_p); 190 191 if (cmn_p->pci_common_refcnt != 0) { 192 pci_intr_teardown(pci_p); 193 cmn_p->pci_p[pci_p->pci_side] = NULL; 194 mutex_exit(&pci_global_mutex); 195 return; 196 } 197 198 /* schizo shared objects - uses cmn_p, must be destroyed before cmn */ 199 ecc_destroy(pci_p); 200 cb_destroy(pci_p); 201 202 free_pci_common_soft_state(cmn_p->pci_common_id); 203 pci_intr_teardown(pci_p); 204 mutex_exit(&pci_global_mutex); 205 } 206 207 /* called by pci_attach() DDI_RESUME to (re)initialize pci objects */ 208 void 209 pci_obj_resume(pci_t *pci_p) 210 { 211 pci_common_t *cmn_p = pci_p->pci_common_p; 212 213 mutex_enter(&pci_global_mutex); 214 215 ib_configure(pci_p->pci_ib_p); 216 iommu_configure(pci_p->pci_iommu_p); 217 218 if (cmn_p->pci_common_attachcnt == 0) 219 ecc_configure(pci_p); 220 221 ib_resume(pci_p->pci_ib_p); 222 223 pbm_configure(pci_p->pci_pbm_p); 224 sc_configure(pci_p->pci_sc_p); 225 226 if (cmn_p->pci_common_attachcnt == 0) 227 cb_resume(pci_p->pci_cb_p); 228 229 pbm_resume(pci_p->pci_pbm_p); 230 231 cmn_p->pci_common_attachcnt++; 232 mutex_exit(&pci_global_mutex); 233 } 234 235 /* called by pci_detach() DDI_SUSPEND to suspend pci objects */ 236 void 237 pci_obj_suspend(pci_t *pci_p) 238 { 239 mutex_enter(&pci_global_mutex); 240 241 pbm_suspend(pci_p->pci_pbm_p); 242 ib_suspend(pci_p->pci_ib_p); 243 244 if (!--pci_p->pci_common_p->pci_common_attachcnt) 245 cb_suspend(pci_p->pci_cb_p); 246 247 mutex_exit(&pci_global_mutex); 248 } 249 250 /* 251 * add an additional 0x35 or 0x36 ino interrupt on platforms don't have them 252 * This routine has multiple places that assumes interrupt takes one cell 253 * each and cell size is same as integer size. 254 */ 255 static int 256 pci_intr_setup(pci_t *pci_p) 257 { 258 dev_info_t *dip = pci_p->pci_dip; 259 pbm_t *pbm_p = pci_p->pci_pbm_p; 260 cb_t *cb_p = pci_p->pci_cb_p; 261 uint32_t *intr_buf, *new_intr_buf; 262 int intr_len, intr_cnt, ret; 263 264 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 265 "interrupts", (caddr_t)&intr_buf, &intr_len) != DDI_SUCCESS) 266 cmn_err(CE_PANIC, "%s%d: no interrupts property\n", 267 ddi_driver_name(dip), ddi_get_instance(dip)); 268 269 intr_cnt = BYTES_TO_1275_CELLS(intr_len); 270 if (intr_cnt < CBNINTR_CDMA) /* CBNINTR_CDMA is 0 based */ 271 cmn_err(CE_PANIC, "%s%d: <%d interrupts", ddi_driver_name(dip), 272 ddi_get_instance(dip), CBNINTR_CDMA); 273 274 if (intr_cnt == CBNINTR_CDMA) 275 intr_cnt++; 276 277 new_intr_buf = kmem_alloc(CELLS_1275_TO_BYTES(intr_cnt), KM_SLEEP); 278 bcopy(intr_buf, new_intr_buf, intr_len); 279 kmem_free(intr_buf, intr_len); 280 281 new_intr_buf[CBNINTR_CDMA] = PBM_CDMA_INO_BASE + pci_p->pci_side; 282 pci_p->pci_inos = new_intr_buf; 283 pci_p->pci_inos_len = CELLS_1275_TO_BYTES(intr_cnt); 284 285 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "interrupts", 286 (int *)new_intr_buf, intr_cnt)) 287 cmn_err(CE_PANIC, "%s%d: cannot update interrupts property\n", 288 ddi_driver_name(dip), ddi_get_instance(dip)); 289 290 if (pci_p->pci_common_p->pci_common_refcnt == 0) { 291 cb_p->cb_no_of_inos = intr_cnt; 292 if (ret = cb_register_intr(pci_p)) 293 goto teardown; 294 if (ret = ecc_register_intr(pci_p)) 295 goto teardown; 296 297 intr_dist_add(cb_intr_dist, cb_p); 298 cb_enable_intr(pci_p); 299 ecc_enable_intr(pci_p); 300 } 301 302 if (CHIP_TYPE(pci_p) != PCI_CHIP_SCHIZO) 303 pbm_p->pbm_sync_ino = pci_p->pci_inos[CBNINTR_PBM]; 304 if (ret = pbm_register_intr(pbm_p)) { 305 if (pci_p->pci_common_p->pci_common_refcnt == 0) 306 intr_dist_rem(cb_intr_dist, cb_p); 307 goto teardown; 308 } 309 intr_dist_add(pbm_intr_dist, pbm_p); 310 ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_PBM]); 311 ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_CDMA]); 312 313 intr_dist_add_weighted(ib_intr_dist_all, pci_p->pci_ib_p); 314 return (DDI_SUCCESS); 315 teardown: 316 pci_intr_teardown(pci_p); 317 return (ret); 318 } 319 320 uint64_t 321 pci_sc_configure(pci_t *pci_p) 322 { 323 int instance; 324 dev_info_t *dip = pci_p->pci_dip; 325 326 instance = ddi_get_instance(dip); 327 if ((pci_xmits_sc_max_prf & (1 << instance)) && 328 (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS)) 329 return (XMITS_SC_MAX_PRF); 330 else 331 return (0); 332 } 333 334 static void 335 pci_schizo_cdma_sync(pbm_t *pbm_p) 336 { 337 pci_t *pci_p = pbm_p->pbm_pci_p; 338 hrtime_t start_time; 339 volatile uint64_t *clr_p = ib_clear_intr_reg_addr(pci_p->pci_ib_p, 340 pci_p->pci_inos[CBNINTR_CDMA]); 341 uint32_t fail_cnt = pci_cdma_intr_count; 342 343 mutex_enter(&pbm_p->pbm_sync_mutex); 344 #ifdef PBM_CDMA_DEBUG 345 pbm_p->pbm_cdma_req_cnt++; 346 #endif /* PBM_CDMA_DEBUG */ 347 pbm_p->pbm_cdma_flag = PBM_CDMA_PEND; 348 IB_INO_INTR_TRIG(clr_p); 349 wait: 350 start_time = gethrtime(); 351 while (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) { 352 if (gethrtime() - start_time <= pci_cdma_intr_timeout) 353 continue; 354 if (--fail_cnt > 0) 355 goto wait; 356 if (pbm_p->pbm_cdma_flag == PBM_CDMA_DONE) 357 break; 358 cmn_err(CE_PANIC, "%s (%s): consistent dma sync timeout", 359 pbm_p->pbm_nameinst_str, pbm_p->pbm_nameaddr_str); 360 } 361 #ifdef PBM_CDMA_DEBUG 362 if (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) 363 pbm_p->pbm_cdma_to_cnt++; 364 else { 365 start_time = gethrtime() - start_time; 366 pbm_p->pbm_cdma_success_cnt++; 367 pbm_p->pbm_cdma_latency_sum += start_time; 368 if (start_time > pbm_p->pbm_cdma_latency_max) 369 pbm_p->pbm_cdma_latency_max = start_time; 370 } 371 #endif /* PBM_CDMA_DEBUG */ 372 mutex_exit(&pbm_p->pbm_sync_mutex); 373 } 374 375 #if !defined(lint) 376 #include <sys/cpuvar.h> 377 #endif 378 379 #define SYNC_HW_BUSY(pa, mask) (lddphysio(pa) & (mask)) 380 381 /* 382 * Consistent DMA Sync/Flush 383 * 384 * XMITS and Tomatillo use multi-threaded sync/flush register. 385 * Called from interrupt wrapper: the associated ino is used to index 386 * the distinctive register bit. 387 * Called from pci_dma_sync(): the bit belongs to PBM is shared 388 * for all calls from pci_dma_sync(). Xmits requires serialization 389 * while Tomatillo does not. 390 */ 391 void 392 pci_pbm_dma_sync(pbm_t *pbm_p, ib_ino_t ino) 393 { 394 pci_t *pci_p = pbm_p->pbm_pci_p; 395 hrtime_t start_time; 396 uint64_t ino_mask, sync_reg_pa; 397 volatile uint64_t flag_val; 398 uint32_t locked, chip_type = CHIP_TYPE(pci_p); 399 int i; 400 401 if (chip_type == PCI_CHIP_SCHIZO) { 402 pci_schizo_cdma_sync(pbm_p); 403 return; 404 } 405 406 sync_reg_pa = pbm_p->pbm_sync_reg_pa; 407 408 locked = 0; 409 if (((chip_type == PCI_CHIP_XMITS) && (ino == pbm_p->pbm_sync_ino)) || 410 pci_sync_lock) { 411 locked = 1; 412 mutex_enter(&pbm_p->pbm_sync_mutex); 413 } 414 ino_mask = 1ull << ino; 415 stdphysio(sync_reg_pa, ino_mask); 416 417 for (i = 0; i < 5; i++) { 418 if ((flag_val = SYNC_HW_BUSY(sync_reg_pa, ino_mask)) == 0) 419 goto done; 420 } 421 422 start_time = gethrtime(); 423 for (; (flag_val = SYNC_HW_BUSY(sync_reg_pa, ino_mask)) != 0; i++) { 424 if (gethrtime() - start_time > pci_sync_buf_timeout) 425 break; 426 } 427 428 if (flag_val && SYNC_HW_BUSY(sync_reg_pa, ino_mask) && !panicstr) 429 cmn_err(CE_PANIC, "%s: pbm dma sync %lx,%lx timeout!", 430 pbm_p->pbm_nameaddr_str, sync_reg_pa, flag_val); 431 done: 432 /* optional: stdphysio(sync_reg_pa - 8, ino_mask); */ 433 if (locked) 434 mutex_exit(&pbm_p->pbm_sync_mutex); 435 436 if (tomatillo_store_store_wrka) { 437 #if !defined(lint) 438 kpreempt_disable(); 439 #endif 440 tomatillo_store_store_order(); 441 #if !defined(lint) 442 kpreempt_enable(); 443 #endif 444 } 445 446 } 447 448 /*ARGSUSED*/ 449 void 450 pci_fix_ranges(pci_ranges_t *rng_p, int rng_entries) 451 { 452 } 453 454 /* 455 * map_pci_registers 456 * 457 * This function is called from the attach routine to map the registers 458 * accessed by this driver. 459 * 460 * used by: pci_attach() 461 * 462 * return value: DDI_FAILURE on failure 463 */ 464 int 465 map_pci_registers(pci_t *pci_p, dev_info_t *dip) 466 { 467 ddi_device_acc_attr_t attr; 468 int len; 469 470 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 471 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 472 473 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 474 475 /* 476 * Register set 0 is PCI CSR Base 477 */ 478 if (ddi_regs_map_setup(dip, 0, &pci_p->pci_address[0], 0, 0, 479 &attr, &pci_p->pci_ac[0]) != DDI_SUCCESS) { 480 len = 0; 481 goto fail; 482 } 483 /* 484 * Register set 1 is Schizo CSR Base 485 */ 486 if (ddi_regs_map_setup(dip, 1, &pci_p->pci_address[1], 0, 0, 487 &attr, &pci_p->pci_ac[1]) != DDI_SUCCESS) { 488 len = 1; 489 goto fail; 490 } 491 492 /* 493 * The third register set contains the bridge's configuration 494 * header. This header is at the very beginning of the bridge's 495 * configuration space. This space has litte-endian byte order. 496 */ 497 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 498 if (ddi_regs_map_setup(dip, 2, &pci_p->pci_address[2], 0, 499 PCI_CONF_HDR_SIZE, &attr, &pci_p->pci_ac[2]) != DDI_SUCCESS) { 500 len = 2; 501 goto fail; 502 } 503 504 if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 505 "reg", &len) || (len / sizeof (pci_nexus_regspec_t) < 4)) 506 goto done; 507 508 /* 509 * The optional fourth register bank points to the 510 * interrupt concentrator registers. 511 */ 512 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 513 if (ddi_regs_map_setup(dip, 3, &pci_p->pci_address[3], 0, 514 0, &attr, &pci_p->pci_ac[3]) != DDI_SUCCESS) { 515 len = 3; 516 goto fail; 517 } 518 519 done: 520 DEBUG4(DBG_ATTACH, dip, "address (%p,%p,%p,%p)\n", 521 pci_p->pci_address[0], pci_p->pci_address[1], 522 pci_p->pci_address[2], pci_p->pci_address[3]); 523 524 return (DDI_SUCCESS); 525 526 527 fail: 528 cmn_err(CE_WARN, "%s%d: unable to map reg entry %d\n", 529 ddi_driver_name(dip), ddi_get_instance(dip), len); 530 for (; len--; ddi_regs_map_free(&pci_p->pci_ac[len])); 531 return (DDI_FAILURE); 532 } 533 534 /* 535 * unmap_pci_registers: 536 * 537 * This routine unmap the registers mapped by map_pci_registers. 538 * 539 * used by: pci_detach() 540 * 541 * return value: none 542 */ 543 void 544 unmap_pci_registers(pci_t *pci_p) 545 { 546 int i; 547 548 for (i = 0; i < 4; i++) { 549 if (pci_p->pci_ac[i]) 550 ddi_regs_map_free(&pci_p->pci_ac[i]); 551 } 552 } 553 554 uint64_t 555 ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id) 556 { 557 uint32_t agent_id; 558 uint32_t node_id; 559 560 /* ensure that cpu_id is only 10 bits. */ 561 ASSERT((cpu_id & ~0x3ff) == 0); 562 563 agent_id = cpu_id & 0x1f; 564 node_id = (cpu_id >> 5) & 0x1f; 565 566 return ((mondo) | (agent_id << COMMON_INTR_MAP_REG_TID_SHIFT) | 567 (node_id << SCHIZO_INTR_MAP_REG_NID_SHIFT) | 568 COMMON_INTR_MAP_REG_VALID); 569 } 570 571 uint32_t 572 ib_map_reg_get_cpu(volatile uint64_t reg) 573 { 574 return (((reg & COMMON_INTR_MAP_REG_TID) >> 575 COMMON_INTR_MAP_REG_TID_SHIFT) | 576 ((reg & SCHIZO_INTR_MAP_REG_NID) >> 577 (SCHIZO_INTR_MAP_REG_NID_SHIFT-5))); 578 } 579 580 uint64_t * 581 ib_intr_map_reg_addr(ib_t *ib_p, ib_ino_t ino) 582 { 583 /* 584 * Schizo maps all interrupts in one contiguous area. 585 * (PCI_CSRBase + 0x00.1000 + INO * 8). 586 */ 587 return ((uint64_t *)(ib_p->ib_intr_map_regs) + (ino & 0x3f)); 588 } 589 590 uint64_t * 591 ib_clear_intr_reg_addr(ib_t *ib_p, ib_ino_t ino) /* XXX - needs work */ 592 { 593 /* 594 * Schizo maps clear intr. registers in contiguous area. 595 * (PCI_CSRBase + 0x00.1400 + INO * 8). 596 */ 597 return ((uint64_t *)(ib_p->ib_slot_clear_intr_regs) + (ino & 0x3f)); 598 } 599 600 /* 601 * schizo does not have mapping register per slot, so no sharing 602 * is done. 603 */ 604 /*ARGSUSED*/ 605 void 606 ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 607 { 608 } 609 610 /* 611 * return true if there are interrupts using this mapping register 612 */ 613 /*ARGSUSED*/ 614 int 615 ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 616 { 617 return (ino_p->ino_ih_size); 618 } 619 620 void 621 pci_pbm_intr_dist(pbm_t *pbm_p) 622 { 623 pci_t *pci_p = pbm_p->pbm_pci_p; 624 ib_t *ib_p = pci_p->pci_ib_p; 625 ib_ino_t ino = IB_MONDO_TO_INO(pci_p->pci_inos[CBNINTR_CDMA]); 626 627 mutex_enter(&pbm_p->pbm_sync_mutex); 628 ib_intr_dist_nintr(ib_p, ino, ib_intr_map_reg_addr(ib_p, ino)); 629 mutex_exit(&pbm_p->pbm_sync_mutex); 630 } 631 632 uint32_t 633 pci_xlate_intr(dev_info_t *dip, dev_info_t *rdip, ib_t *ib_p, uint32_t intr) 634 { 635 return (IB_INO_TO_MONDO(ib_p, intr)); 636 } 637 638 639 /* 640 * Return the cpuid to to be used for an ino. We have no special cpu 641 * assignment constraints for this nexus, so just call intr_dist_cpuid(). 642 */ 643 /* ARGSUSED */ 644 uint32_t 645 pci_intr_dist_cpuid(ib_t *ib_p, ib_ino_info_t *ino_p) 646 { 647 return (intr_dist_cpuid()); 648 } 649 650 void 651 pci_cb_teardown(pci_t *pci_p) 652 { 653 cb_t *cb_p = pci_p->pci_cb_p; 654 uint32_t mondo; 655 656 if (!pci_buserr_interrupt) 657 return; 658 659 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 660 pci_p->pci_inos[CBNINTR_BUS_ERROR]); 661 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 662 663 cb_disable_nintr(cb_p, CBNINTR_BUS_ERROR, IB_INTR_WAIT); 664 rem_ivintr(mondo, NULL); 665 } 666 667 int 668 cb_register_intr(pci_t *pci_p) 669 { 670 uint32_t mondo; 671 672 if (!pci_buserr_interrupt) 673 return (DDI_SUCCESS); 674 675 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 676 pci_p->pci_inos[CBNINTR_BUS_ERROR]); 677 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 678 679 VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_BUS_ERROR], 680 cb_buserr_intr, (caddr_t)pci_p->pci_cb_p, NULL) == 0); 681 682 return (PCI_ATTACH_RETCODE(PCI_CB_OBJ, PCI_OBJ_INTR_ADD, DDI_SUCCESS)); 683 } 684 685 void 686 cb_enable_intr(pci_t *pci_p) 687 { 688 if (pci_buserr_interrupt) 689 cb_enable_nintr(pci_p, CBNINTR_BUS_ERROR); 690 } 691 692 uint64_t 693 cb_ino_to_map_pa(cb_t *cb_p, ib_ino_t ino) 694 { 695 return (cb_p->cb_map_pa + (ino << 3)); 696 } 697 698 uint64_t 699 cb_ino_to_clr_pa(cb_t *cb_p, ib_ino_t ino) 700 { 701 return (cb_p->cb_clr_pa + (ino << 3)); 702 } 703 704 /* 705 * Useful on psycho only. 706 */ 707 int 708 cb_remove_xintr(pci_t *pci_p, dev_info_t *dip, dev_info_t *rdip, ib_ino_t ino, 709 ib_mondo_t mondo) 710 { 711 return (DDI_FAILURE); 712 } 713 714 void 715 pbm_configure(pbm_t *pbm_p) 716 { 717 pci_t *pci_p = pbm_p->pbm_pci_p; 718 dev_info_t *dip = pbm_p->pbm_pci_p->pci_dip; 719 int instance = ddi_get_instance(dip); 720 uint64_t l; 721 uint64_t mask = 1ll << instance; 722 ushort_t s = 0; 723 724 l = *pbm_p->pbm_ctrl_reg; /* save control register state */ 725 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 726 727 /* 728 * See if any SERR# signals are asserted. We'll clear them later. 729 */ 730 if (l & COMMON_PCI_CTRL_SERR) 731 cmn_err(CE_WARN, "%s%d: SERR asserted on pci bus\n", 732 ddi_driver_name(dip), instance); 733 734 /* 735 * Determine if PCI bus is running at 33 or 66 mhz. 736 */ 737 if (l & COMMON_PCI_CTRL_SPEED) 738 pbm_p->pbm_speed = PBM_SPEED_66MHZ; 739 else 740 pbm_p->pbm_speed = PBM_SPEED_33MHZ; 741 DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n", 742 pbm_p->pbm_speed == PBM_SPEED_66MHZ ? 66 : 33); 743 744 if (pci_set_dto_value & mask) { 745 l &= ~(3ull << SCHIZO_PCI_CTRL_PTO_SHIFT); 746 l |= pci_dto_value << SCHIZO_PCI_CTRL_PTO_SHIFT; 747 } else if (PCI_CHIP_ID(pci_p) >= TOMATILLO_VER_21) { 748 l |= (3ull << SCHIZO_PCI_CTRL_PTO_SHIFT); 749 } 750 751 /* 752 * Enable error interrupts. 753 */ 754 if (pci_error_intr_enable & mask) 755 l |= SCHIZO_PCI_CTRL_ERR_INT_EN; 756 else 757 l &= ~SCHIZO_PCI_CTRL_ERR_INT_EN; 758 759 /* 760 * Enable pci streaming byte errors and error interrupts. 761 */ 762 if (pci_sbh_error_intr_enable & mask) 763 l |= SCHIZO_PCI_CTRL_SBH_INT_EN; 764 else 765 l &= ~SCHIZO_PCI_CTRL_SBH_INT_EN; 766 767 /* 768 * Enable pci discard timeout error interrupt. 769 */ 770 if (pci_mmu_error_intr_enable & mask) 771 l |= SCHIZO_PCI_CTRL_MMU_INT_EN; 772 else 773 l &= ~SCHIZO_PCI_CTRL_MMU_INT_EN; 774 775 /* 776 * Enable PCI-X error interrupts. 777 */ 778 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 779 780 if (xmits_error_intr_enable & mask) 781 l |= XMITS_PCI_CTRL_X_ERRINT_EN; 782 else 783 l &= ~XMITS_PCI_CTRL_X_ERRINT_EN; 784 /* 785 * Panic if older XMITS hardware is found. 786 */ 787 if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) 788 if (PCI_CHIP_ID(pci_p) <= XMITS_VER_10) 789 cmn_err(CE_PANIC, "%s (%s): PCIX mode " 790 "unsupported on XMITS version %d\n", 791 pbm_p->pbm_nameinst_str, 792 pbm_p->pbm_nameaddr_str, CHIP_VER(pci_p)); 793 794 if (xmits_perr_recov_int_enable) { 795 if (PCI_CHIP_ID(pci_p) >= XMITS_VER_30) { 796 uint64_t pcix_err; 797 /* 798 * Enable interrupt on PERR 799 */ 800 pcix_err = *pbm_p->pbm_pcix_err_stat_reg; 801 pcix_err |= XMITS_PCIX_STAT_PERR_RECOV_INT_EN; 802 pcix_err &= ~XMITS_PCIX_STAT_SERR_ON_PERR; 803 *pbm_p->pbm_pcix_err_stat_reg = pcix_err; 804 } 805 } 806 807 /* 808 * Enable parity error detection on internal memories 809 */ 810 *pbm_p->pbm_pci_ped_ctrl = 0x3fff; 811 } 812 813 /* 814 * Enable/disable bus parking. 815 */ 816 if ((pci_bus_parking_enable & mask) && 817 !ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 818 "no-bus-parking")) 819 l |= SCHIZO_PCI_CTRL_ARB_PARK; 820 else 821 l &= ~SCHIZO_PCI_CTRL_ARB_PARK; 822 823 /* 824 * Enable arbitration. 825 */ 826 l |= PCI_CHIP_ID(pci_p) == XMITS_VER_10 ? XMITS10_PCI_CTRL_ARB_EN_MASK : 827 SCHIZO_PCI_CTRL_ARB_EN_MASK; 828 829 /* 830 * Make sure SERR is clear 831 */ 832 l |= COMMON_PCI_CTRL_SERR; 833 834 835 /* 836 * Enable DTO interrupt, if desired. 837 */ 838 839 if (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_20 || (pci_dto_intr_enable & 840 mask)) 841 l |= (TOMATILLO_PCI_CTRL_DTO_INT_EN); 842 else 843 l &= ~(TOMATILLO_PCI_CTRL_DTO_INT_EN); 844 845 l |= TOMATILLO_PCI_CTRL_PEN_RD_MLTPL | 846 TOMATILLO_PCI_CTRL_PEN_RD_ONE | 847 TOMATILLO_PCI_CTRL_PEN_RD_LINE; 848 849 /* 850 * Now finally write the control register with the appropriate value. 851 */ 852 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 853 *pbm_p->pbm_ctrl_reg = l; 854 855 /* 856 * Enable IO Prefetch on Tomatillo 857 */ 858 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 859 volatile uint64_t *ioc_csr_p = pbm_p->pbm_ctrl_reg + 860 ((TOMATILLO_IOC_CSR_OFF - 861 SCHIZO_PCI_CTRL_REG_OFFSET) >> 3); 862 *ioc_csr_p = TOMATILLO_WRT_PEN | 863 (1 << TOMATILLO_POFFSET_SHIFT) | 864 TOMATILLO_C_PEN_RD_MLTPL | 865 TOMATILLO_C_PEN_RD_ONE | 866 TOMATILLO_C_PEN_RD_LINE; 867 } 868 869 /* 870 * Allow DMA write parity errors to generate an interrupt. 871 * This is implemented on Schizo 2.5 and greater and XMITS 3.0 872 * and greater. Setting this on earlier versions of XMITS 3.0 873 * has no affect. 874 */ 875 if (((CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO) && 876 PCI_CHIP_ID(pci_p) >= SCHIZO_VER_25) || 877 (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS)) { 878 volatile uint64_t *pbm_icd = pbm_p->pbm_ctrl_reg + 879 ((SCHIZO_PERF_PCI_ICD_OFFSET - 880 SCHIZO_PCI_CTRL_REG_OFFSET) >> 3); 881 882 *pbm_icd |= SCHIZO_PERF_PCI_ICD_DMAW_PARITY_INT_ENABLE; 883 } 884 885 /* 886 * Clear any PBM errors. 887 */ 888 l = (SCHIZO_PCI_AFSR_E_MASK << SCHIZO_PCI_AFSR_PE_SHIFT) | 889 (SCHIZO_PCI_AFSR_E_MASK << SCHIZO_PCI_AFSR_SE_SHIFT); 890 *pbm_p->pbm_async_flt_status_reg = l; 891 892 /* 893 * Allow the diag register to be set based upon variable that 894 * can be configured via /etc/system. 895 */ 896 l = *pbm_p->pbm_diag_reg; 897 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 898 899 /* 900 * Enable/disable retry limit. 901 */ 902 if (pci_retry_disable & mask) 903 l |= COMMON_PCI_DIAG_DIS_RETRY; 904 else 905 l &= ~COMMON_PCI_DIAG_DIS_RETRY; 906 907 /* 908 * Enable/disable DMA write/interrupt synchronization. 909 */ 910 if (pci_intsync_disable & mask) 911 l |= COMMON_PCI_DIAG_DIS_INTSYNC; 912 else 913 l &= ~COMMON_PCI_DIAG_DIS_INTSYNC; 914 915 /* 916 * Enable/disable retry arbitration priority. 917 */ 918 if (pci_enable_retry_arb & mask) 919 l &= ~SCHIZO_PCI_DIAG_DIS_RTRY_ARB; 920 else 921 l |= SCHIZO_PCI_DIAG_DIS_RTRY_ARB; 922 923 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 924 *pbm_p->pbm_diag_reg = l; 925 926 /* 927 * Enable SERR# and parity reporting via command register. 928 */ 929 s = pci_perr_enable & mask ? PCI_COMM_PARITY_DETECT : 0; 930 s |= pci_serr_enable & mask ? PCI_COMM_SERR_ENABLE : 0; 931 932 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s); 933 pbm_p->pbm_config_header->ch_command_reg = s; 934 935 /* 936 * Clear error bits in configuration status register. 937 */ 938 s = PCI_STAT_PERROR | PCI_STAT_S_PERROR | 939 PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB | 940 PCI_STAT_S_TARG_AB | PCI_STAT_S_PERROR; 941 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s); 942 pbm_p->pbm_config_header->ch_status_reg = s; 943 944 /* 945 * The current versions of the obp are suppose to set the latency 946 * timer register but do not. Bug 1234181 is open against this 947 * problem. Until this bug is fixed we check to see if the obp 948 * has attempted to set the latency timer register by checking 949 * for the existence of a "latency-timer" property. 950 */ 951 if (pci_set_latency_timer_register) { 952 DEBUG1(DBG_ATTACH, dip, 953 "pbm_configure: set schizo latency timer to %x\n", 954 pci_latency_timer); 955 pbm_p->pbm_config_header->ch_latency_timer_reg = 956 pci_latency_timer; 957 } 958 959 (void) ndi_prop_update_int(DDI_DEV_T_ANY, dip, "latency-timer", 960 (int)pbm_p->pbm_config_header->ch_latency_timer_reg); 961 962 /* 963 * Adjust xmits_upper_retry_counter if set in /etc/system 964 * 965 * NOTE: current implementation resets UPPR_RTRY counter for 966 * _all_ XMITS' PBMs and does not support tuning per PBM. 967 */ 968 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 969 uint_t xurc = xmits_upper_retry_counter & 970 XMITS_UPPER_RETRY_MASK; 971 972 if (xurc) { 973 *pbm_p->pbm_upper_retry_counter_reg = (uint64_t)xurc; 974 DEBUG1(DBG_ATTACH, dip, "pbm_configure: Setting XMITS" 975 " uppr_rtry counter = 0x%lx\n", 976 *pbm_p->pbm_upper_retry_counter_reg); 977 } 978 } 979 } 980 981 uint_t 982 pbm_disable_pci_errors(pbm_t *pbm_p) 983 { 984 pci_t *pci_p = pbm_p->pbm_pci_p; 985 ib_t *ib_p = pci_p->pci_ib_p; 986 987 /* 988 * Disable error and streaming byte hole interrupts via the 989 * PBM control register. 990 */ 991 *pbm_p->pbm_ctrl_reg &= 992 ~(SCHIZO_PCI_CTRL_ERR_INT_EN | SCHIZO_PCI_CTRL_SBH_INT_EN | 993 SCHIZO_PCI_CTRL_MMU_INT_EN); 994 995 /* 996 * Disable error interrupts via the interrupt mapping register. 997 */ 998 ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_NOWAIT); 999 return (BF_NONE); 1000 } 1001 1002 /* 1003 * Layout of the dvma context bucket bitmap entry: 1004 * 1005 * 63 - 56 55 - 0 1006 * 8-bit lock 56-bit, each represent one context 1007 * DCB_LOCK_BITS DCB_BMAP_BITS 1008 */ 1009 #define DCB_LOCK_BITS 8 1010 #define DCB_BMAP_BITS (64 - DCB_LOCK_BITS) 1011 1012 dvma_context_t 1013 pci_iommu_get_dvma_context(iommu_t *iommu_p, dvma_addr_t dvma_pg_index) 1014 { 1015 dvma_context_t ctx; 1016 int i = (dvma_pg_index >> 6) & 0x1f; /* 5 bit index within bucket */ 1017 uint64_t ctx_mask, test = 1ull << i; 1018 uint32_t bucket_no = dvma_pg_index & 0x3f; 1019 uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no; 1020 1021 uint32_t spl = ddi_enter_critical(); /* block interrupts */ 1022 if (ldstub((uint8_t *)bucket_ptr)) { /* try lock */ 1023 ddi_exit_critical(spl); /* unblock interrupt */ 1024 pci_iommu_ctx_lock_failure++; 1025 return (0); 1026 } 1027 1028 /* clear lock bits */ 1029 ctx_mask = (*bucket_ptr << DCB_LOCK_BITS) >> DCB_LOCK_BITS; 1030 ASSERT(*bucket_ptr >> DCB_BMAP_BITS == 0xff); 1031 ASSERT(ctx_mask >> DCB_BMAP_BITS == 0); 1032 1033 if (ctx_mask & test) /* quick check i bit */ 1034 for (i = 0, test = 1ull; test & ctx_mask; test <<= 1, i++); 1035 if (i < DCB_BMAP_BITS) 1036 ctx_mask |= test; 1037 *bucket_ptr = ctx_mask; /* unlock */ 1038 ddi_exit_critical(spl); /* unblock interrupts */ 1039 1040 ctx = i < DCB_BMAP_BITS ? (bucket_no << 6) | i : 0; 1041 DEBUG3(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip, 1042 "get_dvma_context: ctx_mask=0x%x.%x ctx=0x%x\n", 1043 (uint32_t)(ctx_mask >> 32), (uint32_t)ctx_mask, ctx); 1044 return (ctx); 1045 } 1046 1047 void 1048 pci_iommu_free_dvma_context(iommu_t *iommu_p, dvma_context_t ctx) 1049 { 1050 uint64_t ctx_mask; 1051 uint32_t spl, bucket_no = ctx >> 6; 1052 int bit_no = ctx & 0x3f; 1053 uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no; 1054 1055 DEBUG1(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip, 1056 "free_dvma_context: ctx=0x%x\n", ctx); 1057 1058 spl = ddi_enter_critical(); /* block interrupts */ 1059 while (ldstub((uint8_t *)bucket_ptr)); /* spin lock */ 1060 ctx_mask = (*bucket_ptr << DCB_LOCK_BITS) >> DCB_LOCK_BITS; 1061 /* clear lock bits */ 1062 ASSERT(ctx_mask & (1ull << bit_no)); 1063 *bucket_ptr = ctx_mask ^ (1ull << bit_no); /* clear & unlock */ 1064 ddi_exit_critical(spl); /* unblock interrupt */ 1065 } 1066 1067 int 1068 pci_sc_ctx_inv(dev_info_t *dip, sc_t *sc_p, ddi_dma_impl_t *mp) 1069 { 1070 dvma_context_t ctx = MP2CTX(mp); 1071 volatile uint64_t *reg_addr = sc_p->sc_ctx_match_reg + ctx; 1072 uint64_t matchreg; 1073 1074 if (!*reg_addr) { 1075 DEBUG1(DBG_SC, dip, "ctx=%x no match\n", ctx); 1076 return (DDI_SUCCESS); 1077 } 1078 1079 *sc_p->sc_ctx_invl_reg = ctx; /* 1st flush write */ 1080 matchreg = *reg_addr; /* re-fetch after 1st flush */ 1081 if (!matchreg) 1082 return (DDI_SUCCESS); 1083 1084 matchreg = (matchreg << SC_ENT_SHIFT) >> SC_ENT_SHIFT; /* low 16-bit */ 1085 do { 1086 if (matchreg & 1) 1087 *sc_p->sc_ctx_invl_reg = ctx; 1088 matchreg >>= 1; 1089 } while (matchreg); 1090 1091 if (pci_ctx_no_compat || !*reg_addr) /* compat: active ctx flush */ 1092 return (DDI_SUCCESS); 1093 1094 pci_ctx_unsuccess_count++; 1095 if (pci_ctx_flush_warn) 1096 cmn_err(pci_ctx_flush_warn, "%s%d: ctx flush unsuccessful\n", 1097 NAMEINST(dip)); 1098 return (DDI_FAILURE); 1099 } 1100 1101 void 1102 pci_cb_setup(pci_t *pci_p) 1103 { 1104 dev_info_t *dip = pci_p->pci_dip; 1105 cb_t *cb_p = pci_p->pci_cb_p; 1106 uint64_t pa; 1107 uint32_t chip_id = PCI_CHIP_ID(pci_p); 1108 DEBUG1(DBG_ATTACH, dip, "cb_create: chip id %d\n", chip_id); 1109 1110 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 1111 if ((!tm_mtlb_gc_manual) && 1112 (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_24)) 1113 tm_mtlb_gc = 1; 1114 1115 if (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_23) { 1116 extern int ignore_invalid_vecintr; 1117 ignore_invalid_vecintr = 1; 1118 tomatillo_store_store_wrka = 1; 1119 tomatillo_disallow_bypass = 1; 1120 if (pci_spurintr_msgs == PCI_SPURINTR_MSG_DEFAULT) 1121 pci_spurintr_msgs = 0; 1122 } 1123 } 1124 1125 if (chip_id == TOMATILLO_VER_20 || chip_id == TOMATILLO_VER_21) 1126 cmn_err(CE_WARN, "Unsupported Tomatillo rev (%x)", chip_id); 1127 1128 if (chip_id < SCHIZO_VER_23) 1129 pci_ctx_no_active_flush = 1; 1130 1131 cb_p->cb_node_id = PCI_ID_TO_NODEID(pci_p->pci_id); 1132 cb_p->cb_ign = PCI_ID_TO_IGN(pci_p->pci_id); 1133 1134 /* 1135 * schizo control status reg bank is on the 2nd "reg" property entry 1136 * interrupt mapping/clear/state regs are on the 1st "reg" entry. 1137 * 1138 * ALL internal interrupts except pbm interrupts are shared by both 1139 * sides, 1st-side-attached is used as *the* owner. 1140 */ 1141 pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[1]); 1142 cb_p->cb_base_pa = pa << MMU_PAGESHIFT; 1143 1144 pa = pci_p->pci_address[3] ? 1145 (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[3]) : 0; 1146 cb_p->cb_icbase_pa = (pa == PFN_INVALID) ? 0 : pa << MMU_PAGESHIFT; 1147 1148 pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[0]) 1149 << MMU_PAGESHIFT; 1150 cb_p->cb_map_pa = pa + SCHIZO_IB_INTR_MAP_REG_OFFSET; 1151 cb_p->cb_clr_pa = pa + SCHIZO_IB_CLEAR_INTR_REG_OFFSET; 1152 cb_p->cb_obsta_pa = pa + COMMON_IB_OBIO_INTR_STATE_DIAG_REG; 1153 } 1154 1155 void 1156 pci_ecc_setup(ecc_t *ecc_p) 1157 { 1158 ecc_p->ecc_ue.ecc_errpndg_mask = SCHIZO_ECC_UE_AFSR_ERRPNDG; 1159 ecc_p->ecc_ue.ecc_offset_mask = SCHIZO_ECC_UE_AFSR_QW_OFFSET; 1160 ecc_p->ecc_ue.ecc_offset_shift = SCHIZO_ECC_UE_AFSR_QW_OFFSET_SHIFT; 1161 ecc_p->ecc_ue.ecc_size_log2 = 4; 1162 1163 ecc_p->ecc_ce.ecc_errpndg_mask = SCHIZO_ECC_CE_AFSR_ERRPNDG; 1164 ecc_p->ecc_ce.ecc_offset_mask = SCHIZO_ECC_CE_AFSR_QW_OFFSET; 1165 ecc_p->ecc_ce.ecc_offset_shift = SCHIZO_ECC_CE_AFSR_QW_OFFSET_SHIFT; 1166 ecc_p->ecc_ce.ecc_size_log2 = 4; 1167 } 1168 1169 ushort_t 1170 pci_ecc_get_synd(uint64_t afsr) 1171 { 1172 return ((ushort_t)((afsr & SCHIZO_ECC_CE_AFSR_SYND) >> 1173 SCHIZO_ECC_CE_AFSR_SYND_SHIFT)); 1174 } 1175 1176 /* 1177 * overwrite dvma end address (only on virtual-dma systems) 1178 * initialize tsb size 1179 * reset context bits 1180 * return: IOMMU CSR bank base address (VA) 1181 */ 1182 1183 uintptr_t 1184 pci_iommu_setup(iommu_t *iommu_p) 1185 { 1186 pci_dvma_range_prop_t *dvma_prop; 1187 int dvma_prop_len; 1188 1189 uintptr_t a; 1190 pci_t *pci_p = iommu_p->iommu_pci_p; 1191 dev_info_t *dip = pci_p->pci_dip; 1192 uint_t tsb_size = iommu_tsb_cookie_to_size(pci_p->pci_tsb_cookie); 1193 uint_t tsb_size_prop; 1194 1195 /* 1196 * Initializations for Tomatillo's micro TLB bug. errata #82 1197 */ 1198 if (tm_mtlb_gc) { 1199 iommu_p->iommu_mtlb_nreq = 0; 1200 iommu_p->iommu_mtlb_npgs = 0; 1201 iommu_p->iommu_mtlb_maxpgs = tm_mtlb_maxpgs; 1202 iommu_p->iommu_mtlb_req_p = (dvma_unbind_req_t *) 1203 kmem_zalloc(sizeof (dvma_unbind_req_t) * 1204 (tm_mtlb_maxpgs + 1), KM_SLEEP); 1205 mutex_init(&iommu_p->iommu_mtlb_lock, NULL, MUTEX_DRIVER, NULL); 1206 } 1207 1208 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1209 "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) != 1210 DDI_PROP_SUCCESS) 1211 goto tsb_done; 1212 1213 if (dvma_prop_len != sizeof (pci_dvma_range_prop_t)) { 1214 cmn_err(CE_WARN, "%s%d: invalid virtual-dma property", 1215 ddi_driver_name(dip), ddi_get_instance(dip)); 1216 goto tsb_end; 1217 } 1218 iommu_p->iommu_dvma_end = dvma_prop->dvma_base + 1219 (dvma_prop->dvma_len - 1); 1220 tsb_size_prop = IOMMU_BTOP(dvma_prop->dvma_len) * sizeof (uint64_t); 1221 tsb_size = MIN(tsb_size_prop, tsb_size); 1222 tsb_end: 1223 kmem_free(dvma_prop, dvma_prop_len); 1224 tsb_done: 1225 iommu_p->iommu_tsb_size = iommu_tsb_size_encode(tsb_size); 1226 iommu_p->iommu_ctx_bitmap = 1227 kmem_zalloc(IOMMU_CTX_BITMAP_SIZE, KM_SLEEP); 1228 *iommu_p->iommu_ctx_bitmap = 1ull; /* reserve context 0 */ 1229 1230 /* 1231 * Determine the virtual address of the register block 1232 * containing the iommu control registers and determine 1233 * the virtual address of schizo specific iommu registers. 1234 */ 1235 a = (uintptr_t)pci_p->pci_address[0]; 1236 iommu_p->iommu_flush_ctx_reg = 1237 (uint64_t *)(a + SCHIZO_IOMMU_FLUSH_CTX_REG_OFFSET); 1238 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) 1239 iommu_p->iommu_tfar_reg = 1240 (uint64_t *)(a + TOMATILLO_IOMMU_ERR_TFAR_OFFSET); 1241 return (a); /* PCICSRBase */ 1242 } 1243 1244 void 1245 pci_iommu_teardown(iommu_t *iommu_p) 1246 { 1247 if (pci_use_contexts) 1248 iommu_ctx_free(iommu_p); 1249 if (iommu_p->iommu_mtlb_req_p) { 1250 kmem_free(iommu_p->iommu_mtlb_req_p, 1251 sizeof (dvma_unbind_req_t) * (tm_mtlb_maxpgs + 1)); 1252 mutex_destroy(&iommu_p->iommu_mtlb_lock); 1253 iommu_p->iommu_mtlb_req_p = NULL; 1254 iommu_p->iommu_mtlb_nreq = 0; 1255 iommu_p->iommu_mtlb_npgs = iommu_p->iommu_mtlb_maxpgs = 0; 1256 } 1257 } 1258 1259 uintptr_t 1260 get_pbm_reg_base(pci_t *pci_p) 1261 { 1262 return ((uintptr_t) 1263 (pci_p->pci_address[0] + SCHIZO_PCI_CTRL_REG_OFFSET)); 1264 } 1265 1266 /* ARGSUSED */ 1267 static boolean_t 1268 pci_pbm_panic_callb(void *arg, int code) 1269 { 1270 pbm_t *pbm_p = (pbm_t *)arg; 1271 volatile uint64_t *ctrl_reg_p; 1272 1273 if (pbm_p->pbm_quiesce_count > 0) { 1274 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 1275 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 1276 } 1277 1278 return (B_TRUE); 1279 } 1280 1281 static boolean_t 1282 pci_pbm_debug_callb(void *arg, int code) 1283 { 1284 pbm_t *pbm_p = (pbm_t *)arg; 1285 volatile uint64_t *ctrl_reg_p; 1286 uint64_t ctrl_reg; 1287 1288 if (pbm_p->pbm_quiesce_count > 0) { 1289 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 1290 if (code == 0) { 1291 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 1292 } else { 1293 ctrl_reg = pbm_p->pbm_saved_ctrl_reg; 1294 ctrl_reg &= ~(SCHIZO_PCI_CTRL_ARB_EN_MASK | 1295 SCHIZO_PCI_CTRL_ARB_PARK); 1296 *ctrl_reg_p = ctrl_reg; 1297 } 1298 } 1299 1300 return (B_TRUE); 1301 } 1302 1303 void 1304 pci_pbm_setup(pbm_t *pbm_p) 1305 { 1306 pci_t *pci_p = pbm_p->pbm_pci_p; 1307 caddr_t a = pci_p->pci_address[0]; /* PBM block base VA */ 1308 uint64_t pa = va_to_pa(a); 1309 extern int segkmem_reloc; 1310 1311 mutex_init(&pbm_p->pbm_sync_mutex, NULL, MUTEX_DRIVER, 1312 (void *)ipltospl(XCALL_PIL)); 1313 1314 pbm_p->pbm_config_header = (config_header_t *)pci_p->pci_address[2]; 1315 pbm_p->pbm_ctrl_reg = (uint64_t *)(a + SCHIZO_PCI_CTRL_REG_OFFSET); 1316 pbm_p->pbm_diag_reg = (uint64_t *)(a + SCHIZO_PCI_DIAG_REG_OFFSET); 1317 pbm_p->pbm_async_flt_status_reg = 1318 (uint64_t *)(a + SCHIZO_PCI_ASYNC_FLT_STATUS_REG_OFFSET); 1319 pbm_p->pbm_async_flt_addr_reg = 1320 (uint64_t *)(a + SCHIZO_PCI_ASYNC_FLT_ADDR_REG_OFFSET); 1321 pbm_p->pbm_estar_reg = (uint64_t *)(a + SCHIZO_PCI_ESTAR_REG_OFFSET); 1322 pbm_p->pbm_pcix_err_stat_reg = (uint64_t *)(a + 1323 XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 1324 pbm_p->pbm_pci_ped_ctrl = (uint64_t *)(a + 1325 XMITS_PARITY_DETECT_REG_OFFSET); 1326 1327 /* 1328 * Create a property to indicate that this node supports DVMA 1329 * page relocation. 1330 */ 1331 if (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO && segkmem_reloc != 0) { 1332 pci_dvma_remap_enabled = 1; 1333 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, 1334 pci_p->pci_dip, "dvma-remap-supported"); 1335 } 1336 1337 /* 1338 * Register a panic callback so we can unquiesce this bus 1339 * if it has been placed in the quiesced state. 1340 */ 1341 pbm_p->pbm_panic_cb_id = callb_add(pci_pbm_panic_callb, 1342 (void *)pbm_p, CB_CL_PANIC, "pci_panic"); 1343 pbm_p->pbm_debug_cb_id = callb_add(pci_pbm_panic_callb, 1344 (void *)pbm_p, CB_CL_ENTER_DEBUGGER, "pci_debug_enter"); 1345 1346 if (CHIP_TYPE(pci_p) != PCI_CHIP_SCHIZO) 1347 goto non_schizo; 1348 1349 if (PCI_CHIP_ID(pci_p) >= SCHIZO_VER_23) { 1350 1351 pbm_p->pbm_sync_reg_pa = pa + SCHIZO_PBM_DMA_SYNC_REG_OFFSET; 1352 1353 /* 1354 * This is a software workaround to fix schizo hardware bug. 1355 * Create a boolean property and its existence means consistent 1356 * dma sync should not be done while in prom. The usb polled 1357 * code (OHCI,EHCI) will check for this property and will not 1358 * do dma sync if this property exist. 1359 */ 1360 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, 1361 pci_p->pci_dip, "no-prom-cdma-sync"); 1362 } 1363 return; 1364 non_schizo: 1365 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 1366 pci_dvma_sync_before_unmap = 1; 1367 pa = pci_p->pci_cb_p->cb_icbase_pa; 1368 } 1369 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) 1370 pbm_p->pbm_upper_retry_counter_reg = 1371 (uint64_t *)(a + XMITS_UPPER_RETRY_COUNTER_REG_OFFSET); 1372 1373 pbm_p->pbm_sync_reg_pa = pa + PBM_DMA_SYNC_PEND_REG_OFFSET; 1374 } 1375 1376 void 1377 pci_pbm_teardown(pbm_t *pbm_p) 1378 { 1379 (void) callb_delete(pbm_p->pbm_panic_cb_id); 1380 (void) callb_delete(pbm_p->pbm_debug_cb_id); 1381 } 1382 1383 uintptr_t 1384 pci_ib_setup(ib_t *ib_p) 1385 { 1386 /* 1387 * Determine virtual addresses of bridge specific registers, 1388 */ 1389 pci_t *pci_p = ib_p->ib_pci_p; 1390 uintptr_t a = (uintptr_t)pci_p->pci_address[0]; 1391 1392 ib_p->ib_ign = PCI_ID_TO_IGN(pci_p->pci_id); 1393 ib_p->ib_max_ino = SCHIZO_MAX_INO; 1394 ib_p->ib_slot_intr_map_regs = a + SCHIZO_IB_SLOT_INTR_MAP_REG_OFFSET; 1395 ib_p->ib_intr_map_regs = a + SCHIZO_IB_INTR_MAP_REG_OFFSET; 1396 ib_p->ib_slot_clear_intr_regs = 1397 a + SCHIZO_IB_CLEAR_INTR_REG_OFFSET; 1398 return (a); 1399 } 1400 1401 void 1402 pci_sc_setup(sc_t *sc_p) 1403 { 1404 pci_t *pci_p = sc_p->sc_pci_p; 1405 uintptr_t a; 1406 1407 /* 1408 * Determine the virtual addresses of the stream cache 1409 * control/status and flush registers. 1410 */ 1411 a = (uintptr_t)pci_p->pci_address[0]; /* PCICSRBase */ 1412 sc_p->sc_ctrl_reg = (uint64_t *)(a + SCHIZO_SC_CTRL_REG_OFFSET); 1413 sc_p->sc_invl_reg = (uint64_t *)(a + SCHIZO_SC_INVL_REG_OFFSET); 1414 sc_p->sc_sync_reg = (uint64_t *)(a + SCHIZO_SC_SYNC_REG_OFFSET); 1415 sc_p->sc_ctx_invl_reg = (uint64_t *)(a + SCHIZO_SC_CTX_INVL_REG_OFFSET); 1416 sc_p->sc_ctx_match_reg = 1417 (uint64_t *)(a + SCHIZO_SC_CTX_MATCH_REG_OFFSET); 1418 1419 /* 1420 * Determine the virtual addresses of the streaming cache 1421 * diagnostic access registers. 1422 */ 1423 sc_p->sc_data_diag_acc = (uint64_t *)(a + SCHIZO_SC_DATA_DIAG_OFFSET); 1424 sc_p->sc_tag_diag_acc = (uint64_t *)(a + SCHIZO_SC_TAG_DIAG_OFFSET); 1425 sc_p->sc_ltag_diag_acc = (uint64_t *)(a + SCHIZO_SC_LTAG_DIAG_OFFSET); 1426 } 1427 1428 /*ARGSUSED*/ 1429 int 1430 pci_get_numproxy(dev_info_t *dip) 1431 { 1432 /* 1433 * Schizo does not support interrupt proxies. 1434 */ 1435 return (0); 1436 } 1437 1438 /* 1439 * pcisch error handling 101: 1440 * 1441 * The various functions below are responsible for error handling. Given 1442 * a particular error, they must gather the appropriate state, report all 1443 * errors with correct payload, and attempt recovery where ever possible. 1444 * 1445 * Recovery in the context of this driver is being able notify a leaf device 1446 * of the failed transaction. This leaf device may either be the master or 1447 * target for this transaction and may have already received an error 1448 * notification via a PCI interrupt. Notification is done via DMA and access 1449 * handles. If we capture an address for the transaction then we can map it 1450 * to a handle(if the leaf device is fma-compliant) and fault the handle as 1451 * well as call the device driver registered callback. 1452 * 1453 * The hardware can either interrupt or trap upon detection of an error, in 1454 * some rare cases it also causes a fatal reset. 1455 * 1456 * cb_buserr_intr() is responsible for handling control block 1457 * errors(errors which stem from the host bus side of the bridge). Since 1458 * we support multiple chips and host bus standards, cb_buserr_intr will 1459 * call a bus specific error handler to report and handle the detected 1460 * error. Since this error can either affect or orginate from either of the 1461 * two PCI busses which are connected to the bridge, we need to call 1462 * pci_pbm_err_handler() for each bus as well to report their errors. We 1463 * also need to gather possible errors which have been detected by their 1464 * compliant children(via ndi_fm_handler_dispatch()). 1465 * 1466 * pbm_error_intr() and ecc_intr() are responsible for PCI Block Module 1467 * errors(generic PCI + bridge specific) and ECC errors, respectively. They 1468 * are common between pcisch and pcipsy and therefore exist in pci_pbm.c and 1469 * pci_ecc.c. To support error handling certain chip specific handlers 1470 * must exist and they are defined below. 1471 * 1472 * cpu_deferred_error() and cpu_async_error(), handle the traps that may 1473 * have originated from IO space. They call into the registered IO callbacks 1474 * to report and handle errors that may have caused the trap. 1475 * 1476 * pci_pbm_err_handler() is called by pbm_error_intr() or pci_err_callback() 1477 * (generic fma callback for pcipsy/pcisch, pci_fm.c). pci_err_callback() is 1478 * called when the CPU has trapped because of a possible IO error(TO/BERR/UE). 1479 * It will call pci_pbm_err_handler() to report and handle all PCI/PBM/IOMMU 1480 * related errors which are detected by the chip. 1481 * 1482 * pci_pbm_err_handler() calls a generic interface pbm_afsr_report()(pci_pbm.c) 1483 * to report the pbm specific errors and attempt to map the failed address 1484 * (if captured) to a device instance. pbm_afsr_report() calls a chip specific 1485 * interface to interpret the afsr bits pci_pbm_classify()(pcisch.c/pcipsy.c). 1486 * pci_pbm_err_handler() also calls iommu_err_handler() to handle IOMMU related 1487 * errors. 1488 * 1489 * iommu_err_handler() can recover from most errors, as long as the requesting 1490 * device is notified and the iommu can be flushed. If an IOMMU error occurs 1491 * due to a UE then it will be passed on to the ecc_err_handler() for 1492 * subsequent handling. 1493 * 1494 * ecc_err_handler()(pci_ecc.c) also calls a chip specific interface to 1495 * interpret the afsr, pci_ecc_classify(). ecc_err_handler() also calls 1496 * pci_pbm_err_handler() to report any pbm errors detected. 1497 * 1498 * To make sure that the trap code and the interrupt code are not going 1499 * to step on each others toes we have a per chip pci_fm_mutex. This also 1500 * makes it necessary for us to be caution while we are at a high PIL, so 1501 * that we do not cause a subsequent trap that causes us to hang. 1502 * 1503 * The attempt to commonize code was meant to keep in line with the current 1504 * pci driver implementation and it was not meant to confuse. If you are 1505 * confused then don't worry, I was too. 1506 * 1507 */ 1508 static void 1509 pci_cb_errstate_get(cb_t *cb_p, cb_errstate_t *cb_err_p) 1510 { 1511 uint64_t pa = cb_p->cb_base_pa; 1512 int i; 1513 1514 bzero(cb_err_p, sizeof (cb_errstate_t)); 1515 1516 ASSERT(MUTEX_HELD(&cb_p->cb_pci_cmn_p->pci_fm_mutex)); 1517 1518 cb_err_p->cb_bridge_type = PCI_BRIDGE_TYPE(cb_p->cb_pci_cmn_p); 1519 1520 cb_err_p->cb_csr = lddphysio(pa + SCHIZO_CB_CSR_OFFSET); 1521 cb_err_p->cb_err = lddphysio(pa + SCHIZO_CB_ERRCTRL_OFFSET); 1522 cb_err_p->cb_intr = lddphysio(pa + SCHIZO_CB_INTCTRL_OFFSET); 1523 cb_err_p->cb_elog = lddphysio(pa + SCHIZO_CB_ERRLOG_OFFSET); 1524 cb_err_p->cb_ecc = lddphysio(pa + SCHIZO_CB_ECCCTRL_OFFSET); 1525 cb_err_p->cb_ue_afsr = lddphysio(pa + SCHIZO_CB_UEAFSR_OFFSET); 1526 cb_err_p->cb_ue_afar = lddphysio(pa + SCHIZO_CB_UEAFAR_OFFSET); 1527 cb_err_p->cb_ce_afsr = lddphysio(pa + SCHIZO_CB_CEAFSR_OFFSET); 1528 cb_err_p->cb_ce_afar = lddphysio(pa + SCHIZO_CB_CEAFAR_OFFSET); 1529 1530 if ((CB_CHIP_TYPE((cb_t *)cb_p)) == PCI_CHIP_XMITS) { 1531 cb_err_p->cb_first_elog = lddphysio(pa + 1532 XMITS_CB_FIRST_ERROR_LOG); 1533 cb_err_p->cb_first_eaddr = lddphysio(pa + 1534 XMITS_CB_FIRST_ERROR_ADDR); 1535 cb_err_p->cb_leaf_status = lddphysio(pa + 1536 XMITS_CB_FIRST_ERROR_ADDR); 1537 } 1538 1539 /* Gather PBM state information for both sides of this chip */ 1540 for (i = 0; i < 2; i++) { 1541 if (cb_p->cb_pci_cmn_p->pci_p[i] == NULL) 1542 continue; 1543 pci_pbm_errstate_get(((cb_t *)cb_p)->cb_pci_cmn_p-> 1544 pci_p[i], &cb_err_p->cb_pbm[i]); 1545 } 1546 } 1547 1548 static void 1549 pci_cb_clear_error(cb_t *cb_p, cb_errstate_t *cb_err_p) 1550 { 1551 uint64_t pa = ((cb_t *)cb_p)->cb_base_pa; 1552 1553 stdphysio(pa + SCHIZO_CB_ERRLOG_OFFSET, cb_err_p->cb_elog); 1554 } 1555 1556 static cb_fm_err_t safari_err_tbl[] = { 1557 SAFARI_BAD_CMD, SCHIZO_CB_ELOG_BAD_CMD, CB_FATAL, 1558 SAFARI_SSM_DIS, SCHIZO_CB_ELOG_SSM_DIS, CB_FATAL, 1559 SAFARI_BAD_CMD_PCIA, SCHIZO_CB_ELOG_BAD_CMD_PCIA, CB_FATAL, 1560 SAFARI_BAD_CMD_PCIB, SCHIZO_CB_ELOG_BAD_CMD_PCIB, CB_FATAL, 1561 SAFARI_PAR_ERR_INT_PCIB, XMITS_CB_ELOG_PAR_ERR_INT_PCIB, CB_FATAL, 1562 SAFARI_PAR_ERR_INT_PCIA, XMITS_CB_ELOG_PAR_ERR_INT_PCIA, CB_FATAL, 1563 SAFARI_PAR_ERR_INT_SAF, XMITS_CB_ELOG_PAR_ERR_INT_SAF, CB_FATAL, 1564 SAFARI_PLL_ERR_PCIB, XMITS_CB_ELOG_PLL_ERR_PCIB, CB_FATAL, 1565 SAFARI_PLL_ERR_PCIA, XMITS_CB_ELOG_PLL_ERR_PCIA, CB_FATAL, 1566 SAFARI_PLL_ERR_SAF, XMITS_CB_ELOG_PLL_ERR_SAF, CB_FATAL, 1567 SAFARI_SAF_CIQ_TO, SCHIZO_CB_ELOG_SAF_CIQ_TO, CB_FATAL, 1568 SAFARI_SAF_LPQ_TO, SCHIZO_CB_ELOG_SAF_LPQ_TO, CB_FATAL, 1569 SAFARI_SAF_SFPQ_TO, SCHIZO_CB_ELOG_SAF_SFPQ_TO, CB_FATAL, 1570 SAFARI_APERR, SCHIZO_CB_ELOG_ADDR_PAR_ERR, CB_FATAL, 1571 SAFARI_UNMAP_ERR, SCHIZO_CB_ELOG_UNMAP_ERR, CB_FATAL, 1572 SAFARI_BUS_ERR, SCHIZO_CB_ELOG_BUS_ERR, CB_FATAL, 1573 SAFARI_TO_ERR, SCHIZO_CB_ELOG_TO_ERR, CB_FATAL, 1574 SAFARI_DSTAT_ERR, SCHIZO_CB_ELOG_DSTAT_ERR, CB_FATAL, 1575 SAFARI_SAF_UFPQ_TO, SCHIZO_CB_ELOG_SAF_UFPQ_TO, CB_FATAL, 1576 SAFARI_CPU0_PAR_SINGLE, SCHIZO_CB_ELOG_CPU0_PAR_SINGLE, CB_FATAL, 1577 SAFARI_CPU0_PAR_BIDI, SCHIZO_CB_ELOG_CPU0_PAR_BIDI, CB_FATAL, 1578 SAFARI_CPU1_PAR_SINGLE, SCHIZO_CB_ELOG_CPU1_PAR_SINGLE, CB_FATAL, 1579 SAFARI_CPU1_PAR_BIDI, SCHIZO_CB_ELOG_CPU1_PAR_BIDI, CB_FATAL, 1580 NULL, NULL, NULL, 1581 }; 1582 1583 /* 1584 * Function used to handle and log Safari bus errors. 1585 */ 1586 static int 1587 safari_err_handler(dev_info_t *dip, uint64_t fme_ena, 1588 cb_errstate_t *cb_err_p) 1589 { 1590 int i; 1591 int fatal = 0; 1592 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1593 pci_common_t *cmn_p = pci_p->pci_common_p; 1594 1595 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1596 1597 for (i = 0; safari_err_tbl[i].cb_err_class != NULL; i++) { 1598 if (cb_err_p->cb_elog & safari_err_tbl[i].cb_reg_bit) { 1599 cb_err_p->cb_err_class = safari_err_tbl[i].cb_err_class; 1600 cb_ereport_post(dip, fme_ena, cb_err_p); 1601 fatal += safari_err_tbl[i].cb_fatal; 1602 } 1603 } 1604 1605 if (fatal) 1606 return (DDI_FM_FATAL); 1607 return (DDI_FM_OK); 1608 1609 } 1610 1611 /* 1612 * Check pbm va log register for captured errant address, and fail handle 1613 * if in per device cache. 1614 * Called from jbus_err_handler. 1615 */ 1616 static int 1617 jbus_check_va_log(cb_t *cb_p, uint64_t fme_ena, 1618 cb_errstate_t *cb_err_p) 1619 { 1620 int i; 1621 int ret = DDI_FM_FATAL; 1622 pci_common_t *cmn_p = cb_p->cb_pci_cmn_p; 1623 1624 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1625 /* 1626 * Check VA log register for address associated with error, 1627 * if no address is registered then return failure 1628 */ 1629 for (i = 0; i < 2; i++) { 1630 1631 if (cb_p->cb_pci_cmn_p->pci_p[i] == NULL) 1632 continue; 1633 /* 1634 * Look up and fault handle associated with 1635 * logged DMA address 1636 */ 1637 if (cb_err_p->cb_pbm[i].pbm_va_log) { 1638 void *addr = (void *)&cb_err_p->cb_pbm[i].pbm_va_log; 1639 ret = ndi_fmc_error(cb_p->cb_pci_cmn_p->pci_p[i]-> 1640 pci_dip, NULL, DMA_HANDLE, fme_ena, 1641 (void *)addr); 1642 if (ret == DDI_FM_NONFATAL) 1643 break; 1644 } 1645 } 1646 return (ret); 1647 } 1648 1649 static cb_fm_err_t jbus_err_tbl[] = { 1650 JBUS_APERR, SCHIZO_CB_ELOG_ADDR_PAR_ERR, CB_FATAL, 1651 JBUS_PWR_DATA_PERR, TOMATILLO_CB_ELOG_WR_DATA_PAR_ERR, CB_FATAL, 1652 JBUS_DRD_DATA_PERR, TOMATILLO_CB_ELOG_RD_DATA_PAR_ERR, CB_NONFATAL, 1653 JBUS_CTL_PERR, TOMATILLO_CB_ELOG_CTL_PAR_ERR, CB_FATAL, 1654 JBUS_ILL_BYTE_EN, TOMATILLO_CB_ELOG_ILL_BYTE_EN, CB_FATAL, 1655 JBUS_ILL_COH_IN, TOMATILLO_CB_ELOG_ILL_COH_IN, CB_FATAL, 1656 JBUS_SNOOP_ERR_RD, TOMATILLO_CB_ELOG_SNOOP_ERR_RD, CB_FATAL, 1657 JBUS_SNOOP_ERR_RDS, TOMATILLO_CB_ELOG_SNOOP_ERR_RDS, CB_FATAL, 1658 JBUS_SNOOP_ERR_RDSA, TOMATILLO_CB_ELOG_SNOOP_ERR_RDSA, CB_FATAL, 1659 JBUS_SNOOP_ERR_OWN, TOMATILLO_CB_ELOG_SNOOP_ERR_OWN, CB_FATAL, 1660 JBUS_SNOOP_ERR_RDO, TOMATILLO_CB_ELOG_SNOOP_ERR_RDO, CB_FATAL, 1661 JBUS_SNOOP_ERR_PCI, TOMATILLO_CB_ELOG_SNOOP_ERR_PCI, CB_FATAL, 1662 JBUS_SNOOP_ERR_GR, TOMATILLO_CB_ELOG_SNOOP_ERR_GR, CB_FATAL, 1663 JBUS_SNOOP_ERR, TOMATILLO_CB_ELOG_SNOOP_ERR, CB_FATAL, 1664 JBUS_BAD_CMD, SCHIZO_CB_ELOG_BAD_CMD, CB_FATAL, 1665 JBUS_UNMAP_ERR, SCHIZO_CB_ELOG_UNMAP_ERR, CB_NONFATAL, 1666 JBUS_TO_EXP_ERR, TOMATILLO_CB_ELOG_TO_EXP_ERR, CB_NONFATAL, 1667 JBUS_TO_ERR, SCHIZO_CB_ELOG_TO_ERR, CB_NONFATAL, 1668 JBUS_BUS_ERR, SCHIZO_CB_ELOG_BUS_ERR, CB_NONFATAL, 1669 NULL, NULL, NULL, 1670 }; 1671 1672 /* 1673 * Function used to handle and log Jbus errors. 1674 */ 1675 static int 1676 jbus_err_handler(dev_info_t *dip, uint64_t fme_ena, 1677 cb_errstate_t *cb_err_p) 1678 { 1679 int fatal = 0; 1680 int nonfatal = 0; 1681 int i; 1682 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1683 cb_t *cb_p = pci_p->pci_cb_p; 1684 1685 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1686 1687 for (i = 0; jbus_err_tbl[i].cb_err_class != NULL; i++) { 1688 if (!(cb_err_p->cb_elog & jbus_err_tbl[i].cb_reg_bit)) 1689 continue; 1690 cb_err_p->cb_err_class = jbus_err_tbl[i].cb_err_class; 1691 if (jbus_err_tbl[i].cb_fatal) { 1692 fatal += jbus_err_tbl[i].cb_fatal; 1693 continue; 1694 } 1695 if (jbus_check_va_log(cb_p, fme_ena, cb_err_p) 1696 != DDI_FM_NONFATAL) { 1697 fatal++; 1698 } 1699 cb_ereport_post(dip, fme_ena, cb_err_p); 1700 } 1701 1702 return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 1703 DDI_FM_OK)); 1704 } 1705 1706 /* 1707 * Control Block error interrupt handler. 1708 */ 1709 uint_t 1710 cb_buserr_intr(caddr_t a) 1711 { 1712 cb_t *cb_p = (cb_t *)a; 1713 pci_common_t *cmn_p = cb_p->cb_pci_cmn_p; 1714 pci_t *pci_p = cmn_p->pci_p[0]; 1715 cb_errstate_t cb_err; 1716 ddi_fm_error_t derr; 1717 int ret = DDI_FM_FATAL; 1718 int i; 1719 1720 if (pci_p == NULL) 1721 pci_p = cmn_p->pci_p[1]; 1722 1723 bzero(&derr, sizeof (ddi_fm_error_t)); 1724 derr.fme_version = DDI_FME_VERSION; 1725 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1726 1727 mutex_enter(&cmn_p->pci_fm_mutex); 1728 1729 pci_cb_errstate_get(cb_p, &cb_err); 1730 1731 if (CB_CHIP_TYPE(cb_p) == PCI_CHIP_TOMATILLO) 1732 ret = jbus_err_handler(pci_p->pci_dip, derr.fme_ena, &cb_err); 1733 else if ((CB_CHIP_TYPE(cb_p) == PCI_CHIP_SCHIZO) || 1734 (CB_CHIP_TYPE(cb_p) == PCI_CHIP_XMITS)) 1735 ret = safari_err_handler(pci_p->pci_dip, derr.fme_ena, 1736 &cb_err); 1737 1738 /* 1739 * Check for related errors in PBM and IOMMU. The IOMMU could cause 1740 * a timeout on the jbus due to an IOMMU miss, so we need to check and 1741 * log the IOMMU error registers. 1742 */ 1743 for (i = 0; i < 2; i++) { 1744 if (cmn_p->pci_p[i] == NULL) 1745 continue; 1746 if (pci_pbm_err_handler(cmn_p->pci_p[i]->pci_dip, &derr, 1747 (void *)cmn_p->pci_p[i], PCI_CB_CALL) == DDI_FM_FATAL) 1748 ret = DDI_FM_FATAL; 1749 } 1750 1751 /* Cleanup and reset error bits */ 1752 (void) pci_cb_clear_error(cb_p, &cb_err); 1753 mutex_exit(&cmn_p->pci_fm_mutex); 1754 1755 if (ret == DDI_FM_FATAL) { 1756 fm_panic("Fatal System Bus Error has occurred\n"); 1757 } 1758 1759 return (DDI_INTR_CLAIMED); 1760 } 1761 1762 static ecc_fm_err_t ecc_err_tbl[] = { 1763 PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1764 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_UPA64S, SCH_REG_UPA, 1765 ACC_HANDLE, 1766 1767 PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1768 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_REG, SCH_REG_PCIA_REG, 1769 ACC_HANDLE, 1770 1771 PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1772 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_MEM, SCH_REG_PCIA_MEM, 1773 ACC_HANDLE, 1774 1775 PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1776 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_CFGIO, SCH_REG_PCIA_CFGIO, 1777 ACC_HANDLE, 1778 1779 PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1780 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_REG, SCH_REG_PCIB_REG, 1781 ACC_HANDLE, 1782 1783 PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1784 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_MEM, SCH_REG_PCIB_MEM, 1785 ACC_HANDLE, 1786 1787 PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1788 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_CFGIO, SCH_REG_PCIB_CFGIO, 1789 ACC_HANDLE, 1790 1791 PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1792 PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_SAFARI_REGS, SCH_REG_SAFARI_REGS, 1793 ACC_HANDLE, 1794 1795 PCI_ECC_SEC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1796 PBM_SECONDARY, NULL, NULL, ACC_HANDLE, 1797 1798 PCI_ECC_PIO_CE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_CE, 1799 PBM_PRIMARY, NULL, NULL, ACC_HANDLE, 1800 1801 PCI_ECC_SEC_PIO_CE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_CE, 1802 PBM_SECONDARY, NULL, NULL, ACC_HANDLE, 1803 1804 PCI_ECC_DRD_UE, COMMON_ECC_UE_AFSR_E_DRD, CBNINTR_UE, 1805 PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1806 1807 PCI_ECC_SEC_DRD_UE, COMMON_ECC_UE_AFSR_E_DRD, CBNINTR_UE, 1808 PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1809 1810 PCI_ECC_DRD_CE, COMMON_ECC_UE_AFSR_E_DRD, CBNINTR_CE, 1811 PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1812 1813 PCI_ECC_SEC_DRD_CE, COMMON_ECC_UE_AFSR_E_DRD, CBNINTR_CE, 1814 PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1815 1816 PCI_ECC_DWR_UE, COMMON_ECC_UE_AFSR_E_DWR, CBNINTR_UE, 1817 PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1818 1819 PCI_ECC_SEC_DWR_UE, COMMON_ECC_UE_AFSR_E_DWR, CBNINTR_UE, 1820 PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1821 1822 PCI_ECC_DWR_CE, COMMON_ECC_UE_AFSR_E_DWR, CBNINTR_CE, 1823 PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1824 1825 PCI_ECC_SEC_DWR_CE, COMMON_ECC_UE_AFSR_E_DWR, CBNINTR_CE, 1826 PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1827 1828 NULL, NULL, NULL, NULL, NULL, NULL, 1829 }; 1830 1831 /* 1832 * pci_ecc_classify, called by ecc_handler to classify ecc errors 1833 * and determine if we should panic or not. 1834 */ 1835 void 1836 pci_ecc_classify(uint64_t err, ecc_errstate_t *ecc_err_p) 1837 { 1838 struct async_flt *ecc_p = &ecc_err_p->ecc_aflt; 1839 uint64_t region, afar = ecc_p->flt_addr; 1840 int i, j, ret = 0; 1841 int flag, fatal = 0; 1842 pci_common_t *cmn_p = ecc_err_p->ecc_ii_p.ecc_p->ecc_pci_cmn_p; 1843 pci_t *pci_p = cmn_p->pci_p[0]; 1844 1845 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1846 1847 ecc_err_p->ecc_bridge_type = PCI_BRIDGE_TYPE(cmn_p); 1848 1849 if (pci_p == NULL) 1850 pci_p = cmn_p->pci_p[1]; 1851 1852 ecc_err_p->ecc_ctrl = lddphysio(ecc_err_p->ecc_ii_p.ecc_p->ecc_csr_pa); 1853 ecc_err_p->ecc_err_addr = afar; 1854 region = afar & SCHIZO_ECC_AFAR_PIOW_MASK; 1855 1856 for (i = 0; ecc_err_tbl[i].ecc_err_class != NULL; i++) { 1857 if (!(err & ecc_err_tbl[i].ecc_reg_bit) || 1858 (ecc_err_p->ecc_ii_p.ecc_type != 1859 ecc_err_tbl[i].ecc_type) || 1860 (ecc_err_p->ecc_pri != ecc_err_tbl[i].ecc_pri)) 1861 continue; 1862 1863 ecc_p->flt_erpt_class = ecc_err_tbl[i].ecc_err_class; 1864 flag = ecc_err_tbl[i].ecc_flag; 1865 1866 if (!ecc_err_tbl[i].ecc_pri || 1867 (ecc_err_tbl[i].ecc_type == CBNINTR_CE)) { 1868 fatal += (ecc_err_tbl[i].ecc_type == CBNINTR_UE) ? 1869 1 : 0; 1870 break; 1871 } 1872 1873 if (flag == ACC_HANDLE && 1874 (region & ecc_err_tbl[i].ecc_region_bits)) { 1875 ecc_err_p->ecc_region = ecc_err_tbl[i].ecc_region; 1876 pci_format_ecc_addr(pci_p->pci_dip, 1877 &ecc_err_p->ecc_err_addr, 1878 ecc_err_p->ecc_region); 1879 } 1880 1881 /* 1882 * Lookup and fault errant handle 1883 */ 1884 for (j = 0; j < 2; ++j) { 1885 ret = DDI_FM_UNKNOWN; 1886 if (cmn_p->pci_p[j] == NULL) 1887 continue; 1888 ret = ndi_fmc_error(cmn_p->pci_p[j]->pci_dip, NULL, 1889 flag, ecc_err_p->ecc_ena, 1890 (void *)&ecc_err_p->ecc_err_addr); 1891 if (ret == DDI_FM_NONFATAL) { 1892 fatal = 0; 1893 break; 1894 } else 1895 fatal++; 1896 } 1897 break; 1898 } 1899 1900 if (fatal) 1901 ecc_p->flt_panic = 1; 1902 else if (flag != ACC_HANDLE) 1903 ecc_err_p->ecc_pg_ret = 1; 1904 } 1905 1906 /* 1907 * Tables to define PCI-X Split Completion errors 1908 */ 1909 1910 pcix_err_msg_rec_t pcix_completer_errs[] = { 1911 {PCIX_CPLT_OUT_OF_RANGE, "pcix", "oor" }, 1912 }; 1913 1914 pcix_err_tbl_t pcix_split_errs_tbl[] = { 1915 {PCIX_CLASS_CPLT, 1916 sizeof (pcix_completer_errs)/sizeof (pcix_err_msg_rec_t), 1917 pcix_completer_errs }, 1918 }; 1919 1920 /* 1921 * Tables for the PCI-X error status messages 1922 */ 1923 pcix_err_msg_rec_t pcix_stat_errs[] = { 1924 {XMITS_PCIX_STAT_SC_DSCRD, "pcix", "discard" }, 1925 {XMITS_PCIX_STAT_SC_TTO, "xmits.pbmx", "tato" }, 1926 {XMITS_PCIX_STAT_SMMU, "xmits.pbmx", "stmmu" }, 1927 {XMITS_PCIX_STAT_SDSTAT, "xmits.pbmx", "stdst" }, 1928 {XMITS_PCIX_STAT_CMMU, "xmits.pbmx", "cnmmu" }, 1929 {XMITS_PCIX_STAT_CDSTAT, "xmits.pbmx", "cndst" } 1930 }; 1931 1932 pcix_err_tbl_t pcix_stat_errs_tbl = 1933 {PCIX_NO_CLASS, 1934 sizeof (pcix_stat_errs)/sizeof (pcix_err_msg_rec_t), 1935 pcix_stat_errs }; 1936 1937 1938 /* 1939 * walk thru a table of error messages, printing as appropriate 1940 * 1941 * t - the table of messages to parse 1942 * err - the error to match against 1943 * multi - flag, sometimes multiple error bits may be set/desired 1944 */ 1945 static int 1946 pcix_lookup_err_msgs(dev_info_t *dip, uint64_t ena, pcix_err_tbl_t t, 1947 pbm_errstate_t *pbm_err_p) 1948 { 1949 uint32_t err_bits = pbm_err_p->pbm_err & XMITS_PCIX_MSG_INDEX_MASK; 1950 int nerr = 0; 1951 int j; 1952 char buf[FM_MAX_CLASS]; 1953 1954 for (j = 0; j < t.err_rec_num; j++) { 1955 uint32_t msg_key = t.err_msg_tbl[j].msg_key; 1956 if (pbm_err_p->pbm_multi ? !(err_bits & msg_key) : err_bits 1957 != msg_key) 1958 continue; 1959 1960 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s%s", 1961 t.err_msg_tbl[j].msg_class, 1962 pbm_err_p->pbm_pri ? "" : PCIX_SECONDARY, 1963 t.err_msg_tbl[j].msg_str); 1964 1965 pbm_err_p->pbm_err_class = buf; 1966 pcix_ereport_post(dip, ena, pbm_err_p); 1967 nerr++; 1968 } 1969 return (nerr ? DDI_FM_FATAL : DDI_FM_OK); 1970 } 1971 1972 /* 1973 * Decodes primary(bit 27-24) or secondary(bit 15-12) PCI-X split 1974 * completion error message class and index in PBM AFSR. 1975 */ 1976 static void 1977 pcix_log_split_err(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p) 1978 { 1979 uint32_t class = pbm_err_p->pbm_err & XMITS_PCIX_MSG_CLASS_MASK; 1980 uint32_t num_classes = sizeof (pcix_split_errs_tbl) / 1981 sizeof (struct pcix_err_tbl); 1982 int i; 1983 1984 for (i = 0; i < num_classes; i++) { 1985 if (class == pcix_split_errs_tbl[i].err_class) { 1986 pbm_err_p->pbm_multi = PCIX_SINGLE_ERR; 1987 (void) pcix_lookup_err_msgs(dip, ena, 1988 pcix_split_errs_tbl[i], pbm_err_p); 1989 break; 1990 } 1991 } 1992 } 1993 1994 /* 1995 * Report PBM PCI-X Error Status Register if in PCI-X mode 1996 * 1997 * Once a PCI-X fault tree is constructed, the code below may need to 1998 * change. 1999 */ 2000 static int 2001 pcix_log_pbm(pci_t *pci_p, uint64_t ena, pbm_errstate_t *pbm_err_p) 2002 { 2003 int fatal = 0; 2004 int nonfatal = 0; 2005 uint32_t e; 2006 2007 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2008 2009 DEBUG3(DBG_ERR_INTR, pci_p->pci_dip, "pcix_log_pbm: chip_type=%d " 2010 "ctr_stat=%lx afsr = 0x%lx", CHIP_TYPE(pci_p), 2011 pbm_err_p->pbm_ctl_stat, pbm_err_p->pbm_afsr); 2012 2013 if (!(CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) || 2014 !(pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) 2015 return (DDI_FM_OK); 2016 2017 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) { 2018 pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr); 2019 pbm_err_p->pbm_pri = PBM_PRIMARY; 2020 pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p); 2021 nonfatal++; 2022 } 2023 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) { 2024 pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr); 2025 pbm_err_p->pbm_pri = PBM_PRIMARY; 2026 pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p); 2027 nonfatal++; 2028 } 2029 2030 e = PBM_PCIX_TO_PRIERR(pbm_err_p->pbm_pcix_stat); 2031 if (e) { 2032 pbm_err_p->pbm_pri = PBM_PRIMARY; 2033 pbm_err_p->pbm_err = e; 2034 pbm_err_p->pbm_multi = PCIX_MULTI_ERR; 2035 if (pcix_lookup_err_msgs(pci_p->pci_dip, ena, 2036 pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL) 2037 fatal++; 2038 else 2039 nonfatal++; 2040 } 2041 2042 e = PBM_PCIX_TO_SECERR(pbm_err_p->pbm_pcix_stat); 2043 if (e) { 2044 pbm_err_p->pbm_pri = PBM_SECONDARY; 2045 pbm_err_p->pbm_err = e; 2046 pbm_err_p->pbm_multi = PCIX_MULTI_ERR; 2047 if (pcix_lookup_err_msgs(pci_p->pci_dip, ena, 2048 pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL) 2049 fatal++; 2050 else 2051 nonfatal++; 2052 } 2053 2054 if (!fatal && !nonfatal) 2055 return (DDI_FM_OK); 2056 else if (fatal) 2057 return (DDI_FM_FATAL); 2058 return (DDI_FM_NONFATAL); 2059 } 2060 2061 static pbm_fm_err_t pbm_err_tbl[] = { 2062 PCI_MA, SCHIZO_PCI_AFSR_E_MA, PBM_PRIMARY, 2063 FM_LOG_PCI, PCI_TARG_MA, 2064 2065 PCI_SEC_MA, SCHIZO_PCI_AFSR_E_MA, PBM_SECONDARY, 2066 FM_LOG_PBM, NULL, 2067 2068 PCI_REC_TA, SCHIZO_PCI_AFSR_E_TA, PBM_PRIMARY, 2069 FM_LOG_PCI, PCI_TARG_REC_TA, 2070 2071 PCI_SEC_REC_TA, SCHIZO_PCI_AFSR_E_TA, PBM_SECONDARY, 2072 FM_LOG_PBM, NULL, 2073 2074 PCI_PBM_RETRY, SCHIZO_PCI_AFSR_E_RTRY, PBM_PRIMARY, 2075 FM_LOG_PBM, PCI_PBM_TARG_RETRY, 2076 2077 PCI_SEC_PBM_RETRY, SCHIZO_PCI_AFSR_E_RTRY, PBM_SECONDARY, 2078 FM_LOG_PBM, NULL, 2079 2080 PCI_MDPE, SCHIZO_PCI_AFSR_E_PERR, PBM_PRIMARY, 2081 FM_LOG_PCI, PCI_TARG_MDPE, 2082 2083 PCI_SEC_MDPE, SCHIZO_PCI_AFSR_E_PERR, PBM_SECONDARY, 2084 FM_LOG_PBM, NULL, 2085 2086 PCI_PBM_TTO, SCHIZO_PCI_AFSR_E_TTO, PBM_PRIMARY, 2087 FM_LOG_PBM, PCI_PBM_TARG_TTO, 2088 2089 PCI_SEC_PBM_TTO, SCHIZO_PCI_AFSR_E_TTO, PBM_SECONDARY, 2090 FM_LOG_PBM, NULL, 2091 2092 PCI_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_AFSR_E_UNUSABLE, PBM_PRIMARY, 2093 FM_LOG_PBM, NULL, 2094 2095 PCI_SEC_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_AFSR_E_UNUSABLE, PBM_SECONDARY, 2096 FM_LOG_PBM, NULL, 2097 2098 NULL, NULL, NULL, 2099 NULL, NULL, 2100 }; 2101 2102 2103 /* 2104 * pci_pbm_classify, called by pbm_afsr_report to classify piow afsr. 2105 */ 2106 int 2107 pci_pbm_classify(pbm_errstate_t *pbm_err_p) 2108 { 2109 uint32_t err; 2110 int nerr = 0; 2111 int i; 2112 2113 err = pbm_err_p->pbm_pri ? PBM_AFSR_TO_PRIERR(pbm_err_p->pbm_afsr): 2114 PBM_AFSR_TO_SECERR(pbm_err_p->pbm_afsr); 2115 2116 for (i = 0; pbm_err_tbl[i].pbm_err_class != NULL; i++) { 2117 if ((err & pbm_err_tbl[i].pbm_reg_bit) && 2118 (pbm_err_p->pbm_pri == pbm_err_tbl[i].pbm_pri)) { 2119 if (pbm_err_tbl[i].pbm_flag == FM_LOG_PCI) 2120 pbm_err_p->pbm_pci.pci_err_class = 2121 pbm_err_tbl[i].pbm_err_class; 2122 else 2123 pbm_err_p->pbm_err_class = 2124 pbm_err_tbl[i].pbm_err_class; 2125 2126 pbm_err_p->pbm_terr_class = 2127 pbm_err_tbl[i].pbm_terr_class; 2128 pbm_err_p->pbm_log = pbm_err_tbl[i].pbm_flag; 2129 nerr++; 2130 break; 2131 } 2132 } 2133 2134 return (nerr); 2135 } 2136 2137 /* 2138 * Function used to handle and log IOMMU errors. Called by pci_pbm_err_handler, 2139 * with pci_fm_mutex held. 2140 */ 2141 static int 2142 iommu_err_handler(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p) 2143 { 2144 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2145 iommu_t *iommu_p = pci_p->pci_iommu_p; 2146 ecc_t *ecc_p = pci_p->pci_ecc_p; 2147 uint64_t stat; 2148 ushort_t ta_signalled; 2149 int err = 0; 2150 int fatal = 0; 2151 int nonfatal = 0; 2152 int ret; 2153 2154 ASSERT(MUTEX_HELD(&ecc_p->ecc_pci_cmn_p->pci_fm_mutex)); 2155 if (!((stat = *iommu_p->iommu_ctrl_reg) & TOMATILLO_IOMMU_ERR)) { 2156 pbm_err_p->pbm_err_class = PCI_SCH_MMU_ERR; 2157 iommu_ereport_post(dip, ena, pbm_err_p); 2158 return (DDI_FM_NONFATAL); 2159 } 2160 2161 /* 2162 * Need to make sure a Target Abort was signalled to the device if 2163 * we have any hope of recovering. Tomatillo does not send a TA for 2164 * DMA Writes that result in a Translation Error, thus fooling the 2165 * device into believing everything is as it expects. Ignorance 2166 * is bliss, but knowledge is power. 2167 */ 2168 ta_signalled = pbm_err_p->pbm_pci.pci_cfg_stat & 2169 PCI_STAT_S_TARG_AB; 2170 2171 if (stat & TOMATILLO_IOMMU_ERR_ILLTSBTBW) { 2172 pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_TSBTBW; 2173 err = 1; 2174 iommu_ereport_post(dip, ena, pbm_err_p); 2175 if (!ta_signalled) 2176 fatal++; 2177 else 2178 nonfatal++; 2179 } 2180 2181 if (stat & TOMATILLO_IOMMU_ERR_BAD_VA) { 2182 pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_VA; 2183 err = 1; 2184 iommu_ereport_post(dip, ena, pbm_err_p); 2185 if (!ta_signalled) 2186 fatal++; 2187 else 2188 nonfatal++; 2189 } 2190 2191 if (!err) { 2192 stat = ((stat & TOMATILLO_IOMMU_ERRSTS) >> 2193 TOMATILLO_IOMMU_ERRSTS_SHIFT); 2194 switch (stat) { 2195 case TOMATILLO_IOMMU_PROTECTION_ERR: 2196 pbm_err_p->pbm_err_class = PCI_TOM_MMU_PROT_ERR; 2197 iommu_ereport_post(dip, ena, pbm_err_p); 2198 fatal++; 2199 break; 2200 case TOMATILLO_IOMMU_INVALID_ERR: 2201 pbm_err_p->pbm_err_class = PCI_TOM_MMU_INVAL_ERR; 2202 /* 2203 * Fault the address in iommu_tfar 2204 * register to inform target driver of error 2205 */ 2206 ret = ndi_fmc_error(pci_p->pci_dip, NULL, DMA_HANDLE, 2207 ena, (void *)&pbm_err_p->pbm_iommu.iommu_tfar); 2208 2209 if (ret != DDI_FM_NONFATAL) 2210 if (ta_signalled) 2211 nonfatal++; 2212 else 2213 fatal++; 2214 else 2215 nonfatal++; 2216 2217 iommu_ereport_post(dip, ena, pbm_err_p); 2218 break; 2219 case TOMATILLO_IOMMU_TIMEOUT_ERR: 2220 pbm_err_p->pbm_err_class = PCI_TOM_MMU_TO_ERR; 2221 fatal++; 2222 iommu_ereport_post(dip, ena, pbm_err_p); 2223 break; 2224 case TOMATILLO_IOMMU_ECC_ERR: 2225 pbm_err_p->pbm_err_class = PCI_TOM_MMU_UE; 2226 iommu_ereport_post(dip, ena, pbm_err_p); 2227 break; 2228 } 2229 } 2230 2231 if (fatal) 2232 return (DDI_FM_FATAL); 2233 else if (nonfatal) 2234 return (DDI_FM_NONFATAL); 2235 2236 return (DDI_FM_OK); 2237 } 2238 2239 int 2240 pci_check_error(pci_t *pci_p) 2241 { 2242 pbm_t *pbm_p = pci_p->pci_pbm_p; 2243 uint16_t pci_cfg_stat; 2244 uint64_t pbm_ctl_stat, pbm_afsr, pbm_pcix_stat; 2245 caddr_t a = pci_p->pci_address[0]; 2246 uint64_t *pbm_pcix_stat_reg; 2247 2248 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2249 2250 pci_cfg_stat = pbm_p->pbm_config_header->ch_status_reg; 2251 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2252 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2253 2254 if ((pci_cfg_stat & (PCI_STAT_S_PERROR | PCI_STAT_S_TARG_AB | 2255 PCI_STAT_R_TARG_AB | PCI_STAT_R_MAST_AB | 2256 PCI_STAT_S_SYSERR | PCI_STAT_PERROR)) || 2257 (pbm_ctl_stat & (SCHIZO_PCI_CTRL_BUS_UNUSABLE | 2258 TOMATILLO_PCI_CTRL_PCI_DTO_ERR | 2259 SCHIZO_PCI_CTRL_PCI_TTO_ERR | 2260 SCHIZO_PCI_CTRL_PCI_RTRY_ERR | 2261 SCHIZO_PCI_CTRL_PCI_MMU_ERR | 2262 COMMON_PCI_CTRL_SBH_ERR | 2263 COMMON_PCI_CTRL_SERR)) || 2264 (PBM_AFSR_TO_PRIERR(pbm_afsr))) 2265 return (1); 2266 2267 if ((CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) && 2268 (pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) { 2269 2270 pbm_pcix_stat_reg = (uint64_t *)(a + 2271 XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 2272 2273 pbm_pcix_stat = *pbm_pcix_stat_reg; 2274 2275 if (PBM_PCIX_TO_PRIERR(pbm_pcix_stat)) 2276 return (1); 2277 2278 if (pbm_pcix_stat & XMITS_PCIX_STAT_PERR_RECOV_INT) 2279 return (1); 2280 } 2281 2282 return (0); 2283 2284 } 2285 2286 static pbm_fm_err_t pci_pbm_err_tbl[] = { 2287 PCI_PBM_RETRY, SCHIZO_PCI_CTRL_PCI_RTRY_ERR, 2288 NULL, PBM_NONFATAL, PCI_PBM_TARG_RETRY, 2289 2290 PCI_PBM_TTO, SCHIZO_PCI_CTRL_PCI_TTO_ERR, 2291 NULL, PBM_NONFATAL, PCI_PBM_TARG_TTO, 2292 2293 PCI_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_CTRL_BUS_UNUSABLE, 2294 NULL, PBM_NONFATAL, NULL, 2295 2296 NULL, NULL, 2297 NULL, NULL, NULL 2298 }; 2299 2300 /* 2301 * Function used to log all PCI/PBM/IOMMU errors found in the system. 2302 * It is called by the pbm_error_intr as well as the pci_err_callback(trap 2303 * callback). To protect access we hold the pci_fm_mutex when calling 2304 * this function. 2305 */ 2306 int 2307 pci_pbm_err_handler(dev_info_t *dip, ddi_fm_error_t *derr, 2308 const void *impl_data, int caller) 2309 { 2310 int fatal = 0; 2311 int nonfatal = 0; 2312 int unknown = 0; 2313 uint32_t prierr, secerr; 2314 pbm_errstate_t pbm_err; 2315 char buf[FM_MAX_CLASS]; 2316 pci_t *pci_p = (pci_t *)impl_data; 2317 pbm_t *pbm_p = pci_p->pci_pbm_p; 2318 int i, ret = 0; 2319 2320 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2321 pci_pbm_errstate_get(pci_p, &pbm_err); 2322 2323 derr->fme_ena = derr->fme_ena ? derr->fme_ena : 2324 fm_ena_generate(0, FM_ENA_FMT1); 2325 2326 prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr); 2327 secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr); 2328 2329 if (derr->fme_flag == DDI_FM_ERR_EXPECTED) { 2330 if (caller == PCI_TRAP_CALL) { 2331 /* 2332 * For ddi_caut_get treat all events as nonfatal. 2333 * The trampoline will set err_ena = 0, err_status = 2334 * NONFATAL. We only really call this function so that 2335 * pci_clear_error() and ndi_fm_handler_dispatch() will 2336 * get called. 2337 */ 2338 derr->fme_status = DDI_FM_NONFATAL; 2339 nonfatal++; 2340 goto done; 2341 } else { 2342 /* 2343 * For ddi_caut_put treat all events as nonfatal. Here 2344 * we have the handle and can call ndi_fm_acc_err_set(). 2345 */ 2346 derr->fme_status = DDI_FM_NONFATAL; 2347 ndi_fm_acc_err_set(pbm_p->pbm_excl_handle, derr); 2348 nonfatal++; 2349 goto done; 2350 } 2351 } else if (derr->fme_flag == DDI_FM_ERR_PEEK) { 2352 /* 2353 * For ddi_peek treat all events as nonfatal. We only 2354 * really call this function so that pci_clear_error() 2355 * and ndi_fm_handler_dispatch() will get called. 2356 */ 2357 nonfatal++; 2358 goto done; 2359 } else if (derr->fme_flag == DDI_FM_ERR_POKE) { 2360 /* 2361 * For ddi_poke we can treat as nonfatal if the 2362 * following conditions are met : 2363 * 1. Make sure only primary error is MA/TA 2364 * 2. Make sure no secondary error bits set 2365 * 3. check pci config header stat reg to see MA/TA is 2366 * logged. We cannot verify only MA/TA is recorded 2367 * since it gets much more complicated when a 2368 * PCI-to-PCI bridge is present. 2369 */ 2370 if ((prierr == SCHIZO_PCI_AFSR_E_MA) && !secerr && 2371 (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_MAST_AB)) { 2372 nonfatal++; 2373 goto done; 2374 } else if ((*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) && 2375 pcix_ma_behind_bridge(&pbm_err)) { 2376 /* 2377 * MAs behind a PCI-X bridge get sent back to 2378 * the host as a Split Completion Error Message. 2379 * We handle this the same as the above check. 2380 */ 2381 nonfatal++; 2382 goto done; 2383 } 2384 if ((prierr == SCHIZO_PCI_AFSR_E_TA) && !secerr && 2385 (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_TARG_AB)) { 2386 nonfatal++; 2387 goto done; 2388 } 2389 } 2390 2391 DEBUG2(DBG_ERR_INTR, dip, "pci_pbm_err_handler: prierr=0x%x " 2392 "secerr=0x%x", prierr, secerr); 2393 2394 if (prierr || secerr) { 2395 ret = pbm_afsr_report(dip, derr->fme_ena, &pbm_err); 2396 if (ret == DDI_FM_FATAL) 2397 fatal++; 2398 else 2399 nonfatal++; 2400 } 2401 if ((ret = pcix_log_pbm(pci_p, derr->fme_ena, &pbm_err)) 2402 == DDI_FM_FATAL) 2403 fatal++; 2404 else if (ret == DDI_FM_NONFATAL) 2405 nonfatal++; 2406 2407 if ((ret = pci_cfg_report(dip, derr, &pbm_err.pbm_pci, caller, prierr)) 2408 == DDI_FM_FATAL) 2409 fatal++; 2410 else if (ret == DDI_FM_NONFATAL) 2411 nonfatal++; 2412 2413 for (i = 0; pci_pbm_err_tbl[i].pbm_err_class != NULL; i++) { 2414 if ((pbm_err.pbm_ctl_stat & pci_pbm_err_tbl[i].pbm_reg_bit) && 2415 !prierr) { 2416 pbm_err.pbm_err_class = 2417 pci_pbm_err_tbl[i].pbm_err_class; 2418 pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 2419 if (pci_pbm_err_tbl[i].pbm_flag) 2420 fatal++; 2421 else 2422 nonfatal++; 2423 if (caller == PCI_TRAP_CALL && 2424 pci_pbm_err_tbl[i].pbm_terr_class) 2425 pci_target_enqueue(derr->fme_ena, 2426 pci_pbm_err_tbl[i].pbm_terr_class, 2427 pbm_err.pbm_bridge_type, 2428 (uint64_t)derr->fme_bus_specific); 2429 } 2430 } 2431 2432 if ((pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SBH_ERR) && 2433 (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO)) { 2434 pbm_err.pbm_err_class = PCI_SCH_SBH; 2435 pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 2436 if (pci_panic_on_sbh_errors) 2437 fatal++; 2438 else 2439 nonfatal++; 2440 } 2441 2442 /* 2443 * PBM Received System Error - During any transaction, or 2444 * at any point on the bus, some device may detect a critical 2445 * error and signal a system error to the system. 2446 */ 2447 if (pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SERR) { 2448 /* 2449 * may be expected (master abort from pci-pci bridge during 2450 * poke will generate SERR) 2451 */ 2452 if (derr->fme_flag != DDI_FM_ERR_POKE) { 2453 DEBUG1(DBG_ERR_INTR, dip, "pci_pbm_err_handler: " 2454 "ereport_post: %s", buf); 2455 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2456 PCI_ERROR_SUBCLASS, PCI_REC_SERR); 2457 ddi_fm_ereport_post(dip, buf, derr->fme_ena, 2458 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2459 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 2460 pbm_err.pbm_pci.pci_cfg_stat, PCI_CONFIG_COMMAND, 2461 DATA_TYPE_UINT16, pbm_err.pbm_pci.pci_cfg_comm, 2462 PCI_PA, DATA_TYPE_UINT64, (uint64_t)0, NULL); 2463 } 2464 unknown++; 2465 } 2466 2467 /* 2468 * PCI Retry Timeout - Device fails to retry deferred 2469 * transaction within timeout. Only Tomatillo 2470 */ 2471 if (pbm_err.pbm_ctl_stat & TOMATILLO_PCI_CTRL_PCI_DTO_ERR) { 2472 if (pci_dto_fault_warn == CE_PANIC) 2473 fatal++; 2474 else 2475 nonfatal++; 2476 2477 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2478 PCI_ERROR_SUBCLASS, PCI_DTO); 2479 ddi_fm_ereport_post(dip, buf, derr->fme_ena, DDI_NOSLEEP, 2480 FM_VERSION, DATA_TYPE_UINT8, 0, 2481 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 2482 pbm_err.pbm_pci.pci_cfg_stat, 2483 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, 2484 pbm_err.pbm_pci.pci_cfg_comm, 2485 PCI_PA, DATA_TYPE_UINT64, (uint64_t)0, NULL); 2486 } 2487 2488 /* 2489 * PBM Detected Data Parity Error - DPE detected during a DMA Write 2490 * or PIO Read. Later case is taken care of by cpu_deferred_error 2491 * and sent here to be logged. 2492 */ 2493 if ((pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_PERROR) && 2494 !(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_S_SYSERR)) { 2495 /* 2496 * If we have an address then fault 2497 * it, if not probe for errant device 2498 */ 2499 ret = DDI_FM_FATAL; 2500 if (caller != PCI_TRAP_CALL) { 2501 if (pbm_err.pbm_va_log) { 2502 ret = ndi_fmc_error(dip, NULL, DMA_HANDLE, 2503 derr->fme_ena, (void *)&pbm_err.pbm_va_log); 2504 } 2505 if (ret == DDI_FM_NONFATAL) 2506 nonfatal++; 2507 else 2508 fatal++; 2509 } else 2510 nonfatal++; 2511 2512 } 2513 2514 /* PBM Detected IOMMU Error */ 2515 if (pbm_err.pbm_ctl_stat & SCHIZO_PCI_CTRL_PCI_MMU_ERR) { 2516 if (iommu_err_handler(dip, derr->fme_ena, &pbm_err) 2517 == DDI_FM_FATAL) 2518 fatal++; 2519 else 2520 nonfatal++; 2521 } 2522 2523 done: 2524 ret = ndi_fm_handler_dispatch(dip, NULL, derr); 2525 if (ret == DDI_FM_FATAL) { 2526 fatal++; 2527 } else if (ret == DDI_FM_NONFATAL) { 2528 nonfatal++; 2529 } else if (ret == DDI_FM_UNKNOWN) { 2530 unknown++; 2531 } 2532 2533 /* 2534 * RSERR not claimed as nonfatal by a child is considered fatal 2535 */ 2536 if (unknown && !fatal && !nonfatal) 2537 fatal++; 2538 2539 /* Cleanup and reset error bits */ 2540 pci_clear_error(pci_p, &pbm_err); 2541 2542 return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 2543 (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); 2544 } 2545 2546 /* 2547 * Function returns TRUE if a Primary error is Split Completion Error 2548 * that indicates a Master Abort occured behind a PCI-X bridge. 2549 * This function should only be called for busses running in PCI-X mode. 2550 */ 2551 static int 2552 pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p) 2553 { 2554 uint64_t msg; 2555 2556 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) 2557 return (0); 2558 2559 if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) { 2560 msg = (pbm_err_p->pbm_afsr >> XMITS_PCI_X_P_MSG_SHIFT) & 2561 XMITS_PCIX_MSG_MASK; 2562 if (msg & PCIX_CLASS_BRIDGE) 2563 if (msg & PCIX_BRIDGE_MASTER_ABORT) { 2564 return (1); 2565 } 2566 } 2567 2568 return (0); 2569 } 2570 2571 /* 2572 * Function used to gather PBM/PCI/IOMMU error state for the 2573 * pci_pbm_err_handler and the cb_buserr_intr. This function must be 2574 * called while pci_fm_mutex is held. 2575 */ 2576 static void 2577 pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 2578 { 2579 pbm_t *pbm_p = pci_p->pci_pbm_p; 2580 iommu_t *iommu_p = pci_p->pci_iommu_p; 2581 caddr_t a = pci_p->pci_address[0]; 2582 uint64_t *pbm_pcix_stat_reg; 2583 2584 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2585 bzero(pbm_err_p, sizeof (pbm_errstate_t)); 2586 2587 /* 2588 * Capture all pbm error state for later logging 2589 */ 2590 pbm_err_p->pbm_bridge_type = PCI_BRIDGE_TYPE(pci_p->pci_common_p); 2591 2592 pbm_err_p->pbm_pci.pci_cfg_stat = 2593 pbm_p->pbm_config_header->ch_status_reg; 2594 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2595 pbm_err_p->pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2596 pbm_err_p->pbm_afar = *pbm_p->pbm_async_flt_addr_reg; 2597 pbm_err_p->pbm_iommu.iommu_stat = *iommu_p->iommu_ctrl_reg; 2598 pbm_err_p->pbm_pci.pci_cfg_comm = 2599 pbm_p->pbm_config_header->ch_command_reg; 2600 pbm_err_p->pbm_pci.pci_pa = *pbm_p->pbm_async_flt_addr_reg; 2601 2602 /* 2603 * Record errant slot for Xmits and Schizo 2604 * Not stored in Tomatillo 2605 */ 2606 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS || 2607 CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO) { 2608 pbm_err_p->pbm_err_sl = (pbm_err_p->pbm_ctl_stat & 2609 SCHIZO_PCI_CTRL_ERR_SLOT) >> 2610 SCHIZO_PCI_CTRL_ERR_SLOT_SHIFT; 2611 2612 /* 2613 * The bit 51 on XMITS rev1.0 is same as 2614 * SCHIZO_PCI_CTRL_ERR_SLOT_LOCK on schizo2.3. But 2615 * this bit needs to be cleared to be able to latch 2616 * the slot info on next fault. 2617 * But in XMITS Rev2.0, this bit indicates a DMA Write 2618 * Parity error. 2619 */ 2620 if (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_DMA_WR_PERR) { 2621 if ((PCI_CHIP_ID(pci_p) == XMITS_VER_10) || 2622 (PCI_CHIP_ID(pci_p) <= SCHIZO_VER_23)) { 2623 /* 2624 * top 32 bits are W1C and we just want to 2625 * clear SLOT_LOCK. Leave bottom 32 bits 2626 * unchanged 2627 */ 2628 *pbm_p->pbm_ctrl_reg = 2629 pbm_err_p->pbm_ctl_stat & 2630 (SCHIZO_PCI_CTRL_ERR_SLOT_LOCK | 2631 0xffffffff); 2632 pbm_err_p->pbm_ctl_stat = 2633 *pbm_p->pbm_ctrl_reg; 2634 } 2635 } 2636 } 2637 2638 /* 2639 * Tomatillo specific registers 2640 */ 2641 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 2642 pbm_err_p->pbm_va_log = (uint64_t)va_to_pa( 2643 (void *)(uintptr_t)*(a + TOMATILLO_TGT_ERR_VALOG_OFFSET)); 2644 pbm_err_p->pbm_iommu.iommu_tfar = *iommu_p->iommu_tfar_reg; 2645 } 2646 2647 /* 2648 * Xmits PCI-X register 2649 */ 2650 if ((CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) && 2651 (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) { 2652 2653 pbm_pcix_stat_reg = (uint64_t *)(a + 2654 XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 2655 2656 pbm_err_p->pbm_pcix_stat = *pbm_pcix_stat_reg; 2657 pbm_err_p->pbm_pcix_pfar = pbm_err_p->pbm_pcix_stat & 2658 XMITS_PCI_X_STATUS_PFAR_MASK; 2659 } 2660 } 2661 2662 /* 2663 * Function used to clear PBM/PCI/IOMMU error state after error handling 2664 * is complete. Only clearing error bits which have been logged. Called by 2665 * pci_pbm_err_handler and pci_bus_exit. 2666 */ 2667 static void 2668 pci_clear_error(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 2669 { 2670 pbm_t *pbm_p = pci_p->pci_pbm_p; 2671 iommu_t *iommu_p = pci_p->pci_iommu_p; 2672 2673 ASSERT(MUTEX_HELD(&pbm_p->pbm_pci_p->pci_common_p->pci_fm_mutex)); 2674 2675 if (*pbm_p->pbm_ctrl_reg & SCHIZO_PCI_CTRL_PCI_MMU_ERR) { 2676 iommu_tlb_scrub(pci_p->pci_iommu_p, 1); 2677 } 2678 pbm_p->pbm_config_header->ch_status_reg = 2679 pbm_err_p->pbm_pci.pci_cfg_stat; 2680 *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat; 2681 *pbm_p->pbm_async_flt_status_reg = pbm_err_p->pbm_afsr; 2682 *iommu_p->iommu_ctrl_reg = pbm_err_p->pbm_iommu.iommu_stat; 2683 } 2684 2685 void 2686 pbm_clear_error(pbm_t *pbm_p) 2687 { 2688 uint64_t pbm_afsr, pbm_ctl_stat; 2689 2690 /* 2691 * for poke() support - called from POKE_FLUSH. Spin waiting 2692 * for MA, TA or SERR to be cleared by a pbm_error_intr(). 2693 * We have to wait for SERR too in case the device is beyond 2694 * a pci-pci bridge. 2695 */ 2696 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2697 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2698 while (((pbm_afsr >> SCHIZO_PCI_AFSR_PE_SHIFT) & 2699 (SCHIZO_PCI_AFSR_E_MA | SCHIZO_PCI_AFSR_E_TA)) || 2700 (pbm_ctl_stat & COMMON_PCI_CTRL_SERR)) { 2701 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2702 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2703 } 2704 } 2705 2706 /* 2707 * Function used to convert the 32 bit captured PCI error address 2708 * to the full Safari or Jbus address. This is so we can look this address 2709 * up in our handle caches. 2710 */ 2711 void 2712 pci_format_addr(dev_info_t *dip, uint64_t *afar, uint64_t afsr) 2713 { 2714 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2715 pci_ranges_t *io_range, *mem_range; 2716 uint64_t err_pa = 0; 2717 2718 if (afsr & SCHIZO_PCI_AFSR_CONF_SPACE) { 2719 err_pa |= pci_p->pci_ranges->parent_high; 2720 err_pa = err_pa << 32; 2721 err_pa |= pci_p->pci_ranges->parent_low; 2722 } else if (afsr & SCHIZO_PCI_AFSR_IO_SPACE) { 2723 io_range = pci_p->pci_ranges + 1; 2724 err_pa |= io_range->parent_high; 2725 err_pa = err_pa << 32; 2726 err_pa |= io_range->parent_low; 2727 } else if (afsr & SCHIZO_PCI_AFSR_MEM_SPACE) { 2728 mem_range = pci_p->pci_ranges + 2; 2729 err_pa |= mem_range->parent_high; 2730 err_pa = err_pa << 32; 2731 err_pa |= mem_range->parent_low; 2732 } 2733 *afar |= err_pa; 2734 } 2735 2736 static ecc_format_t ecc_format_tbl[] = { 2737 SCH_REG_UPA, NULL, NULL, 2738 SCH_REG_PCIA_REG, SCHIZO_PCI_AFSR_CONF_SPACE, PCI_SIDEA, 2739 SCH_REG_PCIA_MEM, SCHIZO_PCI_AFSR_MEM_SPACE, PCI_SIDEA, 2740 SCH_REG_PCIA_CFGIO, SCHIZO_PCI_AFSR_IO_SPACE, PCI_SIDEA, 2741 SCH_REG_PCIB_REG, SCHIZO_PCI_AFSR_CONF_SPACE, PCI_SIDEB, 2742 SCH_REG_PCIB_MEM, SCHIZO_PCI_AFSR_MEM_SPACE, PCI_SIDEB, 2743 SCH_REG_PCIB_CFGIO, SCHIZO_PCI_AFSR_IO_SPACE, PCI_SIDEB, 2744 SCH_REG_SAFARI_REGS, NULL, NULL, 2745 NULL, NULL, NULL, 2746 }; 2747 2748 /* 2749 * Function used to convert the 32 bit PIO address captured for a 2750 * Safari Bus UE(during PIO Rd/Wr) to a full Safari Bus Address. 2751 */ 2752 static void 2753 pci_format_ecc_addr(dev_info_t *dip, uint64_t *afar, ecc_region_t region) 2754 { 2755 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2756 pci_common_t *cmn_p = pci_p->pci_common_p; 2757 cb_t *cb_p = pci_p->pci_cb_p; 2758 int i, pci_side = 0; 2759 int swap = 0; 2760 uint64_t pa = cb_p->cb_base_pa; 2761 uint64_t flag, schizo_base, pci_csr_base; 2762 2763 if (pci_p == NULL) 2764 return; 2765 2766 pci_csr_base = va_to_pa(pci_p->pci_address[0]); 2767 2768 /* 2769 * Using the csr_base address to determine which side 2770 * we are on. 2771 */ 2772 if (pci_csr_base & PCI_SIDE_ADDR_MASK) 2773 pci_side = 1; 2774 else 2775 pci_side = 0; 2776 2777 schizo_base = pa - PBM_CTRL_OFFSET; 2778 2779 for (i = 0; ecc_format_tbl[i].ecc_region != NULL; i++) { 2780 if (region == ecc_format_tbl[i].ecc_region) { 2781 flag = ecc_format_tbl[i].ecc_space; 2782 if (ecc_format_tbl[i].ecc_side != pci_side) 2783 swap = 1; 2784 if (region == SCH_REG_SAFARI_REGS) 2785 *afar |= schizo_base; 2786 break; 2787 } 2788 } 2789 2790 if (swap) { 2791 pci_p = cmn_p->pci_p[PCI_OTHER_SIDE(pci_p->pci_side)]; 2792 2793 if (pci_p == NULL) 2794 return; 2795 } 2796 pci_format_addr(pci_p->pci_dip, afar, flag); 2797 } 2798 2799 /* 2800 * Function used to post control block specific ereports. 2801 */ 2802 static void 2803 cb_ereport_post(dev_info_t *dip, uint64_t ena, cb_errstate_t *cb_err) 2804 { 2805 pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2806 char buf[FM_MAX_CLASS], dev_path[MAXPATHLEN], *ptr; 2807 struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; 2808 nvlist_t *ereport, *detector; 2809 errorq_elem_t *eqep; 2810 nv_alloc_t *nva; 2811 2812 DEBUG1(DBG_ATTACH, dip, "cb_ereport_post: elog 0x%lx", 2813 cb_err->cb_elog); 2814 2815 /* 2816 * We do not use ddi_fm_ereport_post because we need to set a 2817 * special detector here. Since we do not have a device path for 2818 * the bridge chip we use what we think it should be to aid in 2819 * diagnosis. 2820 */ 2821 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", DDI_IO_CLASS, 2822 cb_err->cb_bridge_type, cb_err->cb_err_class); 2823 2824 ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2825 2826 eqep = errorq_reserve(fmhdl->fh_errorq); 2827 if (eqep == NULL) 2828 return; 2829 2830 ereport = errorq_elem_nvl(fmhdl->fh_errorq, eqep); 2831 nva = errorq_elem_nva(fmhdl->fh_errorq, eqep); 2832 detector = fm_nvlist_create(nva); 2833 2834 ASSERT(ereport); 2835 ASSERT(nva); 2836 ASSERT(detector); 2837 2838 ddi_pathname(dip, dev_path); 2839 ptr = strrchr(dev_path, (int)','); 2840 2841 if (ptr) 2842 *ptr = '\0'; 2843 2844 fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL, dev_path, NULL); 2845 2846 DEBUG1(DBG_ERR_INTR, dip, "cb_ereport_post: ereport_set: %s", buf); 2847 2848 if (CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO || 2849 CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 2850 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, ena, detector, 2851 SAFARI_CSR, DATA_TYPE_UINT64, cb_err->cb_csr, 2852 SAFARI_ERR, DATA_TYPE_UINT64, cb_err->cb_err, 2853 SAFARI_INTR, DATA_TYPE_UINT64, cb_err->cb_intr, 2854 SAFARI_ELOG, DATA_TYPE_UINT64, cb_err->cb_elog, 2855 SAFARI_PCR, DATA_TYPE_UINT64, cb_err->cb_pcr, 2856 NULL); 2857 } else if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 2858 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, ena, detector, 2859 JBUS_CSR, DATA_TYPE_UINT64, cb_err->cb_csr, 2860 JBUS_ERR, DATA_TYPE_UINT64, cb_err->cb_err, 2861 JBUS_INTR, DATA_TYPE_UINT64, cb_err->cb_intr, 2862 JBUS_ELOG, DATA_TYPE_UINT64, cb_err->cb_elog, 2863 JBUS_PCR, DATA_TYPE_UINT64, cb_err->cb_pcr, 2864 NULL); 2865 } 2866 errorq_commit(fmhdl->fh_errorq, eqep, ERRORQ_ASYNC); 2867 } 2868 2869 /* 2870 * Function used to post IOMMU specific ereports. 2871 */ 2872 static void 2873 iommu_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err) 2874 { 2875 char buf[FM_MAX_CLASS]; 2876 2877 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2878 pbm_err->pbm_bridge_type, pbm_err->pbm_err_class); 2879 2880 ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2881 2882 DEBUG1(DBG_ERR_INTR, dip, "iommu_ereport_post: ereport_set: %s", buf); 2883 2884 ddi_fm_ereport_post(dip, buf, ena, DDI_NOSLEEP, 2885 FM_VERSION, DATA_TYPE_UINT8, 0, 2886 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat, 2887 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm, 2888 PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat, 2889 PCI_PBM_IOMMU_CTRL, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_stat, 2890 PCI_PBM_IOMMU_TFAR, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_tfar, 2891 PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl, 2892 PCI_PBM_VALOG, DATA_TYPE_UINT64, pbm_err->pbm_va_log, 2893 NULL); 2894 } 2895 2896 /* 2897 * Function used to post PCI-X generic ereports. 2898 * This function needs to be fixed once the Fault Boundary Analysis 2899 * for PCI-X is conducted. The payload should be made more generic. 2900 */ 2901 static void 2902 pcix_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err) 2903 { 2904 char buf[FM_MAX_CLASS]; 2905 2906 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2907 pbm_err->pbm_bridge_type, pbm_err->pbm_err_class); 2908 2909 ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2910 2911 DEBUG1(DBG_ERR_INTR, dip, "pcix_ereport_post: ereport_post: %s", buf); 2912 2913 ddi_fm_ereport_post(dip, buf, ena, DDI_NOSLEEP, 2914 FM_VERSION, DATA_TYPE_UINT8, 0, 2915 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat, 2916 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm, 2917 PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat, 2918 PCI_PBM_AFSR, DATA_TYPE_UINT64, pbm_err->pbm_afsr, 2919 PCI_PBM_AFAR, DATA_TYPE_UINT64, pbm_err->pbm_afar, 2920 PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl, 2921 PCIX_STAT, DATA_TYPE_UINT64, pbm_err->pbm_pcix_stat, 2922 PCIX_PFAR, DATA_TYPE_UINT32, pbm_err->pbm_pcix_pfar, 2923 NULL); 2924 } 2925 2926 static void 2927 iommu_ctx_free(iommu_t *iommu_p) 2928 { 2929 kmem_free(iommu_p->iommu_ctx_bitmap, IOMMU_CTX_BITMAP_SIZE); 2930 } 2931 2932 /* 2933 * iommu_tlb_scrub(): 2934 * Exam TLB entries through TLB diagnostic registers and look for errors. 2935 * scrub = 1 : cleanup all error bits in tlb, called in FAULT_RESET case 2936 * scrub = 0 : log all error conditions to console, FAULT_LOG case 2937 * In both cases, it returns number of errors found in tlb entries. 2938 */ 2939 static int 2940 iommu_tlb_scrub(iommu_t *iommu_p, int scrub) 2941 { 2942 int i, nerr = 0; 2943 dev_info_t *dip = iommu_p->iommu_pci_p->pci_dip; 2944 char *neg = "not "; 2945 2946 uint64_t base = (uint64_t)iommu_p->iommu_ctrl_reg - 2947 COMMON_IOMMU_CTRL_REG_OFFSET; 2948 2949 volatile uint64_t *tlb_tag = (volatile uint64_t *) 2950 (base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); 2951 volatile uint64_t *tlb_data = (volatile uint64_t *) 2952 (base + COMMON_IOMMU_TLB_DATA_DIAG_ACC_OFFSET); 2953 for (i = 0; i < IOMMU_TLB_ENTRIES; i++) { 2954 uint64_t tag = tlb_tag[i]; 2955 uint64_t data = tlb_data[i]; 2956 uint32_t errstat; 2957 iopfn_t pfn; 2958 2959 if (!(tag & TLBTAG_ERR_BIT)) 2960 continue; 2961 2962 pfn = (iopfn_t)(data & TLBDATA_MEMPA_BITS); 2963 errstat = (uint32_t) 2964 ((tag & TLBTAG_ERRSTAT_BITS) >> TLBTAG_ERRSTAT_SHIFT); 2965 if (errstat == TLBTAG_ERRSTAT_INVALID) { 2966 if (scrub) 2967 tlb_tag[i] = tlb_data[i] = 0ull; 2968 } else 2969 nerr++; 2970 2971 if (scrub) 2972 continue; 2973 2974 cmn_err(CE_CONT, "%s%d: Error %x on IOMMU TLB entry %x:\n" 2975 "\tContext=%lx %sWritable %sStreamable\n" 2976 "\tPCI Page Size=%sk Address in page %lx\n", 2977 ddi_driver_name(dip), ddi_get_instance(dip), errstat, i, 2978 (tag & TLBTAG_CONTEXT_BITS) >> TLBTAG_CONTEXT_SHIFT, 2979 (tag & TLBTAG_WRITABLE_BIT) ? "" : neg, 2980 (tag & TLBTAG_STREAM_BIT) ? "" : neg, 2981 (tag & TLBTAG_PGSIZE_BIT) ? "64" : "8", 2982 (tag & TLBTAG_PCIVPN_BITS) << 13); 2983 cmn_err(CE_CONT, "Memory: %sValid %sCacheable Page Frame=%lx\n", 2984 (data & TLBDATA_VALID_BIT) ? "" : neg, 2985 (data & TLBDATA_CACHE_BIT) ? "" : neg, pfn); 2986 } 2987 return (nerr); 2988 } 2989 2990 /* 2991 * pci_iommu_disp: calculates the displacement needed in tomatillo's 2992 * iommu control register and modifies the control value template 2993 * from caller. It also clears any error status bit that are new 2994 * in tomatillo. 2995 * return value: an 8-bit mask to enable corresponding 512 MB segments 2996 * suitable for tomatillo's target address register. 2997 * 0x00: no programming is needed, use existing value from prom 2998 * 0x60: use segment 5 and 6 to form a 1GB dvma range 2999 */ 3000 static uint64_t 3001 pci_iommu_disp(iommu_t *iommu_p, uint64_t *ctl_p) 3002 { 3003 uint64_t ctl_old; 3004 if (CHIP_TYPE(iommu_p->iommu_pci_p) != PCI_CHIP_TOMATILLO) 3005 return (0); 3006 3007 ctl_old = *iommu_p->iommu_ctrl_reg; 3008 /* iommu ctrl reg error bits are W1C */ 3009 if (ctl_old >> TOMATIILO_IOMMU_ERR_REG_SHIFT) { 3010 cmn_err(CE_WARN, "Tomatillo iommu err: %lx", ctl_old); 3011 *ctl_p |= (ctl_old >> TOMATIILO_IOMMU_ERR_REG_SHIFT) 3012 << TOMATIILO_IOMMU_ERR_REG_SHIFT; 3013 } 3014 3015 if (iommu_p->iommu_tsb_size != TOMATILLO_IOMMU_TSB_MAX) 3016 return (0); 3017 3018 /* Tomatillo 2.0 and later, and 1GB DVMA range */ 3019 *ctl_p |= 1 << TOMATILLO_IOMMU_SEG_DISP_SHIFT; 3020 return (3 << (iommu_p->iommu_dvma_base >> (32 - 3))); 3021 } 3022 3023 void 3024 pci_iommu_config(iommu_t *iommu_p, uint64_t iommu_ctl, uint64_t cfgpa) 3025 { 3026 uintptr_t pbm_regbase = get_pbm_reg_base(iommu_p->iommu_pci_p); 3027 volatile uint64_t *pbm_csr_p = (volatile uint64_t *)pbm_regbase; 3028 volatile uint64_t *tgt_space_p = (volatile uint64_t *)(pbm_regbase | 3029 (TOMATILLO_TGT_ADDR_SPACE_OFFSET - SCHIZO_PCI_CTRL_REG_OFFSET)); 3030 volatile uint64_t pbm_ctl = *pbm_csr_p; 3031 3032 volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg; 3033 volatile uint64_t tsb_bar_val = iommu_p->iommu_tsb_paddr; 3034 volatile uint64_t *tsb_bar_p = iommu_p->iommu_tsb_base_addr_reg; 3035 uint64_t mask = pci_iommu_disp(iommu_p, &iommu_ctl); 3036 3037 DEBUG2(DBG_ATTACH, iommu_p->iommu_pci_p->pci_dip, 3038 "\npci_iommu_config: pbm_csr_p=%llx pbm_ctl=%llx", 3039 pbm_csr_p, pbm_ctl); 3040 DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 3041 "\n\tiommu_ctl_p=%llx iommu_ctl=%llx", 3042 iommu_ctl_p, iommu_ctl); 3043 DEBUG4(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 3044 "\n\tcfgpa=%llx tgt_space_p=%llx mask=%x tsb=%llx\n", 3045 cfgpa, tgt_space_p, mask, tsb_bar_val); 3046 3047 if (!cfgpa) 3048 goto reprog; 3049 3050 /* disable PBM arbiters - turn off bits 0-7 */ 3051 *pbm_csr_p = (pbm_ctl >> 8) << 8; 3052 3053 /* 3054 * For non-XMITS, flush any previous writes. This is only 3055 * necessary for host bridges that may have a USB keywboard 3056 * attached. XMITS does not. 3057 */ 3058 if (!(CHIP_TYPE(iommu_p->iommu_pci_p) == PCI_CHIP_XMITS)) 3059 (void) ldphysio(cfgpa); 3060 3061 reprog: 3062 if (mask) 3063 *tgt_space_p = mask; 3064 3065 *tsb_bar_p = tsb_bar_val; 3066 *iommu_ctl_p = iommu_ctl; 3067 3068 *pbm_csr_p = pbm_ctl; /* re-enable bus arbitration */ 3069 pbm_ctl = *pbm_csr_p; /* flush all prev writes */ 3070 } 3071 3072 3073 int 3074 pci_get_portid(dev_info_t *dip) 3075 { 3076 return (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 3077 "portid", -1)); 3078 } 3079 3080 /* 3081 * Schizo Safari Performance Events. 3082 */ 3083 pci_kev_mask_t 3084 schizo_saf_events[] = { 3085 {"saf_bus_cycles", 0x1}, {"saf_pause_asserted_cycles", 0x2}, 3086 {"saf_frn_coherent_cmds", 0x3}, {"saf_frn_coherent_hits", 0x4}, 3087 {"saf_my_coherent_cmds", 0x5}, {"saf_my_coherent_hits", 0x6}, 3088 {"saf_frn_io_cmds", 0x7}, {"saf_frn_io_hits", 0x8}, 3089 {"merge_buffer", 0x9}, {"interrupts", 0xa}, 3090 {"csr_pios", 0xc}, {"upa_pios", 0xd}, 3091 {"pcia_pios", 0xe}, {"pcib_pios", 0xf}, 3092 {"saf_pause_seen_cycles", 0x11}, {"dvma_reads", 0x12}, 3093 {"dvma_writes", 0x13}, {"saf_orq_full_cycles", 0x14}, 3094 {"saf_data_in_cycles", 0x15}, {"saf_data_out_cycles", 0x16}, 3095 {"clear_pic", 0x1f} 3096 }; 3097 3098 3099 /* 3100 * Schizo PCI Performance Events. 3101 */ 3102 pci_kev_mask_t 3103 schizo_pci_events[] = { 3104 {"dvma_stream_rd", 0x0}, {"dvma_stream_wr", 0x1}, 3105 {"dvma_const_rd", 0x2}, {"dvma_const_wr", 0x3}, 3106 {"dvma_stream_buf_mis", 0x4}, {"dvma_cycles", 0x5}, 3107 {"dvma_wd_xfr", 0x6}, {"pio_cycles", 0x7}, 3108 {"dvma_tlb_misses", 0x10}, {"interrupts", 0x11}, 3109 {"saf_inter_nack", 0x12}, {"pio_reads", 0x13}, 3110 {"pio_writes", 0x14}, {"dvma_rd_buf_timeout", 0x15}, 3111 {"dvma_rd_rtry_stc", 0x16}, {"dvma_wr_rtry_stc", 0x17}, 3112 {"dvma_rd_rtry_nonstc", 0x18}, {"dvma_wr_rtry_nonstc", 0x19}, 3113 {"E*_slow_transitions", 0x1a}, {"E*_slow_cycles_per_64", 0x1b}, 3114 {"clear_pic", 0x1f} 3115 }; 3116 3117 3118 /* 3119 * Create the picN kstats for the pci 3120 * and safari events. 3121 */ 3122 void 3123 pci_kstat_init() 3124 { 3125 pci_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 3126 KM_NOSLEEP); 3127 3128 if (pci_name_kstat == NULL) { 3129 cmn_err(CE_WARN, "pcisch : no space for kstat\n"); 3130 } else { 3131 pci_name_kstat->pic_no_evs = 3132 sizeof (schizo_pci_events) / sizeof (pci_kev_mask_t); 3133 pci_name_kstat->pic_shift[0] = SCHIZO_SHIFT_PIC0; 3134 pci_name_kstat->pic_shift[1] = SCHIZO_SHIFT_PIC1; 3135 pci_create_name_kstat("pcis", 3136 pci_name_kstat, schizo_pci_events); 3137 } 3138 3139 saf_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 3140 KM_NOSLEEP); 3141 if (saf_name_kstat == NULL) { 3142 cmn_err(CE_WARN, "pcisch : no space for kstat\n"); 3143 } else { 3144 saf_name_kstat->pic_no_evs = 3145 sizeof (schizo_saf_events) / sizeof (pci_kev_mask_t); 3146 saf_name_kstat->pic_shift[0] = SCHIZO_SHIFT_PIC0; 3147 saf_name_kstat->pic_shift[1] = SCHIZO_SHIFT_PIC1; 3148 pci_create_name_kstat("saf", saf_name_kstat, schizo_saf_events); 3149 } 3150 } 3151 3152 void 3153 pci_kstat_fini() 3154 { 3155 if (pci_name_kstat != NULL) { 3156 pci_delete_name_kstat(pci_name_kstat); 3157 kmem_free(pci_name_kstat, sizeof (pci_ksinfo_t)); 3158 pci_name_kstat = NULL; 3159 } 3160 3161 if (saf_name_kstat != NULL) { 3162 pci_delete_name_kstat(saf_name_kstat); 3163 kmem_free(saf_name_kstat, sizeof (pci_ksinfo_t)); 3164 saf_name_kstat = NULL; 3165 } 3166 } 3167 3168 /* 3169 * Create 'counters' kstat for pci events. 3170 */ 3171 void 3172 pci_add_pci_kstat(pci_t *pci_p) 3173 { 3174 pci_cntr_addr_t *cntr_addr_p = &pci_p->pci_ks_addr; 3175 uintptr_t regbase = (uintptr_t)pci_p->pci_address[0]; 3176 3177 cntr_addr_p->pcr_addr = (uint64_t *) 3178 (regbase + SCHIZO_PERF_PCI_PCR_OFFSET); 3179 cntr_addr_p->pic_addr = (uint64_t *) 3180 (regbase + SCHIZO_PERF_PCI_PIC_OFFSET); 3181 3182 pci_p->pci_ksp = pci_create_cntr_kstat(pci_p, "pcis", 3183 NUM_OF_PICS, pci_cntr_kstat_update, cntr_addr_p); 3184 3185 if (pci_p->pci_ksp == NULL) { 3186 cmn_err(CE_WARN, "pcisch : cannot create counter kstat"); 3187 } 3188 } 3189 3190 void 3191 pci_rem_pci_kstat(pci_t *pci_p) 3192 { 3193 if (pci_p->pci_ksp != NULL) 3194 kstat_delete(pci_p->pci_ksp); 3195 pci_p->pci_ksp = NULL; 3196 } 3197 3198 void 3199 pci_add_upstream_kstat(pci_t *pci_p) 3200 { 3201 pci_common_t *cmn_p = pci_p->pci_common_p; 3202 pci_cntr_pa_t *cntr_pa_p = &cmn_p->pci_cmn_uks_pa; 3203 uint64_t regbase = va_to_pa(pci_p->pci_address[1]); 3204 3205 cntr_pa_p->pcr_pa = 3206 regbase + SCHIZO_PERF_SAF_PCR_OFFSET; 3207 cntr_pa_p->pic_pa = 3208 regbase + SCHIZO_PERF_SAF_PIC_OFFSET; 3209 3210 cmn_p->pci_common_uksp = pci_create_cntr_kstat(pci_p, "saf", 3211 NUM_OF_PICS, pci_cntr_kstat_pa_update, cntr_pa_p); 3212 } 3213 3214 /* 3215 * Extract the drivers binding name to identify which chip 3216 * we're binding to. Whenever a new bus bridge is created, the driver alias 3217 * entry should be added here to identify the device if needed. If a device 3218 * isn't added, the identity defaults to PCI_CHIP_UNIDENTIFIED. 3219 */ 3220 static uint32_t 3221 pci_identity_init(pci_t *pci_p) 3222 { 3223 dev_info_t *dip = pci_p->pci_dip; 3224 char *name = ddi_binding_name(dip); 3225 uint32_t ver = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 3226 "version#", 0); 3227 3228 if (strcmp(name, "pci108e,a801") == 0) 3229 return (CHIP_ID(PCI_CHIP_TOMATILLO, ver, 0x00)); 3230 3231 if (strcmp(name, "pci108e,8001") == 0) 3232 return (CHIP_ID(PCI_CHIP_SCHIZO, ver, 0x00)); 3233 3234 if (strcmp(name, "pci108e,8002") == 0) { 3235 uint32_t mod_rev = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 3236 DDI_PROP_DONTPASS, "module-revision#", 0); 3237 return (CHIP_ID(PCI_CHIP_XMITS, ver, mod_rev)); 3238 } 3239 3240 cmn_err(CE_WARN, "%s%d: Unknown PCI Host bridge %s %x\n", 3241 ddi_driver_name(dip), ddi_get_instance(dip), name, ver); 3242 3243 return (PCI_CHIP_UNIDENTIFIED); 3244 } 3245 3246 /* 3247 * Setup a physical pointer to one leaf config space area. This 3248 * is used in several places in order to do a dummy read which 3249 * guarantees the nexus (and not a bus master) has gained control 3250 * of the bus. 3251 */ 3252 static void 3253 pci_setup_cfgpa(pci_t *pci_p) 3254 { 3255 dev_info_t *dip = pci_p->pci_dip; 3256 dev_info_t *cdip; 3257 pbm_t *pbm_p = pci_p->pci_pbm_p; 3258 uint64_t cfgpa = pci_get_cfg_pabase(pci_p); 3259 uint32_t *reg_p; 3260 int reg_len; 3261 3262 for (cdip = ddi_get_child(dip); cdip != NULL; 3263 cdip = ddi_get_next_sibling(cdip)) { 3264 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 3265 "reg", (caddr_t)®_p, ®_len) != DDI_PROP_SUCCESS) 3266 continue; 3267 cfgpa += (*reg_p) & (PCI_CONF_ADDR_MASK ^ PCI_REG_REG_M); 3268 kmem_free(reg_p, reg_len); 3269 break; 3270 } 3271 pbm_p->pbm_anychild_cfgpa = cfgpa; 3272 } 3273 3274 void 3275 pci_post_init_child(pci_t *pci_p, dev_info_t *child) 3276 { 3277 volatile uint64_t *ctrl_reg_p; 3278 pbm_t *pbm_p = pci_p->pci_pbm_p; 3279 3280 pci_setup_cfgpa(pci_p); 3281 3282 /* 3283 * This is a hack for skyhawk/casinni combination to address 3284 * hardware problems between the request and grant signals which 3285 * causes a bus hang. One workaround, which is applied here, 3286 * is to disable bus parking if the child contains the property 3287 * pci-req-removal. Note that if the bus is quiesced we must mask 3288 * off the parking bit in the saved control registers, since the 3289 * quiesce operation temporarily turns off PCI bus parking. 3290 */ 3291 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 3292 "pci-req-removal") == 1) { 3293 3294 if (pbm_p->pbm_quiesce_count > 0) { 3295 pbm_p->pbm_saved_ctrl_reg &= ~SCHIZO_PCI_CTRL_ARB_PARK; 3296 } else { 3297 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3298 *ctrl_reg_p &= ~SCHIZO_PCI_CTRL_ARB_PARK; 3299 } 3300 } 3301 3302 if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 3303 if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) { 3304 int value; 3305 3306 /* 3307 * Due to a XMITS bug, we need to set the outstanding 3308 * split transactions to 1 for all PCI-X functions 3309 * behind the leaf. 3310 */ 3311 value = (xmits_max_transactions << 4) | 3312 (xmits_max_read_bytes << 2); 3313 3314 DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ " 3315 "Workaround: value = %x\n", value); 3316 3317 pcix_set_cmd_reg(child, value); 3318 3319 (void) ndi_prop_update_int(DDI_DEV_T_NONE, 3320 child, "pcix-update-cmd-reg", value); 3321 } 3322 } 3323 } 3324 3325 void 3326 pci_post_uninit_child(pci_t *pci_p) 3327 { 3328 pci_setup_cfgpa(pci_p); 3329 } 3330 3331 static int 3332 pci_tom_nbintr_op(pci_t *pci_p, uint32_t inum, intrfunc f, caddr_t arg, 3333 int flag) 3334 { 3335 uint32_t ino = pci_p->pci_inos[inum]; 3336 uint32_t mondo = IB_INO_TO_NBMONDO(pci_p->pci_ib_p, ino); 3337 int ret = DDI_SUCCESS; 3338 3339 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); /* no op on tom */ 3340 3341 switch (flag) { 3342 case PCI_OBJ_INTR_ADD: 3343 VERIFY(add_ivintr(mondo, pci_pil[inum], f, arg, NULL) == 0); 3344 break; 3345 case PCI_OBJ_INTR_REMOVE: 3346 rem_ivintr(mondo, NULL); 3347 break; 3348 default: 3349 ret = DDI_FAILURE; 3350 break; 3351 } 3352 3353 return (ret); 3354 } 3355 3356 int 3357 pci_ecc_add_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 3358 { 3359 uint32_t mondo; 3360 int r; 3361 3362 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 3363 pci_p->pci_inos[inum]); 3364 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3365 3366 VERIFY(add_ivintr(mondo, pci_pil[inum], ecc_intr, 3367 (caddr_t)eii_p, NULL) == 0); 3368 3369 if (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO) 3370 return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, 3371 DDI_SUCCESS)); 3372 3373 r = pci_tom_nbintr_op(pci_p, inum, ecc_intr, 3374 (caddr_t)eii_p, PCI_OBJ_INTR_ADD); 3375 return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, r)); 3376 } 3377 3378 void 3379 pci_ecc_rem_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 3380 { 3381 uint32_t mondo; 3382 3383 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 3384 pci_p->pci_inos[inum]); 3385 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3386 3387 rem_ivintr(mondo, NULL); 3388 3389 if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) 3390 pci_tom_nbintr_op(pci_p, inum, ecc_intr, 3391 (caddr_t)eii_p, PCI_OBJ_INTR_REMOVE); 3392 } 3393 3394 static uint_t 3395 pci_pbm_cdma_intr(caddr_t a) 3396 { 3397 pbm_t *pbm_p = (pbm_t *)a; 3398 pbm_p->pbm_cdma_flag = PBM_CDMA_DONE; 3399 #ifdef PBM_CDMA_DEBUG 3400 pbm_p->pbm_cdma_intr_cnt++; 3401 #endif /* PBM_CDMA_DEBUG */ 3402 return (DDI_INTR_CLAIMED); 3403 } 3404 3405 int 3406 pci_pbm_add_intr(pci_t *pci_p) 3407 { 3408 uint32_t mondo; 3409 3410 mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_CDMA]); 3411 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3412 3413 VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_CDMA], 3414 pci_pbm_cdma_intr, (caddr_t)pci_p->pci_pbm_p, NULL) == 0); 3415 3416 return (DDI_SUCCESS); 3417 } 3418 3419 void 3420 pci_pbm_rem_intr(pci_t *pci_p) 3421 { 3422 ib_t *ib_p = pci_p->pci_ib_p; 3423 uint32_t mondo; 3424 3425 mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_CDMA]); 3426 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3427 3428 ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_CDMA], IB_INTR_NOWAIT); 3429 rem_ivintr(mondo, NULL); 3430 } 3431 3432 void 3433 pci_pbm_suspend(pci_t *pci_p) 3434 { 3435 pbm_t *pbm_p = pci_p->pci_pbm_p; 3436 ib_ino_t ino = pci_p->pci_inos[CBNINTR_CDMA]; 3437 3438 /* Save CDMA interrupt state */ 3439 pbm_p->pbm_cdma_imr_save = *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino); 3440 } 3441 3442 void 3443 pci_pbm_resume(pci_t *pci_p) 3444 { 3445 pbm_t *pbm_p = pci_p->pci_pbm_p; 3446 ib_ino_t ino = pci_p->pci_inos[CBNINTR_CDMA]; 3447 3448 /* Restore CDMA interrupt state */ 3449 *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino) = pbm_p->pbm_cdma_imr_save; 3450 } 3451 3452 /* 3453 * pci_bus_quiesce 3454 * 3455 * This function is called as the corresponding control ops routine 3456 * to a DDI_CTLOPS_QUIESCE command. Its mission is to halt all DMA 3457 * activity on the bus by disabling arbitration/parking. 3458 */ 3459 int 3460 pci_bus_quiesce(pci_t *pci_p, dev_info_t *dip, void *result) 3461 { 3462 volatile uint64_t *ctrl_reg_p; 3463 volatile uint64_t ctrl_reg; 3464 pbm_t *pbm_p; 3465 3466 pbm_p = pci_p->pci_pbm_p; 3467 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3468 3469 if (pbm_p->pbm_quiesce_count++ == 0) { 3470 3471 DEBUG0(DBG_PWR, dip, "quiescing bus\n"); 3472 3473 ctrl_reg = *ctrl_reg_p; 3474 pbm_p->pbm_saved_ctrl_reg = ctrl_reg; 3475 ctrl_reg &= ~(SCHIZO_PCI_CTRL_ARB_EN_MASK | 3476 SCHIZO_PCI_CTRL_ARB_PARK); 3477 *ctrl_reg_p = ctrl_reg; 3478 #ifdef DEBUG 3479 ctrl_reg = *ctrl_reg_p; 3480 if ((ctrl_reg & (SCHIZO_PCI_CTRL_ARB_EN_MASK | 3481 SCHIZO_PCI_CTRL_ARB_PARK)) != 0) 3482 panic("ctrl_reg didn't quiesce: 0x%lx\n", ctrl_reg); 3483 #endif 3484 if (pbm_p->pbm_anychild_cfgpa) 3485 (void) ldphysio(pbm_p->pbm_anychild_cfgpa); 3486 } 3487 3488 return (DDI_SUCCESS); 3489 } 3490 3491 /* 3492 * pci_bus_unquiesce 3493 * 3494 * This function is called as the corresponding control ops routine 3495 * to a DDI_CTLOPS_UNQUIESCE command. Its mission is to resume paused 3496 * DMA activity on the bus by re-enabling arbitration (and maybe parking). 3497 */ 3498 int 3499 pci_bus_unquiesce(pci_t *pci_p, dev_info_t *dip, void *result) 3500 { 3501 volatile uint64_t *ctrl_reg_p; 3502 pbm_t *pbm_p; 3503 #ifdef DEBUG 3504 volatile uint64_t ctrl_reg; 3505 #endif 3506 3507 pbm_p = pci_p->pci_pbm_p; 3508 ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3509 3510 ASSERT(pbm_p->pbm_quiesce_count > 0); 3511 if (--pbm_p->pbm_quiesce_count == 0) { 3512 *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 3513 #ifdef DEBUG 3514 ctrl_reg = *ctrl_reg_p; 3515 if ((ctrl_reg & (SCHIZO_PCI_CTRL_ARB_EN_MASK | 3516 SCHIZO_PCI_CTRL_ARB_PARK)) == 0) 3517 panic("ctrl_reg didn't unquiesce: 0x%lx\n", ctrl_reg); 3518 #endif 3519 } 3520 3521 return (DDI_SUCCESS); 3522 } 3523 3524 static void 3525 tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, dvma_addr_t dvma_pg, 3526 int npages) 3527 { 3528 uint32_t dur_max, dur_base; 3529 dvma_unbind_req_t *req_p, *req_max_p; 3530 dvma_unbind_req_t *req_base_p = iommu_p->iommu_mtlb_req_p; 3531 uint32_t tlb_vpn[IOMMU_TLB_ENTRIES]; 3532 caddr_t reg_base; 3533 volatile uint64_t *tag_p; 3534 int i, preserv_count = 0; 3535 3536 mutex_enter(&iommu_p->iommu_mtlb_lock); 3537 3538 iommu_p->iommu_mtlb_npgs += npages; 3539 req_max_p = req_base_p + iommu_p->iommu_mtlb_nreq++; 3540 req_max_p->dur_npg = npages; 3541 req_max_p->dur_base = dvma_pg; 3542 req_max_p->dur_flags = mp->dmai_flags & DMAI_FLAGS_VMEMCACHE; 3543 3544 3545 if (iommu_p->iommu_mtlb_npgs <= iommu_p->iommu_mtlb_maxpgs) 3546 goto done; 3547 3548 /* read TLB */ 3549 reg_base = iommu_p->iommu_pci_p->pci_address[0]; 3550 tag_p = (volatile uint64_t *) 3551 (reg_base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); 3552 3553 for (i = 0; i < IOMMU_TLB_ENTRIES; i++) 3554 tlb_vpn[i] = tag_p[i] & SCHIZO_VPN_MASK; 3555 3556 /* for each request search the TLB for a matching address */ 3557 for (req_p = req_base_p; req_p <= req_max_p; req_p++) { 3558 dur_base = req_p->dur_base; 3559 dur_max = req_p->dur_base + req_p->dur_npg; 3560 3561 for (i = 0; i < IOMMU_TLB_ENTRIES; i++) { 3562 uint_t vpn = tlb_vpn[i]; 3563 if (vpn >= dur_base && vpn < dur_max) 3564 break; 3565 } 3566 if (i >= IOMMU_TLB_ENTRIES) { 3567 pci_vmem_do_free(iommu_p, 3568 (void *)IOMMU_PTOB(req_p->dur_base), 3569 req_p->dur_npg, req_p->dur_flags); 3570 iommu_p->iommu_mtlb_npgs -= req_p->dur_npg; 3571 continue; 3572 } 3573 /* if an empty slot exists */ 3574 if ((req_p - req_base_p) != preserv_count) 3575 *(req_base_p + preserv_count) = *req_p; 3576 preserv_count++; 3577 } 3578 3579 iommu_p->iommu_mtlb_nreq = preserv_count; 3580 done: 3581 mutex_exit(&iommu_p->iommu_mtlb_lock); 3582 } 3583 3584 void 3585 pci_vmem_free(iommu_t *iommu_p, ddi_dma_impl_t *mp, void *dvma_addr, 3586 size_t npages) 3587 { 3588 if (tm_mtlb_gc) 3589 tm_vmem_free(mp, iommu_p, 3590 (dvma_addr_t)IOMMU_BTOP((dvma_addr_t)dvma_addr), npages); 3591 else 3592 pci_vmem_do_free(iommu_p, dvma_addr, npages, 3593 (mp->dmai_flags & DMAI_FLAGS_VMEMCACHE)); 3594 } 3595 3596 /* 3597 * pci_iommu_bypass_end_configure 3598 * 3599 * Support for 42-bit bus width to SAFARI and JBUS in DVMA and 3600 * iommu bypass transfers: 3601 */ 3602 3603 dma_bypass_addr_t 3604 pci_iommu_bypass_end_configure(void) 3605 { 3606 3607 return ((dma_bypass_addr_t)SAFARI_JBUS_IOMMU_BYPASS_END); 3608 } 3609