1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Psycho+ specifics implementation: 30 * interrupt mapping register 31 * PBM configuration 32 * ECC and PBM error handling 33 * Iommu mapping handling 34 * Streaming Cache flushing 35 */ 36 37 #include <sys/types.h> 38 #include <sys/kmem.h> 39 #include <sys/sysmacros.h> 40 #include <sys/async.h> 41 #include <sys/ivintr.h> 42 #include <sys/systm.h> 43 #include <sys/intreg.h> /* UPAID_TO_IGN() */ 44 #include <sys/intr.h> 45 #include <sys/sunddi.h> 46 #include <sys/sunndi.h> 47 #include <sys/machsystm.h> 48 #include <sys/fm/util.h> 49 #include <sys/ddi_impldefs.h> 50 #include <sys/iommutsb.h> 51 #include <sys/spl.h> 52 #include <sys/fm/util.h> 53 #include <sys/fm/protocol.h> 54 #include <sys/fm/io/pci.h> 55 #include <sys/fm/io/sun4upci.h> 56 #include <sys/pci/pci_obj.h> 57 #include <sys/pci/pcipsy.h> 58 59 #ifdef _STARFIRE 60 #include <sys/starfire.h> 61 #endif /* _STARFIRE */ 62 63 static uint32_t pci_identity_init(pci_t *pci_p); 64 static int pci_intr_setup(pci_t *pci_p); 65 static void pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p); 66 67 static pci_ksinfo_t *pci_name_kstat; 68 69 /*LINTLIBRARY*/ 70 /* called by pci_attach() DDI_ATTACH to initialize pci objects */ 71 int 72 pci_obj_setup(pci_t *pci_p) 73 { 74 pci_common_t *cmn_p; 75 int ret; 76 77 mutex_enter(&pci_global_mutex); 78 cmn_p = get_pci_common_soft_state(pci_p->pci_id); 79 if (cmn_p == NULL) { 80 uint_t id = pci_p->pci_id; 81 if (alloc_pci_common_soft_state(id) != DDI_SUCCESS) { 82 mutex_exit(&pci_global_mutex); 83 return (DDI_FAILURE); 84 } 85 cmn_p = get_pci_common_soft_state(id); 86 cmn_p->pci_common_id = id; 87 } 88 89 ASSERT((pci_p->pci_side == 0) || (pci_p->pci_side == 1)); 90 if (cmn_p->pci_p[pci_p->pci_side]) { 91 /* second side attach */ 92 pci_p->pci_side = PCI_OTHER_SIDE(pci_p->pci_side); 93 ASSERT(cmn_p->pci_p[pci_p->pci_side] == NULL); 94 } 95 96 cmn_p->pci_p[pci_p->pci_side] = pci_p; 97 pci_p->pci_common_p = cmn_p; 98 99 if (cmn_p->pci_common_refcnt == 0) { 100 /* Perform allocation first to avoid delicate unwinding. */ 101 if (pci_alloc_tsb(pci_p) != DDI_SUCCESS) { 102 cmn_p->pci_p[pci_p->pci_side] = NULL; 103 pci_p->pci_common_p = NULL; 104 free_pci_common_soft_state(cmn_p->pci_common_id); 105 mutex_exit(&pci_global_mutex); 106 return (DDI_FAILURE); 107 } 108 cmn_p->pci_common_tsb_cookie = pci_p->pci_tsb_cookie; 109 cmn_p->pci_chip_id = pci_identity_init(pci_p); 110 111 ib_create(pci_p); 112 cmn_p->pci_common_ib_p = pci_p->pci_ib_p; 113 114 cb_create(pci_p); 115 cmn_p->pci_common_cb_p = pci_p->pci_cb_p; 116 117 iommu_create(pci_p); 118 cmn_p->pci_common_iommu_p = pci_p->pci_iommu_p; 119 120 ecc_create(pci_p); 121 cmn_p->pci_common_ecc_p = pci_p->pci_ecc_p; 122 } else { 123 ASSERT(cmn_p->pci_common_refcnt == 1); 124 125 pci_p->pci_tsb_cookie = cmn_p->pci_common_tsb_cookie; 126 pci_p->pci_ib_p = cmn_p->pci_common_ib_p; 127 pci_p->pci_cb_p = cmn_p->pci_common_cb_p; 128 pci_p->pci_iommu_p = cmn_p->pci_common_iommu_p; 129 pci_p->pci_ecc_p = cmn_p->pci_common_ecc_p; 130 } 131 132 pbm_create(pci_p); 133 sc_create(pci_p); 134 135 pci_fm_create(pci_p); 136 137 if ((ret = pci_intr_setup(pci_p)) != DDI_SUCCESS) 138 goto done; 139 if (CHIP_TYPE(pci_p) == PCI_CHIP_PSYCHO) 140 pci_kstat_create(pci_p); 141 142 cmn_p->pci_common_attachcnt++; 143 cmn_p->pci_common_refcnt++; 144 done: 145 mutex_exit(&pci_global_mutex); 146 if (ret != DDI_SUCCESS) 147 cmn_err(CE_NOTE, "Interrupt register failure, returning 0x%x\n", 148 ret); 149 return (ret); 150 } 151 152 /* called by pci_detach() DDI_DETACH to destroy pci objects */ 153 void 154 pci_obj_destroy(pci_t *pci_p) 155 { 156 pci_common_t *cmn_p; 157 158 mutex_enter(&pci_global_mutex); 159 160 cmn_p = pci_p->pci_common_p; 161 cmn_p->pci_common_refcnt--; 162 cmn_p->pci_common_attachcnt--; 163 164 pci_kstat_destroy(pci_p); 165 166 sc_destroy(pci_p); 167 pbm_destroy(pci_p); 168 pci_fm_destroy(pci_p); 169 170 if (cmn_p->pci_common_refcnt != 0) { 171 cmn_p->pci_p[pci_p->pci_side] = NULL; 172 mutex_exit(&pci_global_mutex); 173 return; 174 } 175 176 ecc_destroy(pci_p); 177 iommu_destroy(pci_p); 178 cb_destroy(pci_p); 179 ib_destroy(pci_p); 180 181 free_pci_common_soft_state(cmn_p->pci_common_id); 182 pci_intr_teardown(pci_p); 183 mutex_exit(&pci_global_mutex); 184 } 185 186 /* called by pci_attach() DDI_RESUME to (re)initialize pci objects */ 187 void 188 pci_obj_resume(pci_t *pci_p) 189 { 190 pci_common_t *cmn_p = pci_p->pci_common_p; 191 192 mutex_enter(&pci_global_mutex); 193 194 if (cmn_p->pci_common_attachcnt == 0) { 195 ib_configure(pci_p->pci_ib_p); 196 iommu_configure(pci_p->pci_iommu_p); 197 ecc_configure(pci_p); 198 ib_resume(pci_p->pci_ib_p); 199 } 200 201 pbm_configure(pci_p->pci_pbm_p); 202 sc_configure(pci_p->pci_sc_p); 203 204 if (cmn_p->pci_common_attachcnt == 0) 205 cb_resume(pci_p->pci_cb_p); 206 207 pbm_resume(pci_p->pci_pbm_p); 208 209 cmn_p->pci_common_attachcnt++; 210 mutex_exit(&pci_global_mutex); 211 } 212 213 /* called by pci_detach() DDI_SUSPEND to suspend pci objects */ 214 void 215 pci_obj_suspend(pci_t *pci_p) 216 { 217 mutex_enter(&pci_global_mutex); 218 219 pbm_suspend(pci_p->pci_pbm_p); 220 if (!--pci_p->pci_common_p->pci_common_attachcnt) { 221 ib_suspend(pci_p->pci_ib_p); 222 cb_suspend(pci_p->pci_cb_p); 223 } 224 225 mutex_exit(&pci_global_mutex); 226 } 227 228 static uint32_t javelin_prom_fix[] = {0xfff800, 0, 0, 0x3f}; 229 static int 230 pci_intr_setup(pci_t *pci_p) 231 { 232 extern char *platform; 233 dev_info_t *dip = pci_p->pci_dip; 234 pbm_t *pbm_p = pci_p->pci_pbm_p; 235 cb_t *cb_p = pci_p->pci_cb_p; 236 int i, no_of_intrs; 237 238 /* 239 * This is a hack to fix a broken imap entry in the javelin PROM. 240 * see bugid 4226603 241 */ 242 if (strcmp((const char *)&platform, "SUNW,Ultra-250") == 0) 243 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 244 "interrupt-map-mask", (caddr_t)javelin_prom_fix, 245 sizeof (javelin_prom_fix)); 246 247 /* 248 * Get the interrupts property. 249 */ 250 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 251 "interrupts", (caddr_t)&pci_p->pci_inos, 252 &pci_p->pci_inos_len) != DDI_SUCCESS) 253 cmn_err(CE_PANIC, "%s%d: no interrupts property\n", 254 ddi_driver_name(dip), ddi_get_instance(dip)); 255 256 /* 257 * figure out number of interrupts in the "interrupts" property 258 * and convert them all into ino. 259 */ 260 i = ddi_getprop(DDI_DEV_T_ANY, dip, 0, "#interrupt-cells", 1); 261 i = CELLS_1275_TO_BYTES(i); 262 no_of_intrs = pci_p->pci_inos_len / i; 263 for (i = 0; i < no_of_intrs; i++) 264 pci_p->pci_inos[i] = IB_MONDO_TO_INO(pci_p->pci_inos[i]); 265 266 if (pci_p->pci_common_p->pci_common_refcnt == 0) { 267 cb_p->cb_no_of_inos = no_of_intrs; 268 if (i = cb_register_intr(pci_p)) 269 goto teardown; 270 if (i = ecc_register_intr(pci_p)) 271 goto teardown; 272 273 intr_dist_add(cb_intr_dist, cb_p); 274 cb_enable_intr(pci_p); 275 ecc_enable_intr(pci_p); 276 } 277 278 if (i = pbm_register_intr(pbm_p)) { 279 if (pci_p->pci_common_p->pci_common_refcnt == 0) 280 intr_dist_rem(cb_intr_dist, cb_p); 281 goto teardown; 282 } 283 intr_dist_add(pbm_intr_dist, pbm_p); 284 ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_PBM]); 285 286 if (pci_p->pci_common_p->pci_common_refcnt == 0) 287 intr_dist_add_weighted(ib_intr_dist_all, pci_p->pci_ib_p); 288 return (DDI_SUCCESS); 289 teardown: 290 pci_intr_teardown(pci_p); 291 return (i); 292 } 293 294 /* 295 * pci_fix_ranges - fixes the config space entry of the "ranges" 296 * property on psycho+ platforms 297 */ 298 void 299 pci_fix_ranges(pci_ranges_t *rng_p, int rng_entries) 300 { 301 int i; 302 for (i = 0; i < rng_entries; i++, rng_p++) 303 if ((rng_p->child_high & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) 304 rng_p->parent_low |= rng_p->child_high; 305 } 306 307 /* 308 * map_pci_registers 309 * 310 * This function is called from the attach routine to map the registers 311 * accessed by this driver. 312 * 313 * used by: pci_attach() 314 * 315 * return value: DDI_FAILURE on failure 316 */ 317 int 318 map_pci_registers(pci_t *pci_p, dev_info_t *dip) 319 { 320 ddi_device_acc_attr_t attr; 321 322 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 323 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 324 325 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 326 if (ddi_regs_map_setup(dip, 0, &pci_p->pci_address[0], 0, 0, 327 &attr, &pci_p->pci_ac[0]) != DDI_SUCCESS) { 328 cmn_err(CE_WARN, "%s%d: unable to map reg entry 0\n", 329 ddi_driver_name(dip), ddi_get_instance(dip)); 330 return (DDI_FAILURE); 331 } 332 /* 333 * if we don't have streaming buffer, then we don't have 334 * pci_address[2]. 335 */ 336 if (pci_stream_buf_exists && 337 ddi_regs_map_setup(dip, 2, &pci_p->pci_address[2], 0, 0, 338 &attr, &pci_p->pci_ac[2]) != DDI_SUCCESS) { 339 cmn_err(CE_WARN, "%s%d: unable to map reg entry 2\n", 340 ddi_driver_name(dip), ddi_get_instance(dip)); 341 ddi_regs_map_free(&pci_p->pci_ac[0]); 342 return (DDI_FAILURE); 343 } 344 345 /* 346 * The second register set contains the bridge's configuration 347 * header. This header is at the very beginning of the bridge's 348 * configuration space. This space has litte-endian byte order. 349 */ 350 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 351 if (ddi_regs_map_setup(dip, 1, &pci_p->pci_address[1], 0, 352 PCI_CONF_HDR_SIZE, &attr, &pci_p->pci_ac[1]) != DDI_SUCCESS) { 353 354 cmn_err(CE_WARN, "%s%d: unable to map reg entry 1\n", 355 ddi_driver_name(dip), ddi_get_instance(dip)); 356 ddi_regs_map_free(&pci_p->pci_ac[0]); 357 if (pci_stream_buf_exists) 358 ddi_regs_map_free(&pci_p->pci_ac[2]); 359 return (DDI_FAILURE); 360 } 361 DEBUG3(DBG_ATTACH, dip, "address (%p,%p,%p)\n", 362 pci_p->pci_address[0], pci_p->pci_address[1], 363 pci_p->pci_address[2]); 364 365 return (DDI_SUCCESS); 366 } 367 368 /* 369 * unmap_pci_registers: 370 * 371 * This routine unmap the registers mapped by map_pci_registers. 372 * 373 * used by: pci_detach() 374 * 375 * return value: none 376 */ 377 void 378 unmap_pci_registers(pci_t *pci_p) 379 { 380 ddi_regs_map_free(&pci_p->pci_ac[0]); 381 ddi_regs_map_free(&pci_p->pci_ac[1]); 382 if (pci_stream_buf_exists) 383 ddi_regs_map_free(&pci_p->pci_ac[2]); 384 } 385 386 /* 387 * These convenience wrappers relies on map_pci_registers() to setup 388 * pci_address[0-2] correctly at first. 389 */ 390 /* The psycho+ reg base is at 1fe.0000.0000 */ 391 static uintptr_t 392 get_reg_base(pci_t *pci_p) 393 { 394 return ((uintptr_t)pci_p->pci_address[pci_stream_buf_exists ? 2 : 0]); 395 } 396 397 /* The psycho+ config reg base is always the 2nd reg entry */ 398 static uintptr_t 399 get_config_reg_base(pci_t *pci_p) 400 { 401 return ((uintptr_t)(pci_p->pci_address[1])); 402 } 403 404 uint64_t 405 ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id) 406 { 407 return ((mondo) | (cpu_id << COMMON_INTR_MAP_REG_TID_SHIFT) | 408 COMMON_INTR_MAP_REG_VALID); 409 410 } 411 412 uint32_t 413 ib_map_reg_get_cpu(volatile uint64_t reg) 414 { 415 return ((reg & COMMON_INTR_MAP_REG_TID) >> 416 COMMON_INTR_MAP_REG_TID_SHIFT); 417 } 418 419 uint64_t * 420 ib_intr_map_reg_addr(ib_t *ib_p, ib_ino_t ino) 421 { 422 uint64_t *addr; 423 424 if (ino & 0x20) 425 addr = (uint64_t *)(ib_p->ib_obio_intr_map_regs + 426 (((uint_t)ino & 0x1f) << 3)); 427 else 428 addr = (uint64_t *)(ib_p->ib_slot_intr_map_regs + 429 (((uint_t)ino & 0x3c) << 1)); 430 return (addr); 431 } 432 433 uint64_t * 434 ib_clear_intr_reg_addr(ib_t *ib_p, ib_ino_t ino) 435 { 436 uint64_t *addr; 437 438 if (ino & 0x20) 439 addr = (uint64_t *)(ib_p->ib_obio_clear_intr_regs + 440 (((uint_t)ino & 0x1f) << 3)); 441 else 442 addr = (uint64_t *)(ib_p->ib_slot_clear_intr_regs + 443 (((uint_t)ino & 0x1f) << 3)); 444 return (addr); 445 } 446 447 /* 448 * psycho have one mapping register per slot 449 */ 450 void 451 ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 452 { 453 if (!IB_IS_OBIO_INO(ino)) { 454 ASSERT(ino_p->ino_slot_no < 8); 455 ib_p->ib_map_reg_counters[ino_p->ino_slot_no]++; 456 } 457 } 458 459 /* 460 * return true if the ino shares mapping register with other interrupts 461 * of the same slot, or is still shared by other On-board devices. 462 */ 463 int 464 ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 465 { 466 ASSERT(IB_IS_OBIO_INO(ino) || ino_p->ino_slot_no < 8); 467 468 if (IB_IS_OBIO_INO(ino)) 469 return (ino_p->ino_ih_size); 470 else 471 return (--ib_p->ib_map_reg_counters[ino_p->ino_slot_no]); 472 } 473 474 /*ARGSUSED*/ 475 void 476 pci_pbm_intr_dist(pbm_t *pbm_p) 477 { 478 } 479 480 uintptr_t 481 pci_ib_setup(ib_t *ib_p) 482 { 483 pci_t *pci_p = ib_p->ib_pci_p; 484 uintptr_t a = get_reg_base(pci_p); 485 486 ib_p->ib_ign = PCI_ID_TO_IGN(pci_p->pci_id); 487 ib_p->ib_max_ino = PSYCHO_MAX_INO; 488 ib_p->ib_slot_intr_map_regs = a + PSYCHO_IB_SLOT_INTR_MAP_REG_OFFSET; 489 ib_p->ib_obio_intr_map_regs = a + PSYCHO_IB_OBIO_INTR_MAP_REG_OFFSET; 490 ib_p->ib_obio_clear_intr_regs = 491 a + PSYCHO_IB_OBIO_CLEAR_INTR_REG_OFFSET; 492 return (a); 493 } 494 495 uint32_t 496 pci_xlate_intr(dev_info_t *dip, dev_info_t *rdip, ib_t *ib_p, uint32_t intr) 497 { 498 int32_t len; 499 dev_info_t *cdip; 500 pci_regspec_t *pci_rp; 501 uint32_t bus, dev, phys_hi; 502 503 if ((intr > PCI_INTD) || (intr < PCI_INTA)) 504 goto done; 505 if (ddi_prop_exists(DDI_DEV_T_ANY, rdip, NULL, "interrupt-map")) 506 goto done; 507 /* 508 * Hack for pre 1275 imap machines e.g. quark & tazmo 509 * We need to turn any PCI interrupts into ino interrupts. machines 510 * supporting imap will have this done in the map. 511 */ 512 cdip = get_my_childs_dip(dip, rdip); 513 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, "reg", 514 (caddr_t)&pci_rp, &len) != DDI_SUCCESS) 515 return (0); 516 phys_hi = pci_rp->pci_phys_hi; 517 kmem_free(pci_rp, len); 518 519 bus = PCI_REG_BUS_G(phys_hi); 520 dev = PCI_REG_DEV_G(phys_hi); 521 522 /* 523 * The ino for a given device id is derived as 0BSSNN where 524 * 525 * B = 0 for bus A, 1 for bus B 526 * SS = dev - 1 for bus A, dev - 2 for bus B 527 * NN = 00 for INTA#, 01 for INTB#, 10 for INTC#, 11 for INTD# 528 * 529 * if pci bus number > 0x80, then devices are located on the A side(66) 530 */ 531 DEBUG3(DBG_IB, dip, "pci_xlate_intr: bus=%x, dev=%x, intr=%x\n", 532 bus, dev, intr); 533 intr--; 534 intr |= (bus & 0x80) ? ((dev - 1) << 2) : (0x10 | ((dev - 2) << 2)); 535 536 DEBUG1(DBG_IB, dip, "pci_xlate_intr: done ino=%x\n", intr); 537 done: 538 return (IB_INO_TO_MONDO(ib_p, intr)); 539 } 540 541 /* 542 * Return the cpuid to to be used for an ino. Psycho has special slot-cpu 543 * constraints on cpu assignment: 544 * 545 * On multi-function pci cards, functions have separate devinfo nodes and 546 * interrupts. Some pci support hardware, such as the psycho/pcipsy chip, 547 * control interrupt-to-cpu binding on a per pci-slot basis instead of per 548 * function. For hardware like this, if an interrupt for one function has 549 * already been directed to a particular cpu, we can't choose a different 550 * cpu for another function implemented in the same pci-slot - if we did 551 * we would be redirecting the first function too (which causes problems 552 * for consistent interrupt distribution). 553 * 554 * This function determines if there is already an established slot-oriented 555 * interrupt-to-cpu binding established, if there is then it returns that 556 * cpu. Otherwise a new cpu is selected by intr_dist_cpuid(). 557 * 558 * The devinfo node we are trying to associate a cpu with is 559 * ino_p->ino_ih_head->ih_dip. 560 */ 561 uint32_t 562 pci_intr_dist_cpuid(ib_t *ib_p, ib_ino_info_t *ino_p) 563 { 564 dev_info_t *rdip = ino_p->ino_ih_head->ih_dip; 565 dev_info_t *prdip = ddi_get_parent(rdip); 566 ib_ino_info_t *sino_p; 567 dev_info_t *sdip; 568 dev_info_t *psdip; 569 char *buf1 = NULL, *buf2 = NULL; 570 char *s1, *s2, *s3; 571 int l2; 572 int cpu_id; 573 574 /* must be psycho driver parent (not ebus) */ 575 if (strcmp(ddi_driver_name(prdip), "pcipsy") != 0) 576 goto newcpu; 577 578 /* 579 * From PCI 1275 binding: 2.2.1.3 Unit Address representation: 580 * Since the "unit-number" is the address that appears in on Open 581 * Firmware 'device path', it follows that only the DD and DD,FF 582 * forms of the text representation can appear in a 'device path'. 583 * 584 * The rdip unit address is of the form "DD[,FF]". Define two 585 * unit address strings that represent same-slot use: "DD" and "DD,". 586 * The first compare uses strcmp, the second uses strncmp. 587 */ 588 s1 = ddi_get_name_addr(rdip); 589 if (s1 == NULL) 590 goto newcpu; 591 592 buf1 = kmem_alloc(MAXNAMELEN, KM_SLEEP); /* strcmp */ 593 buf2 = kmem_alloc(MAXNAMELEN, KM_SLEEP); /* strncmp */ 594 s1 = strcpy(buf1, s1); 595 s2 = strcpy(buf2, s1); 596 597 s1 = strrchr(s1, ','); 598 if (s1) { 599 *s1 = '\0'; /* have "DD,FF" */ 600 s1 = buf1; /* search via strcmp "DD" */ 601 602 s2 = strrchr(s2, ','); 603 *(s2 + 1) = '\0'; 604 s2 = buf2; 605 l2 = strlen(s2); /* search via strncmp "DD," */ 606 } else { 607 (void) strcat(s2, ","); /* have "DD" */ 608 l2 = strlen(s2); /* search via strncmp "DD," */ 609 } 610 611 /* 612 * Search the established ino list for devinfo nodes bound 613 * to an ino that matches one of the slot use strings. 614 */ 615 ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex)); 616 for (sino_p = ib_p->ib_ino_lst; sino_p; sino_p = sino_p->ino_next) { 617 /* skip self and non-established */ 618 if ((sino_p == ino_p) || (sino_p->ino_established == 0)) 619 continue; 620 621 /* skip non-siblings */ 622 sdip = sino_p->ino_ih_head->ih_dip; 623 psdip = ddi_get_parent(sdip); 624 if (psdip != prdip) 625 continue; 626 627 /* must be psycho driver parent (not ebus) */ 628 if (strcmp(ddi_driver_name(psdip), "pcipsy") != 0) 629 continue; 630 631 s3 = ddi_get_name_addr(sdip); 632 if ((s1 && (strcmp(s1, s3) == 0)) || 633 (strncmp(s2, s3, l2) == 0)) { 634 extern int intr_dist_debug; 635 636 if (intr_dist_debug) 637 cmn_err(CE_CONT, "intr_dist: " 638 "pcipsy`pci_intr_dist_cpuid " 639 "%s#%d %s: cpu %d established " 640 "by %s#%d %s\n", ddi_driver_name(rdip), 641 ddi_get_instance(rdip), 642 ddi_deviname(rdip, buf1), sino_p->ino_cpuid, 643 ddi_driver_name(sdip), 644 ddi_get_instance(sdip), 645 ddi_deviname(sdip, buf2)); 646 break; 647 } 648 } 649 650 /* If a slot use match is found then use established cpu */ 651 if (sino_p) { 652 cpu_id = sino_p->ino_cpuid; /* target established cpu */ 653 goto out; 654 } 655 656 newcpu: cpu_id = intr_dist_cpuid(); /* target new cpu */ 657 658 out: if (buf1) 659 kmem_free(buf1, MAXNAMELEN); 660 if (buf2) 661 kmem_free(buf2, MAXNAMELEN); 662 return (cpu_id); 663 } 664 665 666 /*ARGSUSED*/ 667 static void 668 cb_thermal_timeout(void *arg) 669 { 670 do_shutdown(); 671 672 /* 673 * In case do_shutdown() fails to halt the system. 674 */ 675 (void) timeout((void(*)(void *))power_down, NULL, 676 thermal_powerdown_delay * hz); 677 } 678 679 /* 680 * High-level handler for psycho's CBNINTR_THERMAL interrupt. 681 * 682 * Use timeout(9f) to implement the core functionality so that the 683 * timeout(9f) function can sleep, if needed. 684 */ 685 /*ARGSUSED*/ 686 uint_t 687 cb_thermal_intr(caddr_t a) 688 { 689 cmn_err(CE_WARN, "pci: Thermal warning detected!\n"); 690 if (pci_thermal_intr_fatal) { 691 (void) timeout(cb_thermal_timeout, NULL, 0); 692 } 693 return (DDI_INTR_CLAIMED); 694 } 695 696 void 697 pci_cb_teardown(pci_t *pci_p) 698 { 699 cb_t *cb_p = pci_p->pci_cb_p; 700 uint32_t mondo; 701 702 if (pci_p->pci_thermal_interrupt != -1) { 703 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 704 pci_p->pci_inos[CBNINTR_THERMAL]); 705 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 706 707 cb_disable_nintr(cb_p, CBNINTR_THERMAL, IB_INTR_WAIT); 708 rem_ivintr(mondo, NULL); 709 } 710 #ifdef _STARFIRE 711 pc_ittrans_uninit(cb_p->cb_ittrans_cookie); 712 #endif /* _STARFIRE */ 713 } 714 715 int 716 cb_register_intr(pci_t *pci_p) 717 { 718 uint32_t mondo; 719 720 if (pci_p->pci_thermal_interrupt == -1) 721 return (DDI_SUCCESS); 722 723 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 724 pci_p->pci_inos[CBNINTR_THERMAL]); 725 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 726 727 VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_THERMAL], 728 cb_thermal_intr, (caddr_t)pci_p->pci_cb_p, NULL) == 0); 729 730 return (PCI_ATTACH_RETCODE(PCI_CB_OBJ, PCI_OBJ_INTR_ADD, DDI_SUCCESS)); 731 } 732 733 void 734 cb_enable_intr(pci_t *pci_p) 735 { 736 if (pci_p->pci_thermal_interrupt != -1) 737 cb_enable_nintr(pci_p, CBNINTR_THERMAL); 738 } 739 740 uint64_t 741 cb_ino_to_map_pa(cb_t *cb_p, ib_ino_t ino) 742 { 743 return (cb_p->cb_map_pa + ((ino & 0x1f) << 3)); 744 } 745 746 uint64_t 747 cb_ino_to_clr_pa(cb_t *cb_p, ib_ino_t ino) 748 { 749 return (cb_p->cb_clr_pa + ((ino & 0x1f) << 3)); 750 } 751 752 /* 753 * allow removal of exported/shared thermal interrupt 754 */ 755 int 756 cb_remove_xintr(pci_t *pci_p, dev_info_t *dip, dev_info_t *rdip, 757 ib_ino_t ino, ib_mondo_t mondo) 758 { 759 if (ino != pci_p->pci_inos[CBNINTR_THERMAL]) 760 return (DDI_FAILURE); 761 762 cb_disable_nintr(pci_p->pci_cb_p, CBNINTR_THERMAL, IB_INTR_WAIT); 763 rem_ivintr(mondo, NULL); 764 765 DEBUG1(DBG_R_INTX, dip, "remove xintr %x\n", ino); 766 return (DDI_SUCCESS); 767 } 768 769 int 770 pci_ecc_add_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 771 { 772 uint32_t mondo; 773 774 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 775 pci_p->pci_inos[inum]); 776 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 777 778 VERIFY(add_ivintr(mondo, pci_pil[inum], ecc_intr, 779 (caddr_t)eii_p, NULL) == 0); 780 781 return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, DDI_SUCCESS)); 782 } 783 784 void 785 pci_ecc_rem_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 786 { 787 uint32_t mondo; 788 789 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 790 pci_p->pci_inos[inum]); 791 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 792 793 rem_ivintr(mondo, NULL); 794 } 795 796 static int pbm_has_pass_1_cheerio(pci_t *pci_p); 797 798 void 799 pbm_configure(pbm_t *pbm_p) 800 { 801 pci_t *pci_p = pbm_p->pbm_pci_p; 802 cb_t *cb_p = pci_p->pci_cb_p; 803 dev_info_t *dip = pci_p->pci_dip; 804 int instance = ddi_get_instance(dip); 805 uint32_t mask = 1 << instance; 806 uint64_t l; 807 uint16_t s = 0; 808 809 /* 810 * Workarounds for hardware bugs: 811 * 812 * bus parking 813 * 814 * Pass 2 psycho parts have a bug that requires bus 815 * parking to be disabled. 816 * 817 * Pass 1 cheerio parts have a bug which prevents them 818 * from working on a PBM with bus parking enabled. 819 * 820 * rerun disable 821 * 822 * Pass 1 and 2 psycho's require that the rerun's be 823 * enabled. 824 * 825 * retry limit 826 * 827 * For pass 1 and pass 2 psycho parts we disable the 828 * retry limit. This is because the limit of 16 seems 829 * too restrictive for devices that are children of pci 830 * to pci bridges. For pass 3 this limit will be 64. 831 * 832 * DMA write/PIO read sync 833 * 834 * For pass 2 psycho, the disable this feature. 835 */ 836 l = lddphysio(cb_p->cb_base_pa + PSYCHO_CB_CONTROL_STATUS_REG_OFFSET); 837 l &= PSYCHO_CB_CONTROL_STATUS_VER; 838 l >>= PSYCHO_CB_CONTROL_STATUS_VER_SHIFT; 839 840 DEBUG2(DBG_ATTACH, dip, "cb_create: ver=%d, mask=%x\n", l, mask); 841 pci_rerun_disable = (uint32_t)-1; 842 843 switch (l) { 844 case 0: 845 DEBUG0(DBG_ATTACH, dip, "cb_create: psycho pass 1\n"); 846 if (!pci_disable_pass1_workarounds) { 847 if (pbm_has_pass_1_cheerio(pci_p)) 848 pci_bus_parking_enable &= ~mask; 849 pci_rerun_disable &= ~mask; 850 pci_retry_disable |= mask; 851 } 852 break; 853 case 1: 854 if (!pci_disable_pass2_workarounds) { 855 pci_bus_parking_enable &= ~mask; 856 pci_rerun_disable &= ~mask; 857 pci_retry_disable |= mask; 858 pci_dwsync_disable |= mask; 859 } 860 break; 861 case 2: 862 if (!pci_disable_pass3_workarounds) { 863 pci_dwsync_disable |= mask; 864 if (pbm_has_pass_1_cheerio(pci_p)) 865 pci_bus_parking_enable &= ~mask; 866 } 867 break; 868 case 3: 869 if (!pci_disable_plus_workarounds) { 870 pci_dwsync_disable |= mask; 871 if (pbm_has_pass_1_cheerio(pci_p)) 872 pci_bus_parking_enable &= ~mask; 873 } 874 break; 875 default: 876 if (!pci_disable_default_workarounds) { 877 pci_dwsync_disable |= mask; 878 if (pbm_has_pass_1_cheerio(pci_p)) 879 pci_bus_parking_enable &= ~mask; 880 } 881 break; 882 } 883 884 /* 885 * Clear any PBM errors. 886 */ 887 l = (PSYCHO_PCI_AFSR_E_MASK << PSYCHO_PCI_AFSR_PE_SHIFT) | 888 (PSYCHO_PCI_AFSR_E_MASK << PSYCHO_PCI_AFSR_SE_SHIFT); 889 *pbm_p->pbm_async_flt_status_reg = l; 890 891 /* 892 * Clear error bits in configuration status register. 893 */ 894 s = PCI_STAT_PERROR | PCI_STAT_S_PERROR | 895 PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB | 896 PCI_STAT_S_TARG_AB | PCI_STAT_S_PERROR; 897 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s); 898 pbm_p->pbm_config_header->ch_status_reg = s; 899 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg==%x\n", 900 pbm_p->pbm_config_header->ch_status_reg); 901 902 l = *pbm_p->pbm_ctrl_reg; /* save control register state */ 903 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg==%llx\n", l); 904 905 /* 906 * See if any SERR# signals are asserted. We'll clear them later. 907 */ 908 if (l & COMMON_PCI_CTRL_SERR) 909 cmn_err(CE_WARN, "%s%d: SERR asserted on pci bus\n", 910 ddi_driver_name(dip), instance); 911 912 /* 913 * Determine if PCI bus is running at 33 or 66 mhz. 914 */ 915 if (l & COMMON_PCI_CTRL_SPEED) 916 pbm_p->pbm_speed = PBM_SPEED_66MHZ; 917 else 918 pbm_p->pbm_speed = PBM_SPEED_33MHZ; 919 DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n", 920 pbm_p->pbm_speed == PBM_SPEED_66MHZ ? 66 : 33); 921 922 /* 923 * Enable error interrupts. 924 */ 925 if (pci_error_intr_enable & mask) 926 l |= PSYCHO_PCI_CTRL_ERR_INT_EN; 927 else 928 l &= ~PSYCHO_PCI_CTRL_ERR_INT_EN; 929 930 /* 931 * Disable pci streaming byte errors and error interrupts. 932 */ 933 pci_sbh_error_intr_enable &= ~mask; 934 l &= ~PSYCHO_PCI_CTRL_SBH_INT_EN; 935 936 /* 937 * Enable/disable bus parking. 938 */ 939 if ((pci_bus_parking_enable & mask) && 940 !ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 941 "no-bus-parking")) 942 l |= PSYCHO_PCI_CTRL_ARB_PARK; 943 else 944 l &= ~PSYCHO_PCI_CTRL_ARB_PARK; 945 946 /* 947 * Enable arbitration. 948 */ 949 if (pci_p->pci_side == B) 950 l = (l & ~PSYCHO_PCI_CTRL_ARB_EN_MASK) | pci_b_arb_enable; 951 else 952 l = (l & ~PSYCHO_PCI_CTRL_ARB_EN_MASK) | pci_a_arb_enable; 953 954 /* 955 * Make sure SERR is clear 956 */ 957 l |= COMMON_PCI_CTRL_SERR; 958 959 /* 960 * Make sure power management interrupt is disabled. 961 */ 962 l &= ~PSYCHO_PCI_CTRL_WAKEUP_EN; 963 964 #ifdef _STARFIRE 965 /* 966 * Hack to determine whether we do Starfire special handling 967 * For starfire, we simply program a constant odd-value 968 * (0x1D) in the MID field. 969 * 970 * Zero out the MID field before ORing. We leave the LSB of 971 * the MID field intact since we cannot have a zero (even) 972 * MID value. 973 */ 974 l &= 0xFF0FFFFFFFFFFFFFULL; 975 l |= 0x1DULL << 51; 976 977 /* 978 * Program in the Interrupt Group Number. Here we have to 979 * convert the starfire 7bit upaid into a 5bit value. 980 */ 981 l |= (uint64_t)STARFIRE_UPAID2HWIGN(pbm_p->pbm_pci_p->pci_id) 982 << COMMON_CB_CONTROL_STATUS_IGN_SHIFT; 983 #endif /* _STARFIRE */ 984 985 /* 986 * Now finally write the control register with the appropriate value. 987 */ 988 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 989 *pbm_p->pbm_ctrl_reg = l; 990 991 /* 992 * Allow the diag register to be set based upon variable that 993 * can be configured via /etc/system. 994 */ 995 l = *pbm_p->pbm_diag_reg; 996 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg==%llx\n", l); 997 if (pci_retry_disable & mask) 998 l |= COMMON_PCI_DIAG_DIS_RETRY; 999 if (pci_retry_enable & mask) 1000 l &= ~COMMON_PCI_DIAG_DIS_RETRY; 1001 if (pci_intsync_disable & mask) 1002 l |= COMMON_PCI_DIAG_DIS_INTSYNC; 1003 else 1004 l &= ~COMMON_PCI_DIAG_DIS_INTSYNC; 1005 if (pci_dwsync_disable & mask) 1006 l |= PSYCHO_PCI_DIAG_DIS_DWSYNC; 1007 else 1008 l &= ~PSYCHO_PCI_DIAG_DIS_DWSYNC; 1009 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 1010 *pbm_p->pbm_diag_reg = l; 1011 1012 /* 1013 * Enable SERR# and parity reporting via command register. 1014 */ 1015 s = pci_perr_enable & mask ? PCI_COMM_PARITY_DETECT : 0; 1016 s |= pci_serr_enable & mask ? PCI_COMM_SERR_ENABLE : 0; 1017 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s); 1018 pbm_p->pbm_config_header->ch_command_reg = s; 1019 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg==%x\n", 1020 pbm_p->pbm_config_header->ch_command_reg); 1021 1022 /* 1023 * The current versions of the obp are suppose to set the latency 1024 * timer register but do not. Bug 1234181 is open against this 1025 * problem. Until this bug is fixed we check to see if the obp 1026 * has attempted to set the latency timer register by checking 1027 * for the existence of a "latency-timer" property. 1028 */ 1029 if (pci_set_latency_timer_register) { 1030 DEBUG1(DBG_ATTACH, dip, 1031 "pbm_configure: set psycho latency timer to %x\n", 1032 pci_latency_timer); 1033 pbm_p->pbm_config_header->ch_latency_timer_reg = 1034 pci_latency_timer; 1035 } 1036 1037 (void) ndi_prop_update_int(DDI_DEV_T_ANY, dip, "latency-timer", 1038 (int)pbm_p->pbm_config_header->ch_latency_timer_reg); 1039 } 1040 1041 uint_t 1042 pbm_disable_pci_errors(pbm_t *pbm_p) 1043 { 1044 pci_t *pci_p = pbm_p->pbm_pci_p; 1045 ib_t *ib_p = pci_p->pci_ib_p; 1046 1047 /* 1048 * Disable error and streaming byte hole interrupts via the 1049 * PBM control register. 1050 */ 1051 *pbm_p->pbm_ctrl_reg &= 1052 ~(PSYCHO_PCI_CTRL_ERR_INT_EN | PSYCHO_PCI_CTRL_SBH_INT_EN); 1053 1054 /* 1055 * Disable error interrupts via the interrupt mapping register. 1056 */ 1057 ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_NOWAIT); 1058 return (BF_NONE); 1059 } 1060 1061 /*ARGSUSED*/ 1062 uint64_t 1063 pci_sc_configure(pci_t *pci_p) 1064 { 1065 return (0); 1066 } 1067 1068 /*ARGSUSED*/ 1069 void 1070 pci_pbm_dma_sync(pbm_t *pbm_p, ib_ino_t ino) 1071 { 1072 uint64_t pa = pbm_p->pbm_sync_reg_pa; 1073 if (pa) 1074 (void) lddphysio(pa); /* Load from Sync Register */ 1075 } 1076 1077 /*ARGSUSED*/ 1078 dvma_context_t 1079 pci_iommu_get_dvma_context(iommu_t *iommu_p, dvma_addr_t dvma_pg_index) 1080 { 1081 ASSERT(0); 1082 return (0); 1083 } 1084 1085 /*ARGSUSED*/ 1086 void 1087 pci_iommu_free_dvma_context(iommu_t *iommu_p, dvma_context_t ctx) 1088 { 1089 ASSERT(0); 1090 } 1091 1092 void 1093 pci_iommu_config(iommu_t *iommu_p, uint64_t iommu_ctl, uint64_t cfgpa) 1094 { 1095 volatile uint64_t *pbm_csr_p = (volatile uint64_t *) 1096 get_pbm_reg_base(iommu_p->iommu_pci_p); 1097 volatile uint64_t pbm_ctl = *pbm_csr_p; 1098 1099 volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg; 1100 volatile uint64_t tsb_bar_val = iommu_p->iommu_tsb_paddr; 1101 volatile uint64_t *tsb_bar_p = iommu_p->iommu_tsb_base_addr_reg; 1102 1103 DEBUG2(DBG_ATTACH, iommu_p->iommu_pci_p->pci_dip, 1104 "\npci_iommu_config: pbm_csr_p=%016llx pbm_ctl=%016llx", 1105 pbm_csr_p, pbm_ctl); 1106 DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 1107 "\n\tiommu_ctl_p=%016llx iommu_ctl=%016llx", 1108 iommu_ctl_p, iommu_ctl); 1109 DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 1110 "\n\tcfgpa=%016llx tsb_bar_val=%016llx", cfgpa, tsb_bar_val); 1111 1112 if (!cfgpa) 1113 goto reprog; 1114 1115 /* disable PBM arbiters - turn off bits 0-7 */ 1116 *pbm_csr_p = (pbm_ctl >> 8) << 8; 1117 1118 /* make sure we own the bus by reading any child device config space */ 1119 (void) ldphysio(cfgpa); /* also flushes the prev write */ 1120 reprog: 1121 *tsb_bar_p = tsb_bar_val; 1122 *iommu_ctl_p = iommu_ctl; 1123 1124 *pbm_csr_p = pbm_ctl; /* re-enable bus arbitration */ 1125 pbm_ctl = *pbm_csr_p; /* flush all prev writes */ 1126 } 1127 1128 int 1129 pci_sc_ctx_inv(dev_info_t *dip, sc_t *sc_p, ddi_dma_impl_t *mp) 1130 { 1131 ASSERT(0); 1132 return (DDI_FAILURE); 1133 } 1134 1135 void 1136 pci_cb_setup(pci_t *pci_p) 1137 { 1138 uint64_t csr, csr_pa, pa; 1139 cb_t *cb_p = pci_p->pci_cb_p; 1140 1141 /* cb_p->cb_node_id = 0; */ 1142 cb_p->cb_ign = PCI_ID_TO_IGN(pci_p->pci_id); 1143 pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[0]); 1144 cb_p->cb_base_pa = pa = pa >> (32 - MMU_PAGESHIFT) << 32; 1145 cb_p->cb_map_pa = pa + PSYCHO_IB_OBIO_INTR_MAP_REG_OFFSET; 1146 cb_p->cb_clr_pa = pa + PSYCHO_IB_OBIO_CLEAR_INTR_REG_OFFSET; 1147 cb_p->cb_obsta_pa = pa + COMMON_IB_OBIO_INTR_STATE_DIAG_REG; 1148 1149 csr_pa = pa + PSYCHO_CB_CONTROL_STATUS_REG_OFFSET; 1150 csr = lddphysio(csr_pa); 1151 1152 /* 1153 * Clear any pending address parity errors. 1154 */ 1155 if (csr & COMMON_CB_CONTROL_STATUS_APERR) { 1156 csr |= COMMON_CB_CONTROL_STATUS_APERR; 1157 cmn_err(CE_WARN, "clearing UPA address parity error\n"); 1158 } 1159 csr |= COMMON_CB_CONTROL_STATUS_APCKEN; 1160 csr &= ~COMMON_CB_CONTROL_STATUS_IAP; 1161 stdphysio(csr_pa, csr); 1162 1163 #ifdef _STARFIRE 1164 /* Setup Starfire interrupt target translation */ 1165 pc_ittrans_init(pci_p->pci_id, &cb_p->cb_ittrans_cookie); 1166 #endif /* _STARFIRE */ 1167 1168 } 1169 1170 void 1171 pci_ecc_setup(ecc_t *ecc_p) 1172 { 1173 ecc_p->ecc_ue.ecc_errpndg_mask = 0; 1174 ecc_p->ecc_ue.ecc_offset_mask = PSYCHO_ECC_UE_AFSR_DW_OFFSET; 1175 ecc_p->ecc_ue.ecc_offset_shift = PSYCHO_ECC_UE_AFSR_DW_OFFSET_SHIFT; 1176 ecc_p->ecc_ue.ecc_size_log2 = 3; 1177 1178 ecc_p->ecc_ce.ecc_errpndg_mask = 0; 1179 ecc_p->ecc_ce.ecc_offset_mask = PSYCHO_ECC_CE_AFSR_DW_OFFSET; 1180 ecc_p->ecc_ce.ecc_offset_shift = PSYCHO_ECC_CE_AFSR_DW_OFFSET_SHIFT; 1181 ecc_p->ecc_ce.ecc_size_log2 = 3; 1182 } 1183 1184 /* 1185 * overwrite dvma end address (only on virtual-dma systems) 1186 * initialize tsb size 1187 * reset context bits 1188 * return: IOMMU CSR bank base address (VA) 1189 */ 1190 uintptr_t 1191 pci_iommu_setup(iommu_t *iommu_p) 1192 { 1193 pci_dvma_range_prop_t *dvma_prop; 1194 int dvma_prop_len; 1195 1196 pci_t *pci_p = iommu_p->iommu_pci_p; 1197 dev_info_t *dip = pci_p->pci_dip; 1198 uint_t tsb_size = iommu_tsb_cookie_to_size(pci_p->pci_tsb_cookie); 1199 uint_t tsb_size_prop; 1200 1201 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1202 "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) != 1203 DDI_PROP_SUCCESS) 1204 goto tsb_done; 1205 1206 if (dvma_prop_len != sizeof (pci_dvma_range_prop_t)) { 1207 cmn_err(CE_WARN, "%s%d: invalid virtual-dma property", 1208 ddi_driver_name(dip), ddi_get_instance(dip)); 1209 goto tsb_end; 1210 } 1211 iommu_p->iommu_dvma_end = dvma_prop->dvma_base + 1212 (dvma_prop->dvma_len - 1); 1213 tsb_size_prop = IOMMU_BTOP(dvma_prop->dvma_len) * sizeof (uint64_t); 1214 tsb_size = MIN(tsb_size_prop, tsb_size); 1215 tsb_end: 1216 kmem_free(dvma_prop, dvma_prop_len); 1217 tsb_done: 1218 iommu_p->iommu_tsb_size = iommu_tsb_size_encode(tsb_size); 1219 1220 if (CHIP_TYPE(pci_p) != PCI_CHIP_HUMMINGBIRD) 1221 pci_preserve_iommu_tsb = 0; 1222 1223 /* 1224 * Psycho has no context support. 1225 */ 1226 iommu_p->iommu_ctx_bitmap = NULL; 1227 iommu_p->iommu_flush_ctx_reg = NULL; 1228 pci_use_contexts = 0; 1229 pci_sc_use_contexts = 0; 1230 1231 /* 1232 * Determine the virtual address of the register block 1233 * containing the iommu control registers. 1234 */ 1235 return (get_reg_base(pci_p)); 1236 } 1237 1238 /*ARGSUSED*/ 1239 void 1240 pci_iommu_teardown(iommu_t *iommu_p) 1241 { 1242 } 1243 1244 /* The psycho+ PBM reg base is at 1fe.0000.2000 */ 1245 uintptr_t 1246 get_pbm_reg_base(pci_t *pci_p) 1247 { 1248 return ((uintptr_t)(pci_p->pci_address[0] + 1249 (pci_stream_buf_exists ? 0 : PSYCHO_PCI_PBM_REG_BASE))); 1250 } 1251 1252 void 1253 pci_post_uninit_child(pci_t *pci_p) 1254 { 1255 } 1256 1257 void 1258 pci_pbm_setup(pbm_t *pbm_p) 1259 { 1260 pci_t *pci_p = pbm_p->pbm_pci_p; 1261 1262 /* 1263 * Get the base virtual address for the PBM control block. 1264 */ 1265 uintptr_t a = get_pbm_reg_base(pci_p); 1266 1267 /* 1268 * Get the virtual address of the PCI configuration header. 1269 * This should be mapped little-endian. 1270 */ 1271 pbm_p->pbm_config_header = 1272 (config_header_t *)get_config_reg_base(pci_p); 1273 1274 /* 1275 * Get the virtual addresses for control, error and diag 1276 * registers. 1277 */ 1278 pbm_p->pbm_ctrl_reg = (uint64_t *)(a + PSYCHO_PCI_CTRL_REG_OFFSET); 1279 pbm_p->pbm_diag_reg = (uint64_t *)(a + PSYCHO_PCI_DIAG_REG_OFFSET); 1280 pbm_p->pbm_async_flt_status_reg = 1281 (uint64_t *)(a + PSYCHO_PCI_ASYNC_FLT_STATUS_REG_OFFSET); 1282 pbm_p->pbm_async_flt_addr_reg = 1283 (uint64_t *)(a + PSYCHO_PCI_ASYNC_FLT_ADDR_REG_OFFSET); 1284 1285 if (CHIP_TYPE(pci_p) >= PCI_CHIP_SABRE) 1286 pbm_p->pbm_sync_reg_pa = 1287 pci_p->pci_cb_p->cb_base_pa + DMA_WRITE_SYNC_REG; 1288 } 1289 1290 /*ARGSUSED*/ 1291 void 1292 pci_pbm_teardown(pbm_t *pbm_p) 1293 { 1294 } 1295 1296 void 1297 pci_sc_setup(sc_t *sc_p) 1298 { 1299 pci_t *pci_p = sc_p->sc_pci_p; 1300 1301 /* 1302 * Determine the virtual addresses of the streaming cache 1303 * control/status and flush registers. 1304 */ 1305 uintptr_t a = get_pbm_reg_base(pci_p); 1306 sc_p->sc_ctrl_reg = (uint64_t *)(a + PSYCHO_SC_CTRL_REG_OFFSET); 1307 sc_p->sc_invl_reg = (uint64_t *)(a + PSYCHO_SC_INVL_REG_OFFSET); 1308 sc_p->sc_sync_reg = (uint64_t *)(a + PSYCHO_SC_SYNC_REG_OFFSET); 1309 1310 /* 1311 * Determine the virtual addresses of the streaming cache 1312 * diagnostic access registers. 1313 */ 1314 a = get_reg_base(pci_p); 1315 if (pci_p->pci_bus_range.lo != 0) { 1316 sc_p->sc_data_diag_acc = (uint64_t *) 1317 (a + PSYCHO_SC_A_DATA_DIAG_OFFSET); 1318 sc_p->sc_tag_diag_acc = (uint64_t *) 1319 (a + PSYCHO_SC_A_TAG_DIAG_OFFSET); 1320 sc_p->sc_ltag_diag_acc = (uint64_t *) 1321 (a + PSYCHO_SC_A_LTAG_DIAG_OFFSET); 1322 } else { 1323 sc_p->sc_data_diag_acc = (uint64_t *) 1324 (a + PSYCHO_SC_B_DATA_DIAG_OFFSET); 1325 sc_p->sc_tag_diag_acc = (uint64_t *) 1326 (a + PSYCHO_SC_B_TAG_DIAG_OFFSET); 1327 sc_p->sc_ltag_diag_acc = (uint64_t *) 1328 (a + PSYCHO_SC_B_LTAG_DIAG_OFFSET); 1329 } 1330 } 1331 1332 int 1333 pci_get_numproxy(dev_info_t *dip) 1334 { 1335 return (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1336 "#upa-interrupt-proxies", 1)); 1337 } 1338 1339 int 1340 pci_get_portid(dev_info_t *dip) 1341 { 1342 return (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1343 "upa-portid", -1)); 1344 } 1345 1346 /* 1347 * pbm_has_pass_1_cheerio 1348 * 1349 * 1350 * Given a PBM soft state pointer, this routine scans it child nodes 1351 * to see if one is a pass 1 cheerio. 1352 * 1353 * return value: 1 if pass 1 cheerio is found, 0 otherwise 1354 */ 1355 static int 1356 pbm_has_pass_1_cheerio(pci_t *pci_p) 1357 { 1358 dev_info_t *cdip; 1359 int found = 0; 1360 char *s; 1361 int rev; 1362 1363 cdip = ddi_get_child(pci_p->pci_dip); 1364 while (cdip != NULL && found == 0) { 1365 s = ddi_get_name(cdip); 1366 if (strcmp(s, "ebus") == 0 || strcmp(s, "pci108e,1000") == 0) { 1367 rev = 1368 ddi_getprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 1369 "revision-id", 0); 1370 if (rev == 0) 1371 found = 1; 1372 } 1373 cdip = ddi_get_next_sibling(cdip); 1374 } 1375 return (found); 1376 } 1377 1378 /* 1379 * Psycho Performance Events. 1380 */ 1381 pci_kev_mask_t 1382 psycho_pci_events[] = { 1383 {"dvma_stream_rd_a", 0x0}, {"dvma_stream_wr_a", 0x1}, 1384 {"dvma_const_rd_a", 0x2}, {"dvma_const_wr_a", 0x3}, 1385 {"dvma_stream_buf_mis_a", 0x4}, {"dvma_cycles_a", 0x5}, 1386 {"dvma_wd_xfr_a", 0x6}, {"pio_cycles_a", 0x7}, 1387 {"dvma_stream_rd_b", 0x8}, {"dvma_stream_wr_b", 0x9}, 1388 {"dvma_const_rd_b", 0xa}, {"dvma_const_wr_b", 0xb}, 1389 {"dvma_stream_buf_mis_b", 0xc}, {"dvma_cycles_b", 0xd}, 1390 {"dvma_wd_xfr_b", 0xe}, {"pio_cycles_b", 0xf}, 1391 {"dvma_tlb_misses", 0x10}, {"interrupts", 0x11}, 1392 {"upa_inter_nack", 0x12}, {"pio_reads", 0x13}, 1393 {"pio_writes", 0x14}, {"merge_buffer", 0x15}, 1394 {"dma_tbwalk_a", 0x16}, {"dma_stc_a", 0x17}, 1395 {"dma_tbwalk_b", 0x18}, {"dma_stc_b", 0x19}, 1396 {"clear_pic", 0x1f} 1397 }; 1398 1399 /* 1400 * Create the picN kstat's. 1401 */ 1402 void 1403 pci_kstat_init() 1404 { 1405 pci_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 1406 KM_NOSLEEP); 1407 1408 if (pci_name_kstat == NULL) { 1409 cmn_err(CE_WARN, "pcipsy : no space for kstat\n"); 1410 } else { 1411 pci_name_kstat->pic_no_evs = 1412 sizeof (psycho_pci_events) / sizeof (pci_kev_mask_t); 1413 pci_name_kstat->pic_shift[0] = PSYCHO_SHIFT_PIC0; 1414 pci_name_kstat->pic_shift[1] = PSYCHO_SHIFT_PIC1; 1415 pci_create_name_kstat("pcip", 1416 pci_name_kstat, psycho_pci_events); 1417 } 1418 } 1419 1420 /* 1421 * Called from _fini() 1422 */ 1423 void 1424 pci_kstat_fini() 1425 { 1426 if (pci_name_kstat != NULL) { 1427 pci_delete_name_kstat(pci_name_kstat); 1428 kmem_free(pci_name_kstat, sizeof (pci_ksinfo_t)); 1429 pci_name_kstat = NULL; 1430 } 1431 } 1432 1433 /* ARGSUSED */ 1434 void 1435 pci_add_pci_kstat(pci_t *pci_p) 1436 { 1437 } 1438 1439 /* ARGSUSED */ 1440 void 1441 pci_rem_pci_kstat(pci_t *pci_p) 1442 { 1443 } 1444 1445 /* 1446 * Create the performance 'counters' kstat. 1447 */ 1448 void 1449 pci_add_upstream_kstat(pci_t *pci_p) 1450 { 1451 pci_common_t *cmn_p = pci_p->pci_common_p; 1452 pci_cntr_pa_t *cntr_pa_p = &cmn_p->pci_cmn_uks_pa; 1453 uint64_t regbase = va_to_pa((void *)get_reg_base(pci_p)); 1454 1455 cntr_pa_p->pcr_pa = regbase + PSYCHO_PERF_PCR_OFFSET; 1456 cntr_pa_p->pic_pa = regbase + PSYCHO_PERF_PIC_OFFSET; 1457 cmn_p->pci_common_uksp = pci_create_cntr_kstat(pci_p, "pcip", 1458 NUM_OF_PICS, pci_cntr_kstat_pa_update, cntr_pa_p); 1459 } 1460 1461 /* 1462 * Extract the drivers binding name to identify which chip 1463 * we're binding to. Whenever a new bus bridge is created, the driver alias 1464 * entry should be added here to identify the device if needed. If a device 1465 * isn't added, the identity defaults to PCI_CHIP_UNIDENTIFIED. 1466 */ 1467 static uint32_t 1468 pci_identity_init(pci_t *pci_p) 1469 { 1470 dev_info_t *dip = pci_p->pci_dip; 1471 char *name = ddi_binding_name(dip); 1472 1473 if (strcmp(name, "pci108e,8000") == 0) 1474 return (CHIP_ID(PCI_CHIP_PSYCHO, 0x00, 0x00)); 1475 if (strcmp(name, "pci108e,a000") == 0) 1476 return (CHIP_ID(PCI_CHIP_SABRE, 0x00, 0x00)); 1477 if (strcmp(name, "pci108e,a001") == 0) 1478 return (CHIP_ID(PCI_CHIP_HUMMINGBIRD, 0x00, 0x00)); 1479 cmn_err(CE_CONT, "?%s%d:using default chip identity\n", 1480 ddi_driver_name(dip), ddi_get_instance(dip)); 1481 return (CHIP_ID(PCI_CHIP_PSYCHO, 0x00, 0x00)); 1482 } 1483 1484 /*ARGSUSED*/ 1485 void 1486 pci_post_init_child(pci_t *pci_p, dev_info_t *child) 1487 { 1488 } 1489 1490 /*ARGSUSED*/ 1491 int 1492 pci_pbm_add_intr(pci_t *pci_p) 1493 { 1494 return (DDI_SUCCESS); 1495 } 1496 1497 /*ARGSUSED*/ 1498 void 1499 pci_pbm_rem_intr(pci_t *pci_p) 1500 { 1501 } 1502 1503 /*ARGSUSED*/ 1504 void 1505 pci_pbm_suspend(pci_t *pci_p) 1506 { 1507 } 1508 1509 /*ARGSUSED*/ 1510 void 1511 pci_pbm_resume(pci_t *pci_p) 1512 { 1513 } 1514 1515 /* 1516 * pcipsy error handling 101: 1517 * 1518 * The various functions below are responsible for error handling. Given 1519 * a particular error, they must gather the appropriate state, report all 1520 * errors with correct payload, and attempt recovery where ever possible. 1521 * 1522 * Recovery in the context of this driver is being able notify a leaf device 1523 * of the failed transaction. This leaf device may either be the master or 1524 * target for this transaction and may have already received an error 1525 * notification via a PCI interrupt. Notification is done via DMA and access 1526 * handles. If we capture an address for the transaction then we can map it 1527 * to a handle(if the leaf device is fma-compliant) and fault the handle as 1528 * well as call the device driver registered callback. 1529 * 1530 * The hardware can either interrupt or trap upon detection of an error, in 1531 * some rare cases it also causes a fatal reset. 1532 * 1533 * pbm_error_intr() and ecc_intr() are responsible for PCI Block Module 1534 * errors(generic PCI + bridge specific) and ECC errors, respectively. They 1535 * are common between pcisch and pcipsy and therefore exist in pci_pbm.c and 1536 * pci_ecc.c. To support error handling certain chip specific handlers 1537 * must exist and they are defined below. 1538 * 1539 * cpu_deferred_error() and cpu_async_error(), handle the traps that may 1540 * have originated from IO space. They call into the registered IO callbacks 1541 * to report and handle errors that may have caused the trap. 1542 * 1543 * pci_pbm_err_handler() is called by pbm_error_intr() or pci_err_callback() 1544 * (generic fma callback for pcipsy/pcisch, pci_fm.c). pci_err_callback() is 1545 * called when the CPU has trapped because of a possible IO error(TO/BERR/UE). 1546 * It will call pci_pbm_err_handler() to report and handle all PCI/PBM/IOMMU 1547 * related errors which are detected by the chip. 1548 * 1549 * pci_pbm_err_handler() calls a generic interface pbm_afsr_report()(pci_pbm.c) 1550 * to report the pbm specific errors and attempt to map the failed address 1551 * (if captured) to a device instance. pbm_afsr_report() calls a chip specific 1552 * interface to interpret the afsr bits pci_pbm_classify()(pcisch.c/pcipsy.c). 1553 * 1554 * ecc_err_handler()(pci_ecc.c) also calls a chip specific interface to 1555 * interpret the afsr, pci_ecc_classify(). ecc_err_handler() also calls 1556 * pci_pbm_err_handler() and ndi_fm_handler_dispatch() to log any related 1557 * errors. 1558 * 1559 * To make sure that the trap code and the interrupt code are not going 1560 * to step on each others toes we have a per chip pci_fm_mutex. This also 1561 * makes it necessary for us to be cautious while we are at a high PIL, so 1562 * that we do not cause a subsequent trap that causes us to hang. 1563 * 1564 * The attempt to commonize code was meant to keep in line with the current 1565 * pci driver implementation and it was not meant to confuse. If you are 1566 * confused then don't worry, I was too. 1567 */ 1568 1569 /* 1570 * For Psycho, a UE is always fatal, except if it is a translation error on a 1571 * Darwin platform. We ignore these because they do not cause data corruption. 1572 */ 1573 int 1574 ecc_ue_is_fatal(struct async_flt *ecc) 1575 { 1576 return (((uint_t)(ecc->flt_stat >> SABRE_UE_AFSR_PDTE_SHIFT) & 1577 SABRE_UE_AFSR_E_PDTE) == 0); 1578 } 1579 1580 /* 1581 * pci_ecc_classify, called by ecc_handler to classify ecc errors 1582 * and determine if we should panic or not. 1583 * 1584 * Note that it is possible yet extremely rare for more than one 1585 * primary error bit to be set. We classify the ecc error based 1586 * on the first set bit that is found. 1587 */ 1588 void 1589 pci_ecc_classify(uint64_t err, ecc_errstate_t *ecc_err_p) 1590 { 1591 struct async_flt *ecc = &ecc_err_p->ecc_aflt; 1592 pci_common_t *cmn_p = ecc_err_p->ecc_ii_p.ecc_p->ecc_pci_cmn_p; 1593 1594 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1595 1596 ecc_err_p->ecc_bridge_type = PCI_BRIDGE_TYPE(cmn_p); 1597 /* 1598 * Get the parent bus id that caused the error. 1599 */ 1600 ecc_err_p->ecc_dev_id = (ecc_err_p->ecc_afsr & PSYCHO_ECC_UE_AFSR_ID) 1601 >> PSYCHO_ECC_UE_AFSR_ID_SHIFT; 1602 /* 1603 * Determine the doubleword offset of the error. 1604 */ 1605 ecc_err_p->ecc_dw_offset = (ecc_err_p->ecc_afsr & 1606 PSYCHO_ECC_UE_AFSR_DW_OFFSET) 1607 >> PSYCHO_ECC_UE_AFSR_DW_OFFSET_SHIFT; 1608 /* 1609 * Determine the primary error type. 1610 */ 1611 if (err & COMMON_ECC_UE_AFSR_E_PIO) { 1612 if (ecc_err_p->ecc_ii_p.ecc_type == CBNINTR_UE) { 1613 if (ecc_err_p->ecc_pri) { 1614 ecc->flt_erpt_class = PCI_ECC_PIO_UE; 1615 } else { 1616 ecc->flt_erpt_class = PCI_ECC_SEC_PIO_UE; 1617 } 1618 ecc->flt_panic = ecc_ue_is_fatal(&ecc_err_p->ecc_aflt); 1619 } else { 1620 ecc->flt_erpt_class = ecc_err_p->ecc_pri ? 1621 PCI_ECC_PIO_CE : PCI_ECC_SEC_PIO_CE; 1622 return; 1623 } 1624 } else if (err & COMMON_ECC_UE_AFSR_E_DRD) { 1625 if (ecc_err_p->ecc_ii_p.ecc_type == CBNINTR_UE) { 1626 if (ecc_err_p->ecc_pri) { 1627 ecc->flt_erpt_class = PCI_ECC_DRD_UE; 1628 } else { 1629 ecc->flt_erpt_class = PCI_ECC_SEC_DRD_UE; 1630 } 1631 ecc->flt_panic = ecc_ue_is_fatal(&ecc_err_p->ecc_aflt); 1632 } else { 1633 ecc->flt_erpt_class = ecc_err_p->ecc_pri ? 1634 PCI_ECC_DRD_CE : PCI_ECC_SEC_DRD_CE; 1635 return; 1636 } 1637 } else if (err & COMMON_ECC_UE_AFSR_E_DWR) { 1638 if (ecc_err_p->ecc_ii_p.ecc_type == CBNINTR_UE) { 1639 if (ecc_err_p->ecc_pri) { 1640 ecc->flt_erpt_class = PCI_ECC_DWR_UE; 1641 } else { 1642 ecc->flt_erpt_class = PCI_ECC_SEC_DWR_UE; 1643 } 1644 ecc->flt_panic = ecc_ue_is_fatal(&ecc_err_p->ecc_aflt); 1645 } else { 1646 ecc->flt_erpt_class = ecc_err_p->ecc_pri ? 1647 PCI_ECC_DWR_CE : PCI_ECC_SEC_DWR_CE; 1648 return; 1649 } 1650 } 1651 } 1652 1653 ushort_t 1654 pci_ecc_get_synd(uint64_t afsr) 1655 { 1656 return ((ushort_t)((afsr & PSYCHO_ECC_CE_AFSR_SYND) 1657 >> PSYCHO_ECC_CE_AFSR_SYND_SHIFT)); 1658 } 1659 1660 /* 1661 * pci_pbm_classify, called by pbm_afsr_report to classify piow afsr. 1662 */ 1663 int 1664 pci_pbm_classify(pbm_errstate_t *pbm_err_p) 1665 { 1666 uint32_t e; 1667 int nerr = 0; 1668 char **tmp_class; 1669 1670 if (pbm_err_p->pbm_pri) { 1671 tmp_class = &pbm_err_p->pbm_pci.pci_err_class; 1672 e = PBM_AFSR_TO_PRIERR(pbm_err_p->pbm_afsr); 1673 pbm_err_p->pbm_log = FM_LOG_PCI; 1674 } else { 1675 tmp_class = &pbm_err_p->pbm_err_class; 1676 e = PBM_AFSR_TO_SECERR(pbm_err_p->pbm_afsr); 1677 pbm_err_p->pbm_log = FM_LOG_PBM; 1678 } 1679 1680 if (e & PSYCHO_PCI_AFSR_E_MA) { 1681 *tmp_class = pbm_err_p->pbm_pri ? PCI_MA : PCI_SEC_MA; 1682 nerr++; 1683 } 1684 if (e & PSYCHO_PCI_AFSR_E_TA) { 1685 *tmp_class = pbm_err_p->pbm_pri ? PCI_REC_TA : PCI_SEC_REC_TA; 1686 nerr++; 1687 } 1688 if (e & PSYCHO_PCI_AFSR_E_RTRY) { 1689 pbm_err_p->pbm_err_class = pbm_err_p->pbm_pri ? 1690 PCI_PBM_RETRY : PCI_SEC_PBM_RETRY; 1691 pbm_err_p->pbm_log = FM_LOG_PBM; 1692 nerr++; 1693 } 1694 if (e & PSYCHO_PCI_AFSR_E_PERR) { 1695 *tmp_class = pbm_err_p->pbm_pri ? PCI_MDPE : PCI_SEC_MDPE; 1696 nerr++; 1697 } 1698 return (nerr); 1699 } 1700 1701 /* 1702 * Function used to clear PBM/PCI/IOMMU error state after error handling 1703 * is complete. Only clearing error bits which have been logged. Called by 1704 * pci_pbm_err_handler and pci_bus_exit. 1705 */ 1706 static void 1707 pci_clear_error(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 1708 { 1709 pbm_t *pbm_p = pci_p->pci_pbm_p; 1710 1711 ASSERT(MUTEX_HELD(&pbm_p->pbm_pci_p->pci_common_p->pci_fm_mutex)); 1712 1713 *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat; 1714 *pbm_p->pbm_async_flt_status_reg = pbm_err_p->pbm_afsr; 1715 pbm_p->pbm_config_header->ch_status_reg = 1716 pbm_err_p->pbm_pci.pci_cfg_stat; 1717 } 1718 1719 /*ARGSUSED*/ 1720 int 1721 pci_pbm_err_handler(dev_info_t *dip, ddi_fm_error_t *derr, 1722 const void *impl_data, int caller) 1723 { 1724 int fatal = 0; 1725 int nonfatal = 0; 1726 int unknown = 0; 1727 uint32_t prierr, secerr; 1728 pbm_errstate_t pbm_err; 1729 char buf[FM_MAX_CLASS]; 1730 pci_t *pci_p = (pci_t *)impl_data; 1731 pbm_t *pbm_p = pci_p->pci_pbm_p; 1732 int ret = 0; 1733 uint64_t pbm_ctl_stat; 1734 uint16_t pci_cfg_stat; 1735 1736 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1737 pci_pbm_errstate_get(pci_p, &pbm_err); 1738 1739 derr->fme_ena = derr->fme_ena ? derr->fme_ena : 1740 fm_ena_generate(0, FM_ENA_FMT1); 1741 1742 prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr); 1743 secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr); 1744 1745 if (derr->fme_flag == DDI_FM_ERR_EXPECTED) { 1746 if (caller == PCI_TRAP_CALL) { 1747 /* 1748 * For ddi_caut_get treat all events as 1749 * nonfatal. The trampoline will set 1750 * err_ena = 0, err_status = NONFATAL. We only 1751 * really call this function so that pci_clear_error() 1752 * and ndi_fm_handler_dispatch() will get called. 1753 */ 1754 derr->fme_status = DDI_FM_NONFATAL; 1755 nonfatal++; 1756 goto done; 1757 } else { 1758 /* 1759 * For ddi_caut_put treat all events as nonfatal. Here 1760 * we have the handle and can call ndi_fm_acc_err_set(). 1761 */ 1762 derr->fme_status = DDI_FM_NONFATAL; 1763 ndi_fm_acc_err_set(pbm_p->pbm_excl_handle, derr); 1764 nonfatal++; 1765 goto done; 1766 } 1767 } else if (derr->fme_flag == DDI_FM_ERR_PEEK) { 1768 /* 1769 * For ddi_peek treat all events as nonfatal. We only 1770 * really call this function so that pci_clear_error() 1771 * and ndi_fm_handler_dispatch() will get called. 1772 */ 1773 nonfatal++; 1774 goto done; 1775 } else if (derr->fme_flag == DDI_FM_ERR_POKE) { 1776 /* 1777 * For ddi_poke we can treat as nonfatal if the 1778 * following conditions are met : 1779 * 1. Make sure only primary error is MA/TA 1780 * 2. Make sure no secondary error 1781 * 3. check pci config header stat reg to see MA/TA is 1782 * logged. We cannot verify only MA/TA is recorded 1783 * since it gets much more complicated when a 1784 * PCI-to-PCI bridge is present. 1785 */ 1786 if ((prierr == PSYCHO_PCI_AFSR_E_MA) && !secerr && 1787 (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_MAST_AB)) { 1788 nonfatal++; 1789 goto done; 1790 } 1791 if ((prierr == PSYCHO_PCI_AFSR_E_TA) && !secerr && 1792 (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_TARG_AB)) { 1793 nonfatal++; 1794 goto done; 1795 } 1796 } 1797 1798 if (prierr || secerr) { 1799 ret = pbm_afsr_report(dip, derr->fme_ena, &pbm_err); 1800 if (ret == DDI_FM_FATAL) 1801 fatal++; 1802 else 1803 nonfatal++; 1804 } 1805 1806 ret = pci_cfg_report(dip, derr, &pbm_err.pbm_pci, caller, prierr); 1807 if (ret == DDI_FM_FATAL) 1808 fatal++; 1809 else if (ret == DDI_FM_NONFATAL) 1810 nonfatal++; 1811 1812 pbm_ctl_stat = pbm_err.pbm_ctl_stat; 1813 pci_cfg_stat = pbm_err.pbm_pci.pci_cfg_stat; 1814 1815 /* 1816 * PBM Received System Error - During any transaction, or 1817 * at any point on the bus, some device may detect a critical 1818 * error and signal a system error to the system. 1819 */ 1820 if (pbm_ctl_stat & COMMON_PCI_CTRL_SERR) { 1821 /* 1822 * may be expected (master abort from pci-pci bridge during 1823 * poke will generate SERR) 1824 */ 1825 if (derr->fme_flag != DDI_FM_ERR_POKE) { 1826 pbm_err.pbm_pci.pci_err_class = PCI_REC_SERR; 1827 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 1828 PCI_ERROR_SUBCLASS, pbm_err.pbm_pci.pci_err_class); 1829 ddi_fm_ereport_post(dip, buf, derr->fme_ena, 1830 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1831 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pci_cfg_stat, 1832 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, 1833 pbm_err.pbm_pci.pci_cfg_comm, PCI_PA, 1834 DATA_TYPE_UINT64, (uint64_t)0, NULL); 1835 } 1836 unknown++; 1837 } 1838 1839 /* Streaming Byte Hole Error */ 1840 if (pbm_ctl_stat & COMMON_PCI_CTRL_SBH_ERR) { 1841 if (pci_panic_on_sbh_errors) 1842 fatal++; 1843 else 1844 nonfatal++; 1845 pbm_err.pbm_err_class = PCI_PSY_SBH; 1846 pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 1847 } 1848 done: 1849 ret = ndi_fm_handler_dispatch(dip, NULL, derr); 1850 if (ret == DDI_FM_FATAL) { 1851 fatal++; 1852 } else if (ret == DDI_FM_NONFATAL) { 1853 nonfatal++; 1854 } else if (ret == DDI_FM_UNKNOWN) { 1855 unknown++; 1856 } 1857 1858 /* 1859 * rserr not claimed as nonfatal by a child is treated as fatal 1860 */ 1861 if (unknown && !nonfatal && !fatal) 1862 fatal++; 1863 1864 /* Cleanup and reset error bits */ 1865 pci_clear_error(pci_p, &pbm_err); 1866 1867 return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 1868 (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); 1869 } 1870 1871 int 1872 pci_check_error(pci_t *pci_p) 1873 { 1874 pbm_t *pbm_p = pci_p->pci_pbm_p; 1875 uint16_t pci_cfg_stat; 1876 uint64_t pbm_ctl_stat, pbm_afsr; 1877 1878 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1879 1880 pci_cfg_stat = pbm_p->pbm_config_header->ch_status_reg; 1881 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 1882 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 1883 1884 if ((pci_cfg_stat & (PCI_STAT_S_PERROR | PCI_STAT_S_TARG_AB | 1885 PCI_STAT_R_TARG_AB | PCI_STAT_R_MAST_AB | 1886 PCI_STAT_S_SYSERR | PCI_STAT_PERROR)) || 1887 (pbm_ctl_stat & (COMMON_PCI_CTRL_SBH_ERR | 1888 COMMON_PCI_CTRL_SERR)) || 1889 (PBM_AFSR_TO_PRIERR(pbm_afsr))) 1890 return (1); 1891 1892 return (0); 1893 1894 } 1895 1896 /* 1897 * Function used to gather PBM/PCI error state for the 1898 * pci_pbm_err_handler. This function must be called while pci_fm_mutex 1899 * is held. 1900 */ 1901 static void 1902 pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 1903 { 1904 pbm_t *pbm_p = pci_p->pci_pbm_p; 1905 1906 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1907 bzero(pbm_err_p, sizeof (pbm_errstate_t)); 1908 1909 /* 1910 * Capture all pbm error state for later logging 1911 */ 1912 pbm_err_p->pbm_bridge_type = PCI_BRIDGE_TYPE(pci_p->pci_common_p); 1913 pbm_err_p->pbm_pci.pci_cfg_stat = 1914 pbm_p->pbm_config_header->ch_status_reg; 1915 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 1916 pbm_err_p->pbm_pci.pci_cfg_comm = 1917 pbm_p->pbm_config_header->ch_command_reg; 1918 pbm_err_p->pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 1919 pbm_err_p->pbm_afar = *pbm_p->pbm_async_flt_addr_reg; 1920 pbm_err_p->pbm_pci.pci_pa = *pbm_p->pbm_async_flt_addr_reg; 1921 } 1922 1923 void 1924 pbm_clear_error(pbm_t *pbm_p) 1925 { 1926 uint64_t pbm_afsr, pbm_ctl_stat; 1927 1928 /* 1929 * for poke() support - called from POKE_FLUSH. Spin waiting 1930 * for MA, TA or SERR to be cleared by a pbm_error_intr(). 1931 * We have to wait for SERR too in case the device is beyond 1932 * a pci-pci bridge. 1933 */ 1934 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 1935 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 1936 while (((pbm_afsr >> PSYCHO_PCI_AFSR_PE_SHIFT) & 1937 (PSYCHO_PCI_AFSR_E_MA | PSYCHO_PCI_AFSR_E_TA)) || 1938 (pbm_ctl_stat & COMMON_PCI_CTRL_SERR)) { 1939 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 1940 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 1941 } 1942 } 1943 1944 /*ARGSUSED*/ 1945 void 1946 pci_format_addr(dev_info_t *dip, uint64_t *afar, uint64_t afsr) 1947 { 1948 /* 1949 * For Psycho the full address is stored in hardware. So 1950 * there is no need to format it. 1951 */ 1952 } 1953 1954 /*ARGSUSED*/ 1955 int 1956 pci_bus_quiesce(pci_t *pci_p, dev_info_t *dip, void *result) 1957 { 1958 return (DDI_FAILURE); 1959 } 1960 1961 /*ARGSUSED*/ 1962 int 1963 pci_bus_unquiesce(pci_t *pci_p, dev_info_t *dip, void *result) 1964 { 1965 return (DDI_FAILURE); 1966 } 1967 1968 int 1969 pci_reloc_getkey(void) 1970 { 1971 return (0x100); 1972 } 1973 1974 void 1975 pci_vmem_free(iommu_t *iommu_p, ddi_dma_impl_t *mp, void *dvma_addr, 1976 size_t npages) 1977 { 1978 pci_vmem_do_free(iommu_p, dvma_addr, npages, 1979 (mp->dmai_flags & DMAI_FLAGS_VMEMCACHE)); 1980 } 1981 1982 1983 /* 1984 * NOTE: This call is only used by legacy systems (eg. E250 and E450) that 1985 * require unregistering the pci driver's thermal intrerrupt handler before 1986 * they can register their own. 1987 */ 1988 void 1989 pci_thermal_rem_intr(dev_info_t *rdip, uint_t inum) 1990 { 1991 pci_t *pci_p; 1992 dev_info_t *pdip; 1993 uint32_t dev_mondo, pci_mondo; 1994 int instance; 1995 1996 for (pdip = ddi_get_parent(rdip); pdip; pdip = ddi_get_parent(pdip)) { 1997 if (strcmp(ddi_driver_name(pdip), "pcipsy") == 0) 1998 break; 1999 } 2000 2001 if (!pdip) { 2002 cmn_err(CE_WARN, "pci_thermal_rem_intr() no pcipsy parent\n"); 2003 return; 2004 } 2005 2006 instance = ddi_get_instance(pdip); 2007 pci_p = get_pci_soft_state(instance); 2008 2009 /* Calculate the requesting device's mondo */ 2010 dev_mondo = pci_xlate_intr(pci_p->pci_dip, rdip, pci_p->pci_ib_p, 2011 IB_MONDO_TO_INO(i_ddi_get_inum(rdip, inum))); 2012 2013 /* get pci's thermal mondo */ 2014 pci_mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 2015 pci_p->pci_inos[CBNINTR_THERMAL]); 2016 pci_mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, pci_mondo); 2017 2018 if (pci_mondo == dev_mondo) { 2019 DEBUG2(DBG_ATTACH, rdip, "pci_thermal_rem_intr unregistered " 2020 "for dip=%s%d:", ddi_driver_name(rdip), 2021 ddi_get_instance(rdip)); 2022 rem_ivintr(pci_mondo, NULL); 2023 } 2024 } 2025 2026 /* 2027 * pci_iommu_bypass_end_configure 2028 * 2029 * Support for 40-bit bus width to UPA in DVMA and iommu bypass transfers: 2030 */ 2031 2032 dma_bypass_addr_t 2033 pci_iommu_bypass_end_configure(void) 2034 { 2035 2036 return ((dma_bypass_addr_t)UPA_IOMMU_BYPASS_END); 2037 } 2038