1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI nexus utility routines: 30 * property and config routines for attach() 31 * reg/intr/range/assigned-address property routines for bus_map() 32 * init_child() 33 * fault handling 34 */ 35 36 #include <sys/types.h> 37 #include <sys/kmem.h> 38 #include <sys/async.h> 39 #include <sys/sysmacros.h> 40 #include <sys/sunddi.h> 41 #include <sys/sunndi.h> 42 #include <sys/fm/protocol.h> 43 #include <sys/fm/io/pci.h> 44 #include <sys/fm/util.h> 45 #include <sys/ddi_impldefs.h> 46 #include <sys/pci/pci_obj.h> 47 48 /*LINTLIBRARY*/ 49 50 /* 51 * get_pci_properties 52 * 53 * This function is called from the attach routine to get the key 54 * properties of the pci nodes. 55 * 56 * used by: pci_attach() 57 * 58 * return value: DDI_FAILURE on failure 59 */ 60 int 61 get_pci_properties(pci_t *pci_p, dev_info_t *dip) 62 { 63 int i; 64 65 /* 66 * Get the device's port id. 67 */ 68 if ((pci_p->pci_id = (uint32_t)pci_get_portid(dip)) == -1u) { 69 cmn_err(CE_WARN, "%s%d: no portid property\n", 70 ddi_driver_name(dip), ddi_get_instance(dip)); 71 return (DDI_FAILURE); 72 } 73 74 /* 75 * Get the bus-ranges property. 76 */ 77 i = sizeof (pci_p->pci_bus_range); 78 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 79 "bus-range", (caddr_t)&pci_p->pci_bus_range, &i) != DDI_SUCCESS) { 80 cmn_err(CE_WARN, "%s%d: no bus-range property\n", 81 ddi_driver_name(dip), ddi_get_instance(dip)); 82 return (DDI_FAILURE); 83 } 84 DEBUG2(DBG_ATTACH, dip, "get_pci_properties: bus-range (%x,%x)\n", 85 pci_p->pci_bus_range.lo, pci_p->pci_bus_range.hi); 86 87 /* 88 * disable streaming cache if necessary, this must be done 89 * before PBM is configured. 90 */ 91 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 92 "no-streaming-cache")) { 93 pci_stream_buf_enable = 0; 94 pci_stream_buf_exists = 0; 95 } 96 97 /* 98 * Get the ranges property. 99 */ 100 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 101 (caddr_t)&pci_p->pci_ranges, &pci_p->pci_ranges_length) != 102 DDI_SUCCESS) { 103 104 cmn_err(CE_WARN, "%s%d: no ranges property\n", 105 ddi_driver_name(dip), ddi_get_instance(dip)); 106 return (DDI_FAILURE); 107 } 108 pci_fix_ranges(pci_p->pci_ranges, 109 pci_p->pci_ranges_length / sizeof (pci_ranges_t)); 110 111 /* 112 * Determine the number upa slot interrupts. 113 */ 114 pci_p->pci_numproxy = pci_get_numproxy(pci_p->pci_dip); 115 DEBUG1(DBG_ATTACH, dip, "get_pci_properties: numproxy=%d\n", 116 pci_p->pci_numproxy); 117 118 pci_p->pci_thermal_interrupt = 119 ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 120 "thermal-interrupt", -1); 121 DEBUG1(DBG_ATTACH, dip, "get_pci_properties: thermal_interrupt=%d\n", 122 pci_p->pci_thermal_interrupt); 123 return (DDI_SUCCESS); 124 } 125 126 /* 127 * free_pci_properties: 128 * 129 * This routine frees the memory used to cache the 130 * "ranges" properties of the pci bus device node. 131 * 132 * used by: pci_detach() 133 * 134 * return value: none 135 */ 136 void 137 free_pci_properties(pci_t *pci_p) 138 { 139 kmem_free(pci_p->pci_ranges, pci_p->pci_ranges_length); 140 } 141 142 /* 143 * pci_reloc_reg 144 * 145 * If the "reg" entry (*pci_rp) is relocatable, lookup "assigned-addresses" 146 * property to fetch corresponding relocated address. 147 * 148 * used by: pci_map() 149 * 150 * return value: 151 * 152 * DDI_SUCCESS - on success 153 * DDI_ME_INVAL - regspec is invalid 154 */ 155 int 156 pci_reloc_reg(dev_info_t *dip, dev_info_t *rdip, pci_t *pci_p, 157 pci_regspec_t *rp) 158 { 159 int assign_len, assign_entries, i; 160 pci_regspec_t *assign_p; 161 register uint32_t phys_hi = rp->pci_phys_hi; 162 register uint32_t mask = PCI_REG_ADDR_M | PCI_CONF_ADDR_MASK; 163 register uint32_t phys_addr = phys_hi & mask; 164 165 DEBUG5(DBG_MAP | DBG_CONT, dip, "\tpci_reloc_reg fr: %x.%x.%x %x.%x\n", 166 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low, 167 rp->pci_size_hi, rp->pci_size_low); 168 169 if ((phys_hi & PCI_RELOCAT_B) || !(phys_hi & PCI_ADDR_MASK)) 170 return (DDI_SUCCESS); 171 172 /* phys_mid must be 0 regardless space type. */ 173 if (rp->pci_phys_mid != 0 || rp->pci_size_hi != 0) { 174 DEBUG0(DBG_MAP | DBG_CONT, pci_p->pci_dip, 175 "phys_mid or size_hi not 0\n"); 176 return (DDI_ME_INVAL); 177 } 178 179 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 180 "assigned-addresses", (caddr_t)&assign_p, &assign_len)) 181 return (DDI_ME_INVAL); 182 183 assign_entries = assign_len / sizeof (pci_regspec_t); 184 for (i = 0; i < assign_entries; i++, assign_p++) { 185 if ((assign_p->pci_phys_hi & mask) == phys_addr) { 186 rp->pci_phys_low += assign_p->pci_phys_low; 187 break; 188 } 189 } 190 kmem_free(assign_p - i, assign_len); 191 DEBUG5(DBG_MAP | DBG_CONT, dip, "\tpci_reloc_reg to: %x.%x.%x %x.%x\n", 192 rp->pci_phys_hi, rp->pci_phys_mid, rp->pci_phys_low, 193 rp->pci_size_hi, rp->pci_size_low); 194 return (i < assign_entries ? DDI_SUCCESS : DDI_ME_INVAL); 195 } 196 197 /* 198 * use "ranges" to translate relocated pci regspec into parent space 199 */ 200 int 201 pci_xlate_reg(pci_t *pci_p, pci_regspec_t *pci_rp, struct regspec *new_rp) 202 { 203 int n; 204 pci_ranges_t *rng_p = pci_p->pci_ranges; 205 int rng_n = pci_p->pci_ranges_length / sizeof (pci_ranges_t); 206 207 uint32_t space_type = PCI_REG_ADDR_G(pci_rp->pci_phys_hi); 208 uint32_t reg_end, reg_begin = pci_rp->pci_phys_low; 209 uint32_t sz = pci_rp->pci_size_low; 210 211 uint32_t rng_begin, rng_end; 212 213 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) { 214 if (reg_begin > PCI_CONF_HDR_SIZE) 215 return (DDI_ME_INVAL); 216 sz = sz ? MIN(sz, PCI_CONF_HDR_SIZE) : PCI_CONF_HDR_SIZE; 217 reg_begin += pci_rp->pci_phys_hi; 218 } 219 reg_end = reg_begin + sz - 1; 220 221 for (n = 0; n < rng_n; n++, rng_p++) { 222 if (space_type != PCI_REG_ADDR_G(rng_p->child_high)) 223 continue; /* not the same space type */ 224 225 rng_begin = rng_p->child_low; 226 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) 227 rng_begin += rng_p->child_high; 228 229 rng_end = rng_begin + rng_p->size_low - 1; 230 if (reg_begin >= rng_begin && reg_end <= rng_end) 231 break; 232 } 233 if (n >= rng_n) 234 return (DDI_ME_REGSPEC_RANGE); 235 236 new_rp->regspec_addr = reg_begin - rng_begin + rng_p->parent_low; 237 new_rp->regspec_bustype = rng_p->parent_high; 238 new_rp->regspec_size = sz; 239 DEBUG4(DBG_MAP | DBG_CONT, pci_p->pci_dip, 240 "\tpci_xlate_reg: entry %d new_rp %x.%x %x\n", 241 n, new_rp->regspec_bustype, new_rp->regspec_addr, sz); 242 243 return (DDI_SUCCESS); 244 } 245 246 247 /* 248 * report_dev 249 * 250 * This function is called from our control ops routine on a 251 * DDI_CTLOPS_REPORTDEV request. 252 * 253 * The display format is 254 * 255 * <name><inst> at <pname><pinst> device <dev> function <func> 256 * 257 * where 258 * 259 * <name> this device's name property 260 * <inst> this device's instance number 261 * <name> parent device's name property 262 * <inst> parent device's instance number 263 * <dev> this device's device number 264 * <func> this device's function number 265 */ 266 int 267 report_dev(dev_info_t *dip) 268 { 269 if (dip == (dev_info_t *)0) 270 return (DDI_FAILURE); 271 cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n", 272 ddi_node_name(dip), ddi_get_name_addr(dip), 273 ddi_driver_name(dip), 274 ddi_get_instance(dip)); 275 return (DDI_SUCCESS); 276 } 277 278 279 /* 280 * reg property for pcimem nodes that covers the entire address 281 * space for the node: config, io, or memory. 282 */ 283 pci_regspec_t pci_pcimem_reg[3] = 284 { 285 {PCI_ADDR_CONFIG, 0, 0, 0, 0x800000 }, 286 {(uint_t)(PCI_ADDR_IO|PCI_RELOCAT_B), 0, 0, 0, PCI_IO_SIZE }, 287 {(uint_t)(PCI_ADDR_MEM32|PCI_RELOCAT_B), 0, 0, 0, PCI_MEM_SIZE } 288 }; 289 290 /* 291 * name_child 292 * 293 * This function is called from init_child to name a node. It is 294 * also passed as a callback for node merging functions. 295 * 296 * return value: DDI_SUCCESS, DDI_FAILURE 297 */ 298 static int 299 name_child(dev_info_t *child, char *name, int namelen) 300 { 301 pci_regspec_t *pci_rp; 302 int reglen; 303 uint_t func; 304 char **unit_addr; 305 uint_t n; 306 307 /* 308 * Set the address portion of the node name based on 309 * unit-address property, if it exists. 310 * The interpretation of the unit-address is DD[,F] 311 * where DD is the device id and F is the function. 312 */ 313 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 314 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) == 315 DDI_PROP_SUCCESS) { 316 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 317 cmn_err(CE_WARN, "unit-address property in %s.conf" 318 " not well-formed", ddi_driver_name(child)); 319 ddi_prop_free(unit_addr); 320 return (DDI_FAILURE); 321 } 322 (void) snprintf(name, namelen, "%s", *unit_addr); 323 ddi_prop_free(unit_addr); 324 return (DDI_SUCCESS); 325 } 326 327 /* 328 * The unit-address property is does not exist. Set the address 329 * portion of the node name based on the function and device number. 330 */ 331 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 332 "reg", (int **)&pci_rp, (uint_t *)®len) == DDI_SUCCESS) { 333 if (((reglen * sizeof (int)) % sizeof (pci_regspec_t)) != 0) { 334 cmn_err(CE_WARN, "reg property not well-formed"); 335 return (DDI_FAILURE); 336 } 337 338 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 339 if (func != 0) 340 (void) snprintf(name, namelen, "%x,%x", 341 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi), func); 342 else 343 (void) snprintf(name, namelen, "%x", 344 PCI_REG_DEV_G(pci_rp[0].pci_phys_hi)); 345 ddi_prop_free(pci_rp); 346 return (DDI_SUCCESS); 347 } 348 349 cmn_err(CE_WARN, "cannot name pci child '%s'", ddi_node_name(child)); 350 return (DDI_FAILURE); 351 } 352 353 int 354 uninit_child(pci_t *pci_p, dev_info_t *child) 355 { 356 DEBUG2(DBG_CTLOPS, pci_p->pci_dip, 357 "DDI_CTLOPS_UNINITCHILD: arg=%s%d\n", 358 ddi_driver_name(child), ddi_get_instance(child)); 359 360 361 (void) pm_uninit_child(child); 362 363 ddi_set_name_addr(child, NULL); 364 ddi_remove_minor_node(child, NULL); 365 impl_rem_dev_props(child); 366 367 DEBUG0(DBG_PWR, ddi_get_parent(child), "\n\n"); 368 369 /* 370 * Handle chip specific post-uninit-child tasks. 371 */ 372 pci_post_uninit_child(pci_p); 373 374 return (DDI_SUCCESS); 375 } 376 377 /* 378 * init_child 379 * 380 * This function is called from our control ops routine on a 381 * DDI_CTLOPS_INITCHILD request. It builds and sets the device's 382 * parent private data area. 383 * 384 * used by: pci_ctlops() 385 * 386 * return value: none 387 */ 388 int 389 init_child(pci_t *pci_p, dev_info_t *child) 390 { 391 pci_regspec_t *pci_rp; 392 char name[10]; 393 ddi_acc_handle_t config_handle; 394 uint16_t command_preserve, command; 395 uint8_t bcr; 396 uint8_t header_type, min_gnt; 397 uint16_t latency_timer; 398 uint_t n; 399 int i, no_config; 400 401 /* 402 * The following is a special case for pcimem nodes. 403 * For these nodes we create a reg property with a 404 * single entry that covers the entire address space 405 * for the node (config, io or memory). 406 */ 407 if (strcmp(ddi_driver_name(child), "pcimem") == 0) { 408 (void) ddi_prop_create(DDI_DEV_T_NONE, child, 409 DDI_PROP_CANSLEEP, "reg", (caddr_t)pci_pcimem_reg, 410 sizeof (pci_pcimem_reg)); 411 ddi_set_name_addr(child, "0"); 412 ddi_set_parent_data(child, NULL); 413 return (DDI_SUCCESS); 414 } 415 416 /* 417 * Check whether the node has config space or is a hard decode 418 * node (possibly created by a driver.conf file). 419 */ 420 no_config = ddi_prop_get_int(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 421 "no-config", 0); 422 423 /* 424 * Pseudo nodes indicate a prototype node with per-instance 425 * properties to be merged into the real h/w device node. 426 * However, do not merge if the no-config property is set 427 * (see PSARC 2000/088). 428 */ 429 if ((ndi_dev_is_persistent_node(child) == 0) && (no_config == 0)) { 430 extern int pci_allow_pseudo_children; 431 432 if (ddi_getlongprop(DDI_DEV_T_ANY, child, 433 DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp, &i) == 434 DDI_SUCCESS) { 435 cmn_err(CE_WARN, "cannot merge prototype from %s.conf", 436 ddi_driver_name(child)); 437 kmem_free(pci_rp, i); 438 return (DDI_NOT_WELL_FORMED); 439 } 440 /* 441 * Name the child 442 */ 443 if (name_child(child, name, 10) != DDI_SUCCESS) 444 return (DDI_FAILURE); 445 446 ddi_set_name_addr(child, name); 447 ddi_set_parent_data(child, NULL); 448 449 /* 450 * Try to merge the properties from this prototype 451 * node into real h/w nodes. 452 */ 453 if (ndi_merge_node(child, name_child) == DDI_SUCCESS) { 454 /* 455 * Merged ok - return failure to remove the node. 456 */ 457 ddi_set_name_addr(child, NULL); 458 return (DDI_FAILURE); 459 } 460 461 /* workaround for ddivs to run under PCI */ 462 if (pci_allow_pseudo_children) 463 return (DDI_SUCCESS); 464 465 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 466 ddi_driver_name(child), ddi_get_name_addr(child), 467 ddi_driver_name(child)); 468 ddi_set_name_addr(child, NULL); 469 return (DDI_NOT_WELL_FORMED); 470 } 471 472 if (name_child(child, name, 10) != DDI_SUCCESS) 473 return (DDI_FAILURE); 474 ddi_set_name_addr(child, name); 475 476 if (no_config != 0) { 477 /* 478 * There is no config space so there's nothing more to do. 479 */ 480 return (DDI_SUCCESS); 481 } 482 483 if (pm_init_child(child) != DDI_SUCCESS) 484 return (DDI_FAILURE); 485 486 487 /* 488 * If configuration registers were previously saved by 489 * child (before it went to D3), then let the child do the 490 * restore to set up the config regs as it'll first need to 491 * power the device out of D3. 492 */ 493 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 494 "config-regs-saved-by-child") == 1) { 495 DEBUG0(DBG_PWR, child, 496 "INITCHILD: config regs to be restored by child\n"); 497 498 return (DDI_SUCCESS); 499 } 500 501 DEBUG2(DBG_PWR, ddi_get_parent(child), 502 "INITCHILD: config regs setup for %s@%s\n", 503 ddi_node_name(child), ddi_get_name_addr(child)); 504 505 /* 506 * Map the child configuration space to for initialization. 507 * We assume the obp will do the following in the devices 508 * config space: 509 * 510 * Set the latency-timer register to values appropriate 511 * for the devices on the bus (based on other devices 512 * MIN_GNT and MAX_LAT registers. 513 * 514 * Set the fast back-to-back enable bit in the command 515 * register if it's supported and all devices on the bus 516 * have the capability. 517 * 518 */ 519 if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) { 520 (void) pm_uninit_child(child); 521 ddi_set_name_addr(child, NULL); 522 523 return (DDI_FAILURE); 524 } 525 526 /* 527 * Determine the configuration header type. 528 */ 529 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 530 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: header_type=%x\n", 531 ddi_driver_name(child), header_type); 532 533 /* 534 * Support for "command-preserve" property. Note that we 535 * add PCI_COMM_BACK2BACK_ENAB to the bits to be preserved 536 * since the obp will set this if the device supports and 537 * all targets on the same bus support it. Since psycho 538 * doesn't support PCI_COMM_BACK2BACK_ENAB, it will never 539 * be set. This is just here in case future revs do support 540 * PCI_COMM_BACK2BACK_ENAB. 541 */ 542 command_preserve = 543 ddi_prop_get_int(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 544 "command-preserve", 0); 545 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: command-preserve=%x\n", 546 ddi_driver_name(child), command_preserve); 547 command = pci_config_get16(config_handle, PCI_CONF_COMM); 548 command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB); 549 command |= (pci_command_default & ~command_preserve); 550 pci_config_put16(config_handle, PCI_CONF_COMM, command); 551 command = pci_config_get16(config_handle, PCI_CONF_COMM); 552 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: command=%x\n", 553 ddi_driver_name(child), 554 pci_config_get16(config_handle, PCI_CONF_COMM)); 555 556 /* 557 * If the device has a bus control register then program it 558 * based on the settings in the command register. 559 */ 560 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 561 bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL); 562 if (pci_command_default & PCI_COMM_PARITY_DETECT) 563 bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 564 if (pci_command_default & PCI_COMM_SERR_ENABLE) 565 bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE; 566 bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE; 567 pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr); 568 } 569 570 /* 571 * Initialize cache-line-size configuration register if needed. 572 */ 573 if (pci_set_cache_line_size_register && 574 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 575 "cache-line-size", 0) == 0) { 576 577 pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ, 578 PCI_CACHE_LINE_SIZE); 579 n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 580 if (n != 0) 581 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 582 "cache-line-size", n); 583 } 584 585 /* 586 * Initialize latency timer registers if needed. 587 */ 588 if (pci_set_latency_timer_register && 589 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 590 "latency-timer", 0) == 0) { 591 592 latency_timer = pci_latency_timer; 593 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 594 pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER, 595 latency_timer); 596 } else { 597 min_gnt = pci_config_get8(config_handle, 598 PCI_CONF_MIN_G); 599 DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: min_gnt=%x\n", 600 ddi_driver_name(child), min_gnt); 601 if (min_gnt != 0) { 602 switch (pci_p->pci_pbm_p->pbm_speed) { 603 case PBM_SPEED_33MHZ: 604 latency_timer = min_gnt * 8; 605 break; 606 case PBM_SPEED_66MHZ: 607 latency_timer = min_gnt * 4; 608 break; 609 } 610 } 611 } 612 latency_timer = MIN(latency_timer, 0xff); 613 pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER, 614 latency_timer); 615 n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 616 if (n != 0) 617 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 618 "latency-timer", n); 619 } 620 621 pci_config_teardown(&config_handle); 622 623 /* 624 * Handle chip specific init-child tasks. 625 */ 626 pci_post_init_child(pci_p, child); 627 628 return (DDI_SUCCESS); 629 } 630 631 /* 632 * get_nreg_set 633 * 634 * Given a dev info pointer to a pci child, this routine returns the 635 * number of sets in its "reg" property. 636 * 637 * used by: pci_ctlops() - DDI_CTLOPS_NREGS 638 * 639 * return value: # of reg sets on success, zero on error 640 */ 641 uint_t 642 get_nreg_set(dev_info_t *child) 643 { 644 pci_regspec_t *pci_rp; 645 int i, n; 646 647 /* 648 * Get the reg property for the device. 649 */ 650 if (ddi_getlongprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, "reg", 651 (caddr_t)&pci_rp, &i) != DDI_SUCCESS) 652 return (0); 653 654 n = i / (int)sizeof (pci_regspec_t); 655 kmem_free(pci_rp, i); 656 return (n); 657 } 658 659 660 /* 661 * get_nintr 662 * 663 * Given a dev info pointer to a pci child, this routine returns the 664 * number of items in its "interrupts" property. 665 * 666 * used by: pci_ctlops() - DDI_CTLOPS_NREGS 667 * 668 * return value: # of interrupts on success, zero on error 669 */ 670 uint_t 671 get_nintr(dev_info_t *child) 672 { 673 int *pci_ip; 674 int i, n; 675 676 if (ddi_getlongprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 677 "interrupts", (caddr_t)&pci_ip, &i) != DDI_SUCCESS) 678 return (0); 679 680 n = i / (int)sizeof (uint_t); 681 kmem_free(pci_ip, i); 682 return (n); 683 } 684 685 uint64_t 686 pci_get_cfg_pabase(pci_t *pci_p) 687 { 688 int i; 689 pci_ranges_t *rangep = pci_p->pci_ranges; 690 int nrange = pci_p->pci_ranges_length / sizeof (pci_ranges_t); 691 uint32_t cfg_space_type = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 692 693 ASSERT(cfg_space_type == 0); 694 695 for (i = 0; i < nrange; i++, rangep++) { 696 if (PCI_REG_ADDR_G(rangep->child_high) == cfg_space_type) 697 break; 698 } 699 700 if (i >= nrange) 701 cmn_err(CE_PANIC, "no cfg space in pci(%p) ranges prop.\n", 702 (void *)pci_p); 703 704 return (((uint64_t)rangep->parent_high << 32) | rangep->parent_low); 705 } 706 707 int 708 pci_cfg_report(dev_info_t *dip, ddi_fm_error_t *derr, pci_errstate_t *pci_err_p, 709 int caller, uint32_t prierr) 710 { 711 int fatal = 0; 712 int nonfatal = 0; 713 int i; 714 715 ASSERT(dip); 716 717 derr->fme_ena = derr->fme_ena ? derr->fme_ena : 718 fm_ena_generate(0, FM_ENA_FMT1); 719 720 for (i = 0; pci_err_tbl[i].err_class != NULL; i++) { 721 if (pci_err_p->pci_cfg_stat & pci_err_tbl[i].reg_bit) { 722 char buf[FM_MAX_CLASS]; 723 724 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 725 PCI_ERROR_SUBCLASS, 726 pci_err_tbl[i].err_class); 727 ddi_fm_ereport_post(dip, buf, derr->fme_ena, 728 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 729 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 730 pci_err_p->pci_cfg_stat, 731 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, 732 pci_err_p->pci_cfg_comm, 733 PCI_PA, DATA_TYPE_UINT64, 734 pci_err_p->pci_pa, 735 NULL); 736 737 switch (pci_err_tbl[i].reg_bit) { 738 case PCI_STAT_S_SYSERR: 739 /* 740 * address parity error on dma - treat as fatal 741 */ 742 fatal++; 743 break; 744 case PCI_STAT_R_MAST_AB: 745 case PCI_STAT_R_TARG_AB: 746 case PCI_STAT_S_PERROR: 747 if (prierr) { 748 /* 749 * piow case are already handled in 750 * pbm_afsr_report() 751 */ 752 break; 753 } 754 if (caller != PCI_TRAP_CALL) { 755 /* 756 * if we haven't come from trap handler 757 * we won't have an address 758 */ 759 fatal++; 760 break; 761 } 762 763 /* 764 * queue target ereport - use return from 765 * pci_lookup_handle() to determine if sync 766 * or async 767 */ 768 nonfatal++; 769 pci_target_enqueue(derr->fme_ena, 770 pci_err_tbl[i].terr_class, 771 PCI_ERROR_SUBCLASS, 772 (uint64_t)derr->fme_bus_specific); 773 break; 774 default: 775 /* 776 * dpe on dma write or ta on dma 777 */ 778 nonfatal++; 779 break; 780 } 781 } 782 } 783 784 if (fatal) 785 return (DDI_FM_FATAL); 786 else if (nonfatal) 787 return (DDI_FM_NONFATAL); 788 789 return (DDI_FM_OK); 790 } 791 792 void 793 pci_child_cfg_save(dev_info_t *dip) 794 { 795 dev_info_t *cdip; 796 int ret = DDI_SUCCESS; 797 798 /* 799 * Save the state of the configuration headers of child 800 * nodes. 801 */ 802 803 for (cdip = ddi_get_child(dip); cdip != NULL; 804 cdip = ddi_get_next_sibling(cdip)) { 805 806 /* 807 * Not interested in children who are not already 808 * init'ed. They will be set up in init_child(). 809 */ 810 if (i_ddi_node_state(cdip) < DS_INITIALIZED) { 811 DEBUG2(DBG_DETACH, dip, "DDI_SUSPEND: skipping " 812 "%s%d not in CF1\n", ddi_driver_name(cdip), 813 ddi_get_instance(cdip)); 814 815 continue; 816 } 817 818 /* 819 * Only save config registers if not already saved by child. 820 */ 821 if (ddi_prop_exists(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 822 SAVED_CONFIG_REGS) == 1) { 823 824 continue; 825 } 826 827 /* 828 * The nexus needs to save config registers. Create a property 829 * so it knows to restore on resume. 830 */ 831 ret = ndi_prop_create_boolean(DDI_DEV_T_NONE, cdip, 832 "nexus-saved-config-regs"); 833 834 if (ret != DDI_PROP_SUCCESS) { 835 cmn_err(CE_WARN, "%s%d can't update prop %s", 836 ddi_driver_name(cdip), ddi_get_instance(cdip), 837 "nexus-saved-config-regs"); 838 } 839 840 (void) pci_save_config_regs(cdip); 841 } 842 } 843 844 void 845 pci_child_cfg_restore(dev_info_t *dip) 846 { 847 dev_info_t *cdip; 848 849 /* 850 * Restore config registers for children that did not save 851 * their own registers. Children pwr states are UNKNOWN after 852 * a resume since it is possible for the PM framework to call 853 * resume without an actual power cycle. (ie if suspend fails). 854 */ 855 for (cdip = ddi_get_child(dip); cdip != NULL; 856 cdip = ddi_get_next_sibling(cdip)) { 857 858 /* 859 * Not interested in children who are not already 860 * init'ed. They will be set up by init_child(). 861 */ 862 if (i_ddi_node_state(cdip) < DS_INITIALIZED) { 863 DEBUG2(DBG_DETACH, dip, 864 "DDI_RESUME: skipping %s%d not in CF1\n", 865 ddi_driver_name(cdip), ddi_get_instance(cdip)); 866 continue; 867 } 868 869 /* 870 * Only restore config registers if saved by nexus. 871 */ 872 if (ddi_prop_exists(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 873 "nexus-saved-config-regs") == 1) { 874 (void) pci_restore_config_regs(cdip); 875 876 DEBUG2(DBG_PWR, dip, 877 "DDI_RESUME: nexus restoring %s%d config regs\n", 878 ddi_driver_name(cdip), ddi_get_instance(cdip)); 879 880 if (ndi_prop_remove(DDI_DEV_T_NONE, cdip, 881 "nexus-saved-config-regs") != DDI_PROP_SUCCESS) { 882 cmn_err(CE_WARN, "%s%d can't remove prop %s", 883 ddi_driver_name(cdip), 884 ddi_get_instance(cdip), 885 "nexus-saved-config-regs"); 886 } 887 } 888 } 889 } 890