1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Sun4u PCI to PCI bus bridge nexus driver 31 */ 32 33 #include <sys/conf.h> 34 #include <sys/kmem.h> 35 #include <sys/debug.h> 36 #include <sys/modctl.h> 37 #include <sys/autoconf.h> 38 #include <sys/ddi_impldefs.h> 39 #include <sys/ddi_subrdefs.h> 40 #include <sys/pci.h> 41 #include <sys/pci/pci_nexus.h> 42 #include <sys/pci/pci_regs.h> 43 #include <sys/ddi.h> 44 #include <sys/sunndi.h> 45 #include <sys/sunddi.h> 46 #include <sys/fm/protocol.h> 47 #include <sys/ddifm.h> 48 #include <sys/pci/pci_pwr.h> 49 #include <sys/pci/pci_debug.h> 50 #include <sys/hotplug/pci/pcihp.h> 51 #include <sys/open.h> 52 #include <sys/stat.h> 53 #include <sys/file.h> 54 55 #define NUM_LOGICAL_SLOTS 32 56 57 #define PPB_RANGE_LEN 2 58 59 #define PPB_32BIT_IO 1 60 #define PPB_32bit_MEM 1 61 62 #define PPB_MEMGRAIN 0x100000 63 #define PPB_IOGRAIN 0x1000 64 65 #define PPB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8)) 66 #define PPB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo)) 67 #define PPB_32bit_MEMADDR(addr) (PPB_LADDR(0, ((uint16_t)(addr) & 0xFFF0))) 68 69 typedef struct slot_table { 70 uchar_t bus_id[128]; 71 uchar_t slot_name[32]; 72 uint8_t device_no; 73 uint8_t phys_slot_num; 74 } slot_table_t; 75 76 /* 77 * The following typedef is used to represent an entry in the "ranges" 78 * property of a device node. 79 */ 80 typedef struct { 81 uint32_t child_high; 82 uint32_t child_mid; 83 uint32_t child_low; 84 uint32_t parent_high; 85 uint32_t parent_mid; 86 uint32_t parent_low; 87 uint32_t size_high; 88 uint32_t size_low; 89 } ppb_ranges_t; 90 91 /* 92 * The variable controls the default setting of the command register 93 * for pci devices. See ppb_initchild() for details. 94 */ 95 static ushort_t ppb_command_default = PCI_COMM_SERR_ENABLE | 96 PCI_COMM_WAIT_CYC_ENAB | 97 PCI_COMM_PARITY_DETECT | 98 PCI_COMM_ME | 99 PCI_COMM_MAE | 100 PCI_COMM_IO; 101 102 static int ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, 103 off_t, off_t, caddr_t *); 104 static int ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, 105 void *, void *); 106 static int ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, 107 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 108 109 /* 110 * fm_init busop to initialize our children 111 */ 112 static int ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 113 ddi_iblock_cookie_t *ibc); 114 static void ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle); 115 static void ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle); 116 static int ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, 117 void *arg, void *result); 118 119 struct bus_ops ppb_bus_ops = { 120 BUSO_REV, 121 ppb_bus_map, 122 0, 123 0, 124 0, 125 i_ddi_map_fault, 126 ddi_dma_map, 127 ddi_dma_allochdl, 128 ddi_dma_freehdl, 129 ddi_dma_bindhdl, 130 ddi_dma_unbindhdl, 131 ddi_dma_flush, 132 ddi_dma_win, 133 ddi_dma_mctl, 134 ppb_ctlops, 135 ddi_bus_prop_op, 136 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 137 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 138 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 139 ndi_post_event, /* (*bus_post_event)(); */ 140 0, /* (*bus_intr_ctl)(); */ 141 0, /* (*bus_config)(); */ 142 0, /* (*bus_unconfig)(); */ 143 ppb_fm_init_child, /* (*bus_fm_init)(); */ 144 NULL, /* (*bus_fm_fini)(); */ 145 ppb_bus_enter, /* (*bus_enter)() */ 146 ppb_bus_exit, /* (*bus_exit)() */ 147 ppb_bus_power, /* (*bus_power)() */ 148 ppb_intr_ops /* (*bus_intr_op)(); */ 149 }; 150 151 static int ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp); 152 static int ppb_close(dev_t dev, int flags, int otyp, cred_t *credp); 153 static int ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, 154 cred_t *credp, int *rvalp); 155 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 156 int flags, char *name, caddr_t valuep, int *lengthp); 157 158 static struct cb_ops ppb_cb_ops = { 159 ppb_open, /* open */ 160 ppb_close, /* close */ 161 nulldev, /* strategy */ 162 nulldev, /* print */ 163 nulldev, /* dump */ 164 nulldev, /* read */ 165 nulldev, /* write */ 166 ppb_ioctl, /* ioctl */ 167 nodev, /* devmap */ 168 nodev, /* mmap */ 169 nodev, /* segmap */ 170 nochpoll, /* poll */ 171 ppb_prop_op, /* cb_prop_op */ 172 NULL, /* streamtab */ 173 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 174 CB_REV, /* rev */ 175 nodev, /* int (*cb_aread)() */ 176 nodev /* int (*cb_awrite)() */ 177 }; 178 179 static int ppb_probe(dev_info_t *); 180 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 181 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 182 static int ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 183 void *arg, void **result); 184 static int ppb_pwr(dev_info_t *dip, int component, int level); 185 186 struct dev_ops ppb_ops = { 187 DEVO_REV, /* devo_rev */ 188 0, /* refcnt */ 189 ppb_info, /* info */ 190 nulldev, /* identify */ 191 ppb_probe, /* probe */ 192 ppb_attach, /* attach */ 193 ppb_detach, /* detach */ 194 nulldev, /* reset */ 195 &ppb_cb_ops, /* driver operations */ 196 &ppb_bus_ops, /* bus operations */ 197 ppb_pwr 198 }; 199 200 /* 201 * Module linkage information for the kernel. 202 */ 203 204 static struct modldrv modldrv = { 205 &mod_driverops, /* Type of module */ 206 "Standard PCI to PCI bridge nexus driver %I%", 207 &ppb_ops, /* driver ops */ 208 }; 209 210 static struct modlinkage modlinkage = { 211 MODREV_1, 212 (void *)&modldrv, 213 NULL 214 }; 215 216 /* 217 * soft state pointer and structure template: 218 */ 219 static void *ppb_state; 220 221 static struct ppb_cfg_state { 222 dev_info_t *dip; 223 ushort_t command; 224 uchar_t cache_line_size; 225 uchar_t latency_timer; 226 uchar_t header_type; 227 uchar_t sec_latency_timer; 228 ushort_t bridge_control; 229 }; 230 231 typedef struct { 232 233 dev_info_t *dip; 234 235 /* 236 * configuration register state for the bus: 237 */ 238 uchar_t ppb_cache_line_size; 239 uchar_t ppb_latency_timer; 240 241 /* 242 * PM support 243 */ 244 ddi_acc_handle_t ppb_conf_hdl; 245 uint8_t ppb_pmcsr_offset; 246 pci_pwr_t *ppb_pwr_p; 247 248 /* 249 * HP support 250 */ 251 boolean_t hotplug_capable; 252 253 kmutex_t ppb_mutex; 254 uint_t ppb_soft_state; 255 #define PPB_SOFT_STATE_CLOSED 0x00 256 #define PPB_SOFT_STATE_OPEN 0x01 257 #define PPB_SOFT_STATE_OPEN_EXCL 0x02 258 int fm_cap; 259 ddi_iblock_cookie_t fm_ibc; 260 } ppb_devstate_t; 261 262 /* 263 * The following variable enables a workaround for the following obp bug: 264 * 265 * 1234181 - obp should set latency timer registers in pci 266 * configuration header 267 * 268 * Until this bug gets fixed in the obp, the following workaround should 269 * be enabled. 270 */ 271 static uint_t ppb_set_latency_timer_register = 1; 272 273 /* 274 * The following variable enables a workaround for an obp bug to be 275 * submitted. A bug requesting a workaround fof this problem has 276 * been filed: 277 * 278 * 1235094 - need workarounds on positron nexus drivers to set cache 279 * line size registers 280 * 281 * Until this bug gets fixed in the obp, the following workaround should 282 * be enabled. 283 */ 284 static uint_t ppb_set_cache_line_size_register = 1; 285 286 /* 287 * forward function declarations: 288 */ 289 290 /* 291 * FMA error callback 292 * Register error handling callback with our parent. We will just call 293 * our children's error callbacks and return their status. 294 */ 295 static int ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, 296 const void *impl_data); 297 298 /* 299 * init/fini routines to alloc/dealloc fm structures and 300 * register/unregister our callback. 301 */ 302 static void ppb_fm_init(ppb_devstate_t *ppb_p); 303 static void ppb_fm_fini(ppb_devstate_t *ppb_p); 304 305 static void ppb_removechild(dev_info_t *); 306 static int ppb_initchild(dev_info_t *child); 307 static dev_info_t *get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 308 static void ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *dip); 309 static void ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip); 310 static void ppb_init_hotplug(ppb_devstate_t *ppb); 311 static void ppb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t); 312 extern uint64_t pci_debug_flags = 0; 313 314 int 315 _init(void) 316 { 317 int e; 318 if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t), 319 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 320 ddi_soft_state_fini(&ppb_state); 321 return (e); 322 } 323 324 int 325 _fini(void) 326 { 327 int e; 328 329 if ((e = mod_remove(&modlinkage)) == 0) 330 ddi_soft_state_fini(&ppb_state); 331 return (e); 332 } 333 334 int 335 _info(struct modinfo *modinfop) 336 { 337 return (mod_info(&modlinkage, modinfop)); 338 } 339 340 /*ARGSUSED*/ 341 static int 342 ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 343 { 344 ppb_devstate_t *ppb_p; /* per ppb state pointer */ 345 minor_t minor = getminor((dev_t)arg); 346 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 347 348 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 349 instance); 350 351 switch (infocmd) { 352 default: 353 return (DDI_FAILURE); 354 355 case DDI_INFO_DEVT2INSTANCE: 356 *result = (void *)instance; 357 return (DDI_SUCCESS); 358 359 case DDI_INFO_DEVT2DEVINFO: 360 if (ppb_p == NULL) 361 return (DDI_FAILURE); 362 *result = (void *)ppb_p->dip; 363 return (DDI_SUCCESS); 364 } 365 } 366 367 /*ARGSUSED*/ 368 static int 369 ppb_probe(register dev_info_t *devi) 370 { 371 return (DDI_PROBE_SUCCESS); 372 } 373 374 /*ARGSUSED*/ 375 static int 376 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 377 { 378 int instance; 379 ppb_devstate_t *ppb; 380 ddi_acc_handle_t config_handle; 381 382 switch (cmd) { 383 case DDI_ATTACH: 384 385 /* 386 * Make sure the "device_type" property exists. 387 */ 388 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 389 "device_type", "pci"); 390 391 /* 392 * Allocate and get soft state structure. 393 */ 394 instance = ddi_get_instance(devi); 395 if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS) 396 return (DDI_FAILURE); 397 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, instance); 398 ppb->dip = devi; 399 mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL); 400 ppb->ppb_soft_state = PPB_SOFT_STATE_CLOSED; 401 if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) { 402 mutex_destroy(&ppb->ppb_mutex); 403 ddi_soft_state_free(ppb_state, instance); 404 return (DDI_FAILURE); 405 } 406 ppb_pwr_setup(ppb, devi); 407 408 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 409 mutex_enter(&ppb->ppb_pwr_p->pwr_mutex); 410 411 /* 412 * Before reading config registers, make sure power is 413 * on, and remains on. 414 */ 415 ppb->ppb_pwr_p->pwr_fp++; 416 417 pci_pwr_change(ppb->ppb_pwr_p, 418 ppb->ppb_pwr_p->current_lvl, 419 pci_pwr_new_lvl(ppb->ppb_pwr_p)); 420 } 421 422 ppb->ppb_cache_line_size = 423 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 424 ppb->ppb_latency_timer = 425 pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 426 427 /* 428 * Check whether the "ranges" property is present. 429 * Otherwise create the ranges property by reading 430 * the configuration registers 431 */ 432 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS, 433 "ranges") == 0) { 434 ppb_create_ranges_prop(devi, config_handle); 435 } 436 437 pci_config_teardown(&config_handle); 438 439 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 440 ppb->ppb_pwr_p->pwr_fp--; 441 442 pci_pwr_change(ppb->ppb_pwr_p, 443 ppb->ppb_pwr_p->current_lvl, 444 pci_pwr_new_lvl(ppb->ppb_pwr_p)); 445 446 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 447 } 448 449 /* 450 * Initialize hotplug support on this bus. At minimum 451 * (for non hotplug bus) this would create ":devctl" minor 452 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls 453 * to this bus. This all takes place if this nexus has hot-plug 454 * slots and successfully initializes Hot Plug Framework. 455 */ 456 ppb->hotplug_capable = B_FALSE; 457 ppb_init_hotplug(ppb); 458 if (ppb->hotplug_capable == B_FALSE) { 459 /* 460 * create minor node for devctl interfaces 461 */ 462 if (ddi_create_minor_node(devi, "devctl", S_IFCHR, 463 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 464 DDI_NT_NEXUS, 0) != DDI_SUCCESS) { 465 if (ppb->ppb_pwr_p != NULL) { 466 ppb_pwr_teardown(ppb, devi); 467 } 468 mutex_destroy(&ppb->ppb_mutex); 469 ddi_soft_state_free(ppb_state, instance); 470 return (DDI_FAILURE); 471 } 472 } 473 474 DEBUG1(DBG_ATTACH, devi, 475 "ppb_attach(): this nexus %s hotplug slots\n", 476 ppb->hotplug_capable == B_TRUE ? "has":"has no"); 477 478 ppb_fm_init(ppb); 479 ddi_report_dev(devi); 480 481 return (DDI_SUCCESS); 482 483 case DDI_RESUME: 484 /* 485 * Get the soft state structure for the bridge. 486 */ 487 ppb = (ppb_devstate_t *) 488 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 489 490 pci_pwr_resume(devi, ppb->ppb_pwr_p); 491 492 return (DDI_SUCCESS); 493 } 494 return (DDI_FAILURE); 495 } 496 497 /*ARGSUSED*/ 498 static int 499 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 500 { 501 ppb_devstate_t *ppb; 502 503 switch (cmd) { 504 case DDI_DETACH: 505 /* 506 * And finally free the per-pci soft state after 507 * uninitializing hotplug support for this bus. 508 */ 509 ppb = (ppb_devstate_t *) 510 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 511 512 ppb_fm_fini(ppb); 513 514 if (ppb->hotplug_capable == B_TRUE) 515 if (pcihp_uninit(devi) == DDI_FAILURE) 516 return (DDI_FAILURE); 517 else 518 ddi_remove_minor_node(devi, "devctl"); 519 520 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 521 522 if (ppb->ppb_pwr_p != NULL) { 523 ppb_pwr_teardown(ppb, devi); 524 } 525 mutex_destroy(&ppb->ppb_mutex); 526 ddi_soft_state_free(ppb_state, ddi_get_instance(devi)); 527 528 return (DDI_SUCCESS); 529 530 case DDI_SUSPEND: 531 ppb = (ppb_devstate_t *) 532 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 533 534 pci_pwr_suspend(devi, ppb->ppb_pwr_p); 535 536 return (DDI_SUCCESS); 537 } 538 return (DDI_FAILURE); 539 } 540 541 /*ARGSUSED*/ 542 static int 543 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 544 off_t offset, off_t len, caddr_t *vaddrp) 545 { 546 register dev_info_t *pdip; 547 548 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 549 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map) 550 (pdip, rdip, mp, offset, len, vaddrp)); 551 } 552 553 /*ARGSUSED*/ 554 static int 555 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip, 556 ddi_ctl_enum_t ctlop, void *arg, void *result) 557 { 558 pci_regspec_t *drv_regp; 559 int reglen; 560 int rn; 561 562 int totreg; 563 564 switch (ctlop) { 565 case DDI_CTLOPS_REPORTDEV: 566 if (rdip == (dev_info_t *)0) 567 return (DDI_FAILURE); 568 cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n", 569 ddi_node_name(rdip), ddi_get_name_addr(rdip), 570 ddi_driver_name(rdip), 571 ddi_get_instance(rdip)); 572 return (DDI_SUCCESS); 573 574 case DDI_CTLOPS_INITCHILD: 575 return (ppb_initchild((dev_info_t *)arg)); 576 577 case DDI_CTLOPS_UNINITCHILD: 578 ppb_removechild((dev_info_t *)arg); 579 return (DDI_SUCCESS); 580 581 case DDI_CTLOPS_SIDDEV: 582 return (DDI_SUCCESS); 583 584 case DDI_CTLOPS_REGSIZE: 585 case DDI_CTLOPS_NREGS: 586 if (rdip == (dev_info_t *)0) 587 return (DDI_FAILURE); 588 break; 589 default: 590 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 591 } 592 593 *(int *)result = 0; 594 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 595 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", 596 (caddr_t)&drv_regp, ®len) != DDI_SUCCESS) 597 return (DDI_FAILURE); 598 599 totreg = reglen / sizeof (pci_regspec_t); 600 if (ctlop == DDI_CTLOPS_NREGS) 601 *(int *)result = totreg; 602 else if (ctlop == DDI_CTLOPS_REGSIZE) { 603 rn = *(int *)arg; 604 if (rn >= totreg) { 605 kmem_free(drv_regp, reglen); 606 return (DDI_FAILURE); 607 } 608 *(off_t *)result = drv_regp[rn].pci_size_low | 609 ((uint64_t)drv_regp[rn].pci_size_hi << 32); 610 } 611 612 kmem_free(drv_regp, reglen); 613 return (DDI_SUCCESS); 614 } 615 616 617 static dev_info_t * 618 get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 619 { 620 dev_info_t *cdip = rdip; 621 622 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 623 ; 624 625 return (cdip); 626 } 627 628 629 static int 630 ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 631 ddi_intr_handle_impl_t *hdlp, void *result) 632 { 633 ddi_ispec_t *ip = (ddi_ispec_t *)hdlp->ih_private; 634 dev_info_t *cdip = rdip; 635 pci_regspec_t *pci_rp; 636 int reglen, len; 637 uint32_t d, intr; 638 639 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 640 goto done; 641 642 /* 643 * If the interrupt-map property is defined at this 644 * node, it will have performed the interrupt 645 * translation as part of the property, so no 646 * rotation needs to be done. 647 */ 648 if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 649 "interrupt-map", &len) == DDI_PROP_SUCCESS) 650 goto done; 651 652 cdip = get_my_childs_dip(dip, rdip); 653 654 /* 655 * Use the devices reg property to determine its 656 * PCI bus number and device number. 657 */ 658 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 659 "reg", (caddr_t)&pci_rp, ®len) != DDI_SUCCESS) 660 return (DDI_FAILURE); 661 662 intr = *ip->is_intr; 663 664 /* Spin the interrupt */ 665 d = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 666 667 if ((intr >= PCI_INTA) && (intr <= PCI_INTD)) 668 *ip->is_intr = ((intr - 1 + (d % 4)) % 4 + 1); 669 else 670 cmn_err(CE_WARN, "%s%d: %s: PCI intr=%x out of range", 671 ddi_driver_name(rdip), ddi_get_instance(rdip), 672 ddi_driver_name(dip), intr); 673 674 kmem_free(pci_rp, reglen); 675 676 done: 677 /* Pass up the request to our parent. */ 678 return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result)); 679 } 680 681 static int 682 ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, 683 void *arg, void *result) 684 { 685 ppb_devstate_t *ppb; 686 687 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 688 ddi_get_instance(dip)); 689 690 return (pci_pwr_ops(ppb->ppb_pwr_p, dip, impl_arg, op, arg, result)); 691 } 692 693 694 /* 695 * name_child 696 * 697 * This function is called from init_child to name a node. It is 698 * also passed as a callback for node merging functions. 699 * 700 * return value: DDI_SUCCESS, DDI_FAILURE 701 */ 702 static int 703 ppb_name_child(dev_info_t *child, char *name, int namelen) 704 { 705 pci_regspec_t *pci_rp; 706 uint_t slot, func; 707 char **unit_addr; 708 uint_t n; 709 710 /* 711 * Pseudo nodes indicate a prototype node with per-instance 712 * properties to be merged into the real h/w device node. 713 * The interpretation of the unit-address is DD[,F] 714 * where DD is the device id and F is the function. 715 */ 716 if (ndi_dev_is_persistent_node(child) == 0) { 717 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 718 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 719 DDI_PROP_SUCCESS) { 720 cmn_err(CE_WARN, "cannot name node from %s.conf", 721 ddi_driver_name(child)); 722 return (DDI_FAILURE); 723 } 724 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 725 cmn_err(CE_WARN, "unit-address property in %s.conf" 726 " not well-formed", ddi_driver_name(child)); 727 ddi_prop_free(unit_addr); 728 return (DDI_FAILURE); 729 } 730 (void) snprintf(name, namelen, "%s", *unit_addr); 731 ddi_prop_free(unit_addr); 732 return (DDI_SUCCESS); 733 } 734 735 /* 736 * Get the address portion of the node name based on 737 * the function and device number. 738 */ 739 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 740 "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 741 return (DDI_FAILURE); 742 } 743 744 slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 745 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 746 747 if (func != 0) 748 (void) snprintf(name, namelen, "%x,%x", slot, func); 749 else 750 (void) snprintf(name, namelen, "%x", slot); 751 752 ddi_prop_free(pci_rp); 753 return (DDI_SUCCESS); 754 } 755 756 static int 757 ppb_initchild(dev_info_t *child) 758 { 759 char name[MAXNAMELEN]; 760 ddi_acc_handle_t config_handle; 761 ushort_t command_preserve, command; 762 uint_t n; 763 ushort_t bcr; 764 uchar_t header_type; 765 uchar_t min_gnt, latency_timer; 766 ppb_devstate_t *ppb; 767 768 /* 769 * Name the child 770 */ 771 if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) 772 return (DDI_FAILURE); 773 774 ddi_set_name_addr(child, name); 775 ddi_set_parent_data(child, NULL); 776 777 /* 778 * Pseudo nodes indicate a prototype node with per-instance 779 * properties to be merged into the real h/w device node. 780 * The interpretation of the unit-address is DD[,F] 781 * where DD is the device id and F is the function. 782 */ 783 if (ndi_dev_is_persistent_node(child) == 0) { 784 extern int pci_allow_pseudo_children; 785 786 /* 787 * Try to merge the properties from this prototype 788 * node into real h/w nodes. 789 */ 790 if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) { 791 /* 792 * Merged ok - return failure to remove the node. 793 */ 794 ppb_removechild(child); 795 return (DDI_FAILURE); 796 } 797 798 /* workaround for ddivs to run under PCI */ 799 if (pci_allow_pseudo_children) 800 return (DDI_SUCCESS); 801 802 /* 803 * The child was not merged into a h/w node, 804 * but there's not much we can do with it other 805 * than return failure to cause the node to be removed. 806 */ 807 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 808 ddi_driver_name(child), ddi_get_name_addr(child), 809 ddi_driver_name(child)); 810 ppb_removechild(child); 811 return (DDI_NOT_WELL_FORMED); 812 } 813 814 ddi_set_parent_data(child, NULL); 815 816 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 817 ddi_get_instance(ddi_get_parent(child))); 818 819 /* 820 * If hardware is PM capable, set up the power info structure. 821 * This also ensures the the bus will not be off (0MHz) otherwise 822 * system panics during a bus access. 823 */ 824 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 825 /* 826 * Create a pwr_info struct for child. Bus will be 827 * at full speed after creating info. 828 */ 829 pci_pwr_create_info(ppb->ppb_pwr_p, child); 830 #ifdef DEBUG 831 ASSERT(ppb->ppb_pwr_p->current_lvl == PM_LEVEL_B0); 832 #endif 833 } 834 835 /* 836 * If configuration registers were previously saved by 837 * child (before it entered D3), then let the child do the 838 * restore to set up the config regs as it'll first need to 839 * power the device out of D3. 840 */ 841 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 842 "config-regs-saved-by-child") == 1) { 843 DEBUG2(DBG_PWR, ddi_get_parent(child), 844 "INITCHILD: config regs to be restored by child" 845 " for %s@%s\n", ddi_node_name(child), 846 ddi_get_name_addr(child)); 847 848 return (DDI_SUCCESS); 849 } 850 851 DEBUG2(DBG_PWR, ddi_get_parent(child), 852 "INITCHILD: config regs setup for %s@%s\n", 853 ddi_node_name(child), ddi_get_name_addr(child)); 854 855 if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) { 856 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 857 pci_pwr_rm_info(ppb->ppb_pwr_p, child); 858 } 859 860 return (DDI_FAILURE); 861 } 862 863 /* 864 * Determine the configuration header type. 865 */ 866 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 867 868 /* 869 * Support for the "command-preserve" property. 870 */ 871 command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child, 872 DDI_PROP_DONTPASS, "command-preserve", 0); 873 command = pci_config_get16(config_handle, PCI_CONF_COMM); 874 command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB); 875 command |= (ppb_command_default & ~command_preserve); 876 pci_config_put16(config_handle, PCI_CONF_COMM, command); 877 878 /* 879 * If the device has a bus control register then program it 880 * based on the settings in the command register. 881 */ 882 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 883 bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL); 884 if (ppb_command_default & PCI_COMM_PARITY_DETECT) 885 bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 886 if (ppb_command_default & PCI_COMM_SERR_ENABLE) 887 bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE; 888 bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE; 889 pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr); 890 } 891 892 /* 893 * Initialize cache-line-size configuration register if needed. 894 */ 895 if (ppb_set_cache_line_size_register && 896 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 897 "cache-line-size", 0) == 0) { 898 pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ, 899 ppb->ppb_cache_line_size); 900 n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 901 if (n != 0) { 902 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 903 "cache-line-size", n); 904 } 905 } 906 907 /* 908 * Initialize latency timer configuration registers if needed. 909 */ 910 if (ppb_set_latency_timer_register && 911 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 912 "latency-timer", 0) == 0) { 913 914 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 915 latency_timer = ppb->ppb_latency_timer; 916 pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER, 917 ppb->ppb_latency_timer); 918 } else { 919 min_gnt = pci_config_get8(config_handle, 920 PCI_CONF_MIN_G); 921 latency_timer = min_gnt * 8; 922 } 923 pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER, 924 latency_timer); 925 n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 926 if (n != 0) { 927 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 928 "latency-timer", n); 929 } 930 } 931 932 /* 933 * Check to see if the XMITS/PCI-X workaround applies. 934 */ 935 n = ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_NOTPROM, 936 "pcix-update-cmd-reg", -1); 937 938 if (n != -1) { 939 extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value); 940 DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ " 941 "Workaround: value = %x\n", n); 942 pcix_set_cmd_reg(child, n); 943 } 944 945 pci_config_teardown(&config_handle); 946 947 return (DDI_SUCCESS); 948 } 949 950 static void 951 ppb_removechild(dev_info_t *dip) 952 { 953 ppb_devstate_t *ppb; 954 955 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 956 ddi_get_instance(ddi_get_parent(dip))); 957 958 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 959 960 DEBUG2(DBG_PWR, ddi_get_parent(dip), 961 "UNINITCHILD: removing pwr_info for %s@%s\n", 962 ddi_node_name(dip), ddi_get_name_addr(dip)); 963 pci_pwr_rm_info(ppb->ppb_pwr_p, dip); 964 } 965 966 ddi_set_name_addr(dip, NULL); 967 968 /* 969 * Strip the node to properly convert it back to prototype form 970 */ 971 ddi_remove_minor_node(dip, NULL); 972 973 impl_rem_dev_props(dip); 974 } 975 976 /* 977 * If bridge is PM capable, set up PM state for nexus. 978 */ 979 static void 980 ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip) 981 { 982 char *comp_array[5]; 983 int i; 984 ddi_acc_handle_t conf_hdl; 985 uint8_t cap_ptr; 986 uint8_t cap_id; 987 uint8_t pmcsr_bse; 988 uint16_t pmcap; 989 990 /* 991 * Determine if bridge is PM capable. If not, leave ppb_pwr_p NULL 992 * and return. 993 */ 994 995 if (pci_config_setup(pdip, &ppb->ppb_conf_hdl) != DDI_SUCCESS) { 996 997 return; 998 } 999 1000 conf_hdl = ppb->ppb_conf_hdl; 1001 1002 cap_ptr = pci_config_get8(conf_hdl, PCI_BCNF_CAP_PTR); 1003 1004 /* 1005 * Walk the capabilities searching for a PM entry. 1006 */ 1007 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) { 1008 cap_id = pci_config_get8(conf_hdl, 1009 cap_ptr + PCI_CAP_ID); 1010 if (cap_id == PCI_CAP_ID_PM) { 1011 break; 1012 } 1013 cap_ptr = pci_config_get8(conf_hdl, 1014 cap_ptr + PCI_CAP_NEXT_PTR); 1015 } 1016 1017 if (cap_ptr == 0) { 1018 DEBUG0(DBG_PWR, pdip, "bridge does not support PM. PCI" 1019 " PM data structure not found in config header\n"); 1020 pci_config_teardown(&conf_hdl); 1021 1022 return; 1023 } 1024 1025 /* 1026 * Allocate PM state structure for ppb. 1027 */ 1028 ppb->ppb_pwr_p = (pci_pwr_t *) 1029 kmem_zalloc(sizeof (pci_pwr_t), KM_SLEEP); 1030 ppb->ppb_pwr_p->pwr_fp = 0; 1031 1032 /* 1033 * Save offset to pmcsr for future references. 1034 */ 1035 ppb->ppb_pmcsr_offset = cap_ptr + PCI_PMCSR; 1036 1037 pmcsr_bse = pci_config_get8(conf_hdl, cap_ptr + PCI_PMCSR_BSE); 1038 1039 pmcap = pci_config_get16(conf_hdl, cap_ptr + PCI_PMCAP); 1040 1041 if (pmcap & PCI_PMCAP_D1) { 1042 DEBUG0(DBG_PWR, pdip, "setup: B1 state supported\n"); 1043 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B1_CAPABLE; 1044 } else { 1045 DEBUG0(DBG_PWR, pdip, "setup: B1 state NOT supported\n"); 1046 } 1047 if (pmcap & PCI_PMCAP_D2) { 1048 DEBUG0(DBG_PWR, pdip, "setup: B2 state supported\n"); 1049 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE; 1050 } else { 1051 DEBUG0(DBG_PWR, pdip, "setup: B2 via D2 NOT supported\n"); 1052 } 1053 1054 if (pmcsr_bse & PCI_PMCSR_BSE_BPCC_EN) { 1055 DEBUG0(DBG_PWR, pdip, 1056 "setup: bridge power/clock control enable\n"); 1057 } else { 1058 DEBUG0(DBG_PWR, pdip, 1059 "setup: bridge power/clock control disabled\n"); 1060 1061 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1062 ppb->ppb_pwr_p = NULL; 1063 pci_config_teardown(&conf_hdl); 1064 1065 return; 1066 } 1067 1068 /* 1069 * PCI states D0 and D3 always are supported for normal PCI 1070 * devices. D1 and D2 are optional which are checked for above. 1071 * Bridge function states D0-D3 correspond to secondary bus states 1072 * B0-B3, EXCEPT if PCI_PMCSR_BSE_B2_B3 is set. In this case, setting 1073 * the bridge function to D3 will set the bridge bus to state B2 instead 1074 * of B3. D2 will not correspond to B2 (and in fact, probably 1075 * won't be D2 capable). Implicitly, this means that if 1076 * PCI_PMCSR_BSE_B2_B3 is set, the bus will not be B3 capable. 1077 */ 1078 if (pmcsr_bse & PCI_PMCSR_BSE_B2_B3) { 1079 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE; 1080 DEBUG0(DBG_PWR, pdip, "B2 supported via D3\n"); 1081 } else { 1082 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B3_CAPABLE; 1083 DEBUG0(DBG_PWR, pdip, "B3 supported via D3\n"); 1084 } 1085 1086 ppb->ppb_pwr_p->pwr_dip = pdip; 1087 mutex_init(&ppb->ppb_pwr_p->pwr_mutex, NULL, MUTEX_DRIVER, NULL); 1088 1089 i = 0; 1090 comp_array[i++] = "NAME=PCI bridge PM"; 1091 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) { 1092 comp_array[i++] = "0=Clock/Power Off (B3)"; 1093 } 1094 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) { 1095 comp_array[i++] = "1=Clock Off (B2)"; 1096 } 1097 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) { 1098 comp_array[i++] = "2=Bus Inactive (B1)"; 1099 } 1100 comp_array[i++] = "3=Full Power (B0)"; 1101 1102 /* 1103 * Create pm-components property. It does not already exist. 1104 */ 1105 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, pdip, 1106 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) { 1107 cmn_err(CE_WARN, 1108 "%s%d pm-components prop update failed", 1109 ddi_driver_name(pdip), ddi_get_instance(pdip)); 1110 pci_config_teardown(&conf_hdl); 1111 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1112 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1113 ppb->ppb_pwr_p = NULL; 1114 1115 return; 1116 } 1117 1118 if (ddi_prop_create(DDI_DEV_T_NONE, pdip, DDI_PROP_CANSLEEP, 1119 "pm-want-child-notification?", NULL, NULL) != DDI_PROP_SUCCESS) { 1120 cmn_err(CE_WARN, 1121 "%s%d fail to create pm-want-child-notification? prop", 1122 ddi_driver_name(pdip), ddi_get_instance(pdip)); 1123 1124 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, "pm-components"); 1125 pci_config_teardown(&conf_hdl); 1126 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1127 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1128 ppb->ppb_pwr_p = NULL; 1129 1130 return; 1131 } 1132 1133 ppb->ppb_pwr_p->current_lvl = 1134 pci_pwr_current_lvl(ppb->ppb_pwr_p); 1135 } 1136 1137 /* 1138 * Remove PM state for nexus. 1139 */ 1140 static void 1141 ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip) 1142 { 1143 int low_lvl; 1144 1145 /* 1146 * Determine the lowest power level supported. 1147 */ 1148 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) { 1149 low_lvl = PM_LEVEL_B3; 1150 } else { 1151 low_lvl = PM_LEVEL_B2; 1152 } 1153 1154 if (pm_lower_power(dip, PCI_PM_COMP_0, low_lvl) != DDI_SUCCESS) { 1155 cmn_err(CE_WARN, "%s%d failed to lower power", 1156 ddi_driver_name(dip), ddi_get_instance(dip)); 1157 } 1158 1159 pci_config_teardown(&ppb->ppb_conf_hdl); 1160 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1161 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1162 1163 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components") != 1164 DDI_PROP_SUCCESS) { 1165 cmn_err(CE_WARN, "%s%d unable to remove prop pm-components", 1166 ddi_driver_name(dip), ddi_get_instance(dip)); 1167 } 1168 1169 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, 1170 "pm-want-child-notification?") != DDI_PROP_SUCCESS) { 1171 cmn_err(CE_WARN, 1172 "%s%d unable to remove prop pm-want_child_notification?", 1173 ddi_driver_name(dip), ddi_get_instance(dip)); 1174 } 1175 } 1176 1177 /* 1178 * Examine the pmcsr register and return the software defined 1179 * state (the difference being whether D3 means B2 or B3). 1180 */ 1181 int 1182 pci_pwr_current_lvl(pci_pwr_t *pwr_p) 1183 { 1184 ppb_devstate_t *ppb; 1185 uint16_t pmcsr; 1186 1187 /* 1188 * Find out current power level 1189 */ 1190 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1191 ddi_get_instance(pwr_p->pwr_dip)); 1192 1193 pmcsr = pci_config_get16(ppb->ppb_conf_hdl, 1194 ppb->ppb_pmcsr_offset); 1195 1196 switch (pmcsr & PCI_PMCSR_STATE_MASK) { 1197 case PCI_PMCSR_D0: 1198 1199 return (PM_LEVEL_B0); 1200 case PCI_PMCSR_D1: 1201 1202 return (PM_LEVEL_B1); 1203 case PCI_PMCSR_D2: 1204 1205 return (PM_LEVEL_B2); 1206 case PCI_PMCSR_D3HOT: 1207 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1208 1209 return (PM_LEVEL_B2); 1210 } else { 1211 1212 return (PM_LEVEL_B3); 1213 } 1214 } 1215 /*NOTREACHED*/ 1216 } 1217 1218 /* 1219 * Power entry point. Called by the PM framework to change the 1220 * current power state of the bus. This function must first verify that 1221 * the requested power change is still valid. 1222 */ 1223 /*ARGSUSED*/ 1224 static int 1225 ppb_pwr(dev_info_t *dip, int component, int lvl) 1226 { 1227 ppb_devstate_t *ppb; 1228 uint16_t pmcsr; 1229 char *str; 1230 int lowest_lvl; 1231 int old_lvl; 1232 int new_lvl; 1233 1234 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1235 ddi_get_instance(dip)); 1236 if (ppb == NULL) { 1237 cmn_err(CE_WARN, "%s%d ppb_pwr: can't get soft state", 1238 ddi_driver_name(dip), ddi_get_instance(dip)); 1239 1240 return (DDI_FAILURE); 1241 } 1242 1243 DEBUG1(DBG_PWR, dip, "ppb_pwr(): ENTER level = %d\n", lvl); 1244 1245 mutex_enter(&ppb->ppb_pwr_p->pwr_mutex); 1246 1247 /* 1248 * Find out if the power setting is possible. If it is not, 1249 * set component busy and return failure. If it is possible, 1250 * and it is the lowest pwr setting possible, set component 1251 * busy so that the framework does not try to lower any further. 1252 */ 1253 lowest_lvl = pci_pwr_new_lvl(ppb->ppb_pwr_p); 1254 if (lowest_lvl > lvl) { 1255 pci_pwr_component_busy(ppb->ppb_pwr_p); 1256 DEBUG2(DBG_PWR, dip, "ppb_pwr: failing power request " 1257 "lowest allowed is %d requested is %d\n", 1258 lowest_lvl, lvl); 1259 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1260 1261 return (DDI_FAILURE); 1262 } else if (lowest_lvl == lvl) { 1263 pci_pwr_component_busy(ppb->ppb_pwr_p); 1264 } else { 1265 pci_pwr_component_idle(ppb->ppb_pwr_p); 1266 } 1267 1268 pmcsr = pci_config_get16(ppb->ppb_conf_hdl, ppb->ppb_pmcsr_offset); 1269 1270 /* 1271 * Save the current power level. This is the actual function level, 1272 * not the translated bridge level stored in pwr_p->current_lvl 1273 */ 1274 old_lvl = pmcsr & PCI_PMCSR_STATE_MASK; 1275 1276 pmcsr &= ~PCI_PMCSR_STATE_MASK; 1277 switch (lvl) { 1278 case PM_LEVEL_B0: 1279 str = "PM_LEVEL_B0 (full speed)"; 1280 pmcsr |= PCI_PMCSR_D0; 1281 break; 1282 case PM_LEVEL_B1: 1283 str = "PM_LEVEL_B1 (light sleep. No bus traffic allowed)"; 1284 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) == 0) { 1285 cmn_err(CE_WARN, "%s%d PCI PM state B1 not supported", 1286 ddi_driver_name(dip), ddi_get_instance(dip)); 1287 1288 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1289 return (DDI_FAILURE); 1290 } 1291 pmcsr |= PCI_PMCSR_D1; 1292 break; 1293 case PM_LEVEL_B2: 1294 str = "PM_LEVEL_B2 (clock off)"; 1295 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) == 0) { 1296 cmn_err(CE_WARN, "%s%d PM state B2 not supported...", 1297 ddi_driver_name(dip), 1298 ddi_get_instance(dip)); 1299 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1300 1301 return (DDI_FAILURE); 1302 } 1303 1304 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1305 /* 1306 * If B3 isn't supported, use D3 for B2 to avoid the 1307 * possible case that D2 for B2 isn't supported. 1308 * Saves and extra check and state flag.. 1309 */ 1310 pmcsr |= PCI_PMCSR_D3HOT; 1311 } else { 1312 pmcsr |= PCI_PMCSR_D2; 1313 } 1314 break; 1315 case PM_LEVEL_B3: 1316 str = "PM_LEVEL_B30 (clock and power off)"; 1317 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1318 cmn_err(CE_WARN, "%s%d PM state B3 not supported...", 1319 ddi_driver_name(dip), 1320 ddi_get_instance(dip)); 1321 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1322 1323 return (DDI_FAILURE); 1324 } 1325 pmcsr |= PCI_PMCSR_D3HOT; 1326 1327 break; 1328 1329 default: 1330 cmn_err(CE_WARN, "%s%d Unknown PM state %d", 1331 ddi_driver_name(dip), ddi_get_instance(dip), lvl); 1332 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1333 1334 return (DDI_FAILURE); 1335 } 1336 1337 new_lvl = pmcsr & PCI_PMCSR_STATE_MASK; 1338 1339 /* 1340 * Save config regs if going into HW state D3 (B2 or B3) 1341 */ 1342 if ((old_lvl != PCI_PMCSR_D3HOT) && (new_lvl == PCI_PMCSR_D3HOT)) { 1343 DEBUG0(DBG_PWR, dip, "ppb_pwr(): SAVING CONFIG REGS\n"); 1344 if (pci_save_config_regs(dip) != DDI_SUCCESS) { 1345 cmn_err(CE_WARN, "%s%d Save config regs failed", 1346 ddi_driver_name(dip), ddi_get_instance(dip)); 1347 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1348 1349 return (DDI_FAILURE); 1350 } 1351 } 1352 1353 pci_config_put16(ppb->ppb_conf_hdl, ppb->ppb_pmcsr_offset, pmcsr); 1354 1355 /* 1356 * No bus transactions should occur without waiting for 1357 * settle time specified in PCI PM spec rev 2.1 sec 5.6.1 1358 * To make things simple, just use the max time specified for 1359 * all state transitions. 1360 */ 1361 delay(drv_usectohz(PCI_CLK_SETTLE_TIME)); 1362 1363 /* 1364 * Restore configuration registers if coming out of HW state D3 1365 */ 1366 if ((old_lvl == PCI_PMCSR_D3HOT) && (new_lvl != PCI_PMCSR_D3HOT)) { 1367 DEBUG0(DBG_PWR, dip, "ppb_pwr(): RESTORING CONFIG REGS\n"); 1368 if (pci_restore_config_regs(dip) != DDI_SUCCESS) { 1369 panic("%s%d restore config regs failed", 1370 ddi_driver_name(dip), ddi_get_instance(dip)); 1371 } 1372 /*NOTREACHED*/ 1373 } 1374 1375 ppb->ppb_pwr_p->current_lvl = lvl; 1376 1377 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1378 1379 DEBUG1(DBG_PWR, dip, "ppb_set_pwr: set PM state to %s\n\n", str); 1380 1381 return (DDI_SUCCESS); 1382 } 1383 1384 /* 1385 * Initialize hotplug framework if we are hotpluggable. 1386 * Sets flag in the soft state if Hot Plug is supported and initialized 1387 * properly. 1388 */ 1389 /*ARGSUSED*/ 1390 static void 1391 ppb_init_hotplug(ppb_devstate_t *ppb) 1392 { 1393 if (ddi_prop_exists(DDI_DEV_T_ANY, ppb->dip, DDI_PROP_DONTPASS, 1394 "hotplug-capable")) { 1395 (void) modload("misc", "pcihp"); 1396 1397 if (pcihp_init(ppb->dip) != DDI_SUCCESS) { 1398 cmn_err(CE_WARN, 1399 "%s #%d: Failed setting hotplug framework", 1400 ddi_driver_name(ppb->dip), 1401 ddi_get_instance(ppb->dip)); 1402 } else 1403 ppb->hotplug_capable = B_TRUE; 1404 } 1405 1406 } 1407 1408 static void 1409 ppb_create_ranges_prop(dev_info_t *dip, 1410 ddi_acc_handle_t config_handle) 1411 { 1412 uint32_t base, limit; 1413 ppb_ranges_t ranges[PPB_RANGE_LEN]; 1414 uint8_t io_base_lo, io_limit_lo; 1415 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit; 1416 int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int); 1417 1418 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW); 1419 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW); 1420 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI); 1421 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI); 1422 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE); 1423 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT); 1424 1425 /* 1426 * Create ranges for IO space 1427 */ 1428 ranges[i].size_low = ranges[i].size_high = 0; 1429 ranges[i].parent_mid = ranges[i].child_mid = 1430 ranges[i].parent_high = 0; 1431 ranges[i].child_high = ranges[i].parent_high |= 1432 (PCI_REG_REL_M | PCI_ADDR_IO); 1433 base = PPB_16bit_IOADDR(io_base_lo); 1434 limit = PPB_16bit_IOADDR(io_limit_lo); 1435 1436 if ((io_base_lo & 0xf) == PPB_32BIT_IO) { 1437 base = PPB_LADDR(base, io_base_hi); 1438 } 1439 if ((io_limit_lo & 0xf) == PPB_32BIT_IO) { 1440 limit = PPB_LADDR(limit, io_limit_hi); 1441 } 1442 1443 if ((io_base_lo & PPB_32BIT_IO) && (io_limit_hi > 0)) { 1444 base = PPB_LADDR(base, io_base_hi); 1445 limit = PPB_LADDR(limit, io_limit_hi); 1446 } 1447 1448 /* 1449 * Create ranges for 32bit memory space 1450 */ 1451 base = PPB_32bit_MEMADDR(mem_base); 1452 limit = PPB_32bit_MEMADDR(mem_limit); 1453 ranges[i].size_low = ranges[i].size_high = 0; 1454 ranges[i].parent_mid = ranges[i].child_mid = 1455 ranges[i].parent_high = 0; 1456 ranges[i].child_high = ranges[i].parent_high |= 1457 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1458 ranges[i].child_low = ranges[i].parent_low = base; 1459 if (limit >= base) { 1460 ranges[i].size_low = limit - base + PPB_MEMGRAIN; 1461 i++; 1462 } 1463 1464 if (i) { 1465 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 1466 (int *)ranges, i * rangelen); 1467 } 1468 } 1469 1470 /* ARGSUSED */ 1471 static int 1472 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 1473 { 1474 ppb_devstate_t *ppb_p; 1475 minor_t minor = getminor(*devp); 1476 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1477 1478 /* 1479 * Make sure the open is for the right file type. 1480 */ 1481 if (otyp != OTYP_CHR) 1482 return (EINVAL); 1483 1484 /* 1485 * Get the soft state structure for the device. 1486 */ 1487 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1488 instance); 1489 1490 if (ppb_p == NULL) 1491 return (ENXIO); 1492 1493 if (ppb_p->hotplug_capable == B_TRUE) 1494 return ((pcihp_get_cb_ops())->cb_open(devp, flags, 1495 otyp, credp)); 1496 1497 /* 1498 * Handle the open by tracking the device state. 1499 */ 1500 mutex_enter(&ppb_p->ppb_mutex); 1501 if (flags & FEXCL) { 1502 if (ppb_p->ppb_soft_state != PPB_SOFT_STATE_CLOSED) { 1503 mutex_exit(&ppb_p->ppb_mutex); 1504 return (EBUSY); 1505 } 1506 ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN_EXCL; 1507 } else { 1508 if (ppb_p->ppb_soft_state == PPB_SOFT_STATE_OPEN_EXCL) { 1509 mutex_exit(&ppb_p->ppb_mutex); 1510 return (EBUSY); 1511 } 1512 ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN; 1513 } 1514 mutex_exit(&ppb_p->ppb_mutex); 1515 return (0); 1516 } 1517 1518 1519 /* ARGSUSED */ 1520 static int 1521 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp) 1522 { 1523 ppb_devstate_t *ppb_p; 1524 minor_t minor = getminor(dev); 1525 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1526 1527 if (otyp != OTYP_CHR) 1528 return (EINVAL); 1529 1530 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1531 instance); 1532 1533 if (ppb_p == NULL) 1534 return (ENXIO); 1535 1536 if (ppb_p->hotplug_capable == B_TRUE) 1537 return ((pcihp_get_cb_ops())->cb_close(dev, flags, 1538 otyp, credp)); 1539 1540 mutex_enter(&ppb_p->ppb_mutex); 1541 ppb_p->ppb_soft_state = PPB_SOFT_STATE_CLOSED; 1542 mutex_exit(&ppb_p->ppb_mutex); 1543 return (0); 1544 } 1545 1546 1547 /* 1548 * ppb_ioctl: devctl hotplug controls 1549 */ 1550 /* ARGSUSED */ 1551 static int 1552 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1553 int *rvalp) 1554 { 1555 ppb_devstate_t *ppb_p; 1556 dev_info_t *self; 1557 struct devctl_iocdata *dcp; 1558 uint_t bus_state; 1559 int rv = 0; 1560 minor_t minor = getminor(dev); 1561 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1562 1563 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1564 instance); 1565 1566 if (ppb_p == NULL) 1567 return (ENXIO); 1568 1569 if (ppb_p->hotplug_capable == B_TRUE) 1570 return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, 1571 arg, mode, credp, rvalp)); 1572 1573 self = ppb_p->dip; 1574 1575 /* 1576 * We can use the generic implementation for these ioctls 1577 */ 1578 switch (cmd) { 1579 case DEVCTL_DEVICE_GETSTATE: 1580 case DEVCTL_DEVICE_ONLINE: 1581 case DEVCTL_DEVICE_OFFLINE: 1582 case DEVCTL_BUS_GETSTATE: 1583 return (ndi_devctl_ioctl(self, cmd, arg, mode, 0)); 1584 } 1585 1586 /* 1587 * read devctl ioctl data 1588 */ 1589 if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) 1590 return (EFAULT); 1591 1592 switch (cmd) { 1593 1594 case DEVCTL_DEVICE_RESET: 1595 rv = ENOTSUP; 1596 break; 1597 1598 case DEVCTL_BUS_QUIESCE: 1599 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1600 if (bus_state == BUS_QUIESCED) 1601 break; 1602 (void) ndi_set_bus_state(self, BUS_QUIESCED); 1603 break; 1604 1605 case DEVCTL_BUS_UNQUIESCE: 1606 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1607 if (bus_state == BUS_ACTIVE) 1608 break; 1609 (void) ndi_set_bus_state(self, BUS_ACTIVE); 1610 break; 1611 1612 case DEVCTL_BUS_RESET: 1613 rv = ENOTSUP; 1614 break; 1615 1616 case DEVCTL_BUS_RESETALL: 1617 rv = ENOTSUP; 1618 break; 1619 1620 default: 1621 rv = ENOTTY; 1622 } 1623 1624 ndi_dc_freehdl(dcp); 1625 return (rv); 1626 } 1627 1628 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 1629 int flags, char *name, caddr_t valuep, int *lengthp) 1630 { 1631 ppb_devstate_t *ppb_p; 1632 minor_t minor = getminor(dev); 1633 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1634 1635 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1636 instance); 1637 1638 if (ppb_p == NULL) 1639 return (ENXIO); 1640 1641 if (ppb_p->hotplug_capable == B_TRUE) 1642 return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, 1643 flags, name, valuep, lengthp)); 1644 1645 return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp)); 1646 } 1647 1648 /* 1649 * Initialize our FMA resources 1650 */ 1651 static void 1652 ppb_fm_init(ppb_devstate_t *ppb_p) 1653 { 1654 ddi_fm_error_t derr; 1655 1656 ppb_p->fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 1657 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 1658 1659 /* 1660 * Request our capability level and get our parents capability 1661 * and ibc. 1662 */ 1663 ddi_fm_init(ppb_p->dip, &ppb_p->fm_cap, &ppb_p->fm_ibc); 1664 ASSERT((ppb_p->fm_cap & DDI_FM_EREPORT_CAPABLE) && 1665 (ppb_p->fm_cap & DDI_FM_ERRCB_CAPABLE)); 1666 1667 pci_ereport_setup(ppb_p->dip); 1668 1669 /* 1670 * clear any outstanding error bits 1671 */ 1672 bzero(&derr, sizeof (ddi_fm_error_t)); 1673 derr.fme_version = DDI_FME_VERSION; 1674 derr.fme_flag = DDI_FM_ERR_EXPECTED; 1675 pci_ereport_post(ppb_p->dip, &derr, NULL); 1676 pci_bdg_ereport_post(ppb_p->dip, &derr, NULL); 1677 1678 /* 1679 * Register error callback with our parent. 1680 */ 1681 ddi_fm_handler_register(ppb_p->dip, ppb_err_callback, NULL); 1682 } 1683 1684 /* 1685 * Breakdown our FMA resources 1686 */ 1687 static void 1688 ppb_fm_fini(ppb_devstate_t *ppb_p) 1689 { 1690 /* 1691 * Clean up allocated fm structures 1692 */ 1693 ddi_fm_handler_unregister(ppb_p->dip); 1694 pci_ereport_teardown(ppb_p->dip); 1695 ddi_fm_fini(ppb_p->dip); 1696 } 1697 1698 /* 1699 * Initialize FMA resources for children devices. Called when 1700 * child calls ddi_fm_init(). 1701 */ 1702 /*ARGSUSED*/ 1703 static int 1704 ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 1705 ddi_iblock_cookie_t *ibc) 1706 { 1707 ppb_devstate_t *ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1708 ddi_get_instance(dip)); 1709 *ibc = ppb_p->fm_ibc; 1710 return (ppb_p->fm_cap); 1711 } 1712 1713 /* 1714 * FMA registered error callback 1715 */ 1716 static int 1717 ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data) 1718 { 1719 uint16_t pci_cfg_stat, pci_cfg_sec_stat; 1720 1721 ASSERT(impl_data == NULL); 1722 pci_ereport_post(dip, derr, &pci_cfg_stat); 1723 pci_bdg_ereport_post(dip, derr, &pci_cfg_sec_stat); 1724 return (pci_bdg_check_status(dip, derr, pci_cfg_stat, 1725 pci_cfg_sec_stat)); 1726 } 1727 1728 static void 1729 ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle) 1730 { 1731 i_ndi_busop_access_enter(dip, handle); 1732 } 1733 1734 /* ARGSUSED */ 1735 static void 1736 ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle) 1737 { 1738 i_ndi_busop_access_exit(dip, handle); 1739 } 1740