1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Sun4u PCI to PCI bus bridge nexus driver 30 */ 31 32 #include <sys/conf.h> 33 #include <sys/kmem.h> 34 #include <sys/debug.h> 35 #include <sys/modctl.h> 36 #include <sys/autoconf.h> 37 #include <sys/ddi_impldefs.h> 38 #include <sys/ddi_subrdefs.h> 39 #include <sys/pci.h> 40 #include <sys/pci_cap.h> 41 #include <sys/pci/pci_nexus.h> 42 #include <sys/pci/pci_regs.h> 43 #include <sys/ddi.h> 44 #include <sys/sunndi.h> 45 #include <sys/sunddi.h> 46 #include <sys/fm/protocol.h> 47 #include <sys/ddifm.h> 48 #include <sys/pci/pci_pwr.h> 49 #include <sys/pci/pci_debug.h> 50 #include <sys/hotplug/pci/pcihp.h> 51 #include <sys/open.h> 52 #include <sys/stat.h> 53 #include <sys/file.h> 54 55 #define NUM_LOGICAL_SLOTS 32 56 57 #define PPB_RANGE_LEN 2 58 59 #define PPB_32BIT_IO 1 60 #define PPB_32bit_MEM 1 61 62 #define PPB_MEMGRAIN 0x100000 63 #define PPB_IOGRAIN 0x1000 64 65 #define PPB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8)) 66 #define PPB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo)) 67 #define PPB_32bit_MEMADDR(addr) (PPB_LADDR(0, ((uint16_t)(addr) & 0xFFF0))) 68 69 typedef struct slot_table { 70 uchar_t bus_id[128]; 71 uchar_t slot_name[32]; 72 uint8_t device_no; 73 uint8_t phys_slot_num; 74 } slot_table_t; 75 76 /* 77 * The variable controls the default setting of the command register 78 * for pci devices. See ppb_initchild() for details. 79 */ 80 static ushort_t ppb_command_default = PCI_COMM_SERR_ENABLE | 81 PCI_COMM_WAIT_CYC_ENAB | 82 PCI_COMM_PARITY_DETECT | 83 PCI_COMM_ME | 84 PCI_COMM_MAE | 85 PCI_COMM_IO; 86 87 static int ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, 88 off_t, off_t, caddr_t *); 89 static int ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, 90 void *, void *); 91 static int ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, 92 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 93 94 /* 95 * fm_init busop to initialize our children 96 */ 97 static int ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 98 ddi_iblock_cookie_t *ibc); 99 static void ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle); 100 static void ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle); 101 static int ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, 102 void *arg, void *result); 103 104 struct bus_ops ppb_bus_ops = { 105 BUSO_REV, 106 ppb_bus_map, 107 0, 108 0, 109 0, 110 i_ddi_map_fault, 111 ddi_dma_map, 112 ddi_dma_allochdl, 113 ddi_dma_freehdl, 114 ddi_dma_bindhdl, 115 ddi_dma_unbindhdl, 116 ddi_dma_flush, 117 ddi_dma_win, 118 ddi_dma_mctl, 119 ppb_ctlops, 120 ddi_bus_prop_op, 121 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 122 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 123 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 124 ndi_post_event, /* (*bus_post_event)(); */ 125 0, /* (*bus_intr_ctl)(); */ 126 0, /* (*bus_config)(); */ 127 0, /* (*bus_unconfig)(); */ 128 ppb_fm_init_child, /* (*bus_fm_init)(); */ 129 NULL, /* (*bus_fm_fini)(); */ 130 ppb_bus_enter, /* (*bus_enter)() */ 131 ppb_bus_exit, /* (*bus_exit)() */ 132 ppb_bus_power, /* (*bus_power)() */ 133 ppb_intr_ops /* (*bus_intr_op)(); */ 134 }; 135 136 static int ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp); 137 static int ppb_close(dev_t dev, int flags, int otyp, cred_t *credp); 138 static int ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, 139 cred_t *credp, int *rvalp); 140 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 141 int flags, char *name, caddr_t valuep, int *lengthp); 142 143 static struct cb_ops ppb_cb_ops = { 144 ppb_open, /* open */ 145 ppb_close, /* close */ 146 nulldev, /* strategy */ 147 nulldev, /* print */ 148 nulldev, /* dump */ 149 nulldev, /* read */ 150 nulldev, /* write */ 151 ppb_ioctl, /* ioctl */ 152 nodev, /* devmap */ 153 nodev, /* mmap */ 154 nodev, /* segmap */ 155 nochpoll, /* poll */ 156 ppb_prop_op, /* cb_prop_op */ 157 NULL, /* streamtab */ 158 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 159 CB_REV, /* rev */ 160 nodev, /* int (*cb_aread)() */ 161 nodev /* int (*cb_awrite)() */ 162 }; 163 164 static int ppb_probe(dev_info_t *); 165 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 166 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 167 static int ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 168 void *arg, void **result); 169 static int ppb_pwr(dev_info_t *dip, int component, int level); 170 171 struct dev_ops ppb_ops = { 172 DEVO_REV, /* devo_rev */ 173 0, /* refcnt */ 174 ppb_info, /* info */ 175 nulldev, /* identify */ 176 ppb_probe, /* probe */ 177 ppb_attach, /* attach */ 178 ppb_detach, /* detach */ 179 nulldev, /* reset */ 180 &ppb_cb_ops, /* driver operations */ 181 &ppb_bus_ops, /* bus operations */ 182 ppb_pwr 183 }; 184 185 /* 186 * Module linkage information for the kernel. 187 */ 188 189 static struct modldrv modldrv = { 190 &mod_driverops, /* Type of module */ 191 "Standard PCI to PCI bridge nexus driver %I%", 192 &ppb_ops, /* driver ops */ 193 }; 194 195 static struct modlinkage modlinkage = { 196 MODREV_1, 197 (void *)&modldrv, 198 NULL 199 }; 200 201 /* 202 * soft state pointer and structure template: 203 */ 204 static void *ppb_state; 205 206 struct ppb_cfg_state { 207 dev_info_t *dip; 208 ushort_t command; 209 uchar_t cache_line_size; 210 uchar_t latency_timer; 211 uchar_t header_type; 212 uchar_t sec_latency_timer; 213 ushort_t bridge_control; 214 }; 215 216 typedef struct { 217 218 dev_info_t *dip; 219 220 /* 221 * configuration register state for the bus: 222 */ 223 uchar_t ppb_cache_line_size; 224 uchar_t ppb_latency_timer; 225 226 /* 227 * PM support 228 */ 229 ddi_acc_handle_t ppb_conf_hdl; 230 uint16_t ppb_pm_cap_ptr; 231 pci_pwr_t *ppb_pwr_p; 232 233 /* 234 * HP support 235 */ 236 boolean_t hotplug_capable; 237 238 kmutex_t ppb_mutex; 239 uint_t ppb_soft_state; 240 #define PPB_SOFT_STATE_CLOSED 0x00 241 #define PPB_SOFT_STATE_OPEN 0x01 242 #define PPB_SOFT_STATE_OPEN_EXCL 0x02 243 int fm_cap; 244 ddi_iblock_cookie_t fm_ibc; 245 } ppb_devstate_t; 246 247 /* 248 * The following variable enables a workaround for the following obp bug: 249 * 250 * 1234181 - obp should set latency timer registers in pci 251 * configuration header 252 * 253 * Until this bug gets fixed in the obp, the following workaround should 254 * be enabled. 255 */ 256 static uint_t ppb_set_latency_timer_register = 1; 257 258 /* 259 * The following variable enables a workaround for an obp bug to be 260 * submitted. A bug requesting a workaround fof this problem has 261 * been filed: 262 * 263 * 1235094 - need workarounds on positron nexus drivers to set cache 264 * line size registers 265 * 266 * Until this bug gets fixed in the obp, the following workaround should 267 * be enabled. 268 */ 269 static uint_t ppb_set_cache_line_size_register = 1; 270 271 /* 272 * forward function declarations: 273 */ 274 275 /* 276 * FMA error callback 277 * Register error handling callback with our parent. We will just call 278 * our children's error callbacks and return their status. 279 */ 280 static int ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, 281 const void *impl_data); 282 283 /* 284 * init/fini routines to alloc/dealloc fm structures and 285 * register/unregister our callback. 286 */ 287 static void ppb_fm_init(ppb_devstate_t *ppb_p); 288 static void ppb_fm_fini(ppb_devstate_t *ppb_p); 289 290 static void ppb_removechild(dev_info_t *); 291 static int ppb_initchild(dev_info_t *child); 292 static dev_info_t *get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 293 static void ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *dip); 294 static void ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip); 295 static void ppb_init_hotplug(ppb_devstate_t *ppb); 296 static void ppb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t); 297 uint64_t pci_debug_flags = 0; 298 299 int 300 _init(void) 301 { 302 int e; 303 if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t), 304 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 305 ddi_soft_state_fini(&ppb_state); 306 return (e); 307 } 308 309 int 310 _fini(void) 311 { 312 int e; 313 314 if ((e = mod_remove(&modlinkage)) == 0) 315 ddi_soft_state_fini(&ppb_state); 316 return (e); 317 } 318 319 int 320 _info(struct modinfo *modinfop) 321 { 322 return (mod_info(&modlinkage, modinfop)); 323 } 324 325 /*ARGSUSED*/ 326 static int 327 ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 328 { 329 ppb_devstate_t *ppb_p; /* per ppb state pointer */ 330 minor_t minor = getminor((dev_t)arg); 331 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 332 333 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 334 instance); 335 336 switch (infocmd) { 337 default: 338 return (DDI_FAILURE); 339 340 case DDI_INFO_DEVT2INSTANCE: 341 *result = (void *)(uintptr_t)instance; 342 return (DDI_SUCCESS); 343 344 case DDI_INFO_DEVT2DEVINFO: 345 if (ppb_p == NULL) 346 return (DDI_FAILURE); 347 *result = (void *)ppb_p->dip; 348 return (DDI_SUCCESS); 349 } 350 } 351 352 /*ARGSUSED*/ 353 static int 354 ppb_probe(register dev_info_t *devi) 355 { 356 return (DDI_PROBE_SUCCESS); 357 } 358 359 /*ARGSUSED*/ 360 static int 361 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 362 { 363 int instance; 364 ppb_devstate_t *ppb; 365 ddi_acc_handle_t config_handle; 366 367 switch (cmd) { 368 case DDI_ATTACH: 369 370 /* 371 * Make sure the "device_type" property exists. 372 */ 373 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 374 "device_type", "pci"); 375 376 /* 377 * Allocate and get soft state structure. 378 */ 379 instance = ddi_get_instance(devi); 380 if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS) 381 return (DDI_FAILURE); 382 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, instance); 383 ppb->dip = devi; 384 mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL); 385 ppb->ppb_soft_state = PPB_SOFT_STATE_CLOSED; 386 if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) { 387 mutex_destroy(&ppb->ppb_mutex); 388 ddi_soft_state_free(ppb_state, instance); 389 return (DDI_FAILURE); 390 } 391 ppb_pwr_setup(ppb, devi); 392 393 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 394 mutex_enter(&ppb->ppb_pwr_p->pwr_mutex); 395 396 /* 397 * Before reading config registers, make sure power is 398 * on, and remains on. 399 */ 400 ppb->ppb_pwr_p->pwr_fp++; 401 402 pci_pwr_change(ppb->ppb_pwr_p, 403 ppb->ppb_pwr_p->current_lvl, 404 pci_pwr_new_lvl(ppb->ppb_pwr_p)); 405 } 406 407 ppb->ppb_cache_line_size = 408 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 409 ppb->ppb_latency_timer = 410 pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 411 412 /* 413 * Check whether the "ranges" property is present. 414 * Otherwise create the ranges property by reading 415 * the configuration registers 416 */ 417 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS, 418 "ranges") == 0) { 419 ppb_create_ranges_prop(devi, config_handle); 420 } 421 422 pci_config_teardown(&config_handle); 423 424 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 425 ppb->ppb_pwr_p->pwr_fp--; 426 427 pci_pwr_change(ppb->ppb_pwr_p, 428 ppb->ppb_pwr_p->current_lvl, 429 pci_pwr_new_lvl(ppb->ppb_pwr_p)); 430 431 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 432 } 433 434 /* 435 * Initialize hotplug support on this bus. At minimum 436 * (for non hotplug bus) this would create ":devctl" minor 437 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls 438 * to this bus. This all takes place if this nexus has hot-plug 439 * slots and successfully initializes Hot Plug Framework. 440 */ 441 ppb->hotplug_capable = B_FALSE; 442 ppb_init_hotplug(ppb); 443 if (ppb->hotplug_capable == B_FALSE) { 444 /* 445 * create minor node for devctl interfaces 446 */ 447 if (ddi_create_minor_node(devi, "devctl", S_IFCHR, 448 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 449 DDI_NT_NEXUS, 0) != DDI_SUCCESS) { 450 if (ppb->ppb_pwr_p != NULL) { 451 ppb_pwr_teardown(ppb, devi); 452 } 453 mutex_destroy(&ppb->ppb_mutex); 454 ddi_soft_state_free(ppb_state, instance); 455 return (DDI_FAILURE); 456 } 457 } 458 459 DEBUG1(DBG_ATTACH, devi, 460 "ppb_attach(): this nexus %s hotplug slots\n", 461 ppb->hotplug_capable == B_TRUE ? "has":"has no"); 462 463 ppb_fm_init(ppb); 464 ddi_report_dev(devi); 465 466 return (DDI_SUCCESS); 467 468 case DDI_RESUME: 469 /* 470 * Get the soft state structure for the bridge. 471 */ 472 ppb = (ppb_devstate_t *) 473 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 474 475 pci_pwr_resume(devi, ppb->ppb_pwr_p); 476 477 return (DDI_SUCCESS); 478 } 479 return (DDI_FAILURE); 480 } 481 482 /*ARGSUSED*/ 483 static int 484 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 485 { 486 ppb_devstate_t *ppb; 487 488 switch (cmd) { 489 case DDI_DETACH: 490 /* 491 * And finally free the per-pci soft state after 492 * uninitializing hotplug support for this bus. 493 */ 494 ppb = (ppb_devstate_t *) 495 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 496 497 ppb_fm_fini(ppb); 498 499 if (ppb->hotplug_capable == B_TRUE) 500 if (pcihp_uninit(devi) == DDI_FAILURE) 501 return (DDI_FAILURE); 502 else 503 ddi_remove_minor_node(devi, "devctl"); 504 505 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 506 507 if (ppb->ppb_pwr_p != NULL) { 508 ppb_pwr_teardown(ppb, devi); 509 } 510 mutex_destroy(&ppb->ppb_mutex); 511 ddi_soft_state_free(ppb_state, ddi_get_instance(devi)); 512 513 return (DDI_SUCCESS); 514 515 case DDI_SUSPEND: 516 ppb = (ppb_devstate_t *) 517 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 518 519 pci_pwr_suspend(devi, ppb->ppb_pwr_p); 520 521 return (DDI_SUCCESS); 522 } 523 return (DDI_FAILURE); 524 } 525 526 /*ARGSUSED*/ 527 static int 528 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 529 off_t offset, off_t len, caddr_t *vaddrp) 530 { 531 register dev_info_t *pdip; 532 533 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 534 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map) 535 (pdip, rdip, mp, offset, len, vaddrp)); 536 } 537 538 /*ARGSUSED*/ 539 static int 540 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip, 541 ddi_ctl_enum_t ctlop, void *arg, void *result) 542 { 543 pci_regspec_t *drv_regp; 544 int reglen; 545 int rn; 546 547 int totreg; 548 549 switch (ctlop) { 550 case DDI_CTLOPS_REPORTDEV: 551 if (rdip == (dev_info_t *)0) 552 return (DDI_FAILURE); 553 cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n", 554 ddi_node_name(rdip), ddi_get_name_addr(rdip), 555 ddi_driver_name(rdip), 556 ddi_get_instance(rdip)); 557 return (DDI_SUCCESS); 558 559 case DDI_CTLOPS_INITCHILD: 560 return (ppb_initchild((dev_info_t *)arg)); 561 562 case DDI_CTLOPS_UNINITCHILD: 563 ppb_removechild((dev_info_t *)arg); 564 return (DDI_SUCCESS); 565 566 case DDI_CTLOPS_SIDDEV: 567 return (DDI_SUCCESS); 568 569 case DDI_CTLOPS_REGSIZE: 570 case DDI_CTLOPS_NREGS: 571 if (rdip == (dev_info_t *)0) 572 return (DDI_FAILURE); 573 break; 574 default: 575 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 576 } 577 578 *(int *)result = 0; 579 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 580 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", 581 (caddr_t)&drv_regp, ®len) != DDI_SUCCESS) 582 return (DDI_FAILURE); 583 584 totreg = reglen / sizeof (pci_regspec_t); 585 if (ctlop == DDI_CTLOPS_NREGS) 586 *(int *)result = totreg; 587 else if (ctlop == DDI_CTLOPS_REGSIZE) { 588 rn = *(int *)arg; 589 if (rn >= totreg) { 590 kmem_free(drv_regp, reglen); 591 return (DDI_FAILURE); 592 } 593 *(off_t *)result = drv_regp[rn].pci_size_low | 594 ((uint64_t)drv_regp[rn].pci_size_hi << 32); 595 } 596 597 kmem_free(drv_regp, reglen); 598 return (DDI_SUCCESS); 599 } 600 601 602 static dev_info_t * 603 get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 604 { 605 dev_info_t *cdip = rdip; 606 607 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 608 ; 609 610 return (cdip); 611 } 612 613 614 static int 615 ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 616 ddi_intr_handle_impl_t *hdlp, void *result) 617 { 618 dev_info_t *cdip = rdip; 619 pci_regspec_t *pci_rp; 620 int reglen, len; 621 uint32_t d, intr; 622 623 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 624 goto done; 625 626 /* 627 * If the interrupt-map property is defined at this 628 * node, it will have performed the interrupt 629 * translation as part of the property, so no 630 * rotation needs to be done. 631 */ 632 if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 633 "interrupt-map", &len) == DDI_PROP_SUCCESS) 634 goto done; 635 636 cdip = get_my_childs_dip(dip, rdip); 637 638 /* 639 * Use the devices reg property to determine its 640 * PCI bus number and device number. 641 */ 642 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 643 "reg", (caddr_t)&pci_rp, ®len) != DDI_SUCCESS) 644 return (DDI_FAILURE); 645 646 intr = hdlp->ih_vector; 647 648 /* Spin the interrupt */ 649 d = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 650 651 if ((intr >= PCI_INTA) && (intr <= PCI_INTD)) 652 hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1); 653 else 654 cmn_err(CE_WARN, "%s%d: %s: PCI intr=%x out of range", 655 ddi_driver_name(rdip), ddi_get_instance(rdip), 656 ddi_driver_name(dip), intr); 657 658 kmem_free(pci_rp, reglen); 659 660 done: 661 /* Pass up the request to our parent. */ 662 return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result)); 663 } 664 665 static int 666 ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, 667 void *arg, void *result) 668 { 669 ppb_devstate_t *ppb; 670 671 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 672 ddi_get_instance(dip)); 673 674 return (pci_pwr_ops(ppb->ppb_pwr_p, dip, impl_arg, op, arg, result)); 675 } 676 677 678 /* 679 * name_child 680 * 681 * This function is called from init_child to name a node. It is 682 * also passed as a callback for node merging functions. 683 * 684 * return value: DDI_SUCCESS, DDI_FAILURE 685 */ 686 static int 687 ppb_name_child(dev_info_t *child, char *name, int namelen) 688 { 689 pci_regspec_t *pci_rp; 690 uint_t slot, func; 691 char **unit_addr; 692 uint_t n; 693 694 /* 695 * Pseudo nodes indicate a prototype node with per-instance 696 * properties to be merged into the real h/w device node. 697 * The interpretation of the unit-address is DD[,F] 698 * where DD is the device id and F is the function. 699 */ 700 if (ndi_dev_is_persistent_node(child) == 0) { 701 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 702 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 703 DDI_PROP_SUCCESS) { 704 cmn_err(CE_WARN, "cannot name node from %s.conf", 705 ddi_driver_name(child)); 706 return (DDI_FAILURE); 707 } 708 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 709 cmn_err(CE_WARN, "unit-address property in %s.conf" 710 " not well-formed", ddi_driver_name(child)); 711 ddi_prop_free(unit_addr); 712 return (DDI_FAILURE); 713 } 714 (void) snprintf(name, namelen, "%s", *unit_addr); 715 ddi_prop_free(unit_addr); 716 return (DDI_SUCCESS); 717 } 718 719 /* 720 * Get the address portion of the node name based on 721 * the function and device number. 722 */ 723 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 724 "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 725 return (DDI_FAILURE); 726 } 727 728 slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 729 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 730 731 if (func != 0) 732 (void) snprintf(name, namelen, "%x,%x", slot, func); 733 else 734 (void) snprintf(name, namelen, "%x", slot); 735 736 ddi_prop_free(pci_rp); 737 return (DDI_SUCCESS); 738 } 739 740 static int 741 ppb_initchild(dev_info_t *child) 742 { 743 char name[MAXNAMELEN]; 744 ddi_acc_handle_t config_handle; 745 ushort_t command_preserve, command; 746 uint_t n; 747 ushort_t bcr; 748 uchar_t header_type; 749 uchar_t min_gnt, latency_timer; 750 ppb_devstate_t *ppb; 751 752 /* 753 * Name the child 754 */ 755 if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) 756 return (DDI_FAILURE); 757 758 ddi_set_name_addr(child, name); 759 ddi_set_parent_data(child, NULL); 760 761 /* 762 * Pseudo nodes indicate a prototype node with per-instance 763 * properties to be merged into the real h/w device node. 764 * The interpretation of the unit-address is DD[,F] 765 * where DD is the device id and F is the function. 766 */ 767 if (ndi_dev_is_persistent_node(child) == 0) { 768 extern int pci_allow_pseudo_children; 769 770 /* 771 * Try to merge the properties from this prototype 772 * node into real h/w nodes. 773 */ 774 if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) { 775 /* 776 * Merged ok - return failure to remove the node. 777 */ 778 ppb_removechild(child); 779 return (DDI_FAILURE); 780 } 781 782 /* workaround for ddivs to run under PCI */ 783 if (pci_allow_pseudo_children) 784 return (DDI_SUCCESS); 785 786 /* 787 * The child was not merged into a h/w node, 788 * but there's not much we can do with it other 789 * than return failure to cause the node to be removed. 790 */ 791 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 792 ddi_driver_name(child), ddi_get_name_addr(child), 793 ddi_driver_name(child)); 794 ppb_removechild(child); 795 return (DDI_NOT_WELL_FORMED); 796 } 797 798 ddi_set_parent_data(child, NULL); 799 800 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 801 ddi_get_instance(ddi_get_parent(child))); 802 803 /* 804 * If hardware is PM capable, set up the power info structure. 805 * This also ensures the the bus will not be off (0MHz) otherwise 806 * system panics during a bus access. 807 */ 808 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 809 /* 810 * Create a pwr_info struct for child. Bus will be 811 * at full speed after creating info. 812 */ 813 pci_pwr_create_info(ppb->ppb_pwr_p, child); 814 #ifdef DEBUG 815 ASSERT(ppb->ppb_pwr_p->current_lvl == PM_LEVEL_B0); 816 #endif 817 } 818 819 /* 820 * If configuration registers were previously saved by 821 * child (before it entered D3), then let the child do the 822 * restore to set up the config regs as it'll first need to 823 * power the device out of D3. 824 */ 825 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 826 "config-regs-saved-by-child") == 1) { 827 DEBUG2(DBG_PWR, ddi_get_parent(child), 828 "INITCHILD: config regs to be restored by child" 829 " for %s@%s\n", ddi_node_name(child), 830 ddi_get_name_addr(child)); 831 832 return (DDI_SUCCESS); 833 } 834 835 DEBUG2(DBG_PWR, ddi_get_parent(child), 836 "INITCHILD: config regs setup for %s@%s\n", 837 ddi_node_name(child), ddi_get_name_addr(child)); 838 839 if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) { 840 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 841 pci_pwr_rm_info(ppb->ppb_pwr_p, child); 842 } 843 844 return (DDI_FAILURE); 845 } 846 847 /* 848 * Determine the configuration header type. 849 */ 850 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 851 852 /* 853 * Support for the "command-preserve" property. 854 */ 855 command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child, 856 DDI_PROP_DONTPASS, "command-preserve", 0); 857 command = pci_config_get16(config_handle, PCI_CONF_COMM); 858 command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB); 859 command |= (ppb_command_default & ~command_preserve); 860 pci_config_put16(config_handle, PCI_CONF_COMM, command); 861 862 /* 863 * If the device has a bus control register then program it 864 * based on the settings in the command register. 865 */ 866 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 867 bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL); 868 if (ppb_command_default & PCI_COMM_PARITY_DETECT) 869 bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 870 if (ppb_command_default & PCI_COMM_SERR_ENABLE) 871 bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE; 872 bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE; 873 pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr); 874 } 875 876 /* 877 * Initialize cache-line-size configuration register if needed. 878 */ 879 if (ppb_set_cache_line_size_register && 880 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 881 "cache-line-size", 0) == 0) { 882 pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ, 883 ppb->ppb_cache_line_size); 884 n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 885 if (n != 0) { 886 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 887 "cache-line-size", n); 888 } 889 } 890 891 /* 892 * Initialize latency timer configuration registers if needed. 893 */ 894 if (ppb_set_latency_timer_register && 895 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 896 "latency-timer", 0) == 0) { 897 898 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 899 latency_timer = ppb->ppb_latency_timer; 900 pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER, 901 ppb->ppb_latency_timer); 902 } else { 903 min_gnt = pci_config_get8(config_handle, 904 PCI_CONF_MIN_G); 905 latency_timer = min_gnt * 8; 906 } 907 pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER, 908 latency_timer); 909 n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 910 if (n != 0) { 911 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 912 "latency-timer", n); 913 } 914 } 915 916 /* 917 * Check to see if the XMITS/PCI-X workaround applies. 918 */ 919 n = ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_NOTPROM, 920 "pcix-update-cmd-reg", -1); 921 922 if (n != -1) { 923 extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value); 924 DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ " 925 "Workaround: value = %x\n", n); 926 pcix_set_cmd_reg(child, n); 927 } 928 929 pci_config_teardown(&config_handle); 930 931 return (DDI_SUCCESS); 932 } 933 934 static void 935 ppb_removechild(dev_info_t *dip) 936 { 937 ppb_devstate_t *ppb; 938 939 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 940 ddi_get_instance(ddi_get_parent(dip))); 941 942 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 943 944 DEBUG2(DBG_PWR, ddi_get_parent(dip), 945 "UNINITCHILD: removing pwr_info for %s@%s\n", 946 ddi_node_name(dip), ddi_get_name_addr(dip)); 947 pci_pwr_rm_info(ppb->ppb_pwr_p, dip); 948 } 949 950 ddi_set_name_addr(dip, NULL); 951 952 /* 953 * Strip the node to properly convert it back to prototype form 954 */ 955 ddi_remove_minor_node(dip, NULL); 956 957 impl_rem_dev_props(dip); 958 } 959 960 /* 961 * If bridge is PM capable, set up PM state for nexus. 962 */ 963 static void 964 ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip) 965 { 966 char *comp_array[5]; 967 int i; 968 ddi_acc_handle_t conf_hdl; 969 uint8_t pmcsr_bse; 970 uint16_t pmcap; 971 972 /* 973 * Determine if bridge is PM capable. If not, leave ppb_pwr_p NULL 974 * and return. 975 */ 976 if (pci_config_setup(pdip, &ppb->ppb_conf_hdl) != DDI_SUCCESS) { 977 978 return; 979 } 980 981 conf_hdl = ppb->ppb_conf_hdl; 982 983 /* 984 * Locate and store the power management cap_ptr for future references. 985 */ 986 if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &ppb->ppb_pm_cap_ptr)) 987 == DDI_FAILURE) { 988 DEBUG0(DBG_PWR, pdip, "bridge does not support PM. PCI" 989 " PM data structure not found in config header\n"); 990 pci_config_teardown(&conf_hdl); 991 992 return; 993 } 994 995 /* 996 * Allocate PM state structure for ppb. 997 */ 998 ppb->ppb_pwr_p = (pci_pwr_t *) 999 kmem_zalloc(sizeof (pci_pwr_t), KM_SLEEP); 1000 ppb->ppb_pwr_p->pwr_fp = 0; 1001 1002 pmcsr_bse = PCI_CAP_GET8(conf_hdl, NULL, ppb->ppb_pm_cap_ptr, 1003 PCI_PMCSR_BSE); 1004 1005 pmcap = PCI_CAP_GET16(conf_hdl, NULL, ppb->ppb_pm_cap_ptr, 1006 PCI_PMCAP); 1007 1008 if (pmcap == PCI_CAP_EINVAL16 || pmcsr_bse == PCI_CAP_EINVAL8) { 1009 pci_config_teardown(&conf_hdl); 1010 return; 1011 } 1012 1013 if (pmcap & PCI_PMCAP_D1) { 1014 DEBUG0(DBG_PWR, pdip, "setup: B1 state supported\n"); 1015 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B1_CAPABLE; 1016 } else { 1017 DEBUG0(DBG_PWR, pdip, "setup: B1 state NOT supported\n"); 1018 } 1019 if (pmcap & PCI_PMCAP_D2) { 1020 DEBUG0(DBG_PWR, pdip, "setup: B2 state supported\n"); 1021 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE; 1022 } else { 1023 DEBUG0(DBG_PWR, pdip, "setup: B2 via D2 NOT supported\n"); 1024 } 1025 1026 if (pmcsr_bse & PCI_PMCSR_BSE_BPCC_EN) { 1027 DEBUG0(DBG_PWR, pdip, 1028 "setup: bridge power/clock control enable\n"); 1029 } else { 1030 DEBUG0(DBG_PWR, pdip, 1031 "setup: bridge power/clock control disabled\n"); 1032 1033 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1034 ppb->ppb_pwr_p = NULL; 1035 pci_config_teardown(&conf_hdl); 1036 1037 return; 1038 } 1039 1040 /* 1041 * PCI states D0 and D3 always are supported for normal PCI 1042 * devices. D1 and D2 are optional which are checked for above. 1043 * Bridge function states D0-D3 correspond to secondary bus states 1044 * B0-B3, EXCEPT if PCI_PMCSR_BSE_B2_B3 is set. In this case, setting 1045 * the bridge function to D3 will set the bridge bus to state B2 instead 1046 * of B3. D2 will not correspond to B2 (and in fact, probably 1047 * won't be D2 capable). Implicitly, this means that if 1048 * PCI_PMCSR_BSE_B2_B3 is set, the bus will not be B3 capable. 1049 */ 1050 if (pmcsr_bse & PCI_PMCSR_BSE_B2_B3) { 1051 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE; 1052 DEBUG0(DBG_PWR, pdip, "B2 supported via D3\n"); 1053 } else { 1054 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B3_CAPABLE; 1055 DEBUG0(DBG_PWR, pdip, "B3 supported via D3\n"); 1056 } 1057 1058 ppb->ppb_pwr_p->pwr_dip = pdip; 1059 mutex_init(&ppb->ppb_pwr_p->pwr_mutex, NULL, MUTEX_DRIVER, NULL); 1060 1061 i = 0; 1062 comp_array[i++] = "NAME=PCI bridge PM"; 1063 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) { 1064 comp_array[i++] = "0=Clock/Power Off (B3)"; 1065 } 1066 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) { 1067 comp_array[i++] = "1=Clock Off (B2)"; 1068 } 1069 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) { 1070 comp_array[i++] = "2=Bus Inactive (B1)"; 1071 } 1072 comp_array[i++] = "3=Full Power (B0)"; 1073 1074 /* 1075 * Create pm-components property. It does not already exist. 1076 */ 1077 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, pdip, 1078 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) { 1079 cmn_err(CE_WARN, 1080 "%s%d pm-components prop update failed", 1081 ddi_driver_name(pdip), ddi_get_instance(pdip)); 1082 pci_config_teardown(&conf_hdl); 1083 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1084 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1085 ppb->ppb_pwr_p = NULL; 1086 1087 return; 1088 } 1089 1090 if (ddi_prop_create(DDI_DEV_T_NONE, pdip, DDI_PROP_CANSLEEP, 1091 "pm-want-child-notification?", NULL, NULL) != DDI_PROP_SUCCESS) { 1092 cmn_err(CE_WARN, 1093 "%s%d fail to create pm-want-child-notification? prop", 1094 ddi_driver_name(pdip), ddi_get_instance(pdip)); 1095 1096 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, "pm-components"); 1097 pci_config_teardown(&conf_hdl); 1098 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1099 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1100 ppb->ppb_pwr_p = NULL; 1101 1102 return; 1103 } 1104 1105 ppb->ppb_pwr_p->current_lvl = 1106 pci_pwr_current_lvl(ppb->ppb_pwr_p); 1107 } 1108 1109 /* 1110 * Remove PM state for nexus. 1111 */ 1112 static void 1113 ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip) 1114 { 1115 int low_lvl; 1116 1117 /* 1118 * Determine the lowest power level supported. 1119 */ 1120 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) { 1121 low_lvl = PM_LEVEL_B3; 1122 } else { 1123 low_lvl = PM_LEVEL_B2; 1124 } 1125 1126 if (pm_lower_power(dip, PCI_PM_COMP_0, low_lvl) != DDI_SUCCESS) { 1127 cmn_err(CE_WARN, "%s%d failed to lower power", 1128 ddi_driver_name(dip), ddi_get_instance(dip)); 1129 } 1130 1131 pci_config_teardown(&ppb->ppb_conf_hdl); 1132 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1133 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1134 1135 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components") != 1136 DDI_PROP_SUCCESS) { 1137 cmn_err(CE_WARN, "%s%d unable to remove prop pm-components", 1138 ddi_driver_name(dip), ddi_get_instance(dip)); 1139 } 1140 1141 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, 1142 "pm-want-child-notification?") != DDI_PROP_SUCCESS) { 1143 cmn_err(CE_WARN, 1144 "%s%d unable to remove prop pm-want_child_notification?", 1145 ddi_driver_name(dip), ddi_get_instance(dip)); 1146 } 1147 } 1148 1149 /* 1150 * Examine the pmcsr register and return the software defined 1151 * state (the difference being whether D3 means B2 or B3). 1152 */ 1153 int 1154 pci_pwr_current_lvl(pci_pwr_t *pwr_p) 1155 { 1156 ppb_devstate_t *ppb; 1157 uint16_t pmcsr; 1158 1159 /* 1160 * Find out current power level 1161 */ 1162 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1163 ddi_get_instance(pwr_p->pwr_dip)); 1164 1165 if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL, 1166 ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16) 1167 return (DDI_FAILURE); 1168 1169 switch (pmcsr & PCI_PMCSR_STATE_MASK) { 1170 case PCI_PMCSR_D0: 1171 1172 return (PM_LEVEL_B0); 1173 case PCI_PMCSR_D1: 1174 1175 return (PM_LEVEL_B1); 1176 case PCI_PMCSR_D2: 1177 1178 return (PM_LEVEL_B2); 1179 case PCI_PMCSR_D3HOT: 1180 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1181 1182 return (PM_LEVEL_B2); 1183 } else { 1184 1185 return (PM_LEVEL_B3); 1186 } 1187 } 1188 /*NOTREACHED*/ 1189 return (PM_LEVEL_B3); 1190 } 1191 1192 /* 1193 * Power entry point. Called by the PM framework to change the 1194 * current power state of the bus. This function must first verify that 1195 * the requested power change is still valid. 1196 */ 1197 /*ARGSUSED*/ 1198 static int 1199 ppb_pwr(dev_info_t *dip, int component, int lvl) 1200 { 1201 ppb_devstate_t *ppb; 1202 uint16_t pmcsr; 1203 char *str; 1204 int lowest_lvl; 1205 int old_lvl; 1206 int new_lvl; 1207 1208 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1209 ddi_get_instance(dip)); 1210 if (ppb == NULL) { 1211 cmn_err(CE_WARN, "%s%d ppb_pwr: can't get soft state", 1212 ddi_driver_name(dip), ddi_get_instance(dip)); 1213 1214 return (DDI_FAILURE); 1215 } 1216 1217 DEBUG1(DBG_PWR, dip, "ppb_pwr(): ENTER level = %d\n", lvl); 1218 1219 mutex_enter(&ppb->ppb_pwr_p->pwr_mutex); 1220 1221 /* 1222 * Find out if the power setting is possible. If it is not, 1223 * set component busy and return failure. If it is possible, 1224 * and it is the lowest pwr setting possible, set component 1225 * busy so that the framework does not try to lower any further. 1226 */ 1227 lowest_lvl = pci_pwr_new_lvl(ppb->ppb_pwr_p); 1228 if (lowest_lvl > lvl) { 1229 pci_pwr_component_busy(ppb->ppb_pwr_p); 1230 DEBUG2(DBG_PWR, dip, "ppb_pwr: failing power request " 1231 "lowest allowed is %d requested is %d\n", 1232 lowest_lvl, lvl); 1233 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1234 1235 return (DDI_FAILURE); 1236 } else if (lowest_lvl == lvl) { 1237 pci_pwr_component_busy(ppb->ppb_pwr_p); 1238 } else { 1239 pci_pwr_component_idle(ppb->ppb_pwr_p); 1240 } 1241 1242 if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL, 1243 ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16) 1244 return (DDI_FAILURE); 1245 1246 /* 1247 * Save the current power level. This is the actual function level, 1248 * not the translated bridge level stored in pwr_p->current_lvl 1249 */ 1250 old_lvl = pmcsr & PCI_PMCSR_STATE_MASK; 1251 1252 pmcsr &= ~PCI_PMCSR_STATE_MASK; 1253 switch (lvl) { 1254 case PM_LEVEL_B0: 1255 str = "PM_LEVEL_B0 (full speed)"; 1256 pmcsr |= PCI_PMCSR_D0; 1257 break; 1258 case PM_LEVEL_B1: 1259 str = "PM_LEVEL_B1 (light sleep. No bus traffic allowed)"; 1260 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) == 0) { 1261 cmn_err(CE_WARN, "%s%d PCI PM state B1 not supported", 1262 ddi_driver_name(dip), ddi_get_instance(dip)); 1263 1264 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1265 return (DDI_FAILURE); 1266 } 1267 pmcsr |= PCI_PMCSR_D1; 1268 break; 1269 case PM_LEVEL_B2: 1270 str = "PM_LEVEL_B2 (clock off)"; 1271 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) == 0) { 1272 cmn_err(CE_WARN, "%s%d PM state B2 not supported...", 1273 ddi_driver_name(dip), 1274 ddi_get_instance(dip)); 1275 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1276 1277 return (DDI_FAILURE); 1278 } 1279 1280 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1281 /* 1282 * If B3 isn't supported, use D3 for B2 to avoid the 1283 * possible case that D2 for B2 isn't supported. 1284 * Saves and extra check and state flag.. 1285 */ 1286 pmcsr |= PCI_PMCSR_D3HOT; 1287 } else { 1288 pmcsr |= PCI_PMCSR_D2; 1289 } 1290 break; 1291 case PM_LEVEL_B3: 1292 str = "PM_LEVEL_B30 (clock and power off)"; 1293 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1294 cmn_err(CE_WARN, "%s%d PM state B3 not supported...", 1295 ddi_driver_name(dip), 1296 ddi_get_instance(dip)); 1297 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1298 1299 return (DDI_FAILURE); 1300 } 1301 pmcsr |= PCI_PMCSR_D3HOT; 1302 1303 break; 1304 1305 default: 1306 cmn_err(CE_WARN, "%s%d Unknown PM state %d", 1307 ddi_driver_name(dip), ddi_get_instance(dip), lvl); 1308 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1309 1310 return (DDI_FAILURE); 1311 } 1312 1313 new_lvl = pmcsr & PCI_PMCSR_STATE_MASK; 1314 1315 /* 1316 * Save config regs if going into HW state D3 (B2 or B3) 1317 */ 1318 if ((old_lvl != PCI_PMCSR_D3HOT) && (new_lvl == PCI_PMCSR_D3HOT)) { 1319 DEBUG0(DBG_PWR, dip, "ppb_pwr(): SAVING CONFIG REGS\n"); 1320 if (pci_save_config_regs(dip) != DDI_SUCCESS) { 1321 cmn_err(CE_WARN, "%s%d Save config regs failed", 1322 ddi_driver_name(dip), ddi_get_instance(dip)); 1323 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1324 1325 return (DDI_FAILURE); 1326 } 1327 } 1328 1329 PCI_CAP_PUT16(ppb->ppb_conf_hdl, NULL, ppb->ppb_pm_cap_ptr, PCI_PMCSR, 1330 pmcsr); 1331 1332 /* 1333 * No bus transactions should occur without waiting for 1334 * settle time specified in PCI PM spec rev 2.1 sec 5.6.1 1335 * To make things simple, just use the max time specified for 1336 * all state transitions. 1337 */ 1338 delay(drv_usectohz(PCI_CLK_SETTLE_TIME)); 1339 1340 /* 1341 * Restore configuration registers if coming out of HW state D3 1342 */ 1343 if ((old_lvl == PCI_PMCSR_D3HOT) && (new_lvl != PCI_PMCSR_D3HOT)) { 1344 DEBUG0(DBG_PWR, dip, "ppb_pwr(): RESTORING CONFIG REGS\n"); 1345 if (pci_restore_config_regs(dip) != DDI_SUCCESS) { 1346 panic("%s%d restore config regs failed", 1347 ddi_driver_name(dip), ddi_get_instance(dip)); 1348 } 1349 /*NOTREACHED*/ 1350 } 1351 1352 ppb->ppb_pwr_p->current_lvl = lvl; 1353 1354 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1355 1356 DEBUG1(DBG_PWR, dip, "ppb_set_pwr: set PM state to %s\n\n", str); 1357 1358 return (DDI_SUCCESS); 1359 } 1360 1361 /* 1362 * Initialize hotplug framework if we are hotpluggable. 1363 * Sets flag in the soft state if Hot Plug is supported and initialized 1364 * properly. 1365 */ 1366 /*ARGSUSED*/ 1367 static void 1368 ppb_init_hotplug(ppb_devstate_t *ppb) 1369 { 1370 if (ddi_prop_exists(DDI_DEV_T_ANY, ppb->dip, DDI_PROP_DONTPASS, 1371 "hotplug-capable")) { 1372 (void) modload("misc", "pcihp"); 1373 1374 if (pcihp_init(ppb->dip) != DDI_SUCCESS) { 1375 cmn_err(CE_WARN, 1376 "%s #%d: Failed setting hotplug framework", 1377 ddi_driver_name(ppb->dip), 1378 ddi_get_instance(ppb->dip)); 1379 } else 1380 ppb->hotplug_capable = B_TRUE; 1381 } 1382 1383 } 1384 1385 static void 1386 ppb_create_ranges_prop(dev_info_t *dip, 1387 ddi_acc_handle_t config_handle) 1388 { 1389 uint32_t base, limit; 1390 ppb_ranges_t ranges[PPB_RANGE_LEN]; 1391 uint8_t io_base_lo, io_limit_lo; 1392 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit; 1393 int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int); 1394 1395 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW); 1396 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW); 1397 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI); 1398 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI); 1399 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE); 1400 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT); 1401 1402 /* 1403 * Create ranges for IO space 1404 */ 1405 ranges[i].size_low = ranges[i].size_high = 0; 1406 ranges[i].parent_mid = ranges[i].child_mid = 1407 ranges[i].parent_high = 0; 1408 ranges[i].child_high = ranges[i].parent_high |= 1409 (PCI_REG_REL_M | PCI_ADDR_IO); 1410 base = PPB_16bit_IOADDR(io_base_lo); 1411 limit = PPB_16bit_IOADDR(io_limit_lo); 1412 1413 if ((io_base_lo & 0xf) == PPB_32BIT_IO) { 1414 base = PPB_LADDR(base, io_base_hi); 1415 } 1416 if ((io_limit_lo & 0xf) == PPB_32BIT_IO) { 1417 limit = PPB_LADDR(limit, io_limit_hi); 1418 } 1419 1420 if ((io_base_lo & PPB_32BIT_IO) && (io_limit_hi > 0)) { 1421 base = PPB_LADDR(base, io_base_hi); 1422 limit = PPB_LADDR(limit, io_limit_hi); 1423 } 1424 1425 /* 1426 * Create ranges for 32bit memory space 1427 */ 1428 base = PPB_32bit_MEMADDR(mem_base); 1429 limit = PPB_32bit_MEMADDR(mem_limit); 1430 ranges[i].size_low = ranges[i].size_high = 0; 1431 ranges[i].parent_mid = ranges[i].child_mid = 1432 ranges[i].parent_high = 0; 1433 ranges[i].child_high = ranges[i].parent_high |= 1434 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1435 ranges[i].child_low = ranges[i].parent_low = base; 1436 if (limit >= base) { 1437 ranges[i].size_low = limit - base + PPB_MEMGRAIN; 1438 i++; 1439 } 1440 1441 if (i) { 1442 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 1443 (int *)ranges, i * rangelen); 1444 } 1445 } 1446 1447 /* ARGSUSED */ 1448 static int 1449 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 1450 { 1451 ppb_devstate_t *ppb_p; 1452 minor_t minor = getminor(*devp); 1453 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1454 1455 /* 1456 * Make sure the open is for the right file type. 1457 */ 1458 if (otyp != OTYP_CHR) 1459 return (EINVAL); 1460 1461 /* 1462 * Get the soft state structure for the device. 1463 */ 1464 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1465 instance); 1466 1467 if (ppb_p == NULL) 1468 return (ENXIO); 1469 1470 if (ppb_p->hotplug_capable == B_TRUE) 1471 return ((pcihp_get_cb_ops())->cb_open(devp, flags, 1472 otyp, credp)); 1473 1474 /* 1475 * Handle the open by tracking the device state. 1476 */ 1477 mutex_enter(&ppb_p->ppb_mutex); 1478 if (flags & FEXCL) { 1479 if (ppb_p->ppb_soft_state != PPB_SOFT_STATE_CLOSED) { 1480 mutex_exit(&ppb_p->ppb_mutex); 1481 return (EBUSY); 1482 } 1483 ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN_EXCL; 1484 } else { 1485 if (ppb_p->ppb_soft_state == PPB_SOFT_STATE_OPEN_EXCL) { 1486 mutex_exit(&ppb_p->ppb_mutex); 1487 return (EBUSY); 1488 } 1489 ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN; 1490 } 1491 mutex_exit(&ppb_p->ppb_mutex); 1492 return (0); 1493 } 1494 1495 1496 /* ARGSUSED */ 1497 static int 1498 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp) 1499 { 1500 ppb_devstate_t *ppb_p; 1501 minor_t minor = getminor(dev); 1502 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1503 1504 if (otyp != OTYP_CHR) 1505 return (EINVAL); 1506 1507 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1508 instance); 1509 1510 if (ppb_p == NULL) 1511 return (ENXIO); 1512 1513 if (ppb_p->hotplug_capable == B_TRUE) 1514 return ((pcihp_get_cb_ops())->cb_close(dev, flags, 1515 otyp, credp)); 1516 1517 mutex_enter(&ppb_p->ppb_mutex); 1518 ppb_p->ppb_soft_state = PPB_SOFT_STATE_CLOSED; 1519 mutex_exit(&ppb_p->ppb_mutex); 1520 return (0); 1521 } 1522 1523 1524 /* 1525 * ppb_ioctl: devctl hotplug controls 1526 */ 1527 /* ARGSUSED */ 1528 static int 1529 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1530 int *rvalp) 1531 { 1532 ppb_devstate_t *ppb_p; 1533 dev_info_t *self; 1534 struct devctl_iocdata *dcp; 1535 uint_t bus_state; 1536 int rv = 0; 1537 minor_t minor = getminor(dev); 1538 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1539 1540 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1541 instance); 1542 1543 if (ppb_p == NULL) 1544 return (ENXIO); 1545 1546 if (ppb_p->hotplug_capable == B_TRUE) 1547 return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, 1548 arg, mode, credp, rvalp)); 1549 1550 self = ppb_p->dip; 1551 1552 /* 1553 * We can use the generic implementation for these ioctls 1554 */ 1555 switch (cmd) { 1556 case DEVCTL_DEVICE_GETSTATE: 1557 case DEVCTL_DEVICE_ONLINE: 1558 case DEVCTL_DEVICE_OFFLINE: 1559 case DEVCTL_BUS_GETSTATE: 1560 return (ndi_devctl_ioctl(self, cmd, arg, mode, 0)); 1561 } 1562 1563 /* 1564 * read devctl ioctl data 1565 */ 1566 if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) 1567 return (EFAULT); 1568 1569 switch (cmd) { 1570 1571 case DEVCTL_DEVICE_RESET: 1572 rv = ENOTSUP; 1573 break; 1574 1575 case DEVCTL_BUS_QUIESCE: 1576 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1577 if (bus_state == BUS_QUIESCED) 1578 break; 1579 (void) ndi_set_bus_state(self, BUS_QUIESCED); 1580 break; 1581 1582 case DEVCTL_BUS_UNQUIESCE: 1583 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1584 if (bus_state == BUS_ACTIVE) 1585 break; 1586 (void) ndi_set_bus_state(self, BUS_ACTIVE); 1587 break; 1588 1589 case DEVCTL_BUS_RESET: 1590 rv = ENOTSUP; 1591 break; 1592 1593 case DEVCTL_BUS_RESETALL: 1594 rv = ENOTSUP; 1595 break; 1596 1597 default: 1598 rv = ENOTTY; 1599 } 1600 1601 ndi_dc_freehdl(dcp); 1602 return (rv); 1603 } 1604 1605 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 1606 int flags, char *name, caddr_t valuep, int *lengthp) 1607 { 1608 ppb_devstate_t *ppb_p; 1609 minor_t minor = getminor(dev); 1610 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1611 1612 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1613 instance); 1614 1615 if (ppb_p == NULL) 1616 return (ENXIO); 1617 1618 if (ppb_p->hotplug_capable == B_TRUE) 1619 return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, 1620 flags, name, valuep, lengthp)); 1621 1622 return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp)); 1623 } 1624 1625 /* 1626 * Initialize our FMA resources 1627 */ 1628 static void 1629 ppb_fm_init(ppb_devstate_t *ppb_p) 1630 { 1631 ppb_p->fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 1632 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 1633 1634 /* 1635 * Request our capability level and get our parents capability 1636 * and ibc. 1637 */ 1638 ddi_fm_init(ppb_p->dip, &ppb_p->fm_cap, &ppb_p->fm_ibc); 1639 ASSERT((ppb_p->fm_cap & DDI_FM_EREPORT_CAPABLE) && 1640 (ppb_p->fm_cap & DDI_FM_ERRCB_CAPABLE)); 1641 1642 pci_ereport_setup(ppb_p->dip); 1643 1644 /* 1645 * Register error callback with our parent. 1646 */ 1647 ddi_fm_handler_register(ppb_p->dip, ppb_err_callback, NULL); 1648 } 1649 1650 /* 1651 * Breakdown our FMA resources 1652 */ 1653 static void 1654 ppb_fm_fini(ppb_devstate_t *ppb_p) 1655 { 1656 /* 1657 * Clean up allocated fm structures 1658 */ 1659 ddi_fm_handler_unregister(ppb_p->dip); 1660 pci_ereport_teardown(ppb_p->dip); 1661 ddi_fm_fini(ppb_p->dip); 1662 } 1663 1664 /* 1665 * Initialize FMA resources for children devices. Called when 1666 * child calls ddi_fm_init(). 1667 */ 1668 /*ARGSUSED*/ 1669 static int 1670 ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 1671 ddi_iblock_cookie_t *ibc) 1672 { 1673 ppb_devstate_t *ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1674 ddi_get_instance(dip)); 1675 *ibc = ppb_p->fm_ibc; 1676 return (ppb_p->fm_cap); 1677 } 1678 1679 /* 1680 * FMA registered error callback 1681 */ 1682 static int 1683 ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data) 1684 { 1685 ASSERT(impl_data == NULL); 1686 pci_ereport_post(dip, derr, NULL); 1687 return (derr->fme_status); 1688 } 1689 1690 static void 1691 ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle) 1692 { 1693 i_ndi_busop_access_enter(dip, handle); 1694 } 1695 1696 /* ARGSUSED */ 1697 static void 1698 ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle) 1699 { 1700 i_ndi_busop_access_exit(dip, handle); 1701 } 1702