1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/ddi.h> 32 #include <sys/sysmacros.h> 33 #include <sys/archsystm.h> 34 #include <sys/vmsystm.h> 35 #include <sys/machparam.h> 36 #include <sys/machsystm.h> 37 #include <sys/machthread.h> 38 #include <sys/cpu.h> 39 #include <sys/cmp.h> 40 #include <sys/elf_SPARC.h> 41 #include <vm/hat_sfmmu.h> 42 #include <vm/seg_kmem.h> 43 #include <sys/cpuvar.h> 44 #include <sys/cheetahregs.h> 45 #include <sys/us3_module.h> 46 #include <sys/async.h> 47 #include <sys/cmn_err.h> 48 #include <sys/debug.h> 49 #include <sys/dditypes.h> 50 #include <sys/prom_debug.h> 51 #include <sys/prom_plat.h> 52 #include <sys/cpu_module.h> 53 #include <sys/sysmacros.h> 54 #include <sys/intreg.h> 55 #include <sys/clock.h> 56 #include <sys/platform_module.h> 57 #include <sys/machtrap.h> 58 #include <sys/ontrap.h> 59 #include <sys/panic.h> 60 #include <sys/memlist.h> 61 #include <sys/bootconf.h> 62 #include <sys/ivintr.h> 63 #include <sys/atomic.h> 64 #include <sys/fm/protocol.h> 65 #include <sys/fm/cpu/UltraSPARC-III.h> 66 #include <sys/fm/util.h> 67 68 #ifdef CHEETAHPLUS_ERRATUM_25 69 #include <sys/cyclic.h> 70 #endif /* CHEETAHPLUS_ERRATUM_25 */ 71 72 /* 73 * See comment above cpu_scrub_cpu_setup() for description 74 */ 75 #define SCRUBBER_NEITHER_CORE_ONLINE 0x0 76 #define SCRUBBER_CORE_0_ONLINE 0x1 77 #define SCRUBBER_CORE_1_ONLINE 0x2 78 #define SCRUBBER_BOTH_CORES_ONLINE (SCRUBBER_CORE_0_ONLINE | \ 79 SCRUBBER_CORE_1_ONLINE) 80 81 static int pn_matching_valid_l2_line(uint64_t faddr, ch_ec_data_t *clo_l2_data); 82 static void cpu_async_log_tlb_parity_err(void *flt); 83 static cpu_t *cpu_get_sibling_core(cpu_t *cpup); 84 85 86 /* 87 * Setup trap handlers. 88 */ 89 void 90 cpu_init_trap(void) 91 { 92 CH_SET_TRAP(tt_pil15, ch_pil15_interrupt_instr); 93 94 CH_SET_TRAP(tt0_fecc, fecc_err_instr); 95 CH_SET_TRAP(tt1_fecc, fecc_err_tl1_instr); 96 CH_SET_TRAP(tt1_swtrap0, fecc_err_tl1_cont_instr); 97 98 CH_SET_TRAP(tt0_dperr, dcache_parity_instr); 99 CH_SET_TRAP(tt1_dperr, dcache_parity_tl1_instr); 100 CH_SET_TRAP(tt1_swtrap1, dcache_parity_tl1_cont_instr); 101 102 CH_SET_TRAP(tt0_iperr, icache_parity_instr); 103 CH_SET_TRAP(tt1_iperr, icache_parity_tl1_instr); 104 CH_SET_TRAP(tt1_swtrap2, icache_parity_tl1_cont_instr); 105 } 106 107 /* 108 * Set the magic constants of the implementation. 109 */ 110 /*ARGSUSED*/ 111 void 112 cpu_fiximp(pnode_t dnode) 113 { 114 int i, a; 115 extern int vac_size, vac_shift; 116 extern uint_t vac_mask; 117 118 dcache_size = CH_DCACHE_SIZE; 119 dcache_linesize = CH_DCACHE_LSIZE; 120 121 icache_size = CHP_ICACHE_MAX_SIZE; 122 icache_linesize = CHP_ICACHE_MIN_LSIZE; 123 124 ecache_size = CH_ECACHE_MAX_SIZE; 125 ecache_alignsize = CH_ECACHE_MAX_LSIZE; 126 ecache_associativity = CHP_ECACHE_MIN_NWAY; 127 128 /* 129 * ecache_setsize needs to maximum of all cpu ecache setsizes 130 */ 131 ecache_setsize = CHP_ECACHE_MAX_SETSIZE; 132 ASSERT(ecache_setsize >= (ecache_size / ecache_associativity)); 133 134 vac_size = CH_VAC_SIZE; 135 vac_mask = MMU_PAGEMASK & (vac_size - 1); 136 i = 0; a = vac_size; 137 while (a >>= 1) 138 ++i; 139 vac_shift = i; 140 shm_alignment = vac_size; 141 vac = 1; 142 } 143 144 /* 145 * Use Panther values for Panther-only domains. 146 * See Panther PRM, 1.5.4 Cache Hierarchy 147 */ 148 void 149 cpu_fix_allpanther(void) 150 { 151 /* dcache same as Ch+ */ 152 icache_size = PN_ICACHE_SIZE; 153 icache_linesize = PN_ICACHE_LSIZE; 154 ecache_size = PN_L3_SIZE; 155 ecache_alignsize = PN_L3_LINESIZE; 156 ecache_associativity = PN_L3_NWAYS; 157 ecache_setsize = PN_L3_SET_SIZE; 158 ASSERT(ecache_setsize >= (ecache_size / ecache_associativity)); 159 /* vac same as Ch+ */ 160 /* fix hwcaps for USIV+-only domains */ 161 cpu_hwcap_flags |= AV_SPARC_POPC; 162 } 163 164 void 165 send_mondo_set(cpuset_t set) 166 { 167 int lo, busy, nack, shipped = 0; 168 uint16_t i, cpuids[IDSR_BN_SETS]; 169 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 170 uint64_t starttick, endtick, tick, lasttick; 171 #if (NCPU > IDSR_BN_SETS) 172 int index = 0; 173 int ncpuids = 0; 174 #endif 175 #ifdef CHEETAHPLUS_ERRATUM_25 176 int recovered = 0; 177 int cpuid; 178 #endif 179 180 ASSERT(!CPUSET_ISNULL(set)); 181 starttick = lasttick = gettick(); 182 183 #if (NCPU <= IDSR_BN_SETS) 184 for (i = 0; i < NCPU; i++) 185 if (CPU_IN_SET(set, i)) { 186 shipit(i, shipped); 187 nackmask |= IDSR_NACK_BIT(shipped); 188 cpuids[shipped++] = i; 189 CPUSET_DEL(set, i); 190 if (CPUSET_ISNULL(set)) 191 break; 192 } 193 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 194 #else 195 for (i = 0; i < NCPU; i++) 196 if (CPU_IN_SET(set, i)) { 197 ncpuids++; 198 199 /* 200 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 201 * find we have shipped to more than (IDSR_BN_SETS) 202 * CPUs, set "index" to the highest numbered CPU in 203 * the set so we can ship to other CPUs a bit later on. 204 */ 205 if (shipped < IDSR_BN_SETS) { 206 shipit(i, shipped); 207 nackmask |= IDSR_NACK_BIT(shipped); 208 cpuids[shipped++] = i; 209 CPUSET_DEL(set, i); 210 if (CPUSET_ISNULL(set)) 211 break; 212 } else 213 index = (int)i; 214 } 215 216 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 217 #endif 218 219 busymask = IDSR_NACK_TO_BUSY(nackmask); 220 busy = nack = 0; 221 endtick = starttick + xc_tick_limit; 222 for (;;) { 223 idsr = getidsr(); 224 #if (NCPU <= IDSR_BN_SETS) 225 if (idsr == 0) 226 break; 227 #else 228 if (idsr == 0 && shipped == ncpuids) 229 break; 230 #endif 231 tick = gettick(); 232 /* 233 * If there is a big jump between the current tick 234 * count and lasttick, we have probably hit a break 235 * point. Adjust endtick accordingly to avoid panic. 236 */ 237 if (tick > (lasttick + xc_tick_jump_limit)) 238 endtick += (tick - lasttick); 239 lasttick = tick; 240 if (tick > endtick) { 241 if (panic_quiesce) 242 return; 243 #ifdef CHEETAHPLUS_ERRATUM_25 244 cpuid = -1; 245 for (i = 0; i < IDSR_BN_SETS; i++) { 246 if (idsr & (IDSR_NACK_BIT(i) | 247 IDSR_BUSY_BIT(i))) { 248 cpuid = cpuids[i]; 249 break; 250 } 251 } 252 if (cheetah_sendmondo_recover && cpuid != -1 && 253 recovered == 0) { 254 if (mondo_recover(cpuid, i)) { 255 /* 256 * We claimed the whole memory or 257 * full scan is disabled. 258 */ 259 recovered++; 260 } 261 tick = gettick(); 262 endtick = tick + xc_tick_limit; 263 lasttick = tick; 264 /* 265 * Recheck idsr 266 */ 267 continue; 268 } else 269 #endif /* CHEETAHPLUS_ERRATUM_25 */ 270 { 271 cmn_err(CE_CONT, "send mondo timeout " 272 "[%d NACK %d BUSY]\nIDSR 0x%" 273 "" PRIx64 " cpuids:", nack, busy, idsr); 274 for (i = 0; i < IDSR_BN_SETS; i++) { 275 if (idsr & (IDSR_NACK_BIT(i) | 276 IDSR_BUSY_BIT(i))) { 277 cmn_err(CE_CONT, " 0x%x", 278 cpuids[i]); 279 } 280 } 281 cmn_err(CE_CONT, "\n"); 282 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 283 } 284 } 285 curnack = idsr & nackmask; 286 curbusy = idsr & busymask; 287 #if (NCPU > IDSR_BN_SETS) 288 if (shipped < ncpuids) { 289 uint64_t cpus_left; 290 uint16_t next = (uint16_t)index; 291 292 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 293 busymask; 294 295 if (cpus_left) { 296 do { 297 /* 298 * Sequence through and ship to the 299 * remainder of the CPUs in the system 300 * (e.g. other than the first 301 * (IDSR_BN_SETS)) in reverse order. 302 */ 303 lo = lowbit(cpus_left) - 1; 304 i = IDSR_BUSY_IDX(lo); 305 shipit(next, i); 306 shipped++; 307 cpuids[i] = next; 308 309 /* 310 * If we've processed all the CPUs, 311 * exit the loop now and save 312 * instructions. 313 */ 314 if (shipped == ncpuids) 315 break; 316 317 for ((index = ((int)next - 1)); 318 index >= 0; index--) 319 if (CPU_IN_SET(set, index)) { 320 next = (uint16_t)index; 321 break; 322 } 323 324 cpus_left &= ~(1ull << lo); 325 } while (cpus_left); 326 #ifdef CHEETAHPLUS_ERRATUM_25 327 /* 328 * Clear recovered because we are sending to 329 * a new set of targets. 330 */ 331 recovered = 0; 332 #endif 333 continue; 334 } 335 } 336 #endif 337 if (curbusy) { 338 busy++; 339 continue; 340 } 341 342 #ifdef SEND_MONDO_STATS 343 { 344 int n = gettick() - starttick; 345 if (n < 8192) 346 x_nack_stimes[n >> 7]++; 347 } 348 #endif 349 while (gettick() < (tick + sys_clock_mhz)) 350 ; 351 do { 352 lo = lowbit(curnack) - 1; 353 i = IDSR_NACK_IDX(lo); 354 shipit(cpuids[i], i); 355 curnack &= ~(1ull << lo); 356 } while (curnack); 357 nack++; 358 busy = 0; 359 } 360 #ifdef SEND_MONDO_STATS 361 { 362 int n = gettick() - starttick; 363 if (n < 8192) 364 x_set_stimes[n >> 7]++; 365 else 366 x_set_ltimes[(n >> 13) & 0xf]++; 367 } 368 x_set_cpus[shipped]++; 369 #endif 370 } 371 372 /* 373 * Handles error logging for implementation specific error types 374 */ 375 /*ARGSUSED1*/ 376 int 377 cpu_impl_async_log_err(void *flt, errorq_elem_t *eqep) 378 { 379 ch_async_flt_t *ch_flt = (ch_async_flt_t *)flt; 380 struct async_flt *aflt = (struct async_flt *)flt; 381 382 switch (ch_flt->flt_type) { 383 384 case CPU_IC_PARITY: 385 cpu_async_log_ic_parity_err(flt); 386 return (CH_ASYNC_LOG_DONE); 387 388 case CPU_DC_PARITY: 389 cpu_async_log_dc_parity_err(flt); 390 return (CH_ASYNC_LOG_DONE); 391 392 case CPU_DUE: 393 cpu_log_err(aflt); 394 cpu_page_retire(ch_flt); 395 return (CH_ASYNC_LOG_DONE); 396 397 case CPU_ITLB_PARITY: 398 case CPU_DTLB_PARITY: 399 cpu_async_log_tlb_parity_err(flt); 400 return (CH_ASYNC_LOG_DONE); 401 402 default: 403 return (CH_ASYNC_LOG_UNKNOWN); 404 } 405 } 406 407 /* 408 * Figure out if Ecache is direct-mapped (Cheetah or Cheetah+ with Ecache 409 * control ECCR_ASSOC bit off or 2-way (Cheetah+ with ECCR_ASSOC on). 410 * We need to do this on the fly because we may have mixed Cheetah+'s with 411 * both direct and 2-way Ecaches. Panther only supports 4-way L3$. 412 */ 413 int 414 cpu_ecache_nway(void) 415 { 416 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation)) 417 return (PN_L3_NWAYS); 418 return ((get_ecache_ctrl() & ECCR_ASSOC) ? 2 : 1); 419 } 420 421 /* 422 * Note that these are entered into the table: Fatal Errors (PERR, IERR, ISAP, 423 * EMU, IMU) first, orphaned UCU/UCC, AFAR Overwrite policy, finally IVU, IVC. 424 * Afar overwrite policy is: 425 * Class 4: 426 * AFSR -- UCC, UCU, TUE, TSCE, TUE_SH 427 * AFSR_EXT -- L3_UCC, L3_UCU, L3_TUE, L3_TUE_SH 428 * Class 3: 429 * AFSR -- UE, DUE, EDU, WDU, CPU 430 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 431 * Class 2: 432 * AFSR -- CE, EDC, EMC, WDC, CPC, THCE 433 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC, L3_THCE 434 * Class 1: 435 * AFSR -- TO, DTO, BERR, DBERR 436 */ 437 ecc_type_to_info_t ecc_type_to_info[] = { 438 439 /* Fatal Errors */ 440 C_AFSR_PERR, "PERR ", ECC_ALL_TRAPS, 441 CPU_FATAL, "PERR Fatal", 442 FM_EREPORT_PAYLOAD_SYSTEM2, 443 FM_EREPORT_CPU_USIII_PERR, 444 C_AFSR_IERR, "IERR ", ECC_ALL_TRAPS, 445 CPU_FATAL, "IERR Fatal", 446 FM_EREPORT_PAYLOAD_SYSTEM2, 447 FM_EREPORT_CPU_USIII_IERR, 448 C_AFSR_ISAP, "ISAP ", ECC_ALL_TRAPS, 449 CPU_FATAL, "ISAP Fatal", 450 FM_EREPORT_PAYLOAD_SYSTEM1, 451 FM_EREPORT_CPU_USIII_ISAP, 452 C_AFSR_L3_TUE_SH, "L3_TUE_SH ", ECC_C_TRAP, 453 CPU_FATAL, "L3_TUE_SH Fatal", 454 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 455 FM_EREPORT_CPU_USIII_L3_TUE_SH, 456 C_AFSR_L3_TUE, "L3_TUE ", ECC_C_TRAP, 457 CPU_FATAL, "L3_TUE Fatal", 458 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 459 FM_EREPORT_CPU_USIII_L3_TUE, 460 C_AFSR_TUE_SH, "TUE_SH ", ECC_C_TRAP, 461 CPU_FATAL, "TUE_SH Fatal", 462 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 463 FM_EREPORT_CPU_USIII_TUE_SH, 464 C_AFSR_TUE, "TUE ", ECC_ALL_TRAPS, 465 CPU_FATAL, "TUE Fatal", 466 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 467 FM_EREPORT_CPU_USIII_TUE, 468 C_AFSR_EMU, "EMU ", ECC_ASYNC_TRAPS, 469 CPU_FATAL, "EMU Fatal", 470 FM_EREPORT_PAYLOAD_MEMORY, 471 FM_EREPORT_CPU_USIII_EMU, 472 C_AFSR_IMU, "IMU ", ECC_C_TRAP, 473 CPU_FATAL, "IMU Fatal", 474 FM_EREPORT_PAYLOAD_SYSTEM1, 475 FM_EREPORT_CPU_USIII_IMU, 476 477 /* L3$ Address parity errors are reported via the MECC bit */ 478 C_AFSR_L3_MECC, "L3_MECC ", ECC_MECC_TRAPS, 479 CPU_L3_ADDR_PE, "L3 Address Parity", 480 FM_EREPORT_PAYLOAD_L3_DATA, 481 FM_EREPORT_CPU_USIII_L3_MECC, 482 483 /* Orphaned UCC/UCU Errors */ 484 C_AFSR_L3_UCU, "L3_OUCU ", ECC_ORPH_TRAPS, 485 CPU_ORPH, "Orphaned L3_UCU", 486 FM_EREPORT_PAYLOAD_L3_DATA, 487 FM_EREPORT_CPU_USIII_L3_UCU, 488 C_AFSR_L3_UCC, "L3_OUCC ", ECC_ORPH_TRAPS, 489 CPU_ORPH, "Orphaned L3_UCC", 490 FM_EREPORT_PAYLOAD_L3_DATA, 491 FM_EREPORT_CPU_USIII_L3_UCC, 492 C_AFSR_UCU, "OUCU ", ECC_ORPH_TRAPS, 493 CPU_ORPH, "Orphaned UCU", 494 FM_EREPORT_PAYLOAD_L2_DATA, 495 FM_EREPORT_CPU_USIII_UCU, 496 C_AFSR_UCC, "OUCC ", ECC_ORPH_TRAPS, 497 CPU_ORPH, "Orphaned UCC", 498 FM_EREPORT_PAYLOAD_L2_DATA, 499 FM_EREPORT_CPU_USIII_UCC, 500 501 /* UCU, UCC */ 502 C_AFSR_L3_UCU, "L3_UCU ", ECC_F_TRAP, 503 CPU_UE_ECACHE, "L3_UCU", 504 FM_EREPORT_PAYLOAD_L3_DATA, 505 FM_EREPORT_CPU_USIII_L3_UCU, 506 C_AFSR_L3_UCC, "L3_UCC ", ECC_F_TRAP, 507 CPU_CE_ECACHE, "L3_UCC", 508 FM_EREPORT_PAYLOAD_L3_DATA, 509 FM_EREPORT_CPU_USIII_L3_UCC, 510 C_AFSR_UCU, "UCU ", ECC_F_TRAP, 511 CPU_UE_ECACHE, "UCU", 512 FM_EREPORT_PAYLOAD_L2_DATA, 513 FM_EREPORT_CPU_USIII_UCU, 514 C_AFSR_UCC, "UCC ", ECC_F_TRAP, 515 CPU_CE_ECACHE, "UCC", 516 FM_EREPORT_PAYLOAD_L2_DATA, 517 FM_EREPORT_CPU_USIII_UCC, 518 C_AFSR_TSCE, "TSCE ", ECC_F_TRAP, 519 CPU_CE_ECACHE, "TSCE", 520 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 521 FM_EREPORT_CPU_USIII_TSCE, 522 523 /* UE, EDU:ST, EDU:BLD, WDU, CPU */ 524 C_AFSR_UE, "UE ", ECC_ASYNC_TRAPS, 525 CPU_UE, "Uncorrectable system bus (UE)", 526 FM_EREPORT_PAYLOAD_MEMORY, 527 FM_EREPORT_CPU_USIII_UE, 528 C_AFSR_L3_EDU, "L3_EDU ", ECC_C_TRAP, 529 CPU_UE_ECACHE_RETIRE, "L3_EDU:ST", 530 FM_EREPORT_PAYLOAD_L3_DATA, 531 FM_EREPORT_CPU_USIII_L3_EDUST, 532 C_AFSR_L3_EDU, "L3_EDU ", ECC_D_TRAP, 533 CPU_UE_ECACHE_RETIRE, "L3_EDU:BLD", 534 FM_EREPORT_PAYLOAD_L3_DATA, 535 FM_EREPORT_CPU_USIII_L3_EDUBL, 536 C_AFSR_L3_WDU, "L3_WDU ", ECC_C_TRAP, 537 CPU_UE_ECACHE_RETIRE, "L3_WDU", 538 FM_EREPORT_PAYLOAD_L3_DATA, 539 FM_EREPORT_CPU_USIII_L3_WDU, 540 C_AFSR_L3_CPU, "L3_CPU ", ECC_C_TRAP, 541 CPU_UE_ECACHE, "L3_CPU", 542 FM_EREPORT_PAYLOAD_L3_DATA, 543 FM_EREPORT_CPU_USIII_L3_CPU, 544 C_AFSR_EDU, "EDU ", ECC_C_TRAP, 545 CPU_UE_ECACHE_RETIRE, "EDU:ST", 546 FM_EREPORT_PAYLOAD_L2_DATA, 547 FM_EREPORT_CPU_USIII_EDUST, 548 C_AFSR_EDU, "EDU ", ECC_D_TRAP, 549 CPU_UE_ECACHE_RETIRE, "EDU:BLD", 550 FM_EREPORT_PAYLOAD_L2_DATA, 551 FM_EREPORT_CPU_USIII_EDUBL, 552 C_AFSR_WDU, "WDU ", ECC_C_TRAP, 553 CPU_UE_ECACHE_RETIRE, "WDU", 554 FM_EREPORT_PAYLOAD_L2_DATA, 555 FM_EREPORT_CPU_USIII_WDU, 556 C_AFSR_CPU, "CPU ", ECC_C_TRAP, 557 CPU_UE_ECACHE, "CPU", 558 FM_EREPORT_PAYLOAD_L2_DATA, 559 FM_EREPORT_CPU_USIII_CPU, 560 C_AFSR_DUE, "DUE ", ECC_C_TRAP, 561 CPU_DUE, "DUE", 562 FM_EREPORT_PAYLOAD_MEMORY, 563 FM_EREPORT_CPU_USIII_DUE, 564 565 /* CE, EDC, EMC, WDC, CPC */ 566 C_AFSR_CE, "CE ", ECC_C_TRAP, 567 CPU_CE, "Corrected system bus (CE)", 568 FM_EREPORT_PAYLOAD_MEMORY, 569 FM_EREPORT_CPU_USIII_CE, 570 C_AFSR_L3_EDC, "L3_EDC ", ECC_C_TRAP, 571 CPU_CE_ECACHE, "L3_EDC", 572 FM_EREPORT_PAYLOAD_L3_DATA, 573 FM_EREPORT_CPU_USIII_L3_EDC, 574 C_AFSR_EDC, "EDC ", ECC_C_TRAP, 575 CPU_CE_ECACHE, "EDC", 576 FM_EREPORT_PAYLOAD_L2_DATA, 577 FM_EREPORT_CPU_USIII_EDC, 578 C_AFSR_EMC, "EMC ", ECC_C_TRAP, 579 CPU_EMC, "EMC", 580 FM_EREPORT_PAYLOAD_MEMORY, 581 FM_EREPORT_CPU_USIII_EMC, 582 C_AFSR_L3_WDC, "L3_WDC ", ECC_C_TRAP, 583 CPU_CE_ECACHE, "L3_WDC", 584 FM_EREPORT_PAYLOAD_L3_DATA, 585 FM_EREPORT_CPU_USIII_L3_WDC, 586 C_AFSR_L3_CPC, "L3_CPC ", ECC_C_TRAP, 587 CPU_CE_ECACHE, "L3_CPC", 588 FM_EREPORT_PAYLOAD_L3_DATA, 589 FM_EREPORT_CPU_USIII_L3_CPC, 590 C_AFSR_L3_THCE, "L3_THCE ", ECC_C_TRAP, 591 CPU_CE_ECACHE, "L3_THCE", 592 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 593 FM_EREPORT_CPU_USIII_L3_THCE, 594 C_AFSR_WDC, "WDC ", ECC_C_TRAP, 595 CPU_CE_ECACHE, "WDC", 596 FM_EREPORT_PAYLOAD_L2_DATA, 597 FM_EREPORT_CPU_USIII_WDC, 598 C_AFSR_CPC, "CPC ", ECC_C_TRAP, 599 CPU_CE_ECACHE, "CPC", 600 FM_EREPORT_PAYLOAD_L2_DATA, 601 FM_EREPORT_CPU_USIII_CPC, 602 C_AFSR_THCE, "THCE ", ECC_C_TRAP, 603 CPU_CE_ECACHE, "THCE", 604 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 605 FM_EREPORT_CPU_USIII_THCE, 606 607 /* TO, BERR */ 608 C_AFSR_TO, "TO ", ECC_ASYNC_TRAPS, 609 CPU_TO, "Timeout (TO)", 610 FM_EREPORT_PAYLOAD_IO, 611 FM_EREPORT_CPU_USIII_TO, 612 C_AFSR_BERR, "BERR ", ECC_ASYNC_TRAPS, 613 CPU_BERR, "Bus Error (BERR)", 614 FM_EREPORT_PAYLOAD_IO, 615 FM_EREPORT_CPU_USIII_BERR, 616 C_AFSR_DTO, "DTO ", ECC_C_TRAP, 617 CPU_TO, "Disrupting Timeout (DTO)", 618 FM_EREPORT_PAYLOAD_IO, 619 FM_EREPORT_CPU_USIII_DTO, 620 C_AFSR_DBERR, "DBERR ", ECC_C_TRAP, 621 CPU_BERR, "Disrupting Bus Error (DBERR)", 622 FM_EREPORT_PAYLOAD_IO, 623 FM_EREPORT_CPU_USIII_DBERR, 624 625 /* IVU, IVC, IMC */ 626 C_AFSR_IVU, "IVU ", ECC_C_TRAP, 627 CPU_IV, "IVU", 628 FM_EREPORT_PAYLOAD_SYSTEM1, 629 FM_EREPORT_CPU_USIII_IVU, 630 C_AFSR_IVC, "IVC ", ECC_C_TRAP, 631 CPU_IV, "IVC", 632 FM_EREPORT_PAYLOAD_SYSTEM1, 633 FM_EREPORT_CPU_USIII_IVC, 634 C_AFSR_IMC, "IMC ", ECC_C_TRAP, 635 CPU_IV, "IMC", 636 FM_EREPORT_PAYLOAD_SYSTEM1, 637 FM_EREPORT_CPU_USIII_IMC, 638 639 0, NULL, 0, 640 0, NULL, 641 FM_EREPORT_PAYLOAD_UNKNOWN, 642 FM_EREPORT_CPU_USIII_UNKNOWN, 643 }; 644 645 /* 646 * See Cheetah+ Delta PRM 10.9 and section P.6.1 of the Panther PRM 647 * Class 4: 648 * AFSR -- UCC, UCU, TUE, TSCE, TUE_SH 649 * AFSR_EXT -- L3_UCC, L3_UCU, L3_TUE, L3_TUE_SH 650 * Class 3: 651 * AFSR -- UE, DUE, EDU, EMU, WDU, CPU 652 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 653 * Class 2: 654 * AFSR -- CE, EDC, EMC, WDC, CPC, THCE 655 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC, L3_THCE 656 * Class 1: 657 * AFSR -- TO, DTO, BERR, DBERR 658 * AFSR_EXT -- 659 */ 660 uint64_t afar_overwrite[] = { 661 /* class 4: */ 662 C_AFSR_UCC | C_AFSR_UCU | C_AFSR_TUE | C_AFSR_TSCE | C_AFSR_TUE_SH | 663 C_AFSR_L3_UCC | C_AFSR_L3_UCU | C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH, 664 /* class 3: */ 665 C_AFSR_UE | C_AFSR_DUE | C_AFSR_EDU | C_AFSR_EMU | C_AFSR_WDU | 666 C_AFSR_CPU | C_AFSR_L3_EDU | C_AFSR_L3_WDU | C_AFSR_L3_CPU, 667 /* class 2: */ 668 C_AFSR_CE | C_AFSR_EDC | C_AFSR_EMC | C_AFSR_WDC | C_AFSR_CPC | 669 C_AFSR_THCE | C_AFSR_L3_EDC | C_AFSR_L3_WDC | C_AFSR_L3_CPC | 670 C_AFSR_L3_THCE, 671 /* class 1: */ 672 C_AFSR_TO | C_AFSR_DTO | C_AFSR_BERR | C_AFSR_DBERR, 673 674 0 675 }; 676 677 /* 678 * See Cheetah+ Delta PRM 10.9. 679 * Class 2: UE, DUE, IVU, EDU, WDU, UCU, CPU 680 * Class 1: CE, IVC, EDC, WDC, UCC, CPC 681 */ 682 uint64_t esynd_overwrite[] = { 683 /* class 2: */ 684 C_AFSR_UE | C_AFSR_DUE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | 685 C_AFSR_UCU | C_AFSR_CPU, 686 /* class 1: */ 687 C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_UCC | 688 C_AFSR_CPC, 689 0 690 }; 691 692 /* 693 * In panther, the E_SYND overwrite policy changed a little bit 694 * by adding one more level. 695 * class 3: 696 * AFSR -- UCU, UCC 697 * AFSR_EXT -- L3_UCU, L3_UCC 698 * Class 2: 699 * AFSR -- UE, DUE, IVU, EDU, WDU, CPU 700 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 701 * Class 1: 702 * AFSR -- CE, IVC, EDC, WDC, CPC 703 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC 704 */ 705 uint64_t pn_esynd_overwrite[] = { 706 /* class 3: */ 707 C_AFSR_UCU | C_AFSR_UCC | 708 C_AFSR_L3_UCU | C_AFSR_L3_UCC, 709 /* class 2: */ 710 C_AFSR_UE | C_AFSR_DUE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | 711 C_AFSR_CPU | 712 C_AFSR_L3_EDU | C_AFSR_L3_WDU | C_AFSR_L3_CPU, 713 /* class 1: */ 714 C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_CPC | 715 C_AFSR_L3_EDC | C_AFSR_L3_WDC | C_AFSR_L3_CPC, 716 717 0 718 }; 719 720 int 721 afsr_to_pn_esynd_status(uint64_t afsr, uint64_t afsr_bit) 722 { 723 return (afsr_to_overw_status(afsr, afsr_bit, pn_esynd_overwrite)); 724 } 725 726 /* 727 * Prioritized list of Error bits for MSYND overwrite. 728 * See Cheetah PRM P.6.3 729 * Class 2: EMU 730 * Class 1: EMC 731 * 732 * Panther adds IMU and IMC. 733 */ 734 uint64_t msynd_overwrite[] = { 735 /* class 2: */ 736 C_AFSR_EMU | C_AFSR_IMU, 737 /* class 1: */ 738 C_AFSR_EMC | C_AFSR_IMC, 739 740 0 741 }; 742 743 /* 744 * change cpu speed bits -- new speed will be normal-speed/divisor. 745 * 746 * The Jalapeno memory controllers are required to drain outstanding 747 * memory transactions within 32 JBus clocks in order to be ready 748 * to enter Estar mode. In some corner cases however, that time 749 * fell short. 750 * 751 * A safe software solution is to force MCU to act like in Estar mode, 752 * then delay 1us (in ppm code) prior to assert J_CHNG_L signal. 753 * To reverse the effect, upon exiting Estar, software restores the 754 * MCU to its original state. 755 */ 756 /* ARGSUSED1 */ 757 void 758 cpu_change_speed(uint64_t divisor, uint64_t arg2) 759 { 760 bus_config_eclk_t *bceclk; 761 uint64_t reg; 762 763 for (bceclk = bus_config_eclk; bceclk->divisor; bceclk++) { 764 if (bceclk->divisor != divisor) 765 continue; 766 reg = get_safari_config(); 767 reg &= ~SAFARI_CONFIG_ECLK_MASK; 768 reg |= bceclk->mask; 769 set_safari_config(reg); 770 CPU->cpu_m.divisor = (uchar_t)divisor; 771 return; 772 } 773 /* 774 * We will reach here only if OBP and kernel don't agree on 775 * the speeds supported by the CPU. 776 */ 777 cmn_err(CE_WARN, "cpu_change_speed: bad divisor %" PRIu64, divisor); 778 } 779 780 /* 781 * Cpu private initialization. This includes allocating the cpu_private 782 * data structure, initializing it, and initializing the scrubber for this 783 * cpu. This function calls cpu_init_ecache_scrub_dr to init the scrubber. 784 * We use kmem_cache_create for the cheetah private data structure because 785 * it needs to be allocated on a PAGESIZE (8192) byte boundary. 786 */ 787 void 788 cpu_init_private(struct cpu *cp) 789 { 790 cheetah_private_t *chprp; 791 int i; 792 793 ASSERT(CPU_PRIVATE(cp) == NULL); 794 795 /* LINTED: E_TRUE_LOGICAL_EXPR */ 796 ASSERT((offsetof(cheetah_private_t, chpr_tl1_err_data) + 797 sizeof (ch_err_tl1_data_t) * CH_ERR_TL1_TLMAX) <= PAGESIZE); 798 799 /* 800 * Running with Cheetah CPUs in a Cheetah+, Jaguar, Panther or 801 * mixed Cheetah+/Jaguar/Panther machine is not a supported 802 * configuration. Attempting to do so may result in unpredictable 803 * failures (e.g. running Cheetah+ CPUs with Cheetah E$ disp flush) 804 * so don't allow it. 805 * 806 * This is just defensive code since this configuration mismatch 807 * should have been caught prior to OS execution. 808 */ 809 if (!(IS_CHEETAH_PLUS(cpunodes[cp->cpu_id].implementation) || 810 IS_JAGUAR(cpunodes[cp->cpu_id].implementation) || 811 IS_PANTHER(cpunodes[cp->cpu_id].implementation))) { 812 cmn_err(CE_PANIC, "CPU%d: UltraSPARC-III not supported" 813 " on UltraSPARC-III+/IV/IV+ code\n", cp->cpu_id); 814 } 815 816 /* 817 * If the ch_private_cache has not been created, create it. 818 */ 819 if (ch_private_cache == NULL) { 820 ch_private_cache = kmem_cache_create("ch_private_cache", 821 sizeof (cheetah_private_t), PAGESIZE, NULL, NULL, 822 NULL, NULL, static_arena, 0); 823 } 824 825 chprp = CPU_PRIVATE(cp) = kmem_cache_alloc(ch_private_cache, KM_SLEEP); 826 827 bzero(chprp, sizeof (cheetah_private_t)); 828 chprp->chpr_fecctl0_logout.clo_data.chd_afar = LOGOUT_INVALID; 829 chprp->chpr_cecc_logout.clo_data.chd_afar = LOGOUT_INVALID; 830 chprp->chpr_async_logout.clo_data.chd_afar = LOGOUT_INVALID; 831 chprp->chpr_tlb_logout.tlo_addr = LOGOUT_INVALID; 832 for (i = 0; i < CH_ERR_TL1_TLMAX; i++) 833 chprp->chpr_tl1_err_data[i].ch_err_tl1_logout.clo_data.chd_afar 834 = LOGOUT_INVALID; 835 836 /* Panther has a larger Icache compared to cheetahplus or Jaguar */ 837 if (IS_PANTHER(cpunodes[cp->cpu_id].implementation)) { 838 chprp->chpr_icache_size = PN_ICACHE_SIZE; 839 chprp->chpr_icache_linesize = PN_ICACHE_LSIZE; 840 } else { 841 chprp->chpr_icache_size = CH_ICACHE_SIZE; 842 chprp->chpr_icache_linesize = CH_ICACHE_LSIZE; 843 } 844 845 cpu_init_ecache_scrub_dr(cp); 846 847 /* 848 * Panther's L2$ and E$ are shared between cores, so the scrubber is 849 * only needed on one of the cores. At this point, we assume all cores 850 * are online, and we only enable the scrubber on core 0. 851 */ 852 if (IS_PANTHER(cpunodes[cp->cpu_id].implementation)) { 853 chprp->chpr_scrub_misc.chsm_core_state = 854 SCRUBBER_BOTH_CORES_ONLINE; 855 if (cp->cpu_id != (processorid_t)cmp_cpu_to_chip(cp->cpu_id)) { 856 chprp->chpr_scrub_misc.chsm_enable[ 857 CACHE_SCRUBBER_INFO_E] = 0; 858 } 859 } 860 861 chprp->chpr_ec_set_size = cpunodes[cp->cpu_id].ecache_size / 862 cpu_ecache_nway(); 863 864 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 865 ch_err_tl1_paddrs[cp->cpu_id] = va_to_pa(chprp); 866 ASSERT(ch_err_tl1_paddrs[cp->cpu_id] != -1); 867 } 868 869 /* 870 * Clear the error state registers for this CPU. 871 * For Cheetah+/Jaguar, just clear the AFSR but 872 * for Panther we also have to clear the AFSR_EXT. 873 */ 874 void 875 set_cpu_error_state(ch_cpu_errors_t *cpu_error_regs) 876 { 877 set_asyncflt(cpu_error_regs->afsr & ~C_AFSR_FATAL_ERRS); 878 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation)) { 879 set_afsr_ext(cpu_error_regs->afsr_ext & ~C_AFSR_EXT_FATAL_ERRS); 880 } 881 } 882 883 void 884 pn_cpu_log_diag_l2_info(ch_async_flt_t *ch_flt) { 885 struct async_flt *aflt = (struct async_flt *)ch_flt; 886 ch_ec_data_t *l2_data = &ch_flt->flt_diag_data.chd_l2_data[0]; 887 uint64_t faddr = aflt->flt_addr; 888 uint8_t log_way_mask = 0; 889 int i; 890 891 /* 892 * Only Panther CPUs have the additional L2$ data that needs 893 * to be logged here 894 */ 895 if (!IS_PANTHER(cpunodes[aflt->flt_inst].implementation)) 896 return; 897 898 /* 899 * We'll use a simple bit mask to keep track of which way(s) 900 * of the stored cache line we want to log. The idea is to 901 * log the entry if it is a valid line and it matches our 902 * fault AFAR. If no match is found, we will simply log all 903 * the ways. 904 */ 905 for (i = 0; i < PN_L2_NWAYS; i++) 906 if (pn_matching_valid_l2_line(faddr, &l2_data[i])) 907 log_way_mask |= (1 << i); 908 909 /* If no matching valid lines were found, we log all ways */ 910 if (log_way_mask == 0) 911 log_way_mask = (1 << PN_L2_NWAYS) - 1; 912 913 /* Log the cache lines */ 914 for (i = 0; i < PN_L2_NWAYS; i++) 915 if (log_way_mask & (1 << i)) 916 l2_data[i].ec_logflag = EC_LOGFLAG_MAGIC; 917 } 918 919 /* 920 * For this routine to return true, the L2 tag in question must be valid 921 * and the tag PA must match the fault address (faddr) assuming the correct 922 * index is being used. 923 */ 924 static int 925 pn_matching_valid_l2_line(uint64_t faddr, ch_ec_data_t *clo_l2_data) { 926 if ((!PN_L2_LINE_INVALID(clo_l2_data->ec_tag)) && 927 ((faddr & P2ALIGN(C_AFAR_PA, PN_L2_SET_SIZE)) == 928 PN_L2TAG_TO_PA(clo_l2_data->ec_tag))) 929 return (1); 930 return (0); 931 } 932 933 /* 934 * This array is used to convert the 3 digit PgSz encoding (as used in 935 * various MMU registers such as MMU_TAG_ACCESS_EXT) into the corresponding 936 * page size. 937 */ 938 static uint64_t tlb_pgsz_to_size[] = { 939 /* 000 = 8KB: */ 940 0x2000, 941 /* 001 = 64KB: */ 942 0x10000, 943 /* 010 = 512KB: */ 944 0x80000, 945 /* 011 = 4MB: */ 946 0x400000, 947 /* 100 = 32MB: */ 948 0x2000000, 949 /* 101 = 256MB: */ 950 0x10000000, 951 /* undefined for encodings 110 and 111: */ 952 0, 0 953 }; 954 955 /* 956 * The itlb_parity_trap and dtlb_parity_trap handlers transfer control here 957 * after collecting logout information related to the TLB parity error and 958 * flushing the offending TTE entries from the ITLB or DTLB. 959 * 960 * DTLB traps which occur at TL>0 are not recoverable because we will most 961 * likely be corrupting some other trap handler's alternate globals. As 962 * such, we simply panic here when that happens. ITLB parity errors are 963 * not expected to happen at TL>0. 964 */ 965 void 966 cpu_tlb_parity_error(struct regs *rp, ulong_t trap_va, ulong_t tlb_info) { 967 ch_async_flt_t ch_flt; 968 struct async_flt *aflt; 969 pn_tlb_logout_t *tlop = NULL; 970 int immu_parity = (tlb_info & PN_TLO_INFO_IMMU) != 0; 971 int tl1_trap = (tlb_info & PN_TLO_INFO_TL1) != 0; 972 char *error_class; 973 974 bzero(&ch_flt, sizeof (ch_async_flt_t)); 975 976 /* 977 * Get the CPU log out info. If we can't find our CPU private 978 * pointer, or if the logout information does not correspond to 979 * this error, then we will have to make due without detailed 980 * logout information. 981 */ 982 if (CPU_PRIVATE(CPU)) { 983 tlop = CPU_PRIVATE_PTR(CPU, chpr_tlb_logout); 984 if ((tlop->tlo_addr != trap_va) || 985 (tlop->tlo_info != tlb_info)) 986 tlop = NULL; 987 } 988 989 if (tlop) { 990 ch_flt.tlb_diag_data = *tlop; 991 992 /* Zero out + invalidate TLB logout. */ 993 bzero(tlop, sizeof (pn_tlb_logout_t)); 994 tlop->tlo_addr = LOGOUT_INVALID; 995 } else { 996 /* 997 * Copy what logout information we have and mark 998 * it incomplete. 999 */ 1000 ch_flt.flt_data_incomplete = 1; 1001 ch_flt.tlb_diag_data.tlo_info = tlb_info; 1002 ch_flt.tlb_diag_data.tlo_addr = trap_va; 1003 } 1004 1005 /* 1006 * Log the error. 1007 */ 1008 aflt = (struct async_flt *)&ch_flt; 1009 aflt->flt_id = gethrtime_waitfree(); 1010 aflt->flt_bus_id = getprocessorid(); 1011 aflt->flt_inst = CPU->cpu_id; 1012 aflt->flt_pc = (caddr_t)rp->r_pc; 1013 aflt->flt_addr = trap_va; 1014 aflt->flt_prot = AFLT_PROT_NONE; 1015 aflt->flt_class = CPU_FAULT; 1016 aflt->flt_priv = (rp->r_tstate & TSTATE_PRIV) ? 1 : 0; 1017 aflt->flt_tl = tl1_trap ? 1 : 0; 1018 aflt->flt_panic = tl1_trap ? 1 : 0; 1019 1020 if (immu_parity) { 1021 aflt->flt_status = ECC_ITLB_TRAP; 1022 ch_flt.flt_type = CPU_ITLB_PARITY; 1023 error_class = FM_EREPORT_CPU_USIII_ITLBPE; 1024 aflt->flt_payload = FM_EREPORT_PAYLOAD_ITLB_PE; 1025 } else { 1026 aflt->flt_status = ECC_DTLB_TRAP; 1027 ch_flt.flt_type = CPU_DTLB_PARITY; 1028 error_class = FM_EREPORT_CPU_USIII_DTLBPE; 1029 aflt->flt_payload = FM_EREPORT_PAYLOAD_DTLB_PE; 1030 } 1031 1032 /* 1033 * The TLB entries have already been flushed by the TL1 trap 1034 * handler so at this point the only thing left to do is log 1035 * the error message. 1036 */ 1037 if (aflt->flt_panic) { 1038 cpu_errorq_dispatch(error_class, (void *)&ch_flt, 1039 sizeof (ch_async_flt_t), ue_queue, aflt->flt_panic); 1040 /* 1041 * Panic here if aflt->flt_panic has been set. Enqueued 1042 * errors will be logged as part of the panic flow. 1043 */ 1044 fm_panic("%sError(s)", immu_parity ? "ITLBPE " : "DTLBPE "); 1045 } else { 1046 cpu_errorq_dispatch(error_class, (void *)&ch_flt, 1047 sizeof (ch_async_flt_t), ce_queue, aflt->flt_panic); 1048 } 1049 } 1050 1051 /* 1052 * This routine is called when a TLB parity error event is 'ue_drain'ed 1053 * or 'ce_drain'ed from the errorq. 1054 */ 1055 void 1056 cpu_async_log_tlb_parity_err(void *flt) { 1057 ch_async_flt_t *ch_flt = (ch_async_flt_t *)flt; 1058 struct async_flt *aflt = (struct async_flt *)flt; 1059 #ifdef lint 1060 aflt = aflt; 1061 #endif 1062 1063 /* 1064 * We only capture TLB information if we encountered 1065 * a TLB parity error and Panther is the only CPU which 1066 * can detect a TLB parity error. 1067 */ 1068 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1069 ASSERT((ch_flt->flt_type == CPU_ITLB_PARITY) || 1070 (ch_flt->flt_type == CPU_DTLB_PARITY)); 1071 1072 if (ch_flt->flt_data_incomplete == 0) { 1073 if (ch_flt->flt_type == CPU_ITLB_PARITY) 1074 ch_flt->tlb_diag_data.tlo_logflag = IT_LOGFLAG_MAGIC; 1075 else /* parity error is in DTLB */ 1076 ch_flt->tlb_diag_data.tlo_logflag = DT_LOGFLAG_MAGIC; 1077 } 1078 } 1079 1080 /* 1081 * Add L1 Prefetch cache data to the ereport payload. 1082 */ 1083 void 1084 cpu_payload_add_pcache(struct async_flt *aflt, nvlist_t *nvl) 1085 { 1086 ch_async_flt_t *ch_flt = (ch_async_flt_t *)aflt; 1087 ch_pc_data_t *pcp; 1088 ch_pc_data_t pcdata[CH_PCACHE_NWAY]; 1089 uint_t nelem; 1090 int i, ways_logged = 0; 1091 1092 /* 1093 * We only capture P$ information if we encountered 1094 * a P$ parity error and Panther is the only CPU which 1095 * can detect a P$ parity error. 1096 */ 1097 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1098 for (i = 0; i < CH_PCACHE_NWAY; i++) { 1099 pcp = &ch_flt->parity_data.dpe.cpl_pc[i]; 1100 if (pcp->pc_logflag == PC_LOGFLAG_MAGIC) { 1101 bcopy(pcp, &pcdata[ways_logged], 1102 sizeof (ch_pc_data_t)); 1103 ways_logged++; 1104 } 1105 } 1106 1107 /* 1108 * Add the pcache data to the payload. 1109 */ 1110 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_L1P_WAYS, 1111 DATA_TYPE_UINT8, (uint8_t)ways_logged, NULL); 1112 if (ways_logged != 0) { 1113 nelem = sizeof (ch_pc_data_t) / sizeof (uint64_t) * ways_logged; 1114 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_L1P_DATA, 1115 DATA_TYPE_UINT64_ARRAY, nelem, (uint64_t *)pcdata, NULL); 1116 } 1117 } 1118 1119 /* 1120 * Add TLB diagnostic data to the ereport payload. 1121 */ 1122 void 1123 cpu_payload_add_tlb(struct async_flt *aflt, nvlist_t *nvl) 1124 { 1125 ch_async_flt_t *ch_flt = (ch_async_flt_t *)aflt; 1126 uint8_t num_entries, tlb_data_words; 1127 1128 /* 1129 * We only capture TLB information if we encountered 1130 * a TLB parity error and Panther is the only CPU which 1131 * can detect a TLB parity error. 1132 */ 1133 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1134 ASSERT((ch_flt->flt_type == CPU_ITLB_PARITY) || 1135 (ch_flt->flt_type == CPU_DTLB_PARITY)); 1136 1137 if (ch_flt->flt_type == CPU_ITLB_PARITY) { 1138 num_entries = (uint8_t)(PN_ITLB_NWAYS * PN_NUM_512_ITLBS); 1139 tlb_data_words = sizeof (ch_tte_entry_t) / sizeof (uint64_t) * 1140 num_entries; 1141 1142 /* 1143 * Add the TLB diagnostic data to the payload 1144 * if it was collected. 1145 */ 1146 if (ch_flt->tlb_diag_data.tlo_logflag == IT_LOGFLAG_MAGIC) { 1147 fm_payload_set(nvl, 1148 FM_EREPORT_PAYLOAD_NAME_ITLB_ENTRIES, 1149 DATA_TYPE_UINT8, num_entries, NULL); 1150 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_ITLB_DATA, 1151 DATA_TYPE_UINT64_ARRAY, tlb_data_words, 1152 (uint64_t *)ch_flt->tlb_diag_data.tlo_itlb_tte, 1153 NULL); 1154 } 1155 } else { 1156 num_entries = (uint8_t)(PN_DTLB_NWAYS * PN_NUM_512_DTLBS); 1157 tlb_data_words = sizeof (ch_tte_entry_t) / sizeof (uint64_t) * 1158 num_entries; 1159 1160 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_VA, 1161 DATA_TYPE_UINT64, ch_flt->tlb_diag_data.tlo_addr, NULL); 1162 1163 /* 1164 * Add the TLB diagnostic data to the payload 1165 * if it was collected. 1166 */ 1167 if (ch_flt->tlb_diag_data.tlo_logflag == DT_LOGFLAG_MAGIC) { 1168 fm_payload_set(nvl, 1169 FM_EREPORT_PAYLOAD_NAME_DTLB_ENTRIES, 1170 DATA_TYPE_UINT8, num_entries, NULL); 1171 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_DTLB_DATA, 1172 DATA_TYPE_UINT64_ARRAY, tlb_data_words, 1173 (uint64_t *)ch_flt->tlb_diag_data.tlo_dtlb_tte, 1174 NULL); 1175 } 1176 } 1177 } 1178 1179 /* 1180 * Panther Cache Scrubbing: 1181 * 1182 * In Jaguar, the E$ was split between cores, so the scrubber must run on both 1183 * cores. For Panther, however, the L2$ and L3$ are shared across cores. 1184 * Therefore, the E$ scrubber only needs to run on one of the two cores. 1185 * 1186 * There are four possible states for the E$ scrubber: 1187 * 1188 * 0. If both cores are offline, add core 0 to cpu_offline_set so that 1189 * the offline scrubber will run on it. 1190 * 1. If core 0 is online and core 1 off, we run the scrubber on core 0. 1191 * 2. If core 1 is online and core 0 off, we move the scrubber to run 1192 * on core 1. 1193 * 3. If both cores are online, only run the scrubber on core 0. 1194 * 1195 * These states are enumerated by the SCRUBBER_[BOTH|CORE|NEITHER]_* defines 1196 * above. One of those values is stored in 1197 * chpr_scrub_misc->chsm_core_state on each core. 1198 * 1199 * Also note that, for Panther, ecache_flush_line() will flush out the L2$ 1200 * before the E$, so the L2$ will be scrubbed by the E$ scrubber. No 1201 * additional code is necessary to scrub the L2$. 1202 * 1203 * For all cpu types, whenever a cpu or core is offlined, add it to 1204 * cpu_offline_set so the necessary scrubbers can still run. This is still 1205 * necessary on Panther so the D$ scrubber can still run. 1206 */ 1207 /*ARGSUSED*/ 1208 int 1209 cpu_scrub_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 1210 { 1211 processorid_t core_0_id; 1212 cpu_t *core_cpus[2]; 1213 ch_scrub_misc_t *core_scrub[2]; 1214 int old_state, i; 1215 int new_state = SCRUBBER_NEITHER_CORE_ONLINE; 1216 1217 switch (what) { 1218 case CPU_ON: 1219 case CPU_INIT: 1220 CPUSET_DEL(cpu_offline_set, cpuid); 1221 break; 1222 case CPU_OFF: 1223 CPUSET_ADD(cpu_offline_set, cpuid); 1224 break; 1225 default: 1226 return (0); 1227 } 1228 1229 if (!IS_PANTHER(cpunodes[cpuid].implementation)) { 1230 return (0); 1231 } 1232 1233 /* 1234 * Update the chsm_enable[CACHE_SCRUBBER_INFO_E] value 1235 * if necessary 1236 */ 1237 core_0_id = cmp_cpu_to_chip(cpuid); 1238 core_cpus[0] = cpu_get(core_0_id); 1239 core_cpus[1] = cpu_get_sibling_core(core_cpus[0]); 1240 1241 for (i = 0; i < 2; i++) { 1242 if (core_cpus[i] == NULL) { 1243 /* 1244 * This may happen during DR - one core is offlined 1245 * and completely unconfigured before the second 1246 * core is offlined. Give up and return quietly, 1247 * since the second core should quickly be removed 1248 * anyways. 1249 */ 1250 return (0); 1251 } 1252 core_scrub[i] = CPU_PRIVATE_PTR(core_cpus[i], chpr_scrub_misc); 1253 } 1254 1255 if (cpuid == (processorid_t)cmp_cpu_to_chip(cpuid)) { 1256 /* cpuid is core 0 */ 1257 if (cpu_is_active(core_cpus[1])) { 1258 new_state |= SCRUBBER_CORE_1_ONLINE; 1259 } 1260 if (what != CPU_OFF) { 1261 new_state |= SCRUBBER_CORE_0_ONLINE; 1262 } 1263 } else { 1264 /* cpuid is core 1 */ 1265 if (cpu_is_active(core_cpus[0])) { 1266 new_state |= SCRUBBER_CORE_0_ONLINE; 1267 } 1268 if (what != CPU_OFF) { 1269 new_state |= SCRUBBER_CORE_1_ONLINE; 1270 } 1271 } 1272 1273 old_state = core_scrub[0]->chsm_core_state; 1274 1275 if (old_state == new_state) { 1276 return (0); 1277 } 1278 1279 if (old_state == SCRUBBER_CORE_1_ONLINE) { 1280 /* 1281 * We need to move the scrubber state from core 1 1282 * back to core 0. This data is not protected by 1283 * locks, but the worst that can happen is some 1284 * lines are scrubbed multiple times. chsm_oustanding is 1285 * set to 0 to make sure an interrupt is scheduled the 1286 * first time through do_scrub(). 1287 */ 1288 core_scrub[0]->chsm_flush_index[CACHE_SCRUBBER_INFO_E] = 1289 core_scrub[1]->chsm_flush_index[CACHE_SCRUBBER_INFO_E]; 1290 core_scrub[0]->chsm_outstanding[CACHE_SCRUBBER_INFO_E] = 0; 1291 } 1292 1293 switch (new_state) { 1294 case SCRUBBER_NEITHER_CORE_ONLINE: 1295 case SCRUBBER_BOTH_CORES_ONLINE: 1296 case SCRUBBER_CORE_0_ONLINE: 1297 core_scrub[1]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 0; 1298 core_scrub[0]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 1; 1299 break; 1300 1301 case SCRUBBER_CORE_1_ONLINE: 1302 default: 1303 /* 1304 * We need to move the scrubber state from core 0 1305 * to core 1. 1306 */ 1307 core_scrub[1]->chsm_flush_index[CACHE_SCRUBBER_INFO_E] = 1308 core_scrub[0]->chsm_flush_index[CACHE_SCRUBBER_INFO_E]; 1309 core_scrub[1]->chsm_outstanding[CACHE_SCRUBBER_INFO_E] = 0; 1310 1311 core_scrub[0]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 0; 1312 core_scrub[1]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 1; 1313 break; 1314 } 1315 1316 core_scrub[0]->chsm_core_state = new_state; 1317 core_scrub[1]->chsm_core_state = new_state; 1318 return (0); 1319 } 1320 1321 /* 1322 * Returns a pointer to the cpu structure of the argument's sibling core. 1323 * If no sibling core can be found, return NULL. 1324 */ 1325 static cpu_t * 1326 cpu_get_sibling_core(cpu_t *cpup) 1327 { 1328 cpu_t *nextp; 1329 1330 if ((cpup == NULL) || (!cmp_cpu_is_cmp(cpup->cpu_id))) 1331 return (NULL); 1332 1333 nextp = cpup->cpu_next_chip; 1334 if ((nextp == NULL) || (nextp == cpup)) 1335 return (NULL); 1336 1337 return (nextp); 1338 } 1339