1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/ddi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/archsystm.h> 33 #include <sys/vmsystm.h> 34 #include <sys/machparam.h> 35 #include <sys/machsystm.h> 36 #include <sys/machthread.h> 37 #include <sys/cpu.h> 38 #include <sys/cmp.h> 39 #include <sys/elf_SPARC.h> 40 #include <vm/hat_sfmmu.h> 41 #include <vm/seg_kmem.h> 42 #include <sys/cpuvar.h> 43 #include <sys/cheetahregs.h> 44 #include <sys/us3_module.h> 45 #include <sys/async.h> 46 #include <sys/cmn_err.h> 47 #include <sys/debug.h> 48 #include <sys/dditypes.h> 49 #include <sys/prom_debug.h> 50 #include <sys/prom_plat.h> 51 #include <sys/cpu_module.h> 52 #include <sys/sysmacros.h> 53 #include <sys/intreg.h> 54 #include <sys/clock.h> 55 #include <sys/platform_module.h> 56 #include <sys/machtrap.h> 57 #include <sys/ontrap.h> 58 #include <sys/panic.h> 59 #include <sys/memlist.h> 60 #include <sys/bootconf.h> 61 #include <sys/ivintr.h> 62 #include <sys/atomic.h> 63 #include <sys/fm/protocol.h> 64 #include <sys/fm/cpu/UltraSPARC-III.h> 65 #include <sys/fm/util.h> 66 67 #ifdef CHEETAHPLUS_ERRATUM_25 68 #include <sys/cyclic.h> 69 #endif /* CHEETAHPLUS_ERRATUM_25 */ 70 71 /* 72 * See comment above cpu_scrub_cpu_setup() for description 73 */ 74 #define SCRUBBER_NEITHER_CORE_ONLINE 0x0 75 #define SCRUBBER_CORE_0_ONLINE 0x1 76 #define SCRUBBER_CORE_1_ONLINE 0x2 77 #define SCRUBBER_BOTH_CORES_ONLINE (SCRUBBER_CORE_0_ONLINE | \ 78 SCRUBBER_CORE_1_ONLINE) 79 80 static int pn_matching_valid_l2_line(uint64_t faddr, ch_ec_data_t *clo_l2_data); 81 static void cpu_async_log_tlb_parity_err(void *flt); 82 static cpu_t *cpu_get_sibling_core(cpu_t *cpup); 83 84 85 /* 86 * Setup trap handlers. 87 */ 88 void 89 cpu_init_trap(void) 90 { 91 CH_SET_TRAP(tt_pil15, ch_pil15_interrupt_instr); 92 93 CH_SET_TRAP(tt0_fecc, fecc_err_instr); 94 CH_SET_TRAP(tt1_fecc, fecc_err_tl1_instr); 95 CH_SET_TRAP(tt1_swtrap0, fecc_err_tl1_cont_instr); 96 97 CH_SET_TRAP(tt0_dperr, dcache_parity_instr); 98 CH_SET_TRAP(tt1_dperr, dcache_parity_tl1_instr); 99 CH_SET_TRAP(tt1_swtrap1, dcache_parity_tl1_cont_instr); 100 101 CH_SET_TRAP(tt0_iperr, icache_parity_instr); 102 CH_SET_TRAP(tt1_iperr, icache_parity_tl1_instr); 103 CH_SET_TRAP(tt1_swtrap2, icache_parity_tl1_cont_instr); 104 } 105 106 /* 107 * Set the magic constants of the implementation. 108 */ 109 /*ARGSUSED*/ 110 void 111 cpu_fiximp(pnode_t dnode) 112 { 113 int i, a; 114 extern int vac_size, vac_shift; 115 extern uint_t vac_mask; 116 117 dcache_size = CH_DCACHE_SIZE; 118 dcache_linesize = CH_DCACHE_LSIZE; 119 120 icache_size = CHP_ICACHE_MAX_SIZE; 121 icache_linesize = CHP_ICACHE_MIN_LSIZE; 122 123 ecache_size = CH_ECACHE_MAX_SIZE; 124 ecache_alignsize = CH_ECACHE_MAX_LSIZE; 125 ecache_associativity = CHP_ECACHE_MIN_NWAY; 126 127 /* 128 * ecache_setsize needs to maximum of all cpu ecache setsizes 129 */ 130 ecache_setsize = CHP_ECACHE_MAX_SETSIZE; 131 ASSERT(ecache_setsize >= (ecache_size / ecache_associativity)); 132 133 vac_size = CH_VAC_SIZE; 134 vac_mask = MMU_PAGEMASK & (vac_size - 1); 135 i = 0; a = vac_size; 136 while (a >>= 1) 137 ++i; 138 vac_shift = i; 139 shm_alignment = vac_size; 140 vac = 1; 141 } 142 143 /* 144 * Use Panther values for Panther-only domains. 145 * See Panther PRM, 1.5.4 Cache Hierarchy 146 */ 147 void 148 cpu_fix_allpanther(void) 149 { 150 /* dcache same as Ch+ */ 151 icache_size = PN_ICACHE_SIZE; 152 icache_linesize = PN_ICACHE_LSIZE; 153 ecache_size = PN_L3_SIZE; 154 ecache_alignsize = PN_L3_LINESIZE; 155 ecache_associativity = PN_L3_NWAYS; 156 ecache_setsize = PN_L3_SET_SIZE; 157 ASSERT(ecache_setsize >= (ecache_size / ecache_associativity)); 158 /* vac same as Ch+ */ 159 /* fix hwcaps for USIV+-only domains */ 160 cpu_hwcap_flags |= AV_SPARC_POPC; 161 } 162 163 void 164 send_mondo_set(cpuset_t set) 165 { 166 int lo, busy, nack, shipped = 0; 167 uint16_t i, cpuids[IDSR_BN_SETS]; 168 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 169 uint64_t starttick, endtick, tick, lasttick; 170 #if (NCPU > IDSR_BN_SETS) 171 int index = 0; 172 int ncpuids = 0; 173 #endif 174 #ifdef CHEETAHPLUS_ERRATUM_25 175 int recovered = 0; 176 int cpuid; 177 #endif 178 179 ASSERT(!CPUSET_ISNULL(set)); 180 starttick = lasttick = gettick(); 181 182 #if (NCPU <= IDSR_BN_SETS) 183 for (i = 0; i < NCPU; i++) 184 if (CPU_IN_SET(set, i)) { 185 shipit(i, shipped); 186 nackmask |= IDSR_NACK_BIT(shipped); 187 cpuids[shipped++] = i; 188 CPUSET_DEL(set, i); 189 if (CPUSET_ISNULL(set)) 190 break; 191 } 192 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 193 #else 194 for (i = 0; i < NCPU; i++) 195 if (CPU_IN_SET(set, i)) { 196 ncpuids++; 197 198 /* 199 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 200 * find we have shipped to more than (IDSR_BN_SETS) 201 * CPUs, set "index" to the highest numbered CPU in 202 * the set so we can ship to other CPUs a bit later on. 203 */ 204 if (shipped < IDSR_BN_SETS) { 205 shipit(i, shipped); 206 nackmask |= IDSR_NACK_BIT(shipped); 207 cpuids[shipped++] = i; 208 CPUSET_DEL(set, i); 209 if (CPUSET_ISNULL(set)) 210 break; 211 } else 212 index = (int)i; 213 } 214 215 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 216 #endif 217 218 busymask = IDSR_NACK_TO_BUSY(nackmask); 219 busy = nack = 0; 220 endtick = starttick + xc_tick_limit; 221 for (;;) { 222 idsr = getidsr(); 223 #if (NCPU <= IDSR_BN_SETS) 224 if (idsr == 0) 225 break; 226 #else 227 if (idsr == 0 && shipped == ncpuids) 228 break; 229 #endif 230 tick = gettick(); 231 /* 232 * If there is a big jump between the current tick 233 * count and lasttick, we have probably hit a break 234 * point. Adjust endtick accordingly to avoid panic. 235 */ 236 if (tick > (lasttick + xc_tick_jump_limit)) 237 endtick += (tick - lasttick); 238 lasttick = tick; 239 if (tick > endtick) { 240 if (panic_quiesce) 241 return; 242 #ifdef CHEETAHPLUS_ERRATUM_25 243 cpuid = -1; 244 for (i = 0; i < IDSR_BN_SETS; i++) { 245 if (idsr & (IDSR_NACK_BIT(i) | 246 IDSR_BUSY_BIT(i))) { 247 cpuid = cpuids[i]; 248 break; 249 } 250 } 251 if (cheetah_sendmondo_recover && cpuid != -1 && 252 recovered == 0) { 253 if (mondo_recover(cpuid, i)) { 254 /* 255 * We claimed the whole memory or 256 * full scan is disabled. 257 */ 258 recovered++; 259 } 260 tick = gettick(); 261 endtick = tick + xc_tick_limit; 262 lasttick = tick; 263 /* 264 * Recheck idsr 265 */ 266 continue; 267 } else 268 #endif /* CHEETAHPLUS_ERRATUM_25 */ 269 { 270 cmn_err(CE_CONT, "send mondo timeout " 271 "[%d NACK %d BUSY]\nIDSR 0x%" 272 "" PRIx64 " cpuids:", nack, busy, idsr); 273 for (i = 0; i < IDSR_BN_SETS; i++) { 274 if (idsr & (IDSR_NACK_BIT(i) | 275 IDSR_BUSY_BIT(i))) { 276 cmn_err(CE_CONT, " 0x%x", 277 cpuids[i]); 278 } 279 } 280 cmn_err(CE_CONT, "\n"); 281 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 282 } 283 } 284 curnack = idsr & nackmask; 285 curbusy = idsr & busymask; 286 #if (NCPU > IDSR_BN_SETS) 287 if (shipped < ncpuids) { 288 uint64_t cpus_left; 289 uint16_t next = (uint16_t)index; 290 291 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 292 busymask; 293 294 if (cpus_left) { 295 do { 296 /* 297 * Sequence through and ship to the 298 * remainder of the CPUs in the system 299 * (e.g. other than the first 300 * (IDSR_BN_SETS)) in reverse order. 301 */ 302 lo = lowbit(cpus_left) - 1; 303 i = IDSR_BUSY_IDX(lo); 304 shipit(next, i); 305 shipped++; 306 cpuids[i] = next; 307 308 /* 309 * If we've processed all the CPUs, 310 * exit the loop now and save 311 * instructions. 312 */ 313 if (shipped == ncpuids) 314 break; 315 316 for ((index = ((int)next - 1)); 317 index >= 0; index--) 318 if (CPU_IN_SET(set, index)) { 319 next = (uint16_t)index; 320 break; 321 } 322 323 cpus_left &= ~(1ull << lo); 324 } while (cpus_left); 325 #ifdef CHEETAHPLUS_ERRATUM_25 326 /* 327 * Clear recovered because we are sending to 328 * a new set of targets. 329 */ 330 recovered = 0; 331 #endif 332 continue; 333 } 334 } 335 #endif 336 if (curbusy) { 337 busy++; 338 continue; 339 } 340 341 #ifdef SEND_MONDO_STATS 342 { 343 int n = gettick() - starttick; 344 if (n < 8192) 345 x_nack_stimes[n >> 7]++; 346 } 347 #endif 348 while (gettick() < (tick + sys_clock_mhz)) 349 ; 350 do { 351 lo = lowbit(curnack) - 1; 352 i = IDSR_NACK_IDX(lo); 353 shipit(cpuids[i], i); 354 curnack &= ~(1ull << lo); 355 } while (curnack); 356 nack++; 357 busy = 0; 358 } 359 #ifdef SEND_MONDO_STATS 360 { 361 int n = gettick() - starttick; 362 if (n < 8192) 363 x_set_stimes[n >> 7]++; 364 else 365 x_set_ltimes[(n >> 13) & 0xf]++; 366 } 367 x_set_cpus[shipped]++; 368 #endif 369 } 370 371 /* 372 * Handles error logging for implementation specific error types 373 */ 374 /*ARGSUSED1*/ 375 int 376 cpu_impl_async_log_err(void *flt, errorq_elem_t *eqep) 377 { 378 ch_async_flt_t *ch_flt = (ch_async_flt_t *)flt; 379 struct async_flt *aflt = (struct async_flt *)flt; 380 381 switch (ch_flt->flt_type) { 382 383 case CPU_IC_PARITY: 384 cpu_async_log_ic_parity_err(flt); 385 return (CH_ASYNC_LOG_DONE); 386 387 case CPU_DC_PARITY: 388 cpu_async_log_dc_parity_err(flt); 389 return (CH_ASYNC_LOG_DONE); 390 391 case CPU_DUE: 392 cpu_log_err(aflt); 393 cpu_page_retire(ch_flt); 394 return (CH_ASYNC_LOG_DONE); 395 396 case CPU_ITLB_PARITY: 397 case CPU_DTLB_PARITY: 398 cpu_async_log_tlb_parity_err(flt); 399 return (CH_ASYNC_LOG_DONE); 400 401 default: 402 return (CH_ASYNC_LOG_UNKNOWN); 403 } 404 } 405 406 /* 407 * Figure out if Ecache is direct-mapped (Cheetah or Cheetah+ with Ecache 408 * control ECCR_ASSOC bit off or 2-way (Cheetah+ with ECCR_ASSOC on). 409 * We need to do this on the fly because we may have mixed Cheetah+'s with 410 * both direct and 2-way Ecaches. Panther only supports 4-way L3$. 411 */ 412 int 413 cpu_ecache_nway(void) 414 { 415 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation)) 416 return (PN_L3_NWAYS); 417 return ((get_ecache_ctrl() & ECCR_ASSOC) ? 2 : 1); 418 } 419 420 /* 421 * Note that these are entered into the table: Fatal Errors (PERR, IERR, ISAP, 422 * EMU, IMU) first, orphaned UCU/UCC, AFAR Overwrite policy, finally IVU, IVC. 423 * Afar overwrite policy is: 424 * Class 4: 425 * AFSR -- UCC, UCU, TUE, TSCE, TUE_SH 426 * AFSR_EXT -- L3_UCC, L3_UCU, L3_TUE, L3_TUE_SH 427 * Class 3: 428 * AFSR -- UE, DUE, EDU, WDU, CPU 429 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 430 * Class 2: 431 * AFSR -- CE, EDC, EMC, WDC, CPC, THCE 432 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC, L3_THCE 433 * Class 1: 434 * AFSR -- TO, DTO, BERR, DBERR 435 */ 436 ecc_type_to_info_t ecc_type_to_info[] = { 437 438 /* Fatal Errors */ 439 C_AFSR_PERR, "PERR ", ECC_ALL_TRAPS, 440 CPU_FATAL, "PERR Fatal", 441 FM_EREPORT_PAYLOAD_SYSTEM2, 442 FM_EREPORT_CPU_USIII_PERR, 443 C_AFSR_IERR, "IERR ", ECC_ALL_TRAPS, 444 CPU_FATAL, "IERR Fatal", 445 FM_EREPORT_PAYLOAD_SYSTEM2, 446 FM_EREPORT_CPU_USIII_IERR, 447 C_AFSR_ISAP, "ISAP ", ECC_ALL_TRAPS, 448 CPU_FATAL, "ISAP Fatal", 449 FM_EREPORT_PAYLOAD_SYSTEM1, 450 FM_EREPORT_CPU_USIII_ISAP, 451 C_AFSR_L3_TUE_SH, "L3_TUE_SH ", ECC_C_TRAP, 452 CPU_FATAL, "L3_TUE_SH Fatal", 453 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 454 FM_EREPORT_CPU_USIII_L3_TUE_SH, 455 C_AFSR_L3_TUE, "L3_TUE ", ECC_C_TRAP, 456 CPU_FATAL, "L3_TUE Fatal", 457 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 458 FM_EREPORT_CPU_USIII_L3_TUE, 459 C_AFSR_TUE_SH, "TUE_SH ", ECC_C_TRAP, 460 CPU_FATAL, "TUE_SH Fatal", 461 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 462 FM_EREPORT_CPU_USIII_TUE_SH, 463 C_AFSR_TUE, "TUE ", ECC_ALL_TRAPS, 464 CPU_FATAL, "TUE Fatal", 465 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 466 FM_EREPORT_CPU_USIII_TUE, 467 C_AFSR_EMU, "EMU ", ECC_ASYNC_TRAPS, 468 CPU_FATAL, "EMU Fatal", 469 FM_EREPORT_PAYLOAD_MEMORY, 470 FM_EREPORT_CPU_USIII_EMU, 471 C_AFSR_IMU, "IMU ", ECC_C_TRAP, 472 CPU_FATAL, "IMU Fatal", 473 FM_EREPORT_PAYLOAD_SYSTEM1, 474 FM_EREPORT_CPU_USIII_IMU, 475 476 /* L3$ Address parity errors are reported via the MECC bit */ 477 C_AFSR_L3_MECC, "L3_MECC ", ECC_MECC_TRAPS, 478 CPU_L3_ADDR_PE, "L3 Address Parity", 479 FM_EREPORT_PAYLOAD_L3_DATA, 480 FM_EREPORT_CPU_USIII_L3_MECC, 481 482 /* Orphaned UCC/UCU Errors */ 483 C_AFSR_L3_UCU, "L3_OUCU ", ECC_ORPH_TRAPS, 484 CPU_ORPH, "Orphaned L3_UCU", 485 FM_EREPORT_PAYLOAD_L3_DATA, 486 FM_EREPORT_CPU_USIII_L3_UCU, 487 C_AFSR_L3_UCC, "L3_OUCC ", ECC_ORPH_TRAPS, 488 CPU_ORPH, "Orphaned L3_UCC", 489 FM_EREPORT_PAYLOAD_L3_DATA, 490 FM_EREPORT_CPU_USIII_L3_UCC, 491 C_AFSR_UCU, "OUCU ", ECC_ORPH_TRAPS, 492 CPU_ORPH, "Orphaned UCU", 493 FM_EREPORT_PAYLOAD_L2_DATA, 494 FM_EREPORT_CPU_USIII_UCU, 495 C_AFSR_UCC, "OUCC ", ECC_ORPH_TRAPS, 496 CPU_ORPH, "Orphaned UCC", 497 FM_EREPORT_PAYLOAD_L2_DATA, 498 FM_EREPORT_CPU_USIII_UCC, 499 500 /* UCU, UCC */ 501 C_AFSR_L3_UCU, "L3_UCU ", ECC_F_TRAP, 502 CPU_UE_ECACHE, "L3_UCU", 503 FM_EREPORT_PAYLOAD_L3_DATA, 504 FM_EREPORT_CPU_USIII_L3_UCU, 505 C_AFSR_L3_UCC, "L3_UCC ", ECC_F_TRAP, 506 CPU_CE_ECACHE, "L3_UCC", 507 FM_EREPORT_PAYLOAD_L3_DATA, 508 FM_EREPORT_CPU_USIII_L3_UCC, 509 C_AFSR_UCU, "UCU ", ECC_F_TRAP, 510 CPU_UE_ECACHE, "UCU", 511 FM_EREPORT_PAYLOAD_L2_DATA, 512 FM_EREPORT_CPU_USIII_UCU, 513 C_AFSR_UCC, "UCC ", ECC_F_TRAP, 514 CPU_CE_ECACHE, "UCC", 515 FM_EREPORT_PAYLOAD_L2_DATA, 516 FM_EREPORT_CPU_USIII_UCC, 517 C_AFSR_TSCE, "TSCE ", ECC_F_TRAP, 518 CPU_CE_ECACHE, "TSCE", 519 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 520 FM_EREPORT_CPU_USIII_TSCE, 521 522 /* UE, EDU:ST, EDU:BLD, WDU, CPU */ 523 C_AFSR_UE, "UE ", ECC_ASYNC_TRAPS, 524 CPU_UE, "Uncorrectable system bus (UE)", 525 FM_EREPORT_PAYLOAD_MEMORY, 526 FM_EREPORT_CPU_USIII_UE, 527 C_AFSR_L3_EDU, "L3_EDU ", ECC_C_TRAP, 528 CPU_UE_ECACHE_RETIRE, "L3_EDU:ST", 529 FM_EREPORT_PAYLOAD_L3_DATA, 530 FM_EREPORT_CPU_USIII_L3_EDUST, 531 C_AFSR_L3_EDU, "L3_EDU ", ECC_D_TRAP, 532 CPU_UE_ECACHE_RETIRE, "L3_EDU:BLD", 533 FM_EREPORT_PAYLOAD_L3_DATA, 534 FM_EREPORT_CPU_USIII_L3_EDUBL, 535 C_AFSR_L3_WDU, "L3_WDU ", ECC_C_TRAP, 536 CPU_UE_ECACHE_RETIRE, "L3_WDU", 537 FM_EREPORT_PAYLOAD_L3_DATA, 538 FM_EREPORT_CPU_USIII_L3_WDU, 539 C_AFSR_L3_CPU, "L3_CPU ", ECC_C_TRAP, 540 CPU_UE_ECACHE, "L3_CPU", 541 FM_EREPORT_PAYLOAD_L3_DATA, 542 FM_EREPORT_CPU_USIII_L3_CPU, 543 C_AFSR_EDU, "EDU ", ECC_C_TRAP, 544 CPU_UE_ECACHE_RETIRE, "EDU:ST", 545 FM_EREPORT_PAYLOAD_L2_DATA, 546 FM_EREPORT_CPU_USIII_EDUST, 547 C_AFSR_EDU, "EDU ", ECC_D_TRAP, 548 CPU_UE_ECACHE_RETIRE, "EDU:BLD", 549 FM_EREPORT_PAYLOAD_L2_DATA, 550 FM_EREPORT_CPU_USIII_EDUBL, 551 C_AFSR_WDU, "WDU ", ECC_C_TRAP, 552 CPU_UE_ECACHE_RETIRE, "WDU", 553 FM_EREPORT_PAYLOAD_L2_DATA, 554 FM_EREPORT_CPU_USIII_WDU, 555 C_AFSR_CPU, "CPU ", ECC_C_TRAP, 556 CPU_UE_ECACHE, "CPU", 557 FM_EREPORT_PAYLOAD_L2_DATA, 558 FM_EREPORT_CPU_USIII_CPU, 559 C_AFSR_DUE, "DUE ", ECC_C_TRAP, 560 CPU_DUE, "DUE", 561 FM_EREPORT_PAYLOAD_MEMORY, 562 FM_EREPORT_CPU_USIII_DUE, 563 564 /* CE, EDC, EMC, WDC, CPC */ 565 C_AFSR_CE, "CE ", ECC_C_TRAP, 566 CPU_CE, "Corrected system bus (CE)", 567 FM_EREPORT_PAYLOAD_MEMORY, 568 FM_EREPORT_CPU_USIII_CE, 569 C_AFSR_L3_EDC, "L3_EDC ", ECC_C_TRAP, 570 CPU_CE_ECACHE, "L3_EDC", 571 FM_EREPORT_PAYLOAD_L3_DATA, 572 FM_EREPORT_CPU_USIII_L3_EDC, 573 C_AFSR_EDC, "EDC ", ECC_C_TRAP, 574 CPU_CE_ECACHE, "EDC", 575 FM_EREPORT_PAYLOAD_L2_DATA, 576 FM_EREPORT_CPU_USIII_EDC, 577 C_AFSR_EMC, "EMC ", ECC_C_TRAP, 578 CPU_EMC, "EMC", 579 FM_EREPORT_PAYLOAD_MEMORY, 580 FM_EREPORT_CPU_USIII_EMC, 581 C_AFSR_L3_WDC, "L3_WDC ", ECC_C_TRAP, 582 CPU_CE_ECACHE, "L3_WDC", 583 FM_EREPORT_PAYLOAD_L3_DATA, 584 FM_EREPORT_CPU_USIII_L3_WDC, 585 C_AFSR_L3_CPC, "L3_CPC ", ECC_C_TRAP, 586 CPU_CE_ECACHE, "L3_CPC", 587 FM_EREPORT_PAYLOAD_L3_DATA, 588 FM_EREPORT_CPU_USIII_L3_CPC, 589 C_AFSR_L3_THCE, "L3_THCE ", ECC_C_TRAP, 590 CPU_CE_ECACHE, "L3_THCE", 591 FM_EREPORT_PAYLOAD_L3_TAG_ECC, 592 FM_EREPORT_CPU_USIII_L3_THCE, 593 C_AFSR_WDC, "WDC ", ECC_C_TRAP, 594 CPU_CE_ECACHE, "WDC", 595 FM_EREPORT_PAYLOAD_L2_DATA, 596 FM_EREPORT_CPU_USIII_WDC, 597 C_AFSR_CPC, "CPC ", ECC_C_TRAP, 598 CPU_CE_ECACHE, "CPC", 599 FM_EREPORT_PAYLOAD_L2_DATA, 600 FM_EREPORT_CPU_USIII_CPC, 601 C_AFSR_THCE, "THCE ", ECC_C_TRAP, 602 CPU_CE_ECACHE, "THCE", 603 FM_EREPORT_PAYLOAD_L2_TAG_ECC, 604 FM_EREPORT_CPU_USIII_THCE, 605 606 /* TO, BERR */ 607 C_AFSR_TO, "TO ", ECC_ASYNC_TRAPS, 608 CPU_TO, "Timeout (TO)", 609 FM_EREPORT_PAYLOAD_IO, 610 FM_EREPORT_CPU_USIII_TO, 611 C_AFSR_BERR, "BERR ", ECC_ASYNC_TRAPS, 612 CPU_BERR, "Bus Error (BERR)", 613 FM_EREPORT_PAYLOAD_IO, 614 FM_EREPORT_CPU_USIII_BERR, 615 C_AFSR_DTO, "DTO ", ECC_C_TRAP, 616 CPU_TO, "Disrupting Timeout (DTO)", 617 FM_EREPORT_PAYLOAD_IO, 618 FM_EREPORT_CPU_USIII_DTO, 619 C_AFSR_DBERR, "DBERR ", ECC_C_TRAP, 620 CPU_BERR, "Disrupting Bus Error (DBERR)", 621 FM_EREPORT_PAYLOAD_IO, 622 FM_EREPORT_CPU_USIII_DBERR, 623 624 /* IVU, IVC, IMC */ 625 C_AFSR_IVU, "IVU ", ECC_C_TRAP, 626 CPU_IV, "IVU", 627 FM_EREPORT_PAYLOAD_SYSTEM1, 628 FM_EREPORT_CPU_USIII_IVU, 629 C_AFSR_IVC, "IVC ", ECC_C_TRAP, 630 CPU_IV, "IVC", 631 FM_EREPORT_PAYLOAD_SYSTEM1, 632 FM_EREPORT_CPU_USIII_IVC, 633 C_AFSR_IMC, "IMC ", ECC_C_TRAP, 634 CPU_IV, "IMC", 635 FM_EREPORT_PAYLOAD_SYSTEM1, 636 FM_EREPORT_CPU_USIII_IMC, 637 638 0, NULL, 0, 639 0, NULL, 640 FM_EREPORT_PAYLOAD_UNKNOWN, 641 FM_EREPORT_CPU_USIII_UNKNOWN, 642 }; 643 644 /* 645 * See Cheetah+ Delta PRM 10.9 and section P.6.1 of the Panther PRM 646 * Class 4: 647 * AFSR -- UCC, UCU, TUE, TSCE, TUE_SH 648 * AFSR_EXT -- L3_UCC, L3_UCU, L3_TUE, L3_TUE_SH 649 * Class 3: 650 * AFSR -- UE, DUE, EDU, EMU, WDU, CPU 651 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 652 * Class 2: 653 * AFSR -- CE, EDC, EMC, WDC, CPC, THCE 654 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC, L3_THCE 655 * Class 1: 656 * AFSR -- TO, DTO, BERR, DBERR 657 * AFSR_EXT -- 658 */ 659 uint64_t afar_overwrite[] = { 660 /* class 4: */ 661 C_AFSR_UCC | C_AFSR_UCU | C_AFSR_TUE | C_AFSR_TSCE | C_AFSR_TUE_SH | 662 C_AFSR_L3_UCC | C_AFSR_L3_UCU | C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH, 663 /* class 3: */ 664 C_AFSR_UE | C_AFSR_DUE | C_AFSR_EDU | C_AFSR_EMU | C_AFSR_WDU | 665 C_AFSR_CPU | C_AFSR_L3_EDU | C_AFSR_L3_WDU | C_AFSR_L3_CPU, 666 /* class 2: */ 667 C_AFSR_CE | C_AFSR_EDC | C_AFSR_EMC | C_AFSR_WDC | C_AFSR_CPC | 668 C_AFSR_THCE | C_AFSR_L3_EDC | C_AFSR_L3_WDC | C_AFSR_L3_CPC | 669 C_AFSR_L3_THCE, 670 /* class 1: */ 671 C_AFSR_TO | C_AFSR_DTO | C_AFSR_BERR | C_AFSR_DBERR, 672 673 0 674 }; 675 676 /* 677 * For Cheetah+, the E_SYND and M_SYND overwrite priorities are combined. 678 * See Cheetah+ Delta PRM 10.9 and Cheetah+ PRM 11.6.2 679 * Class 2: UE, DUE, IVU, EDU, EMU, WDU, UCU, CPU 680 * Class 1: CE, IVC, EDC, EMC, WDC, UCC, CPC 681 */ 682 uint64_t esynd_overwrite[] = { 683 /* class 2: */ 684 C_AFSR_UE | C_AFSR_DUE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_EMU | 685 C_AFSR_WDU | C_AFSR_UCU | C_AFSR_CPU, 686 /* class 1: */ 687 C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_EMC | C_AFSR_WDC | 688 C_AFSR_UCC | C_AFSR_CPC, 689 0 690 }; 691 692 /* 693 * In panther, the E_SYND overwrite policy changed a little bit 694 * by adding one more level. 695 * See Panther PRM P.6.2 696 * class 3: 697 * AFSR -- UCU, UCC 698 * AFSR_EXT -- L3_UCU, L3_UCC 699 * Class 2: 700 * AFSR -- UE, DUE, IVU, EDU, WDU, CPU 701 * AFSR_EXT -- L3_EDU, L3_WDU, L3_CPU 702 * Class 1: 703 * AFSR -- CE, IVC, EDC, WDC, CPC 704 * AFSR_EXT -- L3_EDC, L3_WDC, L3_CPC 705 */ 706 uint64_t pn_esynd_overwrite[] = { 707 /* class 3: */ 708 C_AFSR_UCU | C_AFSR_UCC | 709 C_AFSR_L3_UCU | C_AFSR_L3_UCC, 710 /* class 2: */ 711 C_AFSR_UE | C_AFSR_DUE | C_AFSR_IVU | C_AFSR_EDU | C_AFSR_WDU | 712 C_AFSR_CPU | 713 C_AFSR_L3_EDU | C_AFSR_L3_WDU | C_AFSR_L3_CPU, 714 /* class 1: */ 715 C_AFSR_CE | C_AFSR_IVC | C_AFSR_EDC | C_AFSR_WDC | C_AFSR_CPC | 716 C_AFSR_L3_EDC | C_AFSR_L3_WDC | C_AFSR_L3_CPC, 717 718 0 719 }; 720 721 int 722 afsr_to_pn_esynd_status(uint64_t afsr, uint64_t afsr_bit) 723 { 724 return (afsr_to_overw_status(afsr, afsr_bit, pn_esynd_overwrite)); 725 } 726 727 /* 728 * Prioritized list of Error bits for MSYND overwrite. 729 * See Panther PRM P.6.2 (For Cheetah+, see esynd_overwrite classes) 730 * Class 2: EMU, IMU 731 * Class 1: EMC, IMC 732 * 733 * Panther adds IMU and IMC. 734 */ 735 uint64_t msynd_overwrite[] = { 736 /* class 2: */ 737 C_AFSR_EMU | C_AFSR_IMU, 738 /* class 1: */ 739 C_AFSR_EMC | C_AFSR_IMC, 740 741 0 742 }; 743 744 /* 745 * change cpu speed bits -- new speed will be normal-speed/divisor. 746 * 747 * The Jalapeno memory controllers are required to drain outstanding 748 * memory transactions within 32 JBus clocks in order to be ready 749 * to enter Estar mode. In some corner cases however, that time 750 * fell short. 751 * 752 * A safe software solution is to force MCU to act like in Estar mode, 753 * then delay 1us (in ppm code) prior to assert J_CHNG_L signal. 754 * To reverse the effect, upon exiting Estar, software restores the 755 * MCU to its original state. 756 */ 757 /* ARGSUSED1 */ 758 void 759 cpu_change_speed(uint64_t divisor, uint64_t arg2) 760 { 761 bus_config_eclk_t *bceclk; 762 uint64_t reg; 763 764 for (bceclk = bus_config_eclk; bceclk->divisor; bceclk++) { 765 if (bceclk->divisor != divisor) 766 continue; 767 reg = get_safari_config(); 768 reg &= ~SAFARI_CONFIG_ECLK_MASK; 769 reg |= bceclk->mask; 770 set_safari_config(reg); 771 CPU->cpu_m.divisor = (uchar_t)divisor; 772 return; 773 } 774 /* 775 * We will reach here only if OBP and kernel don't agree on 776 * the speeds supported by the CPU. 777 */ 778 cmn_err(CE_WARN, "cpu_change_speed: bad divisor %" PRIu64, divisor); 779 } 780 781 /* 782 * Cpu private initialization. This includes allocating the cpu_private 783 * data structure, initializing it, and initializing the scrubber for this 784 * cpu. This function calls cpu_init_ecache_scrub_dr to init the scrubber. 785 * We use kmem_cache_create for the cheetah private data structure because 786 * it needs to be allocated on a PAGESIZE (8192) byte boundary. 787 */ 788 void 789 cpu_init_private(struct cpu *cp) 790 { 791 cheetah_private_t *chprp; 792 int i; 793 794 ASSERT(CPU_PRIVATE(cp) == NULL); 795 796 /* LINTED: E_TRUE_LOGICAL_EXPR */ 797 ASSERT((offsetof(cheetah_private_t, chpr_tl1_err_data) + 798 sizeof (ch_err_tl1_data_t) * CH_ERR_TL1_TLMAX) <= PAGESIZE); 799 800 /* 801 * Running with Cheetah CPUs in a Cheetah+, Jaguar, Panther or 802 * mixed Cheetah+/Jaguar/Panther machine is not a supported 803 * configuration. Attempting to do so may result in unpredictable 804 * failures (e.g. running Cheetah+ CPUs with Cheetah E$ disp flush) 805 * so don't allow it. 806 * 807 * This is just defensive code since this configuration mismatch 808 * should have been caught prior to OS execution. 809 */ 810 if (!(IS_CHEETAH_PLUS(cpunodes[cp->cpu_id].implementation) || 811 IS_JAGUAR(cpunodes[cp->cpu_id].implementation) || 812 IS_PANTHER(cpunodes[cp->cpu_id].implementation))) { 813 cmn_err(CE_PANIC, "CPU%d: UltraSPARC-III not supported" 814 " on UltraSPARC-III+/IV/IV+ code\n", cp->cpu_id); 815 } 816 817 /* 818 * If the ch_private_cache has not been created, create it. 819 */ 820 if (ch_private_cache == NULL) { 821 ch_private_cache = kmem_cache_create("ch_private_cache", 822 sizeof (cheetah_private_t), PAGESIZE, NULL, NULL, 823 NULL, NULL, static_arena, 0); 824 } 825 826 chprp = CPU_PRIVATE(cp) = kmem_cache_alloc(ch_private_cache, KM_SLEEP); 827 828 bzero(chprp, sizeof (cheetah_private_t)); 829 chprp->chpr_fecctl0_logout.clo_data.chd_afar = LOGOUT_INVALID; 830 chprp->chpr_cecc_logout.clo_data.chd_afar = LOGOUT_INVALID; 831 chprp->chpr_async_logout.clo_data.chd_afar = LOGOUT_INVALID; 832 chprp->chpr_tlb_logout.tlo_addr = LOGOUT_INVALID; 833 for (i = 0; i < CH_ERR_TL1_TLMAX; i++) 834 chprp->chpr_tl1_err_data[i].ch_err_tl1_logout.clo_data.chd_afar 835 = LOGOUT_INVALID; 836 837 /* Panther has a larger Icache compared to cheetahplus or Jaguar */ 838 if (IS_PANTHER(cpunodes[cp->cpu_id].implementation)) { 839 chprp->chpr_icache_size = PN_ICACHE_SIZE; 840 chprp->chpr_icache_linesize = PN_ICACHE_LSIZE; 841 } else { 842 chprp->chpr_icache_size = CH_ICACHE_SIZE; 843 chprp->chpr_icache_linesize = CH_ICACHE_LSIZE; 844 } 845 846 cpu_init_ecache_scrub_dr(cp); 847 848 /* 849 * Panther's L2$ and E$ are shared between cores, so the scrubber is 850 * only needed on one of the cores. At this point, we assume all cores 851 * are online, and we only enable the scrubber on core 0. 852 */ 853 if (IS_PANTHER(cpunodes[cp->cpu_id].implementation)) { 854 chprp->chpr_scrub_misc.chsm_core_state = 855 SCRUBBER_BOTH_CORES_ONLINE; 856 if (cp->cpu_id != (processorid_t)cmp_cpu_to_chip(cp->cpu_id)) { 857 chprp->chpr_scrub_misc.chsm_enable[ 858 CACHE_SCRUBBER_INFO_E] = 0; 859 } 860 } 861 862 chprp->chpr_ec_set_size = cpunodes[cp->cpu_id].ecache_size / 863 cpu_ecache_nway(); 864 865 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 866 ch_err_tl1_paddrs[cp->cpu_id] = va_to_pa(chprp); 867 ASSERT(ch_err_tl1_paddrs[cp->cpu_id] != -1); 868 } 869 870 /* 871 * Clear the error state registers for this CPU. 872 * For Cheetah+/Jaguar, just clear the AFSR but 873 * for Panther we also have to clear the AFSR_EXT. 874 */ 875 void 876 set_cpu_error_state(ch_cpu_errors_t *cpu_error_regs) 877 { 878 set_asyncflt(cpu_error_regs->afsr & ~C_AFSR_FATAL_ERRS); 879 if (IS_PANTHER(cpunodes[CPU->cpu_id].implementation)) { 880 set_afsr_ext(cpu_error_regs->afsr_ext & ~C_AFSR_EXT_FATAL_ERRS); 881 } 882 } 883 884 void 885 pn_cpu_log_diag_l2_info(ch_async_flt_t *ch_flt) { 886 struct async_flt *aflt = (struct async_flt *)ch_flt; 887 ch_ec_data_t *l2_data = &ch_flt->flt_diag_data.chd_l2_data[0]; 888 uint64_t faddr = aflt->flt_addr; 889 uint8_t log_way_mask = 0; 890 int i; 891 892 /* 893 * Only Panther CPUs have the additional L2$ data that needs 894 * to be logged here 895 */ 896 if (!IS_PANTHER(cpunodes[aflt->flt_inst].implementation)) 897 return; 898 899 /* 900 * We'll use a simple bit mask to keep track of which way(s) 901 * of the stored cache line we want to log. The idea is to 902 * log the entry if it is a valid line and it matches our 903 * fault AFAR. If no match is found, we will simply log all 904 * the ways. 905 */ 906 for (i = 0; i < PN_L2_NWAYS; i++) 907 if (pn_matching_valid_l2_line(faddr, &l2_data[i])) 908 log_way_mask |= (1 << i); 909 910 /* If no matching valid lines were found, we log all ways */ 911 if (log_way_mask == 0) 912 log_way_mask = (1 << PN_L2_NWAYS) - 1; 913 914 /* Log the cache lines */ 915 for (i = 0; i < PN_L2_NWAYS; i++) 916 if (log_way_mask & (1 << i)) 917 l2_data[i].ec_logflag = EC_LOGFLAG_MAGIC; 918 } 919 920 /* 921 * For this routine to return true, the L2 tag in question must be valid 922 * and the tag PA must match the fault address (faddr) assuming the correct 923 * index is being used. 924 */ 925 static int 926 pn_matching_valid_l2_line(uint64_t faddr, ch_ec_data_t *clo_l2_data) { 927 if ((!PN_L2_LINE_INVALID(clo_l2_data->ec_tag)) && 928 ((faddr & P2ALIGN(C_AFAR_PA, PN_L2_SET_SIZE)) == 929 PN_L2TAG_TO_PA(clo_l2_data->ec_tag))) 930 return (1); 931 return (0); 932 } 933 934 /* 935 * This array is used to convert the 3 digit PgSz encoding (as used in 936 * various MMU registers such as MMU_TAG_ACCESS_EXT) into the corresponding 937 * page size. 938 */ 939 static uint64_t tlb_pgsz_to_size[] = { 940 /* 000 = 8KB: */ 941 0x2000, 942 /* 001 = 64KB: */ 943 0x10000, 944 /* 010 = 512KB: */ 945 0x80000, 946 /* 011 = 4MB: */ 947 0x400000, 948 /* 100 = 32MB: */ 949 0x2000000, 950 /* 101 = 256MB: */ 951 0x10000000, 952 /* undefined for encodings 110 and 111: */ 953 0, 0 954 }; 955 956 /* 957 * The itlb_parity_trap and dtlb_parity_trap handlers transfer control here 958 * after collecting logout information related to the TLB parity error and 959 * flushing the offending TTE entries from the ITLB or DTLB. 960 * 961 * DTLB traps which occur at TL>0 are not recoverable because we will most 962 * likely be corrupting some other trap handler's alternate globals. As 963 * such, we simply panic here when that happens. ITLB parity errors are 964 * not expected to happen at TL>0. 965 */ 966 void 967 cpu_tlb_parity_error(struct regs *rp, ulong_t trap_va, ulong_t tlb_info) { 968 ch_async_flt_t ch_flt; 969 struct async_flt *aflt; 970 pn_tlb_logout_t *tlop = NULL; 971 int immu_parity = (tlb_info & PN_TLO_INFO_IMMU) != 0; 972 int tl1_trap = (tlb_info & PN_TLO_INFO_TL1) != 0; 973 char *error_class; 974 975 bzero(&ch_flt, sizeof (ch_async_flt_t)); 976 977 /* 978 * Get the CPU log out info. If we can't find our CPU private 979 * pointer, or if the logout information does not correspond to 980 * this error, then we will have to make due without detailed 981 * logout information. 982 */ 983 if (CPU_PRIVATE(CPU)) { 984 tlop = CPU_PRIVATE_PTR(CPU, chpr_tlb_logout); 985 if ((tlop->tlo_addr != trap_va) || 986 (tlop->tlo_info != tlb_info)) 987 tlop = NULL; 988 } 989 990 if (tlop) { 991 ch_flt.tlb_diag_data = *tlop; 992 993 /* Zero out + invalidate TLB logout. */ 994 bzero(tlop, sizeof (pn_tlb_logout_t)); 995 tlop->tlo_addr = LOGOUT_INVALID; 996 } else { 997 /* 998 * Copy what logout information we have and mark 999 * it incomplete. 1000 */ 1001 ch_flt.flt_data_incomplete = 1; 1002 ch_flt.tlb_diag_data.tlo_info = tlb_info; 1003 ch_flt.tlb_diag_data.tlo_addr = trap_va; 1004 } 1005 1006 /* 1007 * Log the error. 1008 */ 1009 aflt = (struct async_flt *)&ch_flt; 1010 aflt->flt_id = gethrtime_waitfree(); 1011 aflt->flt_bus_id = getprocessorid(); 1012 aflt->flt_inst = CPU->cpu_id; 1013 aflt->flt_pc = (caddr_t)rp->r_pc; 1014 aflt->flt_addr = trap_va; 1015 aflt->flt_prot = AFLT_PROT_NONE; 1016 aflt->flt_class = CPU_FAULT; 1017 aflt->flt_priv = (rp->r_tstate & TSTATE_PRIV) ? 1 : 0; 1018 aflt->flt_tl = tl1_trap ? 1 : 0; 1019 aflt->flt_panic = tl1_trap ? 1 : 0; 1020 1021 if (immu_parity) { 1022 aflt->flt_status = ECC_ITLB_TRAP; 1023 ch_flt.flt_type = CPU_ITLB_PARITY; 1024 error_class = FM_EREPORT_CPU_USIII_ITLBPE; 1025 aflt->flt_payload = FM_EREPORT_PAYLOAD_ITLB_PE; 1026 } else { 1027 aflt->flt_status = ECC_DTLB_TRAP; 1028 ch_flt.flt_type = CPU_DTLB_PARITY; 1029 error_class = FM_EREPORT_CPU_USIII_DTLBPE; 1030 aflt->flt_payload = FM_EREPORT_PAYLOAD_DTLB_PE; 1031 } 1032 1033 /* 1034 * The TLB entries have already been flushed by the TL1 trap 1035 * handler so at this point the only thing left to do is log 1036 * the error message. 1037 */ 1038 if (aflt->flt_panic) { 1039 cpu_errorq_dispatch(error_class, (void *)&ch_flt, 1040 sizeof (ch_async_flt_t), ue_queue, aflt->flt_panic); 1041 /* 1042 * Panic here if aflt->flt_panic has been set. Enqueued 1043 * errors will be logged as part of the panic flow. 1044 */ 1045 fm_panic("%sError(s)", immu_parity ? "ITLBPE " : "DTLBPE "); 1046 } else { 1047 cpu_errorq_dispatch(error_class, (void *)&ch_flt, 1048 sizeof (ch_async_flt_t), ce_queue, aflt->flt_panic); 1049 } 1050 } 1051 1052 /* 1053 * This routine is called when a TLB parity error event is 'ue_drain'ed 1054 * or 'ce_drain'ed from the errorq. 1055 */ 1056 void 1057 cpu_async_log_tlb_parity_err(void *flt) { 1058 ch_async_flt_t *ch_flt = (ch_async_flt_t *)flt; 1059 struct async_flt *aflt = (struct async_flt *)flt; 1060 #ifdef lint 1061 aflt = aflt; 1062 #endif 1063 1064 /* 1065 * We only capture TLB information if we encountered 1066 * a TLB parity error and Panther is the only CPU which 1067 * can detect a TLB parity error. 1068 */ 1069 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1070 ASSERT((ch_flt->flt_type == CPU_ITLB_PARITY) || 1071 (ch_flt->flt_type == CPU_DTLB_PARITY)); 1072 1073 if (ch_flt->flt_data_incomplete == 0) { 1074 if (ch_flt->flt_type == CPU_ITLB_PARITY) 1075 ch_flt->tlb_diag_data.tlo_logflag = IT_LOGFLAG_MAGIC; 1076 else /* parity error is in DTLB */ 1077 ch_flt->tlb_diag_data.tlo_logflag = DT_LOGFLAG_MAGIC; 1078 } 1079 } 1080 1081 /* 1082 * Add L1 Prefetch cache data to the ereport payload. 1083 */ 1084 void 1085 cpu_payload_add_pcache(struct async_flt *aflt, nvlist_t *nvl) 1086 { 1087 ch_async_flt_t *ch_flt = (ch_async_flt_t *)aflt; 1088 ch_pc_data_t *pcp; 1089 ch_pc_data_t pcdata[CH_PCACHE_NWAY]; 1090 uint_t nelem; 1091 int i, ways_logged = 0; 1092 1093 /* 1094 * We only capture P$ information if we encountered 1095 * a P$ parity error and Panther is the only CPU which 1096 * can detect a P$ parity error. 1097 */ 1098 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1099 for (i = 0; i < CH_PCACHE_NWAY; i++) { 1100 pcp = &ch_flt->parity_data.dpe.cpl_pc[i]; 1101 if (pcp->pc_logflag == PC_LOGFLAG_MAGIC) { 1102 bcopy(pcp, &pcdata[ways_logged], 1103 sizeof (ch_pc_data_t)); 1104 ways_logged++; 1105 } 1106 } 1107 1108 /* 1109 * Add the pcache data to the payload. 1110 */ 1111 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_L1P_WAYS, 1112 DATA_TYPE_UINT8, (uint8_t)ways_logged, NULL); 1113 if (ways_logged != 0) { 1114 nelem = sizeof (ch_pc_data_t) / sizeof (uint64_t) * ways_logged; 1115 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_L1P_DATA, 1116 DATA_TYPE_UINT64_ARRAY, nelem, (uint64_t *)pcdata, NULL); 1117 } 1118 } 1119 1120 /* 1121 * Add TLB diagnostic data to the ereport payload. 1122 */ 1123 void 1124 cpu_payload_add_tlb(struct async_flt *aflt, nvlist_t *nvl) 1125 { 1126 ch_async_flt_t *ch_flt = (ch_async_flt_t *)aflt; 1127 uint8_t num_entries, tlb_data_words; 1128 1129 /* 1130 * We only capture TLB information if we encountered 1131 * a TLB parity error and Panther is the only CPU which 1132 * can detect a TLB parity error. 1133 */ 1134 ASSERT(IS_PANTHER(cpunodes[aflt->flt_inst].implementation)); 1135 ASSERT((ch_flt->flt_type == CPU_ITLB_PARITY) || 1136 (ch_flt->flt_type == CPU_DTLB_PARITY)); 1137 1138 if (ch_flt->flt_type == CPU_ITLB_PARITY) { 1139 num_entries = (uint8_t)(PN_ITLB_NWAYS * PN_NUM_512_ITLBS); 1140 tlb_data_words = sizeof (ch_tte_entry_t) / sizeof (uint64_t) * 1141 num_entries; 1142 1143 /* 1144 * Add the TLB diagnostic data to the payload 1145 * if it was collected. 1146 */ 1147 if (ch_flt->tlb_diag_data.tlo_logflag == IT_LOGFLAG_MAGIC) { 1148 fm_payload_set(nvl, 1149 FM_EREPORT_PAYLOAD_NAME_ITLB_ENTRIES, 1150 DATA_TYPE_UINT8, num_entries, NULL); 1151 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_ITLB_DATA, 1152 DATA_TYPE_UINT64_ARRAY, tlb_data_words, 1153 (uint64_t *)ch_flt->tlb_diag_data.tlo_itlb_tte, 1154 NULL); 1155 } 1156 } else { 1157 num_entries = (uint8_t)(PN_DTLB_NWAYS * PN_NUM_512_DTLBS); 1158 tlb_data_words = sizeof (ch_tte_entry_t) / sizeof (uint64_t) * 1159 num_entries; 1160 1161 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_VA, 1162 DATA_TYPE_UINT64, ch_flt->tlb_diag_data.tlo_addr, NULL); 1163 1164 /* 1165 * Add the TLB diagnostic data to the payload 1166 * if it was collected. 1167 */ 1168 if (ch_flt->tlb_diag_data.tlo_logflag == DT_LOGFLAG_MAGIC) { 1169 fm_payload_set(nvl, 1170 FM_EREPORT_PAYLOAD_NAME_DTLB_ENTRIES, 1171 DATA_TYPE_UINT8, num_entries, NULL); 1172 fm_payload_set(nvl, FM_EREPORT_PAYLOAD_NAME_DTLB_DATA, 1173 DATA_TYPE_UINT64_ARRAY, tlb_data_words, 1174 (uint64_t *)ch_flt->tlb_diag_data.tlo_dtlb_tte, 1175 NULL); 1176 } 1177 } 1178 } 1179 1180 /* 1181 * Panther Cache Scrubbing: 1182 * 1183 * In Jaguar, the E$ was split between cores, so the scrubber must run on both 1184 * cores. For Panther, however, the L2$ and L3$ are shared across cores. 1185 * Therefore, the E$ scrubber only needs to run on one of the two cores. 1186 * 1187 * There are four possible states for the E$ scrubber: 1188 * 1189 * 0. If both cores are offline, add core 0 to cpu_offline_set so that 1190 * the offline scrubber will run on it. 1191 * 1. If core 0 is online and core 1 off, we run the scrubber on core 0. 1192 * 2. If core 1 is online and core 0 off, we move the scrubber to run 1193 * on core 1. 1194 * 3. If both cores are online, only run the scrubber on core 0. 1195 * 1196 * These states are enumerated by the SCRUBBER_[BOTH|CORE|NEITHER]_* defines 1197 * above. One of those values is stored in 1198 * chpr_scrub_misc->chsm_core_state on each core. 1199 * 1200 * Also note that, for Panther, ecache_flush_line() will flush out the L2$ 1201 * before the E$, so the L2$ will be scrubbed by the E$ scrubber. No 1202 * additional code is necessary to scrub the L2$. 1203 * 1204 * For all cpu types, whenever a cpu or core is offlined, add it to 1205 * cpu_offline_set so the necessary scrubbers can still run. This is still 1206 * necessary on Panther so the D$ scrubber can still run. 1207 */ 1208 /*ARGSUSED*/ 1209 int 1210 cpu_scrub_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 1211 { 1212 processorid_t core_0_id; 1213 cpu_t *core_cpus[2]; 1214 ch_scrub_misc_t *core_scrub[2]; 1215 int old_state, i; 1216 int new_state = SCRUBBER_NEITHER_CORE_ONLINE; 1217 1218 switch (what) { 1219 case CPU_ON: 1220 case CPU_INIT: 1221 CPUSET_DEL(cpu_offline_set, cpuid); 1222 break; 1223 case CPU_OFF: 1224 CPUSET_ADD(cpu_offline_set, cpuid); 1225 break; 1226 default: 1227 return (0); 1228 } 1229 1230 if (!IS_PANTHER(cpunodes[cpuid].implementation)) { 1231 return (0); 1232 } 1233 1234 /* 1235 * Update the chsm_enable[CACHE_SCRUBBER_INFO_E] value 1236 * if necessary 1237 */ 1238 core_0_id = cmp_cpu_to_chip(cpuid); 1239 core_cpus[0] = cpu_get(core_0_id); 1240 core_cpus[1] = cpu_get_sibling_core(core_cpus[0]); 1241 1242 for (i = 0; i < 2; i++) { 1243 if (core_cpus[i] == NULL) { 1244 /* 1245 * This may happen during DR - one core is offlined 1246 * and completely unconfigured before the second 1247 * core is offlined. Give up and return quietly, 1248 * since the second core should quickly be removed 1249 * anyways. 1250 */ 1251 return (0); 1252 } 1253 core_scrub[i] = CPU_PRIVATE_PTR(core_cpus[i], chpr_scrub_misc); 1254 } 1255 1256 if (cpuid == (processorid_t)cmp_cpu_to_chip(cpuid)) { 1257 /* cpuid is core 0 */ 1258 if (cpu_is_active(core_cpus[1])) { 1259 new_state |= SCRUBBER_CORE_1_ONLINE; 1260 } 1261 if (what != CPU_OFF) { 1262 new_state |= SCRUBBER_CORE_0_ONLINE; 1263 } 1264 } else { 1265 /* cpuid is core 1 */ 1266 if (cpu_is_active(core_cpus[0])) { 1267 new_state |= SCRUBBER_CORE_0_ONLINE; 1268 } 1269 if (what != CPU_OFF) { 1270 new_state |= SCRUBBER_CORE_1_ONLINE; 1271 } 1272 } 1273 1274 old_state = core_scrub[0]->chsm_core_state; 1275 1276 if (old_state == new_state) { 1277 return (0); 1278 } 1279 1280 if (old_state == SCRUBBER_CORE_1_ONLINE) { 1281 /* 1282 * We need to move the scrubber state from core 1 1283 * back to core 0. This data is not protected by 1284 * locks, but the worst that can happen is some 1285 * lines are scrubbed multiple times. chsm_oustanding is 1286 * set to 0 to make sure an interrupt is scheduled the 1287 * first time through do_scrub(). 1288 */ 1289 core_scrub[0]->chsm_flush_index[CACHE_SCRUBBER_INFO_E] = 1290 core_scrub[1]->chsm_flush_index[CACHE_SCRUBBER_INFO_E]; 1291 core_scrub[0]->chsm_outstanding[CACHE_SCRUBBER_INFO_E] = 0; 1292 } 1293 1294 switch (new_state) { 1295 case SCRUBBER_NEITHER_CORE_ONLINE: 1296 case SCRUBBER_BOTH_CORES_ONLINE: 1297 case SCRUBBER_CORE_0_ONLINE: 1298 core_scrub[1]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 0; 1299 core_scrub[0]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 1; 1300 break; 1301 1302 case SCRUBBER_CORE_1_ONLINE: 1303 default: 1304 /* 1305 * We need to move the scrubber state from core 0 1306 * to core 1. 1307 */ 1308 core_scrub[1]->chsm_flush_index[CACHE_SCRUBBER_INFO_E] = 1309 core_scrub[0]->chsm_flush_index[CACHE_SCRUBBER_INFO_E]; 1310 core_scrub[1]->chsm_outstanding[CACHE_SCRUBBER_INFO_E] = 0; 1311 1312 core_scrub[0]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 0; 1313 core_scrub[1]->chsm_enable[CACHE_SCRUBBER_INFO_E] = 1; 1314 break; 1315 } 1316 1317 core_scrub[0]->chsm_core_state = new_state; 1318 core_scrub[1]->chsm_core_state = new_state; 1319 return (0); 1320 } 1321 1322 /* 1323 * Returns a pointer to the cpu structure of the argument's sibling core. 1324 * If no sibling core can be found, return NULL. 1325 */ 1326 static cpu_t * 1327 cpu_get_sibling_core(cpu_t *cpup) 1328 { 1329 cpu_t *nextp; 1330 1331 if ((cpup == NULL) || (!cmp_cpu_is_cmp(cpup->cpu_id))) 1332 return (NULL); 1333 1334 nextp = cpup->cpu_next_chip; 1335 if ((nextp == NULL) || (nextp == cpup)) 1336 return (NULL); 1337 1338 return (nextp); 1339 } 1340