1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/sunddi.h> 32 #include <sys/esunddi.h> 33 #include <sys/sunndi.h> 34 #include <sys/ddi.h> 35 #include <sys/modctl.h> 36 #include <sys/sysmacros.h> 37 #include <sys/note.h> 38 39 #include <sys/platform_module.h> 40 #include <sys/errno.h> 41 #include <sys/i2c/clients/i2c_client.h> 42 #include <sys/cherrystone.h> 43 #include <sys/machsystm.h> 44 #include <sys/promif.h> 45 #include <vm/page.h> 46 #include <sys/memnode.h> 47 #include <vm/vm_dep.h> 48 49 /* Cherrystone Keyswitch Information */ 50 #define CHERRY_KEY_POLL_PORT 3 51 #define CHERRY_KEY_POLL_BIT 2 52 #define CHERRY_KEY_POLL_INTVL 10 53 54 #define SHARED_PCF8584_PATH "/pci@9,700000/ebus@1/i2c@1,2e/nvram@4,a4" 55 static dev_info_t *shared_pcf8584_dip; 56 static kmutex_t cherry_pcf8584_mutex; 57 58 static boolean_t key_locked_bit; 59 static clock_t keypoll_timeout_hz; 60 61 /* 62 * Table that maps memory slices to a specific memnode. 63 */ 64 int slice_to_memnode[CHERRYSTONE_MAX_SLICE]; 65 66 /* 67 * For software memory interleaving support. 68 */ 69 static void update_mem_bounds(int, int, int, uint64_t, uint64_t); 70 71 static uint64_t 72 slice_table[CHERRYSTONE_SBD_SLOTS][CHERRYSTONE_CPUS_PER_BOARD] 73 [CHERRYSTONE_BANKS_PER_MC][2]; 74 75 #define SLICE_PA 0 76 #define SLICE_SPAN 1 77 78 /* Function prototypes */ 79 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 80 81 int (*cherry_ssc050_get_port_bit) (dev_info_t *, int, int, uint8_t *, int); 82 extern void (*abort_seq_handler)(); 83 84 static int cherry_dev_search(dev_info_t *, void *); 85 static void keyswitch_poll(void *); 86 static void cherry_abort_seq_handler(char *msg); 87 88 /* Function definitions from this point forward. */ 89 90 int 91 set_platform_tsb_spares() 92 { 93 return (0); 94 } 95 96 void 97 startup_platform(void) 98 { 99 /* 100 * Disable an active h/w watchdog timer 101 * upon exit to OBP. 102 */ 103 extern int disable_watchdog_on_exit; 104 disable_watchdog_on_exit = 1; 105 106 mutex_init(&cherry_pcf8584_mutex, NULL, NULL, NULL); 107 } 108 109 #pragma weak mmu_init_large_pages 110 111 void 112 set_platform_defaults(void) 113 { 114 extern void mmu_init_large_pages(size_t); 115 116 if ((mmu_page_sizes == max_mmu_page_sizes) && 117 (mmu_ism_pagesize != MMU_PAGESIZE32M)) { 118 if (&mmu_init_large_pages) 119 mmu_init_large_pages(mmu_ism_pagesize); 120 } 121 } 122 123 void 124 load_platform_modules(void) 125 { 126 if (modload("drv", "pmc") < 0) { 127 cmn_err(CE_NOTE, "pmc driver failed to load"); 128 } 129 } 130 131 void 132 load_platform_drivers(void) 133 { 134 char **drv; 135 dev_info_t *i2cnexus_dip; 136 dev_info_t *keysw_dip = NULL; 137 138 static char *boot_time_drivers[] = { 139 "todds1287", 140 "mc-us3", 141 "ssc050", 142 NULL 143 }; 144 145 for (drv = boot_time_drivers; *drv; drv++) { 146 if (i_ddi_attach_hw_nodes(*drv) != DDI_SUCCESS) 147 cmn_err(CE_WARN, "Failed to install \"%s\" driver.", 148 *drv); 149 } 150 151 /* 152 * mc-us3 and ssc050 must stay loaded for plat_get_mem_unum() 153 * and keyswitch_poll() 154 */ 155 (void) ddi_hold_driver(ddi_name_to_major("mc-us3")); 156 (void) ddi_hold_driver(ddi_name_to_major("ssc050")); 157 158 /* Gain access into the ssc050_get_port function */ 159 cherry_ssc050_get_port_bit = (int (*) (dev_info_t *, int, int, 160 uint8_t *, int)) modgetsymvalue("ssc050_get_port_bit", 0); 161 if (cherry_ssc050_get_port_bit == NULL) { 162 cmn_err(CE_WARN, "cannot find ssc050_get_port_bit"); 163 return; 164 } 165 166 e_ddi_walk_driver("i2c-ssc050", cherry_dev_search, (void *)&keysw_dip); 167 ASSERT(keysw_dip != NULL); 168 169 keypoll_timeout_hz = drv_usectohz(10 * MICROSEC); 170 keyswitch_poll(keysw_dip); 171 abort_seq_handler = cherry_abort_seq_handler; 172 173 /* 174 * Figure out which pcf8584_dip is shared with OBP for the nvram 175 * device, so the lock can be acquired. 176 */ 177 178 i2cnexus_dip = e_ddi_hold_devi_by_path(SHARED_PCF8584_PATH, 0); 179 180 ASSERT(i2cnexus_dip != NULL); 181 shared_pcf8584_dip = ddi_get_parent(i2cnexus_dip); 182 183 ndi_hold_devi(shared_pcf8584_dip); 184 ndi_rele_devi(i2cnexus_dip); 185 } 186 187 static int 188 cherry_dev_search(dev_info_t *dip, void *arg) 189 { 190 int *dev_regs; /* Info about where the device is. */ 191 uint_t len; 192 int err; 193 194 if (strcmp(ddi_binding_name(dip), "i2c-ssc050") != 0) 195 return (DDI_WALK_CONTINUE); 196 197 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 198 DDI_PROP_DONTPASS, "reg", &dev_regs, &len); 199 if (err != DDI_PROP_SUCCESS) { 200 return (DDI_WALK_CONTINUE); 201 } 202 /* 203 * regs[0] contains the bus number and regs[1] 204 * contains the device address of the i2c device. 205 * 0x82 is the device address of the i2c device 206 * from which the key switch position is read. 207 */ 208 if (dev_regs[0] == 0 && dev_regs[1] == 0x82) { 209 *((dev_info_t **)arg) = dip; 210 ddi_prop_free(dev_regs); 211 return (DDI_WALK_TERMINATE); 212 } 213 ddi_prop_free(dev_regs); 214 return (DDI_WALK_CONTINUE); 215 } 216 217 static void 218 keyswitch_poll(void *arg) 219 { 220 dev_info_t *dip = arg; 221 uchar_t port_byte; 222 int port = CHERRY_KEY_POLL_PORT; 223 int bit = CHERRY_KEY_POLL_BIT; 224 int err; 225 226 err = cherry_ssc050_get_port_bit(dip, port, bit, 227 &port_byte, I2C_NOSLEEP); 228 if (err != 0) { 229 return; 230 } 231 232 key_locked_bit = (boolean_t)((port_byte & 0x1)); 233 timeout(keyswitch_poll, (caddr_t)dip, keypoll_timeout_hz); 234 } 235 236 static void 237 cherry_abort_seq_handler(char *msg) 238 { 239 if (key_locked_bit == 0) 240 cmn_err(CE_CONT, "KEY in LOCKED position, " 241 "ignoring debug enter sequence"); 242 else { 243 debug_enter(msg); 244 } 245 } 246 247 248 /*ARGSUSED*/ 249 int 250 plat_cpu_poweron(struct cpu *cp) 251 { 252 return (ENOTSUP); /* not supported on this platform */ 253 } 254 255 /*ARGSUSED*/ 256 int 257 plat_cpu_poweroff(struct cpu *cp) 258 { 259 return (ENOTSUP); /* not supported on this platform */ 260 } 261 262 /* 263 * Given a pfn, return the board and beginning/end of the page's 264 * memory controller's address range. 265 */ 266 static int 267 plat_discover_slice(pfn_t pfn, pfn_t *first, pfn_t *last) 268 { 269 int bd, cpu, bank; 270 271 for (bd = 0; bd < CHERRYSTONE_SBD_SLOTS; bd++) { 272 for (cpu = 0; cpu < CHERRYSTONE_CPUS_PER_BOARD; cpu++) { 273 for (bank = 0; bank < CHERRYSTONE_BANKS_PER_MC; 274 bank++) { 275 uint64_t *slice = slice_table[bd][cpu][bank]; 276 uint64_t base = btop(slice[SLICE_PA]); 277 uint64_t len = btop(slice[SLICE_SPAN]); 278 if (len && pfn >= base && pfn < (base + len)) { 279 *first = base; 280 *last = base + len - 1; 281 return (bd); 282 } 283 } 284 } 285 } 286 panic("plat_discover_slice: no slice for pfn 0x%lx\n", pfn); 287 /* NOTREACHED */ 288 } 289 290 /*ARGSUSED*/ 291 void 292 plat_freelist_process(int mnode) 293 {} 294 295 /* 296 * Called for each board/cpu/PA range detected in plat_fill_mc(). 297 */ 298 static void 299 update_mem_bounds(int boardid, int cpuid, int bankid, 300 uint64_t base, uint64_t size) 301 { 302 uint64_t end; 303 int mnode; 304 305 slice_table[boardid][cpuid][bankid][SLICE_PA] = base; 306 slice_table[boardid][cpuid][bankid][SLICE_SPAN] = size; 307 308 end = base + size - 1; 309 310 /* 311 * First see if this board already has a memnode associated 312 * with it. If not, see if this slice has a memnode. This 313 * covers the cases where a single slice covers multiple 314 * boards (cross-board interleaving) and where a single 315 * board has multiple slices (1+GB DIMMs). 316 */ 317 if ((mnode = plat_lgrphand_to_mem_node(boardid)) == -1) { 318 if ((mnode = slice_to_memnode[PA_2_SLICE(base)]) == -1) 319 mnode = mem_node_alloc(); 320 321 ASSERT(mnode >= 0); 322 ASSERT(mnode < MAX_MEM_NODES); 323 plat_assign_lgrphand_to_mem_node(boardid, mnode); 324 } 325 326 base = P2ALIGN(base, (1ul << PA_SLICE_SHIFT)); 327 328 while (base < end) { 329 slice_to_memnode[PA_2_SLICE(base)] = mnode; 330 base += (1ul << PA_SLICE_SHIFT); 331 } 332 } 333 334 /* 335 * Dynamically detect memory slices in the system by decoding 336 * the cpu memory decoder registers at boot time. 337 */ 338 void 339 plat_fill_mc(pnode_t nodeid) 340 { 341 uint64_t mc_addr, saf_addr; 342 uint64_t mc_decode[CHERRYSTONE_BANKS_PER_MC]; 343 uint64_t base, size; 344 uint64_t saf_mask; 345 uint64_t offset; 346 uint32_t regs[4]; 347 int len; 348 int local_mc; 349 int portid; 350 int boardid; 351 int cpuid; 352 int i; 353 354 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) < 0) || 355 (portid == -1)) 356 return; 357 358 /* 359 * Decode the board number from the MC portid. Assumes 360 * portid == safari agentid. 361 */ 362 boardid = CHERRYSTONE_GETSLOT(portid); 363 cpuid = CHERRYSTONE_GETSID(portid); 364 365 /* 366 * The "reg" property returns 4 32-bit values. The first two are 367 * combined to form a 64-bit address. The second two are for a 368 * 64-bit size, but we don't actually need to look at that value. 369 */ 370 len = prom_getproplen(nodeid, "reg"); 371 if (len != (sizeof (uint32_t) * 4)) { 372 prom_printf("Warning: malformed 'reg' property\n"); 373 return; 374 } 375 if (prom_getprop(nodeid, "reg", (caddr_t)regs) < 0) 376 return; 377 mc_addr = ((uint64_t)regs[0]) << 32; 378 mc_addr |= (uint64_t)regs[1]; 379 380 /* 381 * Figure out whether the memory controller we are examining 382 * belongs to this CPU or a different one. 383 */ 384 saf_addr = lddsafaddr(8); 385 saf_mask = (uint64_t)SAF_MASK; 386 if ((mc_addr & saf_mask) == saf_addr) 387 local_mc = 1; 388 else 389 local_mc = 0; 390 391 for (i = 0; i < CHERRYSTONE_BANKS_PER_MC; i++) { 392 /* 393 * Memory decode masks are at offsets 0x10 - 0x28. 394 */ 395 offset = 0x10 + (i << 3); 396 397 /* 398 * If the memory controller is local to this CPU, we use 399 * the special ASI to read the decode registers. 400 * Otherwise, we load the values from a magic address in 401 * I/O space. 402 */ 403 if (local_mc) 404 mc_decode[i] = lddmcdecode(offset); 405 else 406 mc_decode[i] = lddphysio(mc_addr | offset); 407 408 /* 409 * If the upper bit is set, we have a valid mask 410 */ 411 if ((int64_t)mc_decode[i] < 0) { 412 /* 413 * The memory decode register is a bitmask field, 414 * so we can decode that into both a base and 415 * a span. 416 */ 417 base = MC_BASE(mc_decode[i]) << PHYS2UM_SHIFT; 418 size = MC_UK2SPAN(mc_decode[i]); 419 update_mem_bounds(boardid, cpuid, i, base, size); 420 } 421 } 422 } 423 424 /* 425 * This routine is run midway through the boot process. By the time we get 426 * here, we know about all the active CPU boards in the system, and we have 427 * extracted information about each board's memory from the memory 428 * controllers. We have also figured out which ranges of memory will be 429 * assigned to which memnodes, so we walk the slice table to build the table 430 * of memnodes. 431 */ 432 /* ARGSUSED */ 433 void 434 plat_build_mem_nodes(u_longlong_t *list, size_t nelems) 435 { 436 int slice; 437 pfn_t basepfn; 438 pgcnt_t npgs; 439 440 mem_node_pfn_shift = PFN_SLICE_SHIFT; 441 mem_node_physalign = (1ull << PA_SLICE_SHIFT); 442 npgs = 1ull << PFN_SLICE_SHIFT; 443 444 for (slice = 0; slice < CHERRYSTONE_MAX_SLICE; slice++) { 445 if (slice_to_memnode[slice] == -1) 446 continue; 447 basepfn = (uint64_t)slice << PFN_SLICE_SHIFT; 448 mem_node_add_slice(basepfn, basepfn + npgs - 1); 449 } 450 } 451 452 453 454 /* 455 * Cherrystone support for lgroups. 456 * 457 * On Cherrystone, an lgroup platform handle == slot number. 458 * 459 * Mappings between lgroup handles and memnodes are managed 460 * in addition to mappings between memory slices and memnodes 461 * to support cross-board interleaving as well as multiple 462 * slices per board (e.g. >1GB DIMMs). The initial mapping 463 * of memnodes to lgroup handles is determined at boot time. 464 */ 465 466 int 467 plat_pfn_to_mem_node(pfn_t pfn) 468 { 469 return (slice_to_memnode[PFN_2_SLICE(pfn)]); 470 } 471 472 /* 473 * Return the platform handle for the lgroup containing the given CPU 474 * 475 * For Cherrystone, lgroup platform handle == slot/board number 476 */ 477 lgrp_handle_t 478 plat_lgrp_cpu_to_hand(processorid_t id) 479 { 480 return (CHERRYSTONE_GETSLOT(id)); 481 } 482 483 /* 484 * Platform specific lgroup initialization 485 */ 486 void 487 plat_lgrp_init(void) 488 { 489 int i; 490 491 /* 492 * Initialize lookup tables to invalid values so we catch 493 * any illegal use of them. 494 */ 495 for (i = 0; i < CHERRYSTONE_MAX_SLICE; i++) { 496 slice_to_memnode[i] = -1; 497 } 498 } 499 500 /* 501 * Return latency between "from" and "to" lgroups 502 * 503 * This latency number can only be used for relative comparison 504 * between lgroups on the running system, cannot be used across platforms, 505 * and may not reflect the actual latency. It is platform and implementation 506 * specific, so platform gets to decide its value. It would be nice if the 507 * number was at least proportional to make comparisons more meaningful though. 508 * NOTE: The numbers below are supposed to be load latencies for uncached 509 * memory divided by 10. 510 */ 511 int 512 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to) 513 { 514 /* 515 * Return min remote latency when there are more than two lgroups 516 * (root and child) and getting latency between two different lgroups 517 * or root is involved 518 */ 519 if (lgrp_optimizations() && (from != to || 520 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE)) 521 return (21); 522 else 523 return (19); 524 } 525 526 /* 527 * No platform drivers on this platform 528 */ 529 char *platform_module_list[] = { 530 (char *)0 531 }; 532 533 /*ARGSUSED*/ 534 void 535 plat_tod_fault(enum tod_fault_type tod_bad) 536 { 537 } 538 539 /*ARGSUSED*/ 540 int 541 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 542 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 543 { 544 if (flt_in_memory && (p2get_mem_unum != NULL)) 545 return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8), 546 buf, buflen, lenp)); 547 else 548 return (ENOTSUP); 549 } 550 551 /* 552 * This platform hook gets called from mc_add_mem_unum_label() in the mc-us3 553 * driver giving each platform the opportunity to add platform 554 * specific label information to the unum for ECC error logging purposes. 555 */ 556 void 557 plat_add_mem_unum_label(char *unum, int mcid, int bank, int dimm) 558 { 559 _NOTE(ARGUNUSED(bank, dimm)) 560 561 char board = CHERRYSTONE_GETSLOT_LABEL(mcid); 562 char old_unum[UNUM_NAMLEN]; 563 564 strcpy(old_unum, unum); 565 snprintf(unum, UNUM_NAMLEN, "Slot %c: %s", board, old_unum); 566 } 567 568 int 569 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 570 { 571 char board = CHERRYSTONE_GETSLOT_LABEL(cpuid); 572 573 if (snprintf(buf, buflen, "Slot %c", board) >= buflen) { 574 return (ENOSPC); 575 } else { 576 *lenp = strlen(buf); 577 return (0); 578 } 579 } 580 581 /* 582 * Cherrystone's BBC pcf8584 controller is used by both OBP and the OS's i2c 583 * drivers. The 'eeprom' command executes OBP code to handle property requests. 584 * If eeprom didn't do this, or if the controllers were partitioned so that all 585 * devices on a given controller were driven by either OBP or the OS, this 586 * wouldn't be necessary. 587 * 588 * Note that getprop doesn't have the same issue as it reads from cached 589 * memory in OBP. 590 */ 591 592 /* 593 * Common locking enter code 594 */ 595 void 596 plat_setprop_enter(void) 597 { 598 mutex_enter(&cherry_pcf8584_mutex); 599 } 600 601 /* 602 * Common locking exit code 603 */ 604 void 605 plat_setprop_exit(void) 606 { 607 mutex_exit(&cherry_pcf8584_mutex); 608 } 609 610 /* 611 * Called by pcf8584 driver 612 */ 613 void 614 plat_shared_i2c_enter(dev_info_t *i2cnexus_dip) 615 { 616 if (i2cnexus_dip == shared_pcf8584_dip) { 617 plat_setprop_enter(); 618 } 619 } 620 621 /* 622 * Called by pcf8584 driver 623 */ 624 void 625 plat_shared_i2c_exit(dev_info_t *i2cnexus_dip) 626 { 627 if (i2cnexus_dip == shared_pcf8584_dip) { 628 plat_setprop_exit(); 629 } 630 } 631