1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI Express nexus driver tunables 30 */ 31 32 #include <sys/types.h> 33 #include <sys/cmn_err.h> 34 #include <sys/time.h> 35 #include <sys/pcie.h> 36 #include "px_space.h" 37 38 /*LINTLIBRARY*/ 39 40 uint32_t px_spurintr_duration = 60000000; /* One minute */ 41 uint64_t px_spurintr_msgs = PX_SPURINTR_MSG_DEFAULT; 42 43 /* 44 * The following variable enables a workaround for the following obp bug: 45 * 46 * 1234181 - obp should set latency timer registers in pci 47 * configuration header 48 * 49 * Until this bug gets fixed in the obp, the following workaround should 50 * be enabled. 51 */ 52 uint_t px_set_latency_timer_register = 1; 53 54 /* 55 * The following driver parameters are defined as variables to allow 56 * patching for debugging and tuning. Flags that can be set on a per 57 * PBM basis are bit fields where the PBM device instance number maps 58 * to the bit position. 59 */ 60 uint_t px_mmu_error_intr_enable = (uint_t)-1; 61 uint_t px_rerun_disable = 0; 62 63 uint_t px_error_intr_enable = (uint_t)-1; 64 uint_t px_dwsync_disable = 0; 65 uint_t px_intsync_disable = 0; 66 67 uint_t px_intr_retry_intv = 5; /* for interrupt retry reg */ 68 uint8_t px_latency_timer = 0x40; /* for pci latency timer reg */ 69 uint_t px_panic_on_fatal_errors = 1; /* should be 1 at beta */ 70 uint_t px_thermal_intr_fatal = 1; /* thermal interrupts fatal */ 71 uint_t px_buserr_interrupt = 1; /* safari buserr interrupt */ 72 uint_t px_ctx_no_active_flush = 0; /* cannot handle active ctx flush */ 73 uint_t px_use_contexts = 1; 74 75 hrtime_t px_intrpend_timeout = 5ull * NANOSEC; /* 5 seconds in nanoseconds */ 76 77 uint64_t px_perr_fatal = -1ull; 78 uint64_t px_serr_fatal = -1ull; 79 uint64_t px_errtrig_pa = 0x0; 80 81 /* 82 * The following flag controls behavior of the ino handler routine 83 * when multiple interrupts are attached to a single ino. Typically 84 * this case would occur for the ino's assigned to the PCI bus slots 85 * with multi-function devices or bus bridges. 86 * 87 * Setting the flag to zero causes the ino handler routine to return 88 * after finding the first interrupt handler to claim the interrupt. 89 * 90 * Setting the flag to non-zero causes the ino handler routine to 91 * return after making one complete pass through the interrupt 92 * handlers. 93 */ 94 uint_t px_check_all_handlers = 1; 95 96 /* 97 * The following value is the number of consecutive unclaimed interrupts that 98 * will be tolerated for a particular ino_p before the interrupt is deemed to 99 * be jabbering and is blocked. 100 */ 101 uint_t px_unclaimed_intr_max = 20; 102 103 /* 104 * The following value will cause the nexus driver to block an ino after 105 * px_unclaimed_intr_max unclaimed interrupts have been seen. Setting this 106 * value to 0 will cause interrupts to never be blocked, no matter how many 107 * unclaimed interrupts are seen on a particular ino. 108 */ 109 uint_t px_unclaimed_intr_block = 1; 110 111 uint_t px_lock_tlb = 0; 112 113 uint64_t px_dvma_debug_on = 0; 114 uint64_t px_dvma_debug_off = 0; 115 uint32_t px_dvma_debug_rec = 512; 116 117 /* 118 * dvma address space allocation cache variables 119 */ 120 uint_t px_dvma_page_cache_entries = 0x200; /* # of chunks (1 << bits) */ 121 uint_t px_dvma_page_cache_clustsz = 0x8; /* # of pages per chunk */ 122 #ifdef PX_DMA_PROF 123 uint_t px_dvmaft_npages = 0; /* FT fail due npages */ 124 uint_t px_dvmaft_limit = 0; /* FT fail due limits */ 125 uint_t px_dvmaft_free = 0; /* FT free */ 126 uint_t px_dvmaft_success = 0; /* FT success */ 127 uint_t px_dvmaft_exhaust = 0; /* FT vmem fallback */ 128 uint_t px_dvma_vmem_alloc = 0; /* vmem alloc */ 129 uint_t px_dvma_vmem_xalloc = 0; /* vmem xalloc */ 130 uint_t px_dvma_vmem_xfree = 0; /* vmem xfree */ 131 uint_t px_dvma_vmem_free = 0; /* vmem free */ 132 #endif 133 uint_t px_disable_fdvma = 0; 134 uint_t px_mmu_ctx_lock_failure = 0; 135 136 /* 137 * This flag preserves prom MMU settings by copying prom TSB entries 138 * to corresponding kernel TSB entry locations. It should be removed 139 * after the interface properties from obp have become default. 140 */ 141 uint_t px_preserve_mmu_tsb = 1; 142 143 /* 144 * memory callback list id callback list for kmem_alloc failure clients 145 */ 146 uintptr_t px_kmem_clid = 0; 147 148 /* timeout in micro seconds for receiving PME_To_ACK */ 149 uint64_t px_pme_to_ack_timeout = PX_PME_TO_ACK_TIMEOUT; 150 151 /* timeout in micro seconds for receiving link up interrupt */ 152 uint64_t px_lup_poll_to = PX_LUP_POLL_TO; 153 uint64_t px_lup_poll_interval = PX_LUP_POLL_INTERVAL; 154 155 /* PIL at which PME_To_ACK message interrupt is handled */ 156 uint32_t px_pwr_pil = PX_PWR_PIL; 157 158 uint32_t px_max_l1_tries = PX_MAX_L1_TRIES; 159 160 /* Fire PCIe Error that should cause panics */ 161 uint32_t px_fabric_die = 1; 162 163 uint32_t px_fabric_die_rc_ce = 0; 164 uint32_t px_fabric_die_rc_ue = PCIE_AER_UCE_UR | 165 PCIE_AER_UCE_TO | 166 PCIE_AER_UCE_RO | 167 PCIE_AER_UCE_FCP | 168 PCIE_AER_UCE_DLP | 169 PCIE_AER_UCE_ECRC; 170 171 /* Fire PCIe Error that should cause panics even under protected access */ 172 uint32_t px_fabric_die_rc_ce_gos = 0; 173 uint32_t px_fabric_die_rc_ue_gos = PCIE_AER_UCE_RO | 174 PCIE_AER_UCE_FCP | 175 PCIE_AER_UCE_DLP; 176 177 /* Fabric Error that should cause panics */ 178 uint32_t px_fabric_die_ce = 0; 179 uint32_t px_fabric_die_ue = PCIE_AER_UCE_UR | 180 PCIE_AER_UCE_UC | 181 PCIE_AER_UCE_TO | 182 PCIE_AER_UCE_RO | 183 PCIE_AER_UCE_FCP | 184 PCIE_AER_UCE_DLP | 185 PCIE_AER_UCE_TRAINING; 186 187 /* Fabric Error that should cause panics even under protected access */ 188 uint32_t px_fabric_die_ce_gos = 0; 189 uint32_t px_fabric_die_ue_gos = PCIE_AER_UCE_UC | 190 PCIE_AER_UCE_TO | 191 PCIE_AER_UCE_RO | 192 PCIE_AER_UCE_FCP | 193 PCIE_AER_UCE_DLP | 194 PCIE_AER_UCE_TRAINING; 195 196 /* Fabric Bridge Sec. Error that should cause panics */ 197 uint16_t px_fabric_die_bdg_sts = PCI_STAT_S_PERROR | 198 PCI_STAT_R_TARG_AB | 199 PCI_STAT_R_MAST_AB | 200 PCI_STAT_S_SYSERR | 201 PCI_STAT_PERROR; 202 203 /* 204 * Fabric Bridge Sec. Error that should cause panics even under 205 * protected access 206 */ 207 uint16_t px_fabric_die_bdg_sts_gos = PCI_STAT_S_PERROR | 208 PCI_STAT_PERROR; 209 210 /* Fabric Switch Sec. Error that should cause panics */ 211 uint16_t px_fabric_die_sw_sts = PCI_STAT_R_TARG_AB | 212 PCI_STAT_R_MAST_AB | 213 PCI_STAT_S_SYSERR; 214 215 /* 216 * Fabric Switch Sec. Error that should cause panics even under 217 * protected access 218 */ 219 uint16_t px_fabric_die_sw_sts_gos = 0; 220 221 uint32_t px_fabric_die_sue = PCIE_AER_SUCE_TA_ON_SC | 222 PCIE_AER_SUCE_MA_ON_SC | 223 PCIE_AER_SUCE_RCVD_TA | 224 PCIE_AER_SUCE_RCVD_MA | 225 PCIE_AER_SUCE_USC_ERR | 226 PCIE_AER_SUCE_USC_MSG_DATA_ERR | 227 PCIE_AER_SUCE_UC_DATA_ERR | 228 PCIE_AER_SUCE_UC_ATTR_ERR | 229 PCIE_AER_SUCE_UC_ADDR_ERR | 230 PCIE_AER_SUCE_TIMER_EXPIRED | 231 PCIE_AER_SUCE_PERR_ASSERT | 232 PCIE_AER_SUCE_SERR_ASSERT | 233 PCIE_AER_SUCE_INTERNAL_ERR; 234 235 uint32_t px_fabric_die_sue_gos = PCIE_AER_SUCE_TA_ON_SC | 236 PCIE_AER_SUCE_MA_ON_SC | 237 PCIE_AER_SUCE_USC_ERR | 238 PCIE_AER_SUCE_USC_MSG_DATA_ERR | 239 PCIE_AER_SUCE_UC_DATA_ERR | 240 PCIE_AER_SUCE_UC_ATTR_ERR | 241 PCIE_AER_SUCE_UC_ADDR_ERR | 242 PCIE_AER_SUCE_TIMER_EXPIRED | 243 PCIE_AER_SUCE_PERR_ASSERT | 244 PCIE_AER_SUCE_SERR_ASSERT | 245 PCIE_AER_SUCE_INTERNAL_ERR; 246