1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI Express PEC implementation: 31 * initialization 32 * Bus error interrupt handler 33 */ 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/spl.h> 38 #include <sys/sysmacros.h> 39 #include <sys/sunddi.h> 40 #include <sys/machsystm.h> /* ldphysio() */ 41 #include <sys/async.h> 42 #include <sys/ddi_impldefs.h> 43 #include <sys/ontrap.h> 44 #include <sys/membar.h> 45 #include "px_obj.h" 46 47 /*LINTLIBRARY*/ 48 49 extern uint_t px_ranges_phi_mask; 50 51 static uint_t px_pec_error_intr(caddr_t a); 52 static int px_pec_msg_add_intr(px_t *px_p); 53 static void px_pec_msg_rem_intr(px_t *px_p); 54 55 int 56 px_pec_attach(px_t *px_p) 57 { 58 px_pec_t *pec_p; 59 int i, len; 60 int nrange = px_p->px_ranges_length / sizeof (px_ranges_t); 61 dev_info_t *dip = px_p->px_dip; 62 px_ranges_t *rangep = px_p->px_ranges_p; 63 int ret; 64 65 /* 66 * Allocate a state structure for the PEC and cross-link it 67 * to its per px node state structure. 68 */ 69 pec_p = kmem_zalloc(sizeof (px_pec_t), KM_SLEEP); 70 px_p->px_pec_p = pec_p; 71 pec_p->pec_px_p = px_p; 72 73 len = snprintf(pec_p->pec_nameinst_str, 74 sizeof (pec_p->pec_nameinst_str), 75 "%s%d", NAMEINST(dip)); 76 pec_p->pec_nameaddr_str = pec_p->pec_nameinst_str + ++len; 77 (void) snprintf(pec_p->pec_nameaddr_str, 78 sizeof (pec_p->pec_nameinst_str) - len, 79 "%s@%s", NAMEADDR(dip)); 80 81 /* 82 * Add interrupt handlers to process correctable/fatal/non fatal 83 * PCIE messages. 84 */ 85 if ((ret = px_pec_msg_add_intr(px_p)) != DDI_SUCCESS) { 86 px_pec_msg_rem_intr(px_p); 87 return (ret); 88 } 89 90 /* 91 * Get this pec's mem32 and mem64 segments to determine whether 92 * a dma object originates from ths pec. i.e. dev to dev dma 93 */ 94 for (i = 0; i < nrange; i++, rangep++) { 95 uint64_t rng_addr, rng_size, *pfnbp, *pfnlp; 96 uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK; 97 98 switch (rng_type) { 99 case PCI_ADDR_MEM32: 100 pfnbp = &pec_p->pec_base32_pfn; 101 pfnlp = &pec_p->pec_last32_pfn; 102 break; 103 104 case PCI_ADDR_MEM64: 105 pfnbp = &pec_p->pec_base64_pfn; 106 pfnlp = &pec_p->pec_last64_pfn; 107 break; 108 109 case PCI_ADDR_CONFIG: 110 case PCI_ADDR_IO: 111 default: 112 continue; 113 } 114 rng_addr = (uint64_t)(rangep->parent_high & 115 px_ranges_phi_mask) << 32; 116 rng_addr |= (uint64_t)rangep->parent_low; 117 rng_size = (uint64_t)rangep->size_high << 32; 118 rng_size |= (uint64_t)rangep->size_low; 119 120 *pfnbp = mmu_btop(rng_addr); 121 *pfnlp = mmu_btop(rng_addr + rng_size); 122 } 123 124 /* 125 * Register a function to disable pec error interrupts during a panic. 126 * do in px_attach. bus_func_register(BF_TYPE_ERRDIS, 127 * (busfunc_t)pec_disable_pci_errors, pec_p); 128 */ 129 130 mutex_init(&pec_p->pec_pokefault_mutex, NULL, MUTEX_DRIVER, 131 (void *)px_p->px_fm_ibc); 132 133 return (DDI_SUCCESS); 134 } 135 136 uint_t 137 pec_disable_px_errors(px_pec_t *pec_p) 138 { 139 px_t *px_p = pec_p->pec_px_p; 140 px_ib_t *ib_p = px_p->px_ib_p; 141 142 /* 143 * Disable error interrupts via the interrupt mapping register. 144 */ 145 px_ib_intr_disable(ib_p, px_p->px_inos[PX_INTR_PEC], IB_INTR_NOWAIT); 146 return (BF_NONE); 147 } 148 149 void 150 px_pec_detach(px_t *px_p) 151 { 152 dev_info_t *dip = px_p->px_dip; 153 px_pec_t *pec_p = px_p->px_pec_p; 154 px_ib_t *ib_p = px_p->px_ib_p; 155 devino_t ino = px_p->px_inos[PX_INTR_PEC]; 156 157 /* 158 * Free the pokefault mutex. 159 */ 160 DBG(DBG_DETACH, dip, "px_pec_detach:\n"); 161 mutex_destroy(&pec_p->pec_pokefault_mutex); 162 163 /* 164 * Remove the pci error interrupt handler. 165 */ 166 px_ib_intr_disable(ib_p, ino, IB_INTR_WAIT); 167 ddi_remove_intr(dip, 0, NULL); 168 169 /* 170 * Remove the error disable function. 171 */ 172 bus_func_unregister(BF_TYPE_ERRDIS, 173 (busfunc_t)pec_disable_px_errors, pec_p); 174 175 /* 176 * Remove interrupt handlers to process correctable/fatal/non fatal 177 * PCIE messages. 178 */ 179 px_pec_msg_rem_intr(px_p); 180 181 /* 182 * Free the pec state structure. 183 */ 184 kmem_free(pec_p, sizeof (px_pec_t)); 185 px_p->px_pec_p = NULL; 186 } 187 188 /* 189 * pec_msg_add_intr: 190 * 191 * Add interrupt handlers to process correctable/fatal/non fatal 192 * PCIE messages. 193 */ 194 static int 195 px_pec_msg_add_intr(px_t *px_p) 196 { 197 dev_info_t *dip = px_p->px_dip; 198 px_pec_t *pec_p = px_p->px_pec_p; 199 ddi_intr_handle_impl_t hdl; 200 int ret = DDI_SUCCESS; 201 202 DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_add_intr\n"); 203 204 /* Initilize handle */ 205 hdl.ih_cb_func = (ddi_intr_handler_t *)px_err_fabric_intr; 206 hdl.ih_cb_arg1 = NULL; 207 hdl.ih_cb_arg2 = NULL; 208 hdl.ih_ver = DDI_INTR_VERSION; 209 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 210 hdl.ih_dip = dip; 211 hdl.ih_inum = 0; 212 213 /* Add correctable error message handler */ 214 hdl.ih_pri = PX_ERR_LOW_PIL; 215 216 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 217 MSG_REC, (msgcode_t)PCIE_CORR_MSG, 218 &pec_p->pec_corr_msg_msiq_id)) != DDI_SUCCESS) { 219 DBG(DBG_MSG, px_p->px_dip, 220 "PCIE_CORR_MSG registration failed\n"); 221 return (DDI_FAILURE); 222 } 223 224 px_lib_msg_setmsiq(dip, PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 225 px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_VALID); 226 227 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, 228 hdl.ih_inum, px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id), 229 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_CORR_MSG)) != DDI_SUCCESS) { 230 DBG(DBG_MSG, px_p->px_dip, 231 "PCIE_CORR_MSG update interrupt state failed\n"); 232 return (DDI_FAILURE); 233 } 234 235 /* Add non-fatal error message handler */ 236 hdl.ih_pri = PX_ERR_PIL; 237 238 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 239 MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, 240 &pec_p->pec_non_fatal_msg_msiq_id)) != DDI_SUCCESS) { 241 DBG(DBG_MSG, px_p->px_dip, 242 "PCIE_NONFATAL_MSG registration failed\n"); 243 return (DDI_FAILURE); 244 } 245 246 px_lib_msg_setmsiq(dip, PCIE_NONFATAL_MSG, 247 pec_p->pec_non_fatal_msg_msiq_id); 248 px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, PCIE_MSG_VALID); 249 250 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, 251 hdl.ih_inum, px_msiqid_to_devino(px_p, 252 pec_p->pec_non_fatal_msg_msiq_id), PX_INTR_STATE_ENABLE, MSG_REC, 253 PCIE_NONFATAL_MSG)) != DDI_SUCCESS) { 254 DBG(DBG_MSG, px_p->px_dip, 255 "PCIE_NONFATAL_MSG update interrupt state failed\n"); 256 return (DDI_FAILURE); 257 } 258 259 /* Add fatal error message handler */ 260 hdl.ih_pri = PX_ERR_PIL; 261 262 if ((ret = px_add_msiq_intr(dip, dip, &hdl, 263 MSG_REC, (msgcode_t)PCIE_FATAL_MSG, 264 &pec_p->pec_fatal_msg_msiq_id)) != DDI_SUCCESS) { 265 DBG(DBG_MSG, px_p->px_dip, 266 "PCIE_FATAL_MSG registration failed\n"); 267 return (DDI_FAILURE); 268 } 269 270 px_lib_msg_setmsiq(dip, PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 271 px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_VALID); 272 273 if ((ret = px_ib_update_intr_state(px_p, px_p->px_dip, 274 hdl.ih_inum, px_msiqid_to_devino(px_p, 275 pec_p->pec_fatal_msg_msiq_id), PX_INTR_STATE_ENABLE, MSG_REC, 276 PCIE_FATAL_MSG)) != DDI_SUCCESS) { 277 DBG(DBG_MSG, px_p->px_dip, 278 "PCIE_FATAL_MSG update interrupt state failed\n"); 279 return (DDI_FAILURE); 280 } 281 282 return (ret); 283 } 284 285 /* 286 * px_pec_msg_rem_intr: 287 * 288 * Remove interrupt handlers to process correctable/fatal/non fatal 289 * PCIE messages. For now, all these PCIe messages are mapped to 290 * same MSIQ. 291 */ 292 static void 293 px_pec_msg_rem_intr(px_t *px_p) 294 { 295 dev_info_t *dip = px_p->px_dip; 296 px_pec_t *pec_p = px_p->px_pec_p; 297 ddi_intr_handle_impl_t hdl; 298 299 DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_rem_intr: dip 0x%p\n", dip); 300 301 /* Initilize handle */ 302 hdl.ih_ver = DDI_INTR_VERSION; 303 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 304 hdl.ih_dip = dip; 305 hdl.ih_inum = 0; 306 307 if (pec_p->pec_corr_msg_msiq_id >= 0) { 308 px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_INVALID); 309 310 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 311 PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 312 313 (void) px_ib_update_intr_state(px_p, px_p->px_dip, 314 hdl.ih_inum, px_msiqid_to_devino(px_p, 315 pec_p->pec_corr_msg_msiq_id), 316 PX_INTR_STATE_DISABLE, MSG_REC, PCIE_CORR_MSG); 317 318 pec_p->pec_corr_msg_msiq_id = -1; 319 } 320 321 if (pec_p->pec_non_fatal_msg_msiq_id >= 0) { 322 px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, 323 PCIE_MSG_INVALID); 324 325 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 326 PCIE_NONFATAL_MSG, pec_p->pec_non_fatal_msg_msiq_id); 327 328 (void) px_ib_update_intr_state(px_p, px_p->px_dip, 329 hdl.ih_inum, px_msiqid_to_devino(px_p, 330 pec_p->pec_non_fatal_msg_msiq_id), 331 PX_INTR_STATE_DISABLE, MSG_REC, PCIE_NONFATAL_MSG); 332 333 pec_p->pec_non_fatal_msg_msiq_id = -1; 334 } 335 336 if (pec_p->pec_fatal_msg_msiq_id >= 0) { 337 px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_INVALID); 338 339 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 340 PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 341 342 (void) px_ib_update_intr_state(px_p, px_p->px_dip, 343 hdl.ih_inum, px_msiqid_to_devino(px_p, 344 pec_p->pec_fatal_msg_msiq_id), 345 PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG); 346 347 pec_p->pec_fatal_msg_msiq_id = -1; 348 } 349 } 350