1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_IOAPI_H 27 #define _SYS_PX_IOAPI_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #ifndef _ASM 36 37 /* 38 * SUN4V IO Data Definitions 39 * 40 * cpuid - A unique opaque value which represents a target cpu. 41 * 42 * devhandle - Device handle. The device handle uniquely 43 * identifies a SUN4V device. It consists of the 44 * the lower 28-bits of the hi-cell of the first 45 * entry of the SUN4V device's "reg" property as defined 46 * by the SUN4V Bus Binding to Open Firmware. 47 * 48 * devino - Device Interrupt Number. An unsigned integer representing 49 * an interrupt within a specific device. 50 * 51 * sysino - System Interrupt Number. A 64-bit unsigned integer 52 * representing a unique interrupt within a "system". 53 * 54 * intr_state - A flag representing the interrupt state for a 55 * a given sysino. The state values are defined as: 56 * 57 * INTR_IDLE 0 58 * INTR_RECEIVED 1 59 * INTR_DELIVERED 2 60 * 61 * intr_valid_state - A flag representing the 'valid' state for 62 * a given sysino. The state values are defined as: 63 * 64 * INTR_NOTVALID 0 sysino not enabled 65 * INTR_VALID 1 sysino enabled 66 */ 67 68 typedef uint64_t devhandle_t; 69 70 typedef uint32_t cpuid_t; 71 typedef uint32_t devino_t; 72 typedef uint64_t sysino_t; 73 74 typedef enum intr_state { 75 INTR_IDLE_STATE = (uint32_t)0, 76 INTR_RECEIVED_STATE = (uint32_t)1, 77 INTR_DELIVERED_STATE = (uint32_t)2 78 } intr_state_t; 79 80 typedef enum intr_valid_state { 81 INTR_NOTVALID = (uint32_t)0, 82 INTR_VALID = (uint32_t)1 83 } intr_valid_state_t; 84 85 /* 86 * PCI IO Data Definitions 87 * 88 * tsbnum - TSB Number. Identifies which io-tsb is used. 89 * For this version of the spec, tsbnum must be zero. 90 * 91 * tsbindex - TSB Index. Identifies which entry in the tsb is 92 * is used. The first entry is zero. 93 * 94 * tsbid - A 64-bit aligned data structure which contains 95 * a tsbnum and a tsbindex. 96 * bits 63:32 contain the tsbnum. 97 * bits 31:00 contain the tsbindex. 98 * 99 * io_attributes - IO Attributes for iommu mappings. 100 * Attributes for iommu mappings. One or more of the 101 * following attribute bits stored in a 64-bit unsigned int. 102 * 103 * PCI_MAP_ATTR_READ 0x01 - xfr direction is from memory 104 * PCI_MAP_ATTR_WRITE 0x02 - xfr direction is to memory 105 * PCI_MAP_ATTR_RO 0x04 - enable relaxed ordering 106 * 107 * Bits 63:3 are unused and must be set to zero for this 108 * version of the specification. 109 * 110 * Note: For compatibility with future versions of this 111 * specification, the caller must set 63:3 to zero. 112 * The implementation shall ignore bits 63:3 113 * 114 * r_addr - 64-bit Real Address. 115 * 116 * io_addr - 64-bit IO Address. 117 * 118 * pci_device - PCI device address. A PCI device address 119 * identifies a specific device on a specific PCI 120 * bus segment. A PCI device address is a 32-bit unsigned 121 * integer with the following format: 122 * 123 * 00000000.bbbbbbbb.dddddfff.00000000 124 * 125 * Where: 126 * 127 * bbbbbbbb is the 8-bit pci bus number 128 * ddddd is the 5-bit pci device number 129 * fff is the 3-bit pci function number 130 * 131 * 00000000 is the 8-bit literal zero. 132 * 133 * pci_config_offset - PCI Configuration Space offset. 134 * 135 * For conventional PCI, an unsigned integer in the range 136 * 0 .. 255 representing the offset of the field in pci config 137 * space. 138 * 139 * For PCI implementations with extended configuration space, 140 * an unsigned integer in the range 0 .. 4095, representing 141 * the offset of the field in configuration space. Conventional 142 * PCI config space is offset 0 .. 255. Extended config space 143 * is offset 256 .. 4095 144 * 145 * Note: For pci config space accesses, the offset must be 'size' 146 * aligned. 147 * 148 * error_flag - Error flag 149 * 150 * A return value specifies if the action succeeded 151 * or failed, where: 152 * 153 * 0 - No error occurred while performing the service. 154 * non-zero - Error occurred while performing the service. 155 * 156 * io_sync_direction - "direction" definition for pci_dma_sync 157 * 158 * A value specifying the direction for a memory/io sync 159 * operation, The direction value is a flag, one or both 160 * directions may be specified by the caller. 161 * 162 * 0x01 - For device (device read from memory) 163 * 0x02 - For cpu (device write to memory) 164 * 165 * io_page_list - A list of io_page_addresses. An io_page_address 166 * is an r_addr. 167 * 168 * io_page_list_p - A pointer to an io_page_list. 169 */ 170 typedef uint32_t tsbnum_t; 171 typedef uint32_t tsbindex_t; 172 typedef uint64_t tsbid_t; 173 typedef uint64_t r_addr_t; 174 typedef uint64_t io_addr_t; 175 typedef uint64_t io_page_list_t; 176 typedef uint32_t pages_t; 177 typedef uint32_t error_flag_t; 178 179 typedef uint32_t pci_config_offset_t; 180 typedef uint64_t pci_device_t; 181 182 #define PCI_TSB_INDEX 0 183 #define PCI_TSB_INDEX_MASK 0xFFFFFFFF 184 #define PCI_TSB_NUM 32 185 #define PCI_TSB_NUM_MASK 0xFFFFFFFF 186 187 #define PCI_TSBID(tsbnum, tsbindex) \ 188 ((((tsbid_t)tsbnum & PCI_TSB_NUM_MASK) << PCI_TSB_NUM) | \ 189 (((tsbid_t)tsbindex & PCI_TSB_INDEX_MASK) << PCI_TSB_INDEX)) 190 191 #define PCI_TSBID_TO_TSBNUM(tsbid) \ 192 ((tsbid >> PCI_TSB_NUM) & PCI_TSB_NUM_MASK) 193 194 #define PCI_TSBID_TO_TSBINDEX(tsbid) \ 195 ((tsbid >> PCI_TSB_INDEX) & PCI_TSB_INDEX_MASK) 196 197 typedef enum io_attributes { 198 PCI_MAP_ATTR_READ = (uint32_t)0x01, 199 PCI_MAP_ATTR_WRITE = (uint32_t)0x02, 200 PCI_MAP_ATTR_RO = (uint32_t)0x04 201 } io_attributes_t; 202 203 typedef enum io_sync_direction { 204 IO_SYNC_DEVICE = (uint32_t)0x01, 205 IO_SYNC_CPU = (uint32_t)0x02 206 } io_sync_direction_t; 207 208 typedef enum pci_config_size { 209 PCI_CFG_SIZE_BYTE = 0, 210 PCI_CFG_SIZE_WORD, 211 PCI_CFG_SIZE_DWORD 212 } pci_config_size_t; 213 214 typedef union pci_cfg_data { 215 uint8_t b; 216 uint16_t w; 217 uint32_t dw; 218 uint64_t qw; 219 } pci_cfg_data_t; 220 221 /* 222 * MSI Definitions 223 * 224 * MSI - Message Signaled Interrupt 225 * 226 * Message Signaled Interrupt as defined in the PCI Local Bus 227 * Specification and the PCI Express Base Specification. 228 * A device signals an interrupt via MSI using a posted 229 * write cycle to an address specified by system software 230 * using a data value specified by system software. 231 * The MSI capability data structure contains fields for 232 * the PCI address and data values the device uses when 233 * sending an MSI message on the bus. MSI-X is an extended 234 * form of MSI, but uses the same mechanism for signaling 235 * the interrupt as MSI. For the purposes of this document, 236 * the term "MSI" refers to MSI or MSI-X. 237 * 238 * Root complexes that support MSI define an address range 239 * and set of data values that can be used to signal MSIs. 240 * 241 * SUN4V/pci requirements for MSI: 242 * 243 * The root complex defines two address ranges. One in 244 * the 32-bit pci memory space and one in the 64-bit 245 * pci memory address space used as the target of a posted 246 * write to signal an MSI. 247 * 248 * The root complex treats any write to these address 249 * ranges as signaling an MSI, however, only the data 250 * value used in the posted write signals the MSI. 251 * 252 * 253 * MSI EQ - MSI Event Queue 254 * 255 * The MSI Event Queue is a page-aligned main memory data 256 * structure used to store MSI data records. 257 * 258 * Each root port supports several MSI EQs, and each EQ has a 259 * system interrupt associated with it, and can be targeted 260 * (individually) to any cpu. The number of MSI EQs supported 261 * by a root complex is described by a property defined in [3]. 262 * Each MSI EQ must be large enough to contain all possible MSI 263 * data records generated by any one PCI root port. The number 264 * of entries in each MSI EQ is described by a property defined 265 * in [3]. 266 * 267 * Each MSI EQ is compliant with the definition of interrupt 268 * queues described in [5], however, instead of accessing the 269 * queue head/tail registers via ASI-based registers, an API 270 * is provided to access the head/tail registers. 271 * 272 * The SUN4V/pci compliant root complex has the ability to 273 * generate a system interrupt when the MSI EQ is non-empty. 274 * 275 * MSI/Message/INTx Data Record format 276 * 277 * Each data record consists of 64 bytes of data, aligned 278 * on a 64-byte boundary. 279 * 280 * The data record is defined as follows: 281 * 282 * 283 * 6666555555555544444444443333333333222222222211111111110000000000 284 * 3210987654321098765432109876543210987654321098765432109876543210 285 * 286 * 0x00: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVxxxxxxxxxxxxxxxxxxxxxxxxTTTTTTTT 287 * 0x08: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 288 * 0x10: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 289 * 0x18: SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 290 * 0x20: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxRRRRRRRRRRRRRRRR 291 * 0x28: AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 292 * 0x30: DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 293 * 0x38: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 294 * 295 * Where, 296 * 297 * xx..xx are unused bits and must be ignored by sw. 298 * 299 * VV..VV is the version number of this data record 300 * 301 * For this release of the spec, the version number 302 * field must be zero. 303 * 304 * TTTTTTTT is the data record type: 305 * 306 * Upper 4 bits are reserved, and must be zero 307 * 308 * 0000 - Not an MSI data record - reserved for sw use. 309 * 0001 - MSG 310 * 0010 - MSI32 311 * 0011 - MSI64 312 * 0010 - Reserved 313 * ... 314 * 0111 - Reserved 315 * 1000 - INTx 316 * 1001 - Reserved 317 * ... 318 * 1110 - Reserved 319 * 1111 - Not an MSI data record - reserved for sw use. 320 * 321 * All other encodings are reserved. 322 * 323 * II..II is the sysino for INTx (sw defined value), 324 * otherwise zero. 325 * 326 * SS..SS is the message timestamp if available. 327 * If supported by the implementation, a non-zero 328 * value in this field is a copy of the %stick register 329 * at the time the message is created. 330 * 331 * If unsupported, this field will contain zero. 332 * 333 * RR..RR is the requester ID of the device that initiated the MSI/MSG 334 * and has the following format: 335 * 336 * bbbbbbbb.dddddfff 337 * 338 * Where bb..bb is the bus number, 339 * dd..dd is the device number 340 * and fff is the function number. 341 * 342 * Note that for PCI devices or any message where 343 * the requester is unknown, this may be zero, 344 * or the device-id of an intermediate bridge. 345 * 346 * For intx messages, this field should be ignored. 347 * 348 * AA..AA is the MSI address. For MSI32, the upper 32-bits must be zero. 349 * (for data record type MSG or INTx, this field is ignored) 350 * 351 * DD..DD is the MSI/MSG data or INTx number 352 * 353 * For MSI-X, bits 31..0 contain the data from the MSI packet 354 * which is the msi-number. bits 63..32 shall be zero. 355 * 356 * For MSI, bits 15..0 contain the data from the MSI message 357 * which is the msi-number. bits 63..16 shall be zero 358 * 359 * For MSG data, the message code and message routing code 360 * are encoded as follows: 361 * 362 * 63:32 - 0000.0000.0000.0000.0000.0000.GGGG.GGGG 363 * 32:00 - 0000.0000.0000.0CCC.0000.0000.MMMM.MMMM 364 * 365 * Where, 366 * 367 * GG..GG is the target-id of the message in the 368 * following form: 369 * 370 * bbbbbbbb.dddddfff 371 * 372 * where bb..bb is the target bus number. 373 * ddddd is the target deviceid 374 * fff is the target function number. 375 * 376 * CCC is the message routing code as defined by [4] 377 * 378 * MM..MM is the message code as defined by [4] 379 * 380 * For INTx data, bits 63:2 must be zero and 381 * the low order 2 bits are defined as follows: 382 * 383 * 00 - INTA 384 * 01 - INTB 385 * 10 - INTC 386 * 11 - INTD 387 * 388 * cpuid - A unique opaque value which represents a target cpu. 389 * 390 * devhandle - Device handle. The device handle uniquely identifies a 391 * SUN4V device. It consists of the the lower 28-bits of the hi-cell 392 * of the first entry of the SUN4V device's "reg" property as defined 393 * by the SUN4V Bus Binding to Open Firmware. 394 * 395 * msinum - A value defining which MSI is being used. 396 * 397 * msiqhead - The index value of the current head index for a given 398 * MSI-EQ. 399 * 400 * msiqtail - The index value of the current tail index for a given 401 * MSI-EQ. 402 * 403 * msitype - Type specifier for MSI32 or MSI64 404 * 0 - type is MSI32 405 * 1 - type is MSI64 406 * 407 * msiqid - A number from 0 .. 'number of MSI-EQs - 1', defining 408 * which MSI EQ within the device is being used. 409 * 410 * msiqstate - An unsigned integer containing one of the 411 * following values: 412 * 413 * PCI_MSIQSTATE_IDLE 0 # idle (non-error) state 414 * PCI_MSIQSTATE_ERROR 1 # error state 415 * 416 * msiqvalid - An unsigned integer containing one of the 417 * following values: 418 * 419 * PCI_MSIQ_INVALID 0 # disabled/invalid 420 * PCI_MSIQ_VALID 1 # enabled/valid 421 * 422 * msistate - An unsigned integer containing one of the following 423 * values: 424 * 425 * PCI_MSISTATE_IDLE 0 # idle/not enabled 426 * PCI_MSISTATE_DELIVERED 1 # MSI Delivered 427 * 428 * msivalid - An unsigned integer containing one of the 429 * following values: 430 * 431 * PCI_MSI_INVALID 0 # disabled/invalid 432 * PCI_MSI_VALID 1 # enabled/valid 433 * 434 * msgtype - A value defining which MSG type is being used. An unsigned 435 * integer containing one of the following values: 436 * (as per PCIe spec 1.0a) 437 * 438 * PCIE_PME_MSG 0x18 PME message 439 * PCIE_PME_ACK_MSG 0x1b PME ACK message 440 * PCIE_CORR_MSG 0x30 Correctable message 441 * PCIE_NONFATAL_MSG 0x31 Non fatal message 442 * PCIE_FATAL_MSG 0x33 Fatal message 443 */ 444 445 typedef uint32_t msinum_t; 446 typedef uint32_t msiqid_t; 447 typedef uint32_t msgcode_t; 448 typedef uint64_t msiqhead_t; 449 typedef uint64_t msiqtail_t; 450 451 /* MSIQ state */ 452 typedef enum pci_msiq_state { 453 PCI_MSIQ_STATE_IDLE = (uint32_t)0, /* idle (non-error) state */ 454 PCI_MSIQ_STATE_ERROR = (uint32_t)1 /* error state */ 455 } pci_msiq_state_t; 456 457 /* MSIQ valid */ 458 typedef enum pci_msiq_valid_state { 459 PCI_MSIQ_INVALID = (uint32_t)0, /* disabled/invalid */ 460 PCI_MSIQ_VALID = (uint32_t)1 /* enabled/valid */ 461 } pci_msiq_valid_state_t; 462 463 /* MSIQ Record data structure */ 464 typedef struct msiq_rec { 465 uint64_t msiq_rec_version : 32, /* DW 0 - 63:32 */ 466 msiq_rec_rsvd0 : 24, /* DW 0 - 31:09 */ 467 msiq_rec_type : 8; /* DW 0 - 07:00 */ 468 uint64_t msiq_rec_intx; /* DW 1 */ 469 uint64_t msiq_rec_rsvd1; /* DW 2 */ 470 uint64_t msiq_rec_timestamp; /* DW 3 */ 471 uint64_t msiq_rec_rsvd2 : 48, /* DW 4 - 63:16 */ 472 msiq_rec_rid : 16; /* DW 4 - 15:00 */ 473 uint64_t msiq_rec_msi_addr; /* DW 5 - 63:00 */ 474 union { 475 struct { 476 uint64_t msix_rsvd0 : 32, /* DW 6 - 63:32 */ 477 msix_data : 32; /* DW 6 - 31:00 */ 478 } msix; 479 struct { 480 uint64_t msi_rsvd0 : 48, /* DW 6 - 63:16 */ 481 msi_data: 16; /* DW 6 - 15:00 */ 482 } msi; 483 struct { 484 uint64_t msg_rsvd0: 24, /* DW 6 - 63:40 */ 485 msg_targ: 8, /* DW 6 - 39:32 */ 486 msg_rsvd1: 13, /* DW 6 - 31:19 */ 487 msg_route: 3, /* DW 6 - 18:16 */ 488 msg_rsvd2: 8, /* DW 6 - 15:08 */ 489 msg_code: 8; /* DW 6 - 07:00 */ 490 } msg; 491 } msiq_rec_data; 492 uint64_t msiq_rec_rsvd3; /* DW 7 */ 493 } msiq_rec_t; 494 495 /* MSIQ Record type */ 496 typedef enum msiq_rec_type { 497 MSG_REC = (uint32_t)1, /* PCIe message record */ 498 MSI32_REC = (uint32_t)2, /* MSI32 record */ 499 MSI64_REC = (uint32_t)3, /* MSI64 record */ 500 INTX_REC = (uint32_t)8 /* INTx record */ 501 } msiq_rec_type_t; 502 503 /* MSIQ Record type */ 504 typedef enum msi_type { 505 MSI32_TYPE = (uint32_t)0, /* MSI32 type */ 506 MSI64_TYPE = (uint32_t)1 /* MSI64 type */ 507 } msi_type_t; 508 509 /* MSI state */ 510 typedef enum pci_msi_state { 511 PCI_MSI_STATE_IDLE = (uint32_t)0, /* idle/not enabled */ 512 PCI_MSI_STATE_DELIVERED = (uint32_t)1 /* MSI delivered */ 513 } pci_msi_state_t; 514 515 /* MSI valid */ 516 typedef enum pci_msi_valid_state { 517 PCI_MSI_INVALID = (uint32_t)0, /* disabled/invalid */ 518 PCI_MSI_VALID = (uint32_t)1 /* enabled/valid */ 519 } pci_msi_valid_state_t; 520 521 /* MSG valid */ 522 typedef enum pcie_msg_valid_state { 523 PCIE_MSG_INVALID = (uint32_t)0, /* disabled/invalid */ 524 PCIE_MSG_VALID = (uint32_t)1 /* enabled/valid */ 525 } pcie_msg_valid_state_t; 526 527 /* PCIe MSG types */ 528 typedef enum pcie_msg_type { 529 PCIE_PME_MSG = (uint64_t)0x18, /* PME message */ 530 PCIE_PME_ACK_MSG = (uint64_t)0x1b, /* PME ACK message */ 531 PCIE_CORR_MSG = (uint64_t)0x30, /* Correctable message */ 532 PCIE_NONFATAL_MSG = (uint64_t)0x31, /* Non fatal message */ 533 PCIE_FATAL_MSG = (uint64_t)0x33 /* Fatal message */ 534 } pcie_msg_type_t; 535 536 #endif /* _ASM */ 537 538 #ifdef __cplusplus 539 } 540 #endif 541 542 #endif /* _SYS_PX_IOAPI_H */ 543