1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_IOAPI_H 28 #define _SYS_PX_IOAPI_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #ifndef _ASM 37 38 /* 39 * SUN4V IO Data Definitions 40 * 41 * cpuid - A unique opaque value which represents a target cpu. 42 * 43 * devhandle - Device handle. The device handle uniquely 44 * identifies a SUN4V device. It consists of the 45 * the lower 28-bits of the hi-cell of the first 46 * entry of the SUN4V device's "reg" property as defined 47 * by the SUN4V Bus Binding to Open Firmware. 48 * 49 * devino - Device Interrupt Number. An unsigned integer representing 50 * an interrupt within a specific device. 51 * 52 * sysino - System Interrupt Number. A 64-bit unsigned integer 53 * representing a unique interrupt within a "system". 54 * 55 * intr_state - A flag representing the interrupt state for a 56 * a given sysino. The state values are defined as: 57 * 58 * INTR_IDLE 0 59 * INTR_RECEIVED 1 60 * INTR_DELIVERED 2 61 * 62 * intr_valid_state - A flag representing the 'valid' state for 63 * a given sysino. The state values are defined as: 64 * 65 * INTR_NOTVALID 0 sysino not enabled 66 * INTR_VALID 1 sysino enabled 67 */ 68 69 typedef uint64_t devhandle_t; 70 71 typedef uint32_t cpuid_t; 72 typedef uint32_t devino_t; 73 typedef uint64_t sysino_t; 74 75 typedef enum intr_state { 76 INTR_IDLE_STATE = (uint32_t)0, 77 INTR_RECEIVED_STATE = (uint32_t)1, 78 INTR_DELIVERED_STATE = (uint32_t)2 79 } intr_state_t; 80 81 typedef enum intr_valid_state { 82 INTR_NOTVALID = (uint32_t)0, 83 INTR_VALID = (uint32_t)1 84 } intr_valid_state_t; 85 86 /* 87 * PCI IO Data Definitions 88 * 89 * tsbnum - TSB Number. Identifies which io-tsb is used. 90 * For this version of the spec, tsbnum must be zero. 91 * 92 * tsbindex - TSB Index. Identifies which entry in the tsb is 93 * is used. The first entry is zero. 94 * 95 * tsbid - A 64-bit aligned data structure which contains 96 * a tsbnum and a tsbindex. 97 * bits 63:32 contain the tsbnum. 98 * bits 31:00 contain the tsbindex. 99 * 100 * io_attributes - IO Attributes for iommu mappings. 101 * Attributes for iommu mappings. One or more of the 102 * following attribute bits stored in a 64-bit unsigned int. 103 * 104 * PCI_MAP_ATTR_READ 0x01 - xfr direction is from memory 105 * PCI_MAP_ATTR_WRITE 0x02 - xfr direction is to memory 106 * 107 * Bits 63:2 are unused and must be set to zero for this 108 * version of the specification. 109 * 110 * Note: For compatibility with future versions of this 111 * specification, the caller must set 63:2 to zero. 112 * The implementation shall ignore bits 63:2 113 * 114 * r_addr - 64-bit Real Address. 115 * 116 * io_addr - 64-bit IO Address. 117 * 118 * pci_device - PCI device address. A PCI device address 119 * identifies a specific device on a specific PCI 120 * bus segment. A PCI device address is a 32-bit unsigned 121 * integer with the following format: 122 * 123 * 00000000.bbbbbbbb.dddddfff.00000000 124 * 125 * Where: 126 * 127 * bbbbbbbb is the 8-bit pci bus number 128 * ddddd is the 5-bit pci device number 129 * fff is the 3-bit pci function number 130 * 131 * 00000000 is the 8-bit literal zero. 132 * 133 * pci_config_offset - PCI Configuration Space offset. 134 * 135 * For conventional PCI, an unsigned integer in the range 136 * 0 .. 255 representing the offset of the field in pci config 137 * space. 138 * 139 * For PCI implementations with extended configuration space, 140 * an unsigned integer in the range 0 .. 4095, representing 141 * the offset of the field in configuration space. Conventional 142 * PCI config space is offset 0 .. 255. Extended config space 143 * is offset 256 .. 4095 144 * 145 * Note: For pci config space accesses, the offset must be 'size' 146 * aligned. 147 * 148 * error_flag - Error flag 149 * 150 * A return value specifies if the action succeeded 151 * or failed, where: 152 * 153 * 0 - No error occurred while performing the service. 154 * non-zero - Error occurred while performing the service. 155 * 156 * io_sync_direction - "direction" definition for pci_dma_sync 157 * 158 * A value specifying the direction for a memory/io sync 159 * operation, The direction value is a flag, one or both 160 * directions may be specified by the caller. 161 * 162 * 0x01 - For device (device read from memory) 163 * 0x02 - For cpu (device write to memory) 164 * 165 * io_page_list - A list of io_page_addresses. An io_page_address 166 * is an r_addr. 167 * 168 * io_page_list_p - A pointer to an io_page_list. 169 */ 170 typedef uint32_t tsbnum_t; 171 typedef uint32_t tsbindex_t; 172 typedef uint64_t tsbid_t; 173 typedef uint64_t r_addr_t; 174 typedef uint64_t io_addr_t; 175 typedef uint64_t io_page_list_t; 176 typedef uint32_t pages_t; 177 typedef uint32_t error_flag_t; 178 179 typedef uint32_t pci_config_offset_t; 180 typedef uint64_t pci_device_t; 181 182 #define PCI_TSB_INDEX 0 183 #define PCI_TSB_INDEX_MASK 0xFFFFFFFF 184 #define PCI_TSB_NUM 32 185 #define PCI_TSB_NUM_MASK 0xFFFFFFFF 186 187 #define PCI_TSBID(tsbnum, tsbindex) \ 188 ((((tsbid_t)tsbnum & PCI_TSB_NUM_MASK) << PCI_TSB_NUM) | \ 189 (((tsbid_t)tsbindex & PCI_TSB_INDEX_MASK) << PCI_TSB_INDEX)) 190 191 #define PCI_TSBID_TO_TSBNUM(tsbid) \ 192 ((tsbid >> PCI_TSB_NUM) & PCI_TSB_NUM_MASK) 193 194 #define PCI_TSBID_TO_TSBINDEX(tsbid) \ 195 ((tsbid >> PCI_TSB_INDEX) & PCI_TSB_INDEX_MASK) 196 197 typedef enum io_attributes { 198 PCI_MAP_ATTR_READ = (uint32_t)0x01, 199 PCI_MAP_ATTR_WRITE = (uint32_t)0x02 200 } io_attributes_t; 201 202 typedef enum io_sync_direction { 203 IO_SYNC_DEVICE = (uint32_t)0x01, 204 IO_SYNC_CPU = (uint32_t)0x02 205 } io_sync_direction_t; 206 207 typedef enum pci_config_size { 208 PCI_CFG_SIZE_BYTE = 0, 209 PCI_CFG_SIZE_WORD, 210 PCI_CFG_SIZE_DWORD 211 } pci_config_size_t; 212 213 typedef union pci_cfg_data { 214 uint8_t b; 215 uint16_t w; 216 uint32_t dw; 217 uint64_t qw; 218 } pci_cfg_data_t; 219 220 /* 221 * MSI Definitions 222 * 223 * MSI - Message Signaled Interrupt 224 * 225 * Message Signaled Interrupt as defined in the PCI Local Bus 226 * Specification and the PCI Express Base Specification. 227 * A device signals an interrupt via MSI using a posted 228 * write cycle to an address specified by system software 229 * using a data value specified by system software. 230 * The MSI capability data structure contains fields for 231 * the PCI address and data values the device uses when 232 * sending an MSI message on the bus. MSI-X is an extended 233 * form of MSI, but uses the same mechanism for signaling 234 * the interrupt as MSI. For the purposes of this document, 235 * the term "MSI" refers to MSI or MSI-X. 236 * 237 * Root complexes that support MSI define an address range 238 * and set of data values that can be used to signal MSIs. 239 * 240 * SUN4V/pci requirements for MSI: 241 * 242 * The root complex defines two address ranges. One in 243 * the 32-bit pci memory space and one in the 64-bit 244 * pci memory address space used as the target of a posted 245 * write to signal an MSI. 246 * 247 * The root complex treats any write to these address 248 * ranges as signaling an MSI, however, only the data 249 * value used in the posted write signals the MSI. 250 * 251 * 252 * MSI EQ - MSI Event Queue 253 * 254 * The MSI Event Queue is a page-aligned main memory data 255 * structure used to store MSI data records. 256 * 257 * Each root port supports several MSI EQs, and each EQ has a 258 * system interrupt associated with it, and can be targeted 259 * (individually) to any cpu. The number of MSI EQs supported 260 * by a root complex is described by a property defined in [3]. 261 * Each MSI EQ must be large enough to contain all possible MSI 262 * data records generated by any one PCI root port. The number 263 * of entries in each MSI EQ is described by a property defined 264 * in [3]. 265 * 266 * Each MSI EQ is compliant with the definition of interrupt 267 * queues described in [5], however, instead of accessing the 268 * queue head/tail registers via ASI-based registers, an API 269 * is provided to access the head/tail registers. 270 * 271 * The SUN4V/pci compliant root complex has the ability to 272 * generate a system interrupt when the MSI EQ is non-empty. 273 * 274 * MSI/Message/INTx Data Record format 275 * 276 * Each data record consists of 64 bytes of data, aligned 277 * on a 64-byte boundary. 278 * 279 * The data record is defined as follows: 280 * 281 * 282 * 6666555555555544444444443333333333222222222211111111110000000000 283 * 3210987654321098765432109876543210987654321098765432109876543210 284 * 285 * 0x00: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVxxxxxxxxxxxxxxxxxxxxxxxxTTTTTTTT 286 * 0x08: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 287 * 0x10: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 288 * 0x18: SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 289 * 0x20: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxRRRRRRRRRRRRRRRR 290 * 0x28: AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 291 * 0x30: DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 292 * 0x38: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 293 * 294 * Where, 295 * 296 * xx..xx are unused bits and must be ignored by sw. 297 * 298 * VV..VV is the version number of this data record 299 * 300 * For this release of the spec, the version number 301 * field must be zero. 302 * 303 * TTTTTTTT is the data record type: 304 * 305 * Upper 4 bits are reserved, and must be zero 306 * 307 * 0000 - Not an MSI data record - reserved for sw use. 308 * 0001 - MSG 309 * 0010 - MSI32 310 * 0011 - MSI64 311 * 0010 - Reserved 312 * ... 313 * 0111 - Reserved 314 * 1000 - INTx 315 * 1001 - Reserved 316 * ... 317 * 1110 - Reserved 318 * 1111 - Not an MSI data record - reserved for sw use. 319 * 320 * All other encodings are reserved. 321 * 322 * II..II is the sysino for INTx (sw defined value), 323 * otherwise zero. 324 * 325 * SS..SS is the message timestamp if available. 326 * If supported by the implementation, a non-zero 327 * value in this field is a copy of the %stick register 328 * at the time the message is created. 329 * 330 * If unsupported, this field will contain zero. 331 * 332 * RR..RR is the requester ID of the device that initiated the MSI/MSG 333 * and has the following format: 334 * 335 * bbbbbbbb.dddddfff 336 * 337 * Where bb..bb is the bus number, 338 * dd..dd is the device number 339 * and fff is the function number. 340 * 341 * Note that for PCI devices or any message where 342 * the requester is unknown, this may be zero, 343 * or the device-id of an intermediate bridge. 344 * 345 * For intx messages, this field should be ignored. 346 * 347 * AA..AA is the MSI address. For MSI32, the upper 32-bits must be zero. 348 * (for data record type MSG or INTx, this field is ignored) 349 * 350 * DD..DD is the MSI/MSG data or INTx number 351 * 352 * For MSI-X, bits 31..0 contain the data from the MSI packet 353 * which is the msi-number. bits 63..32 shall be zero. 354 * 355 * For MSI, bits 15..0 contain the data from the MSI message 356 * which is the msi-number. bits 63..16 shall be zero 357 * 358 * For MSG data, the message code and message routing code 359 * are encoded as follows: 360 * 361 * 63:32 - 0000.0000.0000.0000.0000.0000.GGGG.GGGG 362 * 32:00 - 0000.0000.0000.0CCC.0000.0000.MMMM.MMMM 363 * 364 * Where, 365 * 366 * GG..GG is the target-id of the message in the 367 * following form: 368 * 369 * bbbbbbbb.dddddfff 370 * 371 * where bb..bb is the target bus number. 372 * ddddd is the target deviceid 373 * fff is the target function number. 374 * 375 * CCC is the message routing code as defined by [4] 376 * 377 * MM..MM is the message code as defined by [4] 378 * 379 * For INTx data, bits 63:2 must be zero and 380 * the low order 2 bits are defined as follows: 381 * 382 * 00 - INTA 383 * 01 - INTB 384 * 10 - INTC 385 * 11 - INTD 386 * 387 * cpuid - A unique opaque value which represents a target cpu. 388 * 389 * devhandle - Device handle. The device handle uniquely identifies a 390 * SUN4V device. It consists of the the lower 28-bits of the hi-cell 391 * of the first entry of the SUN4V device's "reg" property as defined 392 * by the SUN4V Bus Binding to Open Firmware. 393 * 394 * msinum - A value defining which MSI is being used. 395 * 396 * msiqhead - The index value of the current head index for a given 397 * MSI-EQ. 398 * 399 * msiqtail - The index value of the current tail index for a given 400 * MSI-EQ. 401 * 402 * msitype - Type specifier for MSI32 or MSI64 403 * 0 - type is MSI32 404 * 1 - type is MSI64 405 * 406 * msiqid - A number from 0 .. 'number of MSI-EQs - 1', defining 407 * which MSI EQ within the device is being used. 408 * 409 * msiqstate - An unsigned integer containing one of the 410 * following values: 411 * 412 * PCI_MSIQSTATE_IDLE 0 # idle (non-error) state 413 * PCI_MSIQSTATE_ERROR 1 # error state 414 * 415 * msiqvalid - An unsigned integer containing one of the 416 * following values: 417 * 418 * PCI_MSIQ_INVALID 0 # disabled/invalid 419 * PCI_MSIQ_VALID 1 # enabled/valid 420 * 421 * msistate - An unsigned integer containing one of the following 422 * values: 423 * 424 * PCI_MSISTATE_IDLE 0 # idle/not enabled 425 * PCI_MSISTATE_DELIVERED 1 # MSI Delivered 426 * 427 * msivalid - An unsigned integer containing one of the 428 * following values: 429 * 430 * PCI_MSI_INVALID 0 # disabled/invalid 431 * PCI_MSI_VALID 1 # enabled/valid 432 * 433 * msgtype - A value defining which MSG type is being used. An unsigned 434 * integer containing one of the following values: 435 * (as per PCIe spec 1.0a) 436 * 437 * PCIE_PME_MSG 0x18 PME message 438 * PCIE_PME_ACK_MSG 0x1b PME ACK message 439 * PCIE_CORR_MSG 0x30 Correctable message 440 * PCIE_NONFATAL_MSG 0x31 Non fatal message 441 * PCIE_FATAL_MSG 0x33 Fatal message 442 */ 443 444 typedef uint32_t msinum_t; 445 typedef uint32_t msiqid_t; 446 typedef uint32_t msgcode_t; 447 typedef uint64_t msiqhead_t; 448 typedef uint64_t msiqtail_t; 449 450 /* MSIQ state */ 451 typedef enum pci_msiq_state { 452 PCI_MSIQ_STATE_IDLE = (uint32_t)0, /* idle (non-error) state */ 453 PCI_MSIQ_STATE_ERROR = (uint32_t)1 /* error state */ 454 } pci_msiq_state_t; 455 456 /* MSIQ valid */ 457 typedef enum pci_msiq_valid_state { 458 PCI_MSIQ_INVALID = (uint32_t)0, /* disabled/invalid */ 459 PCI_MSIQ_VALID = (uint32_t)1 /* enabled/valid */ 460 } pci_msiq_valid_state_t; 461 462 /* MSIQ Record data structure */ 463 typedef struct msiq_rec { 464 uint64_t msiq_rec_version : 32, /* DW 0 - 63:32 */ 465 msiq_rec_rsvd0 : 24, /* DW 0 - 31:09 */ 466 msiq_rec_type : 8; /* DW 0 - 07:00 */ 467 uint64_t msiq_rec_intx; /* DW 1 */ 468 uint64_t msiq_rec_rsvd1; /* DW 2 */ 469 uint64_t msiq_rec_timestamp; /* DW 3 */ 470 uint64_t msiq_rec_rsvd2 : 48, /* DW 4 - 63:16 */ 471 msiq_rec_rid : 16; /* DW 4 - 15:00 */ 472 uint64_t msiq_rec_msi_addr; /* DW 5 - 63:00 */ 473 union { 474 struct { 475 uint64_t msix_rsvd0 : 32, /* DW 6 - 63:32 */ 476 msix_data : 32; /* DW 6 - 31:00 */ 477 } msix; 478 struct { 479 uint64_t msi_rsvd0 : 48, /* DW 6 - 63:16 */ 480 msi_data: 16; /* DW 6 - 15:00 */ 481 } msi; 482 struct { 483 uint64_t msg_rsvd0: 24, /* DW 6 - 63:40 */ 484 msg_targ: 8, /* DW 6 - 39:32 */ 485 msg_rsvd1: 13, /* DW 6 - 31:19 */ 486 msg_route: 3, /* DW 6 - 18:16 */ 487 msg_rsvd2: 8, /* DW 6 - 15:08 */ 488 msg_code: 8; /* DW 6 - 07:00 */ 489 } msg; 490 } msiq_rec_data; 491 uint64_t msiq_rec_rsvd3; /* DW 7 */ 492 } msiq_rec_t; 493 494 /* MSIQ Record type */ 495 typedef enum msiq_rec_type { 496 MSG_REC = (uint32_t)1, /* PCIe message record */ 497 MSI32_REC = (uint32_t)2, /* MSI32 record */ 498 MSI64_REC = (uint32_t)3, /* MSI64 record */ 499 INTX_REC = (uint32_t)8 /* INTx record */ 500 } msiq_rec_type_t; 501 502 /* MSIQ Record type */ 503 typedef enum msi_type { 504 MSI32_TYPE = (uint32_t)0, /* MSI32 type */ 505 MSI64_TYPE = (uint32_t)1 /* MSI64 type */ 506 } msi_type_t; 507 508 /* MSI state */ 509 typedef enum pci_msi_state { 510 PCI_MSI_STATE_IDLE = (uint32_t)0, /* idle/not enabled */ 511 PCI_MSI_STATE_DELIVERED = (uint32_t)1 /* MSI delivered */ 512 } pci_msi_state_t; 513 514 /* MSI valid */ 515 typedef enum pci_msi_valid_state { 516 PCI_MSI_INVALID = (uint32_t)0, /* disabled/invalid */ 517 PCI_MSI_VALID = (uint32_t)1 /* enabled/valid */ 518 } pci_msi_valid_state_t; 519 520 /* MSG valid */ 521 typedef enum pcie_msg_valid_state { 522 PCIE_MSG_INVALID = (uint32_t)0, /* disabled/invalid */ 523 PCIE_MSG_VALID = (uint32_t)1 /* enabled/valid */ 524 } pcie_msg_valid_state_t; 525 526 /* PCIe MSG types */ 527 typedef enum pcie_msg_type { 528 PCIE_PME_MSG = (uint64_t)0x18, /* PME message */ 529 PCIE_PME_ACK_MSG = (uint64_t)0x1b, /* PME ACK message */ 530 PCIE_CORR_MSG = (uint64_t)0x30, /* Correctable message */ 531 PCIE_NONFATAL_MSG = (uint64_t)0x31, /* Non fatal message */ 532 PCIE_FATAL_MSG = (uint64_t)0x33 /* Fatal message */ 533 } pcie_msg_type_t; 534 535 #endif /* _ASM */ 536 537 #ifdef __cplusplus 538 } 539 #endif 540 541 #endif /* _SYS_PX_IOAPI_H */ 542