1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PX nexus interrupt handling: 31 * PX device interrupt handler wrapper 32 * PIL lookup routine 33 * PX device interrupt related initchild code 34 */ 35 36 #include <sys/types.h> 37 #include <sys/kmem.h> 38 #include <sys/async.h> 39 #include <sys/spl.h> 40 #include <sys/sunddi.h> 41 #include <sys/fm/protocol.h> 42 #include <sys/fm/util.h> 43 #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 44 #include <sys/ddi_impldefs.h> 45 #include <sys/sdt.h> 46 #include <sys/atomic.h> 47 #include "px_obj.h" 48 #include <sys/ontrap.h> 49 #include <sys/membar.h> 50 51 /* 52 * interrupt jabber: 53 * 54 * When an interrupt line is jabbering, every time the state machine for the 55 * associated ino is idled, a new mondo will be sent and the ino will go into 56 * the pending state again. The mondo will cause a new call to 57 * px_intr_wrapper() which normally idles the ino's state machine which would 58 * precipitate another trip round the loop. 59 * 60 * The loop can be broken by preventing the ino's state machine from being 61 * idled when an interrupt line is jabbering. See the comment at the 62 * beginning of px_intr_wrapper() explaining how the 'interrupt jabber 63 * protection' code does this. 64 */ 65 66 /*LINTLIBRARY*/ 67 68 /* 69 * If the unclaimed interrupt count has reached the limit set by 70 * pci_unclaimed_intr_max within the time limit, then all interrupts 71 * on this ino is blocked by not idling the interrupt state machine. 72 */ 73 static int 74 px_spurintr(px_ib_ino_info_t *ino_p) 75 { 76 px_ih_t *ih_p = ino_p->ino_ih_start; 77 px_t *px_p = ino_p->ino_ib_p->ib_px_p; 78 char *err_fmt_str; 79 int i; 80 81 if (ino_p->ino_unclaimed > px_unclaimed_intr_max) 82 return (DDI_INTR_CLAIMED); 83 84 if (!ino_p->ino_unclaimed) 85 ino_p->ino_spurintr_begin = ddi_get_lbolt(); 86 87 ino_p->ino_unclaimed++; 88 89 if (ino_p->ino_unclaimed <= px_unclaimed_intr_max) 90 goto clear; 91 92 if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 93 > px_spurintr_duration) { 94 ino_p->ino_unclaimed = 0; 95 goto clear; 96 } 97 err_fmt_str = "%s%d: ino 0x%x blocked"; 98 goto warn; 99 clear: 100 /* Clear the pending state */ 101 if (px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 102 INTR_IDLE_STATE) != DDI_SUCCESS) 103 return (DDI_INTR_UNCLAIMED); 104 105 err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 106 warn: 107 cmn_err(CE_WARN, err_fmt_str, NAMEINST(px_p->px_dip), ino_p->ino_ino); 108 for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) 109 cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 110 ih_p->ih_inum); 111 cmn_err(CE_CONT, "!\n"); 112 return (DDI_INTR_CLAIMED); 113 } 114 115 extern uint64_t intr_get_time(void); 116 117 /* 118 * px_intx_intr (legacy or intx interrupt handler) 119 * 120 * This routine is used as wrapper around interrupt handlers installed by child 121 * device drivers. This routine invokes the driver interrupt handlers and 122 * examines the return codes. 123 * 124 * There is a count of unclaimed interrupts kept on a per-ino basis. If at 125 * least one handler claims the interrupt then the counter is halved and the 126 * interrupt state machine is idled. If no handler claims the interrupt then 127 * the counter is incremented by one and the state machine is idled. 128 * If the count ever reaches the limit value set by pci_unclaimed_intr_max 129 * then the interrupt state machine is not idled thus preventing any further 130 * interrupts on that ino. The state machine will only be idled again if a 131 * handler is subsequently added or removed. 132 * 133 * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 134 * DDI_INTR_UNCLAIMED otherwise. 135 */ 136 uint_t 137 px_intx_intr(caddr_t arg) 138 { 139 px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg; 140 px_t *px_p = ino_p->ino_ib_p->ib_px_p; 141 px_ih_t *ih_p = ino_p->ino_ih_start; 142 uint_t result = 0, r; 143 int i; 144 145 DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 146 "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n", 147 ino_p->ino_ino, ino_p->ino_sysino, ino_p->ino_pil, 148 ino_p->ino_ih_size, ino_p->ino_ih_head); 149 150 for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) { 151 dev_info_t *dip = ih_p->ih_dip; 152 uint_t (*handler)() = ih_p->ih_handler; 153 caddr_t arg1 = ih_p->ih_handler_arg1; 154 caddr_t arg2 = ih_p->ih_handler_arg2; 155 156 if (ih_p->ih_intr_state == PX_INTR_STATE_DISABLE) { 157 DBG(DBG_INTX_INTR, px_p->px_dip, 158 "px_intx_intr: %s%d interrupt %d is disabled\n", 159 ddi_driver_name(dip), ddi_get_instance(dip), 160 ino_p->ino_ino); 161 162 continue; 163 } 164 165 DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 166 "ino=%x handler=%p arg1 =%p arg2 = %p\n", 167 ino_p->ino_ino, handler, arg1, arg2); 168 169 DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 170 void *, handler, caddr_t, arg1, caddr_t, arg2); 171 172 r = (*handler)(arg1, arg2); 173 174 /* 175 * Account for time used by this interrupt. Protect against 176 * conflicting writes to ih_ticks from ib_intr_dist_all() by 177 * using atomic ops. 178 */ 179 180 if (ino_p->ino_pil <= LOCK_LEVEL) 181 atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 182 183 DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 184 void *, handler, caddr_t, arg1, int, r); 185 186 result += r; 187 188 if (px_check_all_handlers) 189 continue; 190 if (result) 191 break; 192 } 193 194 if (!result && px_unclaimed_intr_block) 195 return (px_spurintr(ino_p)); 196 197 ino_p->ino_unclaimed = 0; 198 199 /* Clear the pending state */ 200 if (px_lib_intr_setstate(ino_p->ino_ib_p->ib_px_p->px_dip, 201 ino_p->ino_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) 202 return (DDI_INTR_UNCLAIMED); 203 204 return (DDI_INTR_CLAIMED); 205 } 206 207 /* 208 * px_msiq_intr (MSI/MSIX/MSG interrupt handler) 209 * 210 * This routine is used as wrapper around interrupt handlers installed by child 211 * device drivers. This routine invokes the driver interrupt handlers and 212 * examines the return codes. 213 * 214 * There is a count of unclaimed interrupts kept on a per-ino basis. If at 215 * least one handler claims the interrupt then the counter is halved and the 216 * interrupt state machine is idled. If no handler claims the interrupt then 217 * the counter is incremented by one and the state machine is idled. 218 * If the count ever reaches the limit value set by pci_unclaimed_intr_max 219 * then the interrupt state machine is not idled thus preventing any further 220 * interrupts on that ino. The state machine will only be idled again if a 221 * handler is subsequently added or removed. 222 * 223 * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 224 * DDI_INTR_UNCLAIMED otherwise. 225 */ 226 uint_t 227 px_msiq_intr(caddr_t arg) 228 { 229 px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg; 230 px_t *px_p = ino_p->ino_ib_p->ib_px_p; 231 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 232 px_msiq_t *msiq_p = ino_p->ino_msiq_p; 233 dev_info_t *dip = px_p->px_dip; 234 msiq_rec_t msiq_rec, *msiq_rec_p = &msiq_rec; 235 msiqhead_t curr_msiq_rec_cnt, new_msiq_rec_cnt; 236 msgcode_t msg_code; 237 px_ih_t *ih_p; 238 int ret; 239 240 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x " 241 "ih_size=%x ih_lst=%x\n", msiq_p->msiq_id, ino_p->ino_ino, 242 ino_p->ino_pil, ino_p->ino_ih_size, ino_p->ino_ih_head); 243 244 /* Read current MSIQ head index */ 245 px_lib_msiq_gethead(dip, msiq_p->msiq_id, &curr_msiq_rec_cnt); 246 msiq_p->msiq_curr = (uint64_t)((caddr_t)msiq_p->msiq_base + 247 curr_msiq_rec_cnt * sizeof (msiq_rec_t)); 248 new_msiq_rec_cnt = curr_msiq_rec_cnt; 249 250 /* Read next MSIQ record */ 251 px_lib_get_msiq_rec(dip, msiq_p, msiq_rec_p); 252 253 /* 254 * Process current MSIQ record as long as request id 255 * field is non-zero. 256 */ 257 while (msiq_rec_p->msiq_rec_rid) { 258 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSIQ RECORD, " 259 "msiq_rec_type 0x%llx msiq_rec_rid 0x%llx\n", 260 msiq_rec_p->msiq_rec_type, msiq_rec_p->msiq_rec_rid); 261 262 /* Get the pointer next EQ record */ 263 msiq_p->msiq_curr = (uint64_t) 264 ((caddr_t)msiq_p->msiq_curr + sizeof (msiq_rec_t)); 265 266 /* Check for overflow condition */ 267 if (msiq_p->msiq_curr >= (uint64_t)((caddr_t)msiq_p->msiq_base + 268 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t))) 269 msiq_p->msiq_curr = msiq_p->msiq_base; 270 271 /* Check MSIQ record type */ 272 switch (msiq_rec_p->msiq_rec_type) { 273 case MSG_REC: 274 msg_code = msiq_rec_p->msiq_rec_data.msg.msg_code; 275 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: PCIE MSG " 276 "record, msg type 0x%x\n", msg_code); 277 break; 278 case MSI32_REC: 279 case MSI64_REC: 280 msg_code = msiq_rec_p->msiq_rec_data.msi.msi_data; 281 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSI record, " 282 "msi 0x%x\n", msg_code); 283 284 /* Clear MSI state */ 285 px_lib_msi_setstate(dip, (msinum_t)msg_code, 286 PCI_MSI_STATE_IDLE); 287 break; 288 default: 289 msg_code = 0; 290 cmn_err(CE_WARN, "%s%d: px_msiq_intr: 0x%x MSIQ " 291 "record type is not supported", 292 ddi_driver_name(dip), ddi_get_instance(dip), 293 msiq_rec_p->msiq_rec_type); 294 goto next_rec; 295 } 296 297 ih_p = ino_p->ino_ih_start; 298 299 /* 300 * Scan through px_ih_t linked list, searching for the 301 * right px_ih_t, matching MSIQ record data. 302 */ 303 while ((ih_p) && (ih_p->ih_msg_code != msg_code) && 304 (ih_p->ih_rec_type != msiq_rec_p->msiq_rec_type)) 305 ih_p = ih_p->ih_next; 306 307 if ((ih_p->ih_msg_code == msg_code) && 308 (ih_p->ih_rec_type == msiq_rec_p->msiq_rec_type)) { 309 dev_info_t *dip = ih_p->ih_dip; 310 uint_t (*handler)() = ih_p->ih_handler; 311 caddr_t arg1 = ih_p->ih_handler_arg1; 312 caddr_t arg2 = ih_p->ih_handler_arg2; 313 314 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: ino=%x data=%x " 315 "handler=%p arg1 =%p arg2=%p\n", ino_p->ino_ino, 316 msg_code, handler, arg1, arg2); 317 318 DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 319 void *, handler, caddr_t, arg1, caddr_t, arg2); 320 321 /* 322 * Special case for PCIE Error Messages. 323 * The current frame work doesn't fit PCIE Err Msgs 324 * This should be fixed when PCIE MESSAGES as a whole 325 * is architected correctly. 326 */ 327 if ((msg_code == PCIE_MSG_CODE_ERR_COR) || 328 (msg_code == PCIE_MSG_CODE_ERR_NONFATAL) || 329 (msg_code == PCIE_MSG_CODE_ERR_FATAL)) { 330 ret = px_err_fabric_intr(px_p, msg_code, 331 msiq_rec_p->msiq_rec_rid); 332 } else 333 ret = (*handler)(arg1, arg2); 334 335 /* 336 * Account for time used by this interrupt. Protect 337 * against conflicting writes to ih_ticks from 338 * ib_intr_dist_all() by using atomic ops. 339 */ 340 341 if (ino_p->ino_pil <= LOCK_LEVEL) 342 atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 343 344 DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 345 void *, handler, caddr_t, arg1, int, ret); 346 } else { 347 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr:" 348 "Not found matching MSIQ record\n"); 349 350 /* px_spurintr(ino_p); */ 351 ino_p->ino_unclaimed++; 352 } 353 354 next_rec: 355 new_msiq_rec_cnt++; 356 357 /* Zero out msiq_rec_rid field */ 358 msiq_rec_p->msiq_rec_rid = 0; 359 360 /* Read next MSIQ record */ 361 px_lib_get_msiq_rec(dip, msiq_p, msiq_rec_p); 362 } 363 364 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: No of MSIQ recs processed %x\n", 365 (new_msiq_rec_cnt - curr_msiq_rec_cnt)); 366 367 /* Update MSIQ head index with no of MSIQ records processed */ 368 if (new_msiq_rec_cnt > curr_msiq_rec_cnt) { 369 if (new_msiq_rec_cnt >= msiq_state_p->msiq_rec_cnt) 370 new_msiq_rec_cnt -= msiq_state_p->msiq_rec_cnt; 371 372 px_lib_msiq_sethead(dip, msiq_p->msiq_id, new_msiq_rec_cnt); 373 } 374 375 /* Clear the pending state */ 376 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 377 INTR_IDLE_STATE) != DDI_SUCCESS) 378 return (DDI_INTR_UNCLAIMED); 379 380 return (DDI_INTR_CLAIMED); 381 } 382 383 dev_info_t * 384 px_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 385 { 386 dev_info_t *cdip = rdip; 387 388 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 389 ; 390 391 return (cdip); 392 } 393 394 /* Default class to pil value mapping */ 395 px_class_val_t px_default_pil [] = { 396 {0x000000, 0xff0000, 0x1}, /* Class code for pre-2.0 devices */ 397 {0x010000, 0xff0000, 0x4}, /* Mass Storage Controller */ 398 {0x020000, 0xff0000, 0x6}, /* Network Controller */ 399 {0x030000, 0xff0000, 0x9}, /* Display Controller */ 400 {0x040000, 0xff0000, 0x9}, /* Multimedia Controller */ 401 {0x050000, 0xff0000, 0xb}, /* Memory Controller */ 402 {0x060000, 0xff0000, 0xb}, /* Bridge Controller */ 403 {0x0c0000, 0xffff00, 0x9}, /* Serial Bus, FireWire (IEEE 1394) */ 404 {0x0c0100, 0xffff00, 0x4}, /* Serial Bus, ACCESS.bus */ 405 {0x0c0200, 0xffff00, 0x4}, /* Serial Bus, SSA */ 406 {0x0c0300, 0xffff00, 0x9}, /* Serial Bus Universal Serial Bus */ 407 {0x0c0400, 0xffff00, 0x6}, /* Serial Bus, Fibre Channel */ 408 {0x0c0600, 0xffff00, 0x6} /* Serial Bus, Infiniband */ 409 }; 410 411 /* 412 * Default class to intr_weight value mapping (% of CPU). A driver.conf 413 * entry on or above the pci node like 414 * 415 * pci-class-intr-weights= 0x020000, 0xff0000, 30; 416 * 417 * can be used to augment or override entries in the default table below. 418 * 419 * NB: The values below give NICs preference on redistribution, and provide 420 * NICs some isolation from other interrupt sources. We need better interfaces 421 * that allow the NIC driver to identify a specific NIC instance as high 422 * bandwidth, and thus deserving of separation from other low bandwidth 423 * NICs additional isolation from other interrupt sources. 424 * 425 * NB: We treat Infiniband like a NIC. 426 */ 427 px_class_val_t px_default_intr_weight [] = { 428 {0x020000, 0xff0000, 35}, /* Network Controller */ 429 {0x010000, 0xff0000, 10}, /* Mass Storage Controller */ 430 {0x0c0400, 0xffff00, 10}, /* Serial Bus, Fibre Channel */ 431 {0x0c0600, 0xffff00, 50} /* Serial Bus, Infiniband */ 432 }; 433 434 static uint32_t 435 px_match_class_val(uint32_t key, px_class_val_t *rec_p, int nrec, 436 uint32_t default_val) 437 { 438 int i; 439 440 for (i = 0; i < nrec; rec_p++, i++) { 441 if ((rec_p->class_code & rec_p->class_mask) == 442 (key & rec_p->class_mask)) 443 return (rec_p->class_val); 444 } 445 446 return (default_val); 447 } 448 449 /* 450 * px_class_to_val 451 * 452 * Return the configuration value, based on class code and sub class code, 453 * from the specified property based or default px_class_val_t table. 454 */ 455 uint32_t 456 px_class_to_val(dev_info_t *rdip, char *property_name, px_class_val_t *rec_p, 457 int nrec, uint32_t default_val) 458 { 459 int property_len; 460 uint32_t class_code; 461 px_class_val_t *conf; 462 uint32_t val = default_val; 463 464 /* 465 * Use the "class-code" property to get the base and sub class 466 * codes for the requesting device. 467 */ 468 class_code = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, rdip, 469 DDI_PROP_DONTPASS, "class-code", -1); 470 471 if (class_code == -1) 472 return (val); 473 474 /* look up the val from the default table */ 475 val = px_match_class_val(class_code, rec_p, nrec, val); 476 477 /* see if there is a more specific property specified value */ 478 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_NOTPROM, 479 property_name, (caddr_t)&conf, &property_len)) 480 return (val); 481 482 if ((property_len % sizeof (px_class_val_t)) == 0) 483 val = px_match_class_val(class_code, conf, 484 property_len / sizeof (px_class_val_t), val); 485 kmem_free(conf, property_len); 486 return (val); 487 } 488 489 /* px_class_to_pil: return the pil for a given device. */ 490 uint32_t 491 px_class_to_pil(dev_info_t *rdip) 492 { 493 uint32_t pil; 494 495 /* default pil is 0 (uninitialized) */ 496 pil = px_class_to_val(rdip, 497 "pci-class-priorities", px_default_pil, 498 sizeof (px_default_pil) / sizeof (px_class_val_t), 0); 499 500 /* range check the result */ 501 if (pil >= 0xf) 502 pil = 0; 503 504 return (pil); 505 } 506 507 /* px_class_to_intr_weight: return the intr_weight for a given device. */ 508 static int32_t 509 px_class_to_intr_weight(dev_info_t *rdip) 510 { 511 int32_t intr_weight; 512 513 /* default weight is 0% */ 514 intr_weight = px_class_to_val(rdip, 515 "pci-class-intr-weights", px_default_intr_weight, 516 sizeof (px_default_intr_weight) / sizeof (px_class_val_t), 0); 517 518 /* range check the result */ 519 if (intr_weight < 0) 520 intr_weight = 0; 521 if (intr_weight > 1000) 522 intr_weight = 1000; 523 524 return (intr_weight); 525 } 526 527 /* ARGSUSED */ 528 int 529 px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 530 ddi_intr_handle_impl_t *hdlp, void *result) 531 { 532 px_t *px_p = DIP_TO_STATE(dip); 533 ddi_ispec_t *ip = (ddi_ispec_t *)hdlp->ih_private; 534 int ret = DDI_SUCCESS; 535 536 DBG(DBG_INTROPS, dip, "px_intx_ops: dip=%x rdip=%x intr_op=%x " 537 "handle=%p\n", dip, rdip, intr_op, hdlp); 538 539 switch (intr_op) { 540 case DDI_INTROP_GETCAP: 541 ret = pci_intx_get_cap(rdip, (int *)result); 542 break; 543 case DDI_INTROP_SETCAP: 544 DBG(DBG_INTROPS, dip, "px_intx_ops: SetCap is not supported\n"); 545 ret = DDI_ENOTSUP; 546 break; 547 case DDI_INTROP_ALLOC: 548 *(int *)result = hdlp->ih_scratch1; 549 break; 550 case DDI_INTROP_FREE: 551 break; 552 case DDI_INTROP_GETPRI: 553 *(int *)result = ip->is_pil ? 554 ip->is_pil : px_class_to_pil(rdip); 555 break; 556 case DDI_INTROP_SETPRI: 557 ip->is_pil = (*(int *)result); 558 break; 559 case DDI_INTROP_ADDISR: 560 hdlp->ih_vector = *ip->is_intr; 561 562 ret = px_add_intx_intr(dip, rdip, hdlp); 563 break; 564 case DDI_INTROP_REMISR: 565 hdlp->ih_vector = *ip->is_intr; 566 567 ret = px_rem_intx_intr(dip, rdip, hdlp); 568 break; 569 case DDI_INTROP_ENABLE: 570 ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 571 *ip->is_intr, PX_INTR_STATE_ENABLE); 572 break; 573 case DDI_INTROP_DISABLE: 574 ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 575 *ip->is_intr, PX_INTR_STATE_DISABLE); 576 break; 577 case DDI_INTROP_SETMASK: 578 ret = pci_intx_set_mask(rdip); 579 break; 580 case DDI_INTROP_CLRMASK: 581 ret = pci_intx_clr_mask(rdip); 582 break; 583 case DDI_INTROP_GETPENDING: 584 ret = pci_intx_get_pending(rdip, (int *)result); 585 break; 586 case DDI_INTROP_NINTRS: 587 case DDI_INTROP_NAVAIL: 588 *(int *)result = i_ddi_get_nintrs(rdip); 589 break; 590 case DDI_INTROP_SUPPORTED_TYPES: 591 *(int *)result = DDI_INTR_TYPE_FIXED; 592 break; 593 default: 594 ret = DDI_ENOTSUP; 595 break; 596 } 597 598 return (ret); 599 } 600 601 /* ARGSUSED */ 602 int 603 px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 604 ddi_intr_handle_impl_t *hdlp, void *result) 605 { 606 px_t *px_p = DIP_TO_STATE(dip); 607 px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 608 msinum_t msi_num; 609 msiqid_t msiq_id; 610 uint_t nintrs; 611 int i, ret = DDI_SUCCESS; 612 613 DBG(DBG_INTROPS, dip, "px_msix_ops: dip=%x rdip=%x intr_op=%x " 614 "handle=%p\n", dip, rdip, intr_op, hdlp); 615 616 switch (intr_op) { 617 case DDI_INTROP_GETCAP: 618 ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result); 619 break; 620 case DDI_INTROP_SETCAP: 621 DBG(DBG_INTROPS, dip, "px_msix_ops: SetCap is not supported\n"); 622 ret = DDI_ENOTSUP; 623 break; 624 case DDI_INTROP_ALLOC: 625 /* 626 * We need to restrict this allocation in future 627 * based on Resource Management policies. 628 */ 629 if ((ret = px_msi_alloc(px_p, rdip, hdlp->ih_inum, 630 hdlp->ih_scratch1, hdlp->ih_scratch2, &msi_num, 631 (int *)result)) != DDI_SUCCESS) { 632 DBG(DBG_INTROPS, dip, "px_msix_ops: MSI allocation " 633 "failed, rdip 0x%p inum 0x%x count 0x%x\n", 634 rdip, hdlp->ih_inum, hdlp->ih_scratch1); 635 636 return (ret); 637 } 638 639 break; 640 case DDI_INTROP_FREE: 641 (void) pci_msi_disable_mode(rdip, hdlp->ih_type, hdlp->ih_inum); 642 (void) pci_msi_unconfigure(rdip, hdlp->ih_type, hdlp->ih_inum); 643 (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 644 hdlp->ih_scratch1); 645 break; 646 case DDI_INTROP_GETPRI: 647 *(int *)result = hdlp->ih_pri ? 648 hdlp->ih_pri : px_class_to_pil(rdip); 649 break; 650 case DDI_INTROP_SETPRI: 651 break; 652 case DDI_INTROP_ADDISR: 653 if ((ret = px_msi_get_msinum(px_p, hdlp->ih_dip, 654 hdlp->ih_inum, &msi_num)) != DDI_SUCCESS) 655 return (ret); 656 657 if ((ret = px_add_msiq_intr(dip, rdip, hdlp, 658 MSI32_REC, msi_num, &msiq_id)) != DDI_SUCCESS) { 659 DBG(DBG_INTROPS, dip, "px_msix_ops: Add MSI handler " 660 "failed, rdip 0x%p msi 0x%x\n", rdip, msi_num); 661 return (ret); 662 } 663 664 DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id); 665 666 if ((ret = px_lib_msi_setmsiq(dip, msi_num, 667 msiq_id, MSI32_TYPE)) != DDI_SUCCESS) { 668 (void) px_rem_msiq_intr(dip, rdip, 669 hdlp, MSI32_REC, msi_num, msiq_id); 670 return (ret); 671 } 672 673 if ((ret = px_lib_msi_setstate(dip, msi_num, 674 PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) { 675 (void) px_rem_msiq_intr(dip, rdip, 676 hdlp, MSI32_REC, msi_num, msiq_id); 677 return (ret); 678 } 679 680 hdlp->ih_vector = msi_num; 681 break; 682 case DDI_INTROP_DUPVEC: 683 DBG(DBG_INTROPS, dip, "px_msix_ops: DupIsr is not supported\n"); 684 ret = DDI_ENOTSUP; 685 break; 686 case DDI_INTROP_REMISR: 687 msi_num = hdlp->ih_vector; 688 689 if ((ret = px_lib_msi_getmsiq(dip, msi_num, 690 &msiq_id)) != DDI_SUCCESS) 691 return (ret); 692 693 if ((ret = px_lib_msi_setstate(dip, msi_num, 694 PCI_MSI_STATE_DELIVERED)) != DDI_SUCCESS) 695 return (ret); 696 697 ret = px_rem_msiq_intr(dip, rdip, 698 hdlp, MSI32_REC, msi_num, msiq_id); 699 700 hdlp->ih_vector = 0; 701 break; 702 case DDI_INTROP_ENABLE: 703 msi_num = hdlp->ih_vector; 704 705 if ((ret = px_lib_msi_setvalid(dip, msi_num, 706 PCI_MSI_VALID)) != DDI_SUCCESS) 707 return (ret); 708 709 if (pci_is_msi_enabled(rdip, hdlp->ih_type) != DDI_SUCCESS) { 710 nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 711 712 if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 713 nintrs, hdlp->ih_inum, msi_state_p->msi_addr32, 714 msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 715 return (ret); 716 717 if ((ret = pci_msi_enable_mode(rdip, hdlp->ih_type, 718 hdlp->ih_inum)) != DDI_SUCCESS) 719 return (ret); 720 } 721 722 ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 723 724 break; 725 case DDI_INTROP_DISABLE: 726 msi_num = hdlp->ih_vector; 727 728 if ((ret = pci_msi_set_mask(rdip, hdlp->ih_type, 729 hdlp->ih_inum)) != DDI_SUCCESS) 730 return (ret); 731 732 ret = px_lib_msi_setvalid(dip, msi_num, PCI_MSI_INVALID); 733 break; 734 case DDI_INTROP_BLOCKENABLE: 735 nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 736 msi_num = hdlp->ih_vector; 737 738 if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 739 nintrs, hdlp->ih_inum, msi_state_p->msi_addr32, 740 msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 741 return (ret); 742 743 for (i = 0; i < nintrs; i++, msi_num++) { 744 if ((ret = px_lib_msi_setvalid(dip, msi_num, 745 PCI_MSI_VALID)) != DDI_SUCCESS) 746 return (ret); 747 } 748 749 ret = pci_msi_enable_mode(rdip, hdlp->ih_type, hdlp->ih_inum); 750 break; 751 case DDI_INTROP_BLOCKDISABLE: 752 nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 753 msi_num = hdlp->ih_vector; 754 755 if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type, 756 hdlp->ih_inum)) != DDI_SUCCESS) 757 return (ret); 758 759 for (i = 0; i < nintrs; i++, msi_num++) { 760 if ((ret = px_lib_msi_setvalid(dip, msi_num, 761 PCI_MSI_INVALID)) != DDI_SUCCESS) 762 return (ret); 763 } 764 765 break; 766 case DDI_INTROP_SETMASK: 767 ret = pci_msi_set_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 768 break; 769 case DDI_INTROP_CLRMASK: 770 ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 771 break; 772 case DDI_INTROP_GETPENDING: 773 ret = pci_msi_get_pending(rdip, hdlp->ih_type, 774 hdlp->ih_inum, (int *)result); 775 break; 776 case DDI_INTROP_NINTRS: 777 ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 778 break; 779 case DDI_INTROP_NAVAIL: 780 /* XXX - a new interface may be needed */ 781 ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 782 break; 783 case DDI_INTROP_SUPPORTED_TYPES: 784 ret = pci_msi_get_supported_type(rdip, (int *)result); 785 break; 786 default: 787 ret = DDI_ENOTSUP; 788 break; 789 } 790 791 return (ret); 792 } 793 794 int 795 px_add_intx_intr(dev_info_t *dip, dev_info_t *rdip, 796 ddi_intr_handle_impl_t *hdlp) 797 { 798 px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 799 px_ib_t *ib_p = px_p->px_ib_p; 800 devino_t ino; 801 px_ih_t *ih_p; 802 px_ib_ino_info_t *ino_p; 803 int32_t weight; 804 int ret = DDI_SUCCESS; 805 806 ino = hdlp->ih_vector; 807 808 DBG(DBG_A_INTX, dip, "px_add_intx_intr: rdip=%s%d ino=%x " 809 "handler=%x arg1=%x arg2=%x\n", ddi_driver_name(rdip), 810 ddi_get_instance(rdip), ino, hdlp->ih_cb_func, 811 hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 812 813 ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, 814 hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, 0, 0); 815 816 mutex_enter(&ib_p->ib_ino_lst_mutex); 817 818 if (ino_p = px_ib_locate_ino(ib_p, ino)) { /* sharing ino */ 819 uint32_t intr_index = hdlp->ih_inum; 820 if (px_ib_ino_locate_intr(ino_p, rdip, intr_index, 0, 0)) { 821 DBG(DBG_A_INTX, dip, "px_add_intx_intr: " 822 "dup intr #%d\n", intr_index); 823 824 ret = DDI_FAILURE; 825 goto fail1; 826 } 827 828 /* Save mondo value in hdlp */ 829 hdlp->ih_vector = ino_p->ino_sysino; 830 831 if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p)) 832 != DDI_SUCCESS) 833 goto fail1; 834 } else { 835 ino_p = px_ib_new_ino(ib_p, ino, ih_p); 836 837 if (hdlp->ih_pri == 0) 838 hdlp->ih_pri = px_class_to_pil(rdip); 839 840 /* Save mondo value in hdlp */ 841 hdlp->ih_vector = ino_p->ino_sysino; 842 843 DBG(DBG_A_INTX, dip, "px_add_intx_intr: pil=0x%x mondo=0x%x\n", 844 hdlp->ih_pri, hdlp->ih_vector); 845 846 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 847 (ddi_intr_handler_t *)px_intx_intr, (caddr_t)ino_p, NULL); 848 849 ret = i_ddi_add_ivintr(hdlp); 850 851 /* 852 * Restore original interrupt handler 853 * and arguments in interrupt handle. 854 */ 855 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 856 ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 857 858 if (ret != DDI_SUCCESS) 859 goto fail2; 860 861 /* Save the pil for this ino */ 862 ino_p->ino_pil = hdlp->ih_pri; 863 864 /* select cpu, saving it for sharing and removal */ 865 ino_p->ino_cpuid = intr_dist_cpuid(); 866 867 /* Enable interrupt */ 868 px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino); 869 } 870 871 /* add weight to the cpu that we are already targeting */ 872 weight = px_class_to_intr_weight(rdip); 873 intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 874 875 ih_p->ih_ino_p = ino_p; 876 if (ih_p->ih_ksp) 877 kstat_install(ih_p->ih_ksp); 878 mutex_exit(&ib_p->ib_ino_lst_mutex); 879 880 DBG(DBG_A_INTX, dip, "px_add_intx_intr: done! Interrupt 0x%x pil=%x\n", 881 ino_p->ino_sysino, hdlp->ih_pri); 882 883 return (ret); 884 fail2: 885 px_ib_delete_ino(ib_p, ino_p); 886 fail1: 887 if (ih_p->ih_config_handle) 888 pci_config_teardown(&ih_p->ih_config_handle); 889 890 mutex_exit(&ib_p->ib_ino_lst_mutex); 891 kmem_free(ih_p, sizeof (px_ih_t)); 892 893 DBG(DBG_A_INTX, dip, "px_add_intx_intr: Failed! Interrupt 0x%x " 894 "pil=%x\n", ino_p->ino_sysino, hdlp->ih_pri); 895 896 return (ret); 897 } 898 899 int 900 px_rem_intx_intr(dev_info_t *dip, dev_info_t *rdip, 901 ddi_intr_handle_impl_t *hdlp) 902 { 903 px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 904 px_ib_t *ib_p = px_p->px_ib_p; 905 devino_t ino; 906 cpuid_t curr_cpu; 907 px_ib_ino_info_t *ino_p; 908 px_ih_t *ih_p; 909 int ret = DDI_SUCCESS; 910 911 ino = hdlp->ih_vector; 912 913 DBG(DBG_R_INTX, dip, "px_rem_intx_intr: rdip=%s%d ino=%x\n", 914 ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 915 916 mutex_enter(&ib_p->ib_ino_lst_mutex); 917 918 ino_p = px_ib_locate_ino(ib_p, ino); 919 ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 0, 0); 920 921 /* Get the current cpu */ 922 if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 923 &curr_cpu)) != DDI_SUCCESS) 924 goto fail; 925 926 if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS) 927 goto fail; 928 929 intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 930 931 if (ino_p->ino_ih_size == 0) { 932 if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 933 INTR_DELIVERED_STATE)) != DDI_SUCCESS) 934 goto fail; 935 936 hdlp->ih_vector = ino_p->ino_sysino; 937 i_ddi_rem_ivintr(hdlp); 938 939 px_ib_delete_ino(ib_p, ino_p); 940 kmem_free(ino_p, sizeof (px_ib_ino_info_t)); 941 } else { 942 /* Re-enable interrupt only if mapping regsiter still shared */ 943 if ((ret = px_lib_intr_settarget(px_p->px_dip, 944 ino_p->ino_sysino, curr_cpu)) != DDI_SUCCESS) 945 goto fail; 946 947 ret = px_lib_intr_setvalid(px_p->px_dip, ino_p->ino_sysino, 948 INTR_VALID); 949 } 950 951 fail: 952 mutex_exit(&ib_p->ib_ino_lst_mutex); 953 return (ret); 954 } 955 956 int 957 px_add_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 958 ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 959 msgcode_t msg_code, msiqid_t *msiq_id_p) 960 { 961 px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 962 px_ib_t *ib_p = px_p->px_ib_p; 963 px_msiq_state_t *msiq_state_p = &ib_p->ib_msiq_state; 964 devino_t ino; 965 px_ih_t *ih_p; 966 px_ib_ino_info_t *ino_p; 967 int32_t weight; 968 int ret = DDI_SUCCESS; 969 970 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=%x " 971 "arg1=%x arg2=%x\n", ddi_driver_name(rdip), ddi_get_instance(rdip), 972 hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 973 974 if ((ret = px_msiq_alloc(px_p, rec_type, msiq_id_p)) != DDI_SUCCESS) { 975 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 976 "msiq allocation failed\n"); 977 return (ret); 978 } 979 980 ino = px_msiqid_to_devino(px_p, *msiq_id_p); 981 982 ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, hdlp->ih_cb_func, 983 hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, rec_type, msg_code); 984 985 mutex_enter(&ib_p->ib_ino_lst_mutex); 986 987 if (ino_p = px_ib_locate_ino(ib_p, ino)) { /* sharing ino */ 988 uint32_t intr_index = hdlp->ih_inum; 989 if (px_ib_ino_locate_intr(ino_p, rdip, 990 intr_index, rec_type, msg_code)) { 991 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 992 "dup intr #%d\n", intr_index); 993 994 ret = DDI_FAILURE; 995 goto fail1; 996 } 997 998 if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p)) 999 != DDI_SUCCESS) 1000 goto fail1; 1001 } else { 1002 ino_p = px_ib_new_ino(ib_p, ino, ih_p); 1003 1004 ino_p->ino_msiq_p = msiq_state_p->msiq_p + 1005 (*msiq_id_p - msiq_state_p->msiq_1st_msiq_id); 1006 1007 if (hdlp->ih_pri == 0) 1008 hdlp->ih_pri = px_class_to_pil(rdip); 1009 1010 /* Save mondo value in hdlp */ 1011 hdlp->ih_vector = ino_p->ino_sysino; 1012 1013 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n", 1014 hdlp->ih_pri, hdlp->ih_vector); 1015 1016 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 1017 (ddi_intr_handler_t *)px_msiq_intr, (caddr_t)ino_p, NULL); 1018 1019 ret = i_ddi_add_ivintr(hdlp); 1020 1021 /* 1022 * Restore original interrupt handler 1023 * and arguments in interrupt handle. 1024 */ 1025 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 1026 ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 1027 1028 if (ret != DDI_SUCCESS) 1029 goto fail2; 1030 1031 /* Save the pil for this ino */ 1032 ino_p->ino_pil = hdlp->ih_pri; 1033 1034 /* Enable MSIQ */ 1035 px_lib_msiq_setstate(dip, *msiq_id_p, PCI_MSIQ_STATE_IDLE); 1036 px_lib_msiq_setvalid(dip, *msiq_id_p, PCI_MSIQ_VALID); 1037 1038 /* select cpu, saving it for sharing and removal */ 1039 ino_p->ino_cpuid = intr_dist_cpuid(); 1040 1041 /* Enable interrupt */ 1042 px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino_p->ino_ino); 1043 } 1044 1045 /* add weight to the cpu that we are already targeting */ 1046 weight = px_class_to_intr_weight(rdip); 1047 intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 1048 1049 ih_p->ih_ino_p = ino_p; 1050 if (ih_p->ih_ksp) 1051 kstat_install(ih_p->ih_ksp); 1052 mutex_exit(&ib_p->ib_ino_lst_mutex); 1053 1054 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n", 1055 ino_p->ino_sysino, hdlp->ih_pri); 1056 1057 return (ret); 1058 fail2: 1059 px_ib_delete_ino(ib_p, ino_p); 1060 fail1: 1061 if (ih_p->ih_config_handle) 1062 pci_config_teardown(&ih_p->ih_config_handle); 1063 1064 mutex_exit(&ib_p->ib_ino_lst_mutex); 1065 kmem_free(ih_p, sizeof (px_ih_t)); 1066 1067 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n", 1068 ino_p->ino_sysino, hdlp->ih_pri); 1069 1070 return (ret); 1071 } 1072 1073 int 1074 px_rem_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 1075 ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 1076 msgcode_t msg_code, msiqid_t msiq_id) 1077 { 1078 px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 1079 px_ib_t *ib_p = px_p->px_ib_p; 1080 devino_t ino = px_msiqid_to_devino(px_p, msiq_id); 1081 cpuid_t curr_cpu; 1082 px_ib_ino_info_t *ino_p; 1083 px_ih_t *ih_p; 1084 int ret = DDI_SUCCESS; 1085 1086 DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n", 1087 ddi_driver_name(rdip), ddi_get_instance(rdip), msiq_id, ino); 1088 1089 mutex_enter(&ib_p->ib_ino_lst_mutex); 1090 1091 ino_p = px_ib_locate_ino(ib_p, ino); 1092 ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 1093 rec_type, msg_code); 1094 1095 /* Get the current cpu */ 1096 if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 1097 &curr_cpu)) != DDI_SUCCESS) 1098 goto fail; 1099 1100 if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS) 1101 goto fail; 1102 1103 intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 1104 1105 if (ino_p->ino_ih_size == 0) { 1106 if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 1107 INTR_DELIVERED_STATE)) != DDI_SUCCESS) 1108 goto fail; 1109 1110 px_lib_msiq_setvalid(dip, px_devino_to_msiqid(px_p, ino), 1111 PCI_MSIQ_INVALID); 1112 1113 hdlp->ih_vector = ino_p->ino_sysino; 1114 i_ddi_rem_ivintr(hdlp); 1115 1116 px_ib_delete_ino(ib_p, ino_p); 1117 1118 (void) px_msiq_free(px_p, msiq_id); 1119 kmem_free(ino_p, sizeof (px_ib_ino_info_t)); 1120 } else { 1121 /* Re-enable interrupt only if mapping regsiter still shared */ 1122 if ((ret = px_lib_intr_settarget(px_p->px_dip, 1123 ino_p->ino_sysino, curr_cpu)) != DDI_SUCCESS) 1124 goto fail; 1125 1126 ret = px_lib_intr_setvalid(px_p->px_dip, ino_p->ino_sysino, 1127 INTR_VALID); 1128 } 1129 1130 fail: 1131 mutex_exit(&ib_p->ib_ino_lst_mutex); 1132 return (ret); 1133 } 1134