1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PX nexus interrupt handling: 30 * PX device interrupt handler wrapper 31 * PIL lookup routine 32 * PX device interrupt related initchild code 33 */ 34 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/async.h> 38 #include <sys/spl.h> 39 #include <sys/sunddi.h> 40 #include <sys/fm/protocol.h> 41 #include <sys/fm/util.h> 42 #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 43 #include <sys/ddi_impldefs.h> 44 #include <sys/sdt.h> 45 #include <sys/atomic.h> 46 #include "px_obj.h" 47 #include <sys/ontrap.h> 48 #include <sys/membar.h> 49 #include <sys/clock.h> 50 51 /* 52 * interrupt jabber: 53 * 54 * When an interrupt line is jabbering, every time the state machine for the 55 * associated ino is idled, a new mondo will be sent and the ino will go into 56 * the pending state again. The mondo will cause a new call to 57 * px_intr_wrapper() which normally idles the ino's state machine which would 58 * precipitate another trip round the loop. 59 * 60 * The loop can be broken by preventing the ino's state machine from being 61 * idled when an interrupt line is jabbering. See the comment at the 62 * beginning of px_intr_wrapper() explaining how the 'interrupt jabber 63 * protection' code does this. 64 */ 65 66 /*LINTLIBRARY*/ 67 68 /* 69 * If the unclaimed interrupt count has reached the limit set by 70 * pci_unclaimed_intr_max within the time limit, then all interrupts 71 * on this ino is blocked by not idling the interrupt state machine. 72 */ 73 static int 74 px_spurintr(px_ib_ino_info_t *ino_p) 75 { 76 px_ih_t *ih_p = ino_p->ino_ih_start; 77 px_t *px_p = ino_p->ino_ib_p->ib_px_p; 78 char *err_fmt_str; 79 int i; 80 81 if (ino_p->ino_unclaimed > px_unclaimed_intr_max) 82 return (DDI_INTR_CLAIMED); 83 84 if (!ino_p->ino_unclaimed) 85 ino_p->ino_spurintr_begin = ddi_get_lbolt(); 86 87 ino_p->ino_unclaimed++; 88 89 if (ino_p->ino_unclaimed <= px_unclaimed_intr_max) 90 goto clear; 91 92 if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 93 > px_spurintr_duration) { 94 ino_p->ino_unclaimed = 0; 95 goto clear; 96 } 97 err_fmt_str = "%s%d: ino 0x%x blocked"; 98 goto warn; 99 clear: 100 /* Clear the pending state */ 101 if (px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 102 INTR_IDLE_STATE) != DDI_SUCCESS) 103 return (DDI_INTR_UNCLAIMED); 104 105 err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 106 warn: 107 cmn_err(CE_WARN, err_fmt_str, NAMEINST(px_p->px_dip), ino_p->ino_ino); 108 for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) 109 cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 110 ih_p->ih_inum); 111 cmn_err(CE_CONT, "!\n"); 112 return (DDI_INTR_CLAIMED); 113 } 114 115 extern uint64_t intr_get_time(void); 116 117 /* 118 * px_intx_intr (INTx or legacy interrupt handler) 119 * 120 * This routine is used as wrapper around interrupt handlers installed by child 121 * device drivers. This routine invokes the driver interrupt handlers and 122 * examines the return codes. 123 * 124 * There is a count of unclaimed interrupts kept on a per-ino basis. If at 125 * least one handler claims the interrupt then the counter is halved and the 126 * interrupt state machine is idled. If no handler claims the interrupt then 127 * the counter is incremented by one and the state machine is idled. 128 * If the count ever reaches the limit value set by pci_unclaimed_intr_max 129 * then the interrupt state machine is not idled thus preventing any further 130 * interrupts on that ino. The state machine will only be idled again if a 131 * handler is subsequently added or removed. 132 * 133 * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 134 * DDI_INTR_UNCLAIMED otherwise. 135 */ 136 uint_t 137 px_intx_intr(caddr_t arg) 138 { 139 px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg; 140 px_t *px_p = ino_p->ino_ib_p->ib_px_p; 141 px_ih_t *ih_p = ino_p->ino_ih_start; 142 uint_t result = 0, r; 143 int i; 144 145 DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 146 "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n", 147 ino_p->ino_ino, ino_p->ino_sysino, ino_p->ino_pil, 148 ino_p->ino_ih_size, ino_p->ino_ih_head); 149 150 for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) { 151 dev_info_t *dip = ih_p->ih_dip; 152 uint_t (*handler)() = ih_p->ih_handler; 153 caddr_t arg1 = ih_p->ih_handler_arg1; 154 caddr_t arg2 = ih_p->ih_handler_arg2; 155 156 if (ih_p->ih_intr_state == PX_INTR_STATE_DISABLE) { 157 DBG(DBG_INTX_INTR, px_p->px_dip, 158 "px_intx_intr: %s%d interrupt %d is disabled\n", 159 ddi_driver_name(dip), ddi_get_instance(dip), 160 ino_p->ino_ino); 161 162 continue; 163 } 164 165 DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 166 "ino=%x handler=%p arg1 =%p arg2 = %p\n", 167 ino_p->ino_ino, handler, arg1, arg2); 168 169 DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 170 void *, handler, caddr_t, arg1, caddr_t, arg2); 171 172 r = (*handler)(arg1, arg2); 173 174 /* 175 * Account for time used by this interrupt. Protect against 176 * conflicting writes to ih_ticks from ib_intr_dist_all() by 177 * using atomic ops. 178 */ 179 180 if (ino_p->ino_pil <= LOCK_LEVEL) 181 atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 182 183 DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 184 void *, handler, caddr_t, arg1, int, r); 185 186 result += r; 187 188 if (px_check_all_handlers) 189 continue; 190 if (result) 191 break; 192 } 193 194 if (!result && px_unclaimed_intr_block) 195 return (px_spurintr(ino_p)); 196 197 ino_p->ino_unclaimed = 0; 198 199 /* Clear the pending state */ 200 if (px_lib_intr_setstate(ino_p->ino_ib_p->ib_px_p->px_dip, 201 ino_p->ino_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) 202 return (DDI_INTR_UNCLAIMED); 203 204 return (DDI_INTR_CLAIMED); 205 } 206 207 /* 208 * px_msiq_intr (MSI/X or PCIe MSG interrupt handler) 209 * 210 * This routine is used as wrapper around interrupt handlers installed by child 211 * device drivers. This routine invokes the driver interrupt handlers and 212 * examines the return codes. 213 * 214 * There is a count of unclaimed interrupts kept on a per-ino basis. If at 215 * least one handler claims the interrupt then the counter is halved and the 216 * interrupt state machine is idled. If no handler claims the interrupt then 217 * the counter is incremented by one and the state machine is idled. 218 * If the count ever reaches the limit value set by pci_unclaimed_intr_max 219 * then the interrupt state machine is not idled thus preventing any further 220 * interrupts on that ino. The state machine will only be idled again if a 221 * handler is subsequently added or removed. 222 * 223 * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 224 * DDI_INTR_UNCLAIMED otherwise. 225 */ 226 uint_t 227 px_msiq_intr(caddr_t arg) 228 { 229 px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg; 230 px_t *px_p = ino_p->ino_ib_p->ib_px_p; 231 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 232 px_msiq_t *msiq_p = ino_p->ino_msiq_p; 233 dev_info_t *dip = px_p->px_dip; 234 msiq_rec_t msiq_rec, *msiq_rec_p = &msiq_rec; 235 msiqhead_t curr_msiq_rec_cnt, new_msiq_rec_cnt; 236 msgcode_t msg_code; 237 px_ih_t *ih_p; 238 int ret; 239 240 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x " 241 "ih_size=%x ih_lst=%x\n", msiq_p->msiq_id, ino_p->ino_ino, 242 ino_p->ino_pil, ino_p->ino_ih_size, ino_p->ino_ih_head); 243 244 /* Read current MSIQ head index */ 245 px_lib_msiq_gethead(dip, msiq_p->msiq_id, &curr_msiq_rec_cnt); 246 msiq_p->msiq_curr = (uint64_t)((caddr_t)msiq_p->msiq_base + 247 curr_msiq_rec_cnt * sizeof (msiq_rec_t)); 248 new_msiq_rec_cnt = curr_msiq_rec_cnt; 249 250 /* Read next MSIQ record */ 251 px_lib_get_msiq_rec(dip, msiq_p, msiq_rec_p); 252 253 /* 254 * Process current MSIQ record as long as record type 255 * field is non-zero. 256 */ 257 while (msiq_rec_p->msiq_rec_type) { 258 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSIQ RECORD, " 259 "msiq_rec_type 0x%llx msiq_rec_rid 0x%llx\n", 260 msiq_rec_p->msiq_rec_type, msiq_rec_p->msiq_rec_rid); 261 262 /* Get the pointer next EQ record */ 263 msiq_p->msiq_curr = (uint64_t) 264 ((caddr_t)msiq_p->msiq_curr + sizeof (msiq_rec_t)); 265 266 /* Check for overflow condition */ 267 if (msiq_p->msiq_curr >= (uint64_t)((caddr_t)msiq_p->msiq_base + 268 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t))) 269 msiq_p->msiq_curr = msiq_p->msiq_base; 270 271 /* Check MSIQ record type */ 272 switch (msiq_rec_p->msiq_rec_type) { 273 case MSG_REC: 274 msg_code = msiq_rec_p->msiq_rec_data.msg.msg_code; 275 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: PCIE MSG " 276 "record, msg type 0x%x\n", msg_code); 277 break; 278 case MSI32_REC: 279 case MSI64_REC: 280 msg_code = msiq_rec_p->msiq_rec_data.msi.msi_data; 281 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSI record, " 282 "msi 0x%x\n", msg_code); 283 284 /* Clear MSI state */ 285 px_lib_msi_setstate(dip, (msinum_t)msg_code, 286 PCI_MSI_STATE_IDLE); 287 break; 288 default: 289 msg_code = 0; 290 cmn_err(CE_WARN, "%s%d: px_msiq_intr: 0x%x MSIQ " 291 "record type is not supported", 292 ddi_driver_name(dip), ddi_get_instance(dip), 293 msiq_rec_p->msiq_rec_type); 294 goto next_rec; 295 } 296 297 ih_p = ino_p->ino_ih_start; 298 299 /* 300 * Scan through px_ih_t linked list, searching for the 301 * right px_ih_t, matching MSIQ record data. 302 */ 303 while ((ih_p) && (ih_p->ih_msg_code != msg_code) && 304 (ih_p->ih_rec_type != msiq_rec_p->msiq_rec_type)) 305 ih_p = ih_p->ih_next; 306 307 if ((ih_p->ih_msg_code == msg_code) && 308 (ih_p->ih_rec_type == msiq_rec_p->msiq_rec_type)) { 309 dev_info_t *dip = ih_p->ih_dip; 310 uint_t (*handler)() = ih_p->ih_handler; 311 caddr_t arg1 = ih_p->ih_handler_arg1; 312 caddr_t arg2 = ih_p->ih_handler_arg2; 313 314 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: ino=%x data=%x " 315 "handler=%p arg1 =%p arg2=%p\n", ino_p->ino_ino, 316 msg_code, handler, arg1, arg2); 317 318 DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 319 void *, handler, caddr_t, arg1, caddr_t, arg2); 320 321 /* 322 * Special case for PCIE Error Messages. 323 * The current frame work doesn't fit PCIE Err Msgs 324 * This should be fixed when PCIE MESSAGES as a whole 325 * is architected correctly. 326 */ 327 if ((msg_code == PCIE_MSG_CODE_ERR_COR) || 328 (msg_code == PCIE_MSG_CODE_ERR_NONFATAL) || 329 (msg_code == PCIE_MSG_CODE_ERR_FATAL)) { 330 ret = px_err_fabric_intr(px_p, msg_code, 331 msiq_rec_p->msiq_rec_rid); 332 } else 333 ret = (*handler)(arg1, arg2); 334 335 /* 336 * Account for time used by this interrupt. Protect 337 * against conflicting writes to ih_ticks from 338 * ib_intr_dist_all() by using atomic ops. 339 */ 340 341 if (ino_p->ino_pil <= LOCK_LEVEL) 342 atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 343 344 DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 345 void *, handler, caddr_t, arg1, int, ret); 346 } else { 347 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr:" 348 "Not found matching MSIQ record\n"); 349 350 /* px_spurintr(ino_p); */ 351 ino_p->ino_unclaimed++; 352 } 353 354 next_rec: 355 new_msiq_rec_cnt++; 356 357 /* Zero out msiq_rec_type field */ 358 msiq_rec_p->msiq_rec_type = 0; 359 360 /* Read next MSIQ record */ 361 px_lib_get_msiq_rec(dip, msiq_p, msiq_rec_p); 362 } 363 364 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: No of MSIQ recs processed %x\n", 365 (new_msiq_rec_cnt - curr_msiq_rec_cnt)); 366 367 /* Update MSIQ head index with no of MSIQ records processed */ 368 if (new_msiq_rec_cnt > curr_msiq_rec_cnt) { 369 if (new_msiq_rec_cnt >= msiq_state_p->msiq_rec_cnt) 370 new_msiq_rec_cnt -= msiq_state_p->msiq_rec_cnt; 371 372 px_lib_msiq_sethead(dip, msiq_p->msiq_id, new_msiq_rec_cnt); 373 } 374 375 /* Clear the pending state */ 376 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 377 INTR_IDLE_STATE) != DDI_SUCCESS) 378 return (DDI_INTR_UNCLAIMED); 379 380 return (DDI_INTR_CLAIMED); 381 } 382 383 dev_info_t * 384 px_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 385 { 386 dev_info_t *cdip = rdip; 387 388 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 389 ; 390 391 return (cdip); 392 } 393 394 /* Default class to pil value mapping */ 395 px_class_val_t px_default_pil [] = { 396 {0x000000, 0xff0000, 0x1}, /* Class code for pre-2.0 devices */ 397 {0x010000, 0xff0000, 0x4}, /* Mass Storage Controller */ 398 {0x020000, 0xff0000, 0x6}, /* Network Controller */ 399 {0x030000, 0xff0000, 0x9}, /* Display Controller */ 400 {0x040000, 0xff0000, 0x9}, /* Multimedia Controller */ 401 {0x050000, 0xff0000, 0xb}, /* Memory Controller */ 402 {0x060000, 0xff0000, 0xb}, /* Bridge Controller */ 403 {0x0c0000, 0xffff00, 0x9}, /* Serial Bus, FireWire (IEEE 1394) */ 404 {0x0c0100, 0xffff00, 0x4}, /* Serial Bus, ACCESS.bus */ 405 {0x0c0200, 0xffff00, 0x4}, /* Serial Bus, SSA */ 406 {0x0c0300, 0xffff00, 0x9}, /* Serial Bus Universal Serial Bus */ 407 {0x0c0400, 0xffff00, 0x6}, /* Serial Bus, Fibre Channel */ 408 {0x0c0600, 0xffff00, 0x6} /* Serial Bus, Infiniband */ 409 }; 410 411 /* 412 * Default class to intr_weight value mapping (% of CPU). A driver.conf 413 * entry on or above the pci node like 414 * 415 * pci-class-intr-weights= 0x020000, 0xff0000, 30; 416 * 417 * can be used to augment or override entries in the default table below. 418 * 419 * NB: The values below give NICs preference on redistribution, and provide 420 * NICs some isolation from other interrupt sources. We need better interfaces 421 * that allow the NIC driver to identify a specific NIC instance as high 422 * bandwidth, and thus deserving of separation from other low bandwidth 423 * NICs additional isolation from other interrupt sources. 424 * 425 * NB: We treat Infiniband like a NIC. 426 */ 427 px_class_val_t px_default_intr_weight [] = { 428 {0x020000, 0xff0000, 35}, /* Network Controller */ 429 {0x010000, 0xff0000, 10}, /* Mass Storage Controller */ 430 {0x0c0400, 0xffff00, 10}, /* Serial Bus, Fibre Channel */ 431 {0x0c0600, 0xffff00, 50} /* Serial Bus, Infiniband */ 432 }; 433 434 static uint32_t 435 px_match_class_val(uint32_t key, px_class_val_t *rec_p, int nrec, 436 uint32_t default_val) 437 { 438 int i; 439 440 for (i = 0; i < nrec; rec_p++, i++) { 441 if ((rec_p->class_code & rec_p->class_mask) == 442 (key & rec_p->class_mask)) 443 return (rec_p->class_val); 444 } 445 446 return (default_val); 447 } 448 449 /* 450 * px_class_to_val 451 * 452 * Return the configuration value, based on class code and sub class code, 453 * from the specified property based or default px_class_val_t table. 454 */ 455 uint32_t 456 px_class_to_val(dev_info_t *rdip, char *property_name, px_class_val_t *rec_p, 457 int nrec, uint32_t default_val) 458 { 459 int property_len; 460 uint32_t class_code; 461 px_class_val_t *conf; 462 uint32_t val = default_val; 463 464 /* 465 * Use the "class-code" property to get the base and sub class 466 * codes for the requesting device. 467 */ 468 class_code = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, rdip, 469 DDI_PROP_DONTPASS, "class-code", -1); 470 471 if (class_code == -1) 472 return (val); 473 474 /* look up the val from the default table */ 475 val = px_match_class_val(class_code, rec_p, nrec, val); 476 477 /* see if there is a more specific property specified value */ 478 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_NOTPROM, 479 property_name, (caddr_t)&conf, &property_len)) 480 return (val); 481 482 if ((property_len % sizeof (px_class_val_t)) == 0) 483 val = px_match_class_val(class_code, conf, 484 property_len / sizeof (px_class_val_t), val); 485 kmem_free(conf, property_len); 486 return (val); 487 } 488 489 /* px_class_to_pil: return the pil for a given device. */ 490 uint32_t 491 px_class_to_pil(dev_info_t *rdip) 492 { 493 uint32_t pil; 494 495 /* default pil is 0 (uninitialized) */ 496 pil = px_class_to_val(rdip, 497 "pci-class-priorities", px_default_pil, 498 sizeof (px_default_pil) / sizeof (px_class_val_t), 0); 499 500 /* range check the result */ 501 if (pil >= 0xf) 502 pil = 0; 503 504 return (pil); 505 } 506 507 /* px_class_to_intr_weight: return the intr_weight for a given device. */ 508 static int32_t 509 px_class_to_intr_weight(dev_info_t *rdip) 510 { 511 int32_t intr_weight; 512 513 /* default weight is 0% */ 514 intr_weight = px_class_to_val(rdip, 515 "pci-class-intr-weights", px_default_intr_weight, 516 sizeof (px_default_intr_weight) / sizeof (px_class_val_t), 0); 517 518 /* range check the result */ 519 if (intr_weight < 0) 520 intr_weight = 0; 521 if (intr_weight > 1000) 522 intr_weight = 1000; 523 524 return (intr_weight); 525 } 526 527 /* ARGSUSED */ 528 int 529 px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 530 ddi_intr_handle_impl_t *hdlp, void *result) 531 { 532 px_t *px_p = DIP_TO_STATE(dip); 533 int ret = DDI_SUCCESS; 534 535 DBG(DBG_INTROPS, dip, "px_intx_ops: dip=%x rdip=%x intr_op=%x " 536 "handle=%p\n", dip, rdip, intr_op, hdlp); 537 538 switch (intr_op) { 539 case DDI_INTROP_GETCAP: 540 ret = pci_intx_get_cap(rdip, (int *)result); 541 break; 542 case DDI_INTROP_SETCAP: 543 DBG(DBG_INTROPS, dip, "px_intx_ops: SetCap is not supported\n"); 544 ret = DDI_ENOTSUP; 545 break; 546 case DDI_INTROP_ALLOC: 547 *(int *)result = hdlp->ih_scratch1; 548 break; 549 case DDI_INTROP_FREE: 550 break; 551 case DDI_INTROP_GETPRI: 552 *(int *)result = hdlp->ih_pri ? 553 hdlp->ih_pri : px_class_to_pil(rdip); 554 break; 555 case DDI_INTROP_SETPRI: 556 break; 557 case DDI_INTROP_ADDISR: 558 ret = px_add_intx_intr(dip, rdip, hdlp); 559 break; 560 case DDI_INTROP_REMISR: 561 ret = px_rem_intx_intr(dip, rdip, hdlp); 562 break; 563 case DDI_INTROP_ENABLE: 564 ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 565 hdlp->ih_vector, PX_INTR_STATE_ENABLE, 0, 0); 566 break; 567 case DDI_INTROP_DISABLE: 568 ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 569 hdlp->ih_vector, PX_INTR_STATE_DISABLE, 0, 0); 570 break; 571 case DDI_INTROP_SETMASK: 572 ret = pci_intx_set_mask(rdip); 573 break; 574 case DDI_INTROP_CLRMASK: 575 ret = pci_intx_clr_mask(rdip); 576 break; 577 case DDI_INTROP_GETPENDING: 578 ret = pci_intx_get_pending(rdip, (int *)result); 579 break; 580 case DDI_INTROP_NINTRS: 581 case DDI_INTROP_NAVAIL: 582 *(int *)result = i_ddi_get_nintrs(rdip); 583 break; 584 default: 585 ret = DDI_ENOTSUP; 586 break; 587 } 588 589 return (ret); 590 } 591 592 /* ARGSUSED */ 593 int 594 px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 595 ddi_intr_handle_impl_t *hdlp, void *result) 596 { 597 px_t *px_p = DIP_TO_STATE(dip); 598 px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 599 msiq_rec_type_t msiq_rec_type; 600 msi_type_t msi_type; 601 uint64_t msi_addr; 602 msinum_t msi_num; 603 msiqid_t msiq_id; 604 uint_t nintrs; 605 int i, ret = DDI_SUCCESS; 606 607 DBG(DBG_INTROPS, dip, "px_msix_ops: dip=%x rdip=%x intr_op=%x " 608 "handle=%p\n", dip, rdip, intr_op, hdlp); 609 610 /* Check for MSI64 support */ 611 if (hdlp->ih_cap & DDI_INTR_FLAG_MSI64) { 612 msiq_rec_type = MSI64_REC; 613 msi_type = MSI64_TYPE; 614 msi_addr = msi_state_p->msi_addr64 ? 615 msi_state_p->msi_addr64:msi_state_p->msi_addr32; 616 } else { 617 msiq_rec_type = MSI32_REC; 618 msi_type = MSI32_TYPE; 619 msi_addr = msi_state_p->msi_addr32; 620 } 621 622 switch (intr_op) { 623 case DDI_INTROP_GETCAP: 624 ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result); 625 break; 626 case DDI_INTROP_SETCAP: 627 DBG(DBG_INTROPS, dip, "px_msix_ops: SetCap is not supported\n"); 628 ret = DDI_ENOTSUP; 629 break; 630 case DDI_INTROP_ALLOC: 631 /* 632 * We need to restrict this allocation in future 633 * based on Resource Management policies. 634 */ 635 if ((ret = px_msi_alloc(px_p, rdip, hdlp->ih_inum, 636 hdlp->ih_scratch1, (int)hdlp->ih_scratch2, &msi_num, 637 (int *)result)) != DDI_SUCCESS) { 638 DBG(DBG_INTROPS, dip, "px_msix_ops: MSI allocation " 639 "failed, rdip 0x%p inum 0x%x count 0x%x\n", 640 rdip, hdlp->ih_inum, hdlp->ih_scratch1); 641 642 return (ret); 643 } 644 645 break; 646 case DDI_INTROP_FREE: 647 (void) pci_msi_disable_mode(rdip, hdlp->ih_type, hdlp->ih_inum); 648 (void) pci_msi_unconfigure(rdip, hdlp->ih_type, hdlp->ih_inum); 649 (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 650 hdlp->ih_scratch1); 651 break; 652 case DDI_INTROP_GETPRI: 653 *(int *)result = hdlp->ih_pri ? 654 hdlp->ih_pri : px_class_to_pil(rdip); 655 break; 656 case DDI_INTROP_SETPRI: 657 break; 658 case DDI_INTROP_ADDISR: 659 if ((ret = px_msi_get_msinum(px_p, hdlp->ih_dip, 660 hdlp->ih_inum, &msi_num)) != DDI_SUCCESS) 661 return (ret); 662 663 if ((ret = px_add_msiq_intr(dip, rdip, hdlp, 664 msiq_rec_type, msi_num, &msiq_id)) != DDI_SUCCESS) { 665 DBG(DBG_INTROPS, dip, "px_msix_ops: Add MSI handler " 666 "failed, rdip 0x%p msi 0x%x\n", rdip, msi_num); 667 return (ret); 668 } 669 670 DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id); 671 672 if ((ret = px_lib_msi_setmsiq(dip, msi_num, 673 msiq_id, msi_type)) != DDI_SUCCESS) { 674 (void) px_rem_msiq_intr(dip, rdip, 675 hdlp, msiq_rec_type, msi_num, msiq_id); 676 return (ret); 677 } 678 679 if ((ret = px_lib_msi_setstate(dip, msi_num, 680 PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) { 681 (void) px_rem_msiq_intr(dip, rdip, 682 hdlp, msiq_rec_type, msi_num, msiq_id); 683 return (ret); 684 } 685 686 hdlp->ih_vector = msi_num; 687 break; 688 case DDI_INTROP_DUPVEC: 689 DBG(DBG_INTROPS, dip, "px_msix_ops: DupIsr is not supported\n"); 690 ret = DDI_ENOTSUP; 691 break; 692 case DDI_INTROP_REMISR: 693 msi_num = hdlp->ih_vector; 694 695 if ((ret = px_lib_msi_getmsiq(dip, msi_num, 696 &msiq_id)) != DDI_SUCCESS) 697 return (ret); 698 699 if ((ret = px_lib_msi_setstate(dip, msi_num, 700 PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) 701 return (ret); 702 703 ret = px_rem_msiq_intr(dip, rdip, 704 hdlp, msiq_rec_type, msi_num, msiq_id); 705 706 hdlp->ih_vector = 0; 707 break; 708 case DDI_INTROP_ENABLE: 709 msi_num = hdlp->ih_vector; 710 711 if ((ret = px_lib_msi_setvalid(dip, msi_num, 712 PCI_MSI_VALID)) != DDI_SUCCESS) 713 return (ret); 714 715 if (pci_is_msi_enabled(rdip, hdlp->ih_type) != DDI_SUCCESS) { 716 nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 717 718 if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 719 nintrs, hdlp->ih_inum, msi_addr, 720 msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 721 return (ret); 722 723 if ((ret = pci_msi_enable_mode(rdip, hdlp->ih_type, 724 hdlp->ih_inum)) != DDI_SUCCESS) 725 return (ret); 726 } 727 728 if ((ret = pci_msi_clr_mask(rdip, hdlp->ih_type, 729 hdlp->ih_inum)) != DDI_SUCCESS) 730 return (ret); 731 732 if ((ret = px_lib_msi_getmsiq(dip, msi_num, 733 &msiq_id)) != DDI_SUCCESS) 734 return (ret); 735 736 ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 737 px_msiqid_to_devino(px_p, msiq_id), PX_INTR_STATE_ENABLE, 738 msiq_rec_type, msi_num); 739 740 break; 741 case DDI_INTROP_DISABLE: 742 msi_num = hdlp->ih_vector; 743 744 if ((ret = pci_msi_set_mask(rdip, hdlp->ih_type, 745 hdlp->ih_inum)) != DDI_SUCCESS) 746 return (ret); 747 748 if ((ret = px_lib_msi_setvalid(dip, msi_num, 749 PCI_MSI_INVALID)) != DDI_SUCCESS) 750 return (ret); 751 752 if ((ret = px_lib_msi_getmsiq(dip, msi_num, 753 &msiq_id)) != DDI_SUCCESS) 754 return (ret); 755 756 ret = px_ib_update_intr_state(px_p, rdip, 757 hdlp->ih_inum, px_msiqid_to_devino(px_p, msiq_id), 758 PX_INTR_STATE_DISABLE, msiq_rec_type, msi_num); 759 760 break; 761 case DDI_INTROP_BLOCKENABLE: 762 nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 763 msi_num = hdlp->ih_vector; 764 765 if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 766 nintrs, hdlp->ih_inum, msi_addr, 767 msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 768 return (ret); 769 770 for (i = 0; i < nintrs; i++, msi_num++) { 771 if ((ret = px_lib_msi_setvalid(dip, msi_num, 772 PCI_MSI_VALID)) != DDI_SUCCESS) 773 return (ret); 774 775 if ((ret = px_lib_msi_getmsiq(dip, msi_num, 776 &msiq_id)) != DDI_SUCCESS) 777 return (ret); 778 779 if ((ret = px_ib_update_intr_state(px_p, rdip, 780 hdlp->ih_inum + i, px_msiqid_to_devino(px_p, 781 msiq_id), PX_INTR_STATE_ENABLE, msiq_rec_type, 782 msi_num)) != DDI_SUCCESS) 783 return (ret); 784 } 785 786 ret = pci_msi_enable_mode(rdip, hdlp->ih_type, hdlp->ih_inum); 787 break; 788 case DDI_INTROP_BLOCKDISABLE: 789 nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 790 msi_num = hdlp->ih_vector; 791 792 if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type, 793 hdlp->ih_inum)) != DDI_SUCCESS) 794 return (ret); 795 796 for (i = 0; i < nintrs; i++, msi_num++) { 797 if ((ret = px_lib_msi_setvalid(dip, msi_num, 798 PCI_MSI_INVALID)) != DDI_SUCCESS) 799 return (ret); 800 801 if ((ret = px_lib_msi_getmsiq(dip, msi_num, 802 &msiq_id)) != DDI_SUCCESS) 803 return (ret); 804 805 if ((ret = px_ib_update_intr_state(px_p, rdip, 806 hdlp->ih_inum + i, px_msiqid_to_devino(px_p, 807 msiq_id), PX_INTR_STATE_DISABLE, msiq_rec_type, 808 msi_num)) != DDI_SUCCESS) 809 return (ret); 810 } 811 812 break; 813 case DDI_INTROP_SETMASK: 814 ret = pci_msi_set_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 815 break; 816 case DDI_INTROP_CLRMASK: 817 ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 818 break; 819 case DDI_INTROP_GETPENDING: 820 ret = pci_msi_get_pending(rdip, hdlp->ih_type, 821 hdlp->ih_inum, (int *)result); 822 break; 823 case DDI_INTROP_NINTRS: 824 ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 825 break; 826 case DDI_INTROP_NAVAIL: 827 /* XXX - a new interface may be needed */ 828 ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 829 break; 830 default: 831 ret = DDI_ENOTSUP; 832 break; 833 } 834 835 return (ret); 836 } 837 838 static struct { 839 kstat_named_t pxintr_ks_name; 840 kstat_named_t pxintr_ks_type; 841 kstat_named_t pxintr_ks_cpu; 842 kstat_named_t pxintr_ks_pil; 843 kstat_named_t pxintr_ks_time; 844 kstat_named_t pxintr_ks_ino; 845 kstat_named_t pxintr_ks_cookie; 846 kstat_named_t pxintr_ks_devpath; 847 kstat_named_t pxintr_ks_buspath; 848 } pxintr_ks_template = { 849 { "name", KSTAT_DATA_CHAR }, 850 { "type", KSTAT_DATA_CHAR }, 851 { "cpu", KSTAT_DATA_UINT64 }, 852 { "pil", KSTAT_DATA_UINT64 }, 853 { "time", KSTAT_DATA_UINT64 }, 854 { "ino", KSTAT_DATA_UINT64 }, 855 { "cookie", KSTAT_DATA_UINT64 }, 856 { "devpath", KSTAT_DATA_STRING }, 857 { "buspath", KSTAT_DATA_STRING }, 858 }; 859 860 static uint32_t pxintr_ks_instance; 861 kmutex_t pxintr_ks_template_lock; 862 863 int 864 px_ks_update(kstat_t *ksp, int rw) 865 { 866 px_ih_t *ih_p = ksp->ks_private; 867 int maxlen = sizeof (pxintr_ks_template.pxintr_ks_name.value.c); 868 px_ib_t *ib_p = ih_p->ih_ino_p->ino_ib_p; 869 px_t *px_p = ib_p->ib_px_p; 870 devino_t ino; 871 sysino_t sysino; 872 char ih_devpath[MAXPATHLEN]; 873 char ih_buspath[MAXPATHLEN]; 874 875 ino = ih_p->ih_ino_p->ino_ino; 876 (void) px_lib_intr_devino_to_sysino(px_p->px_dip, ino, &sysino); 877 878 (void) snprintf(pxintr_ks_template.pxintr_ks_name.value.c, maxlen, 879 "%s%d", ddi_driver_name(ih_p->ih_dip), 880 ddi_get_instance(ih_p->ih_dip)); 881 882 (void) ddi_pathname(ih_p->ih_dip, ih_devpath); 883 (void) ddi_pathname(px_p->px_dip, ih_buspath); 884 kstat_named_setstr(&pxintr_ks_template.pxintr_ks_devpath, ih_devpath); 885 kstat_named_setstr(&pxintr_ks_template.pxintr_ks_buspath, ih_buspath); 886 887 if (ih_p->ih_intr_state == PX_INTR_STATE_ENABLE) { 888 889 (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 890 (ih_p->ih_rec_type == 0) ? "fixed" : "msi"); 891 pxintr_ks_template.pxintr_ks_cpu.value.ui64 = 892 ih_p->ih_ino_p->ino_cpuid; 893 pxintr_ks_template.pxintr_ks_pil.value.ui64 = 894 ih_p->ih_ino_p->ino_pil; 895 pxintr_ks_template.pxintr_ks_time.value.ui64 = ih_p->ih_nsec + 896 (uint64_t)tick2ns((hrtime_t)ih_p->ih_ticks, 897 ih_p->ih_ino_p->ino_cpuid); 898 pxintr_ks_template.pxintr_ks_ino.value.ui64 = ino; 899 pxintr_ks_template.pxintr_ks_cookie.value.ui64 = sysino; 900 } else { 901 (void) strcpy(pxintr_ks_template.pxintr_ks_type.value.c, 902 "disabled"); 903 pxintr_ks_template.pxintr_ks_cpu.value.ui64 = 0; 904 pxintr_ks_template.pxintr_ks_pil.value.ui64 = 0; 905 pxintr_ks_template.pxintr_ks_time.value.ui64 = 0; 906 pxintr_ks_template.pxintr_ks_ino.value.ui64 = 0; 907 pxintr_ks_template.pxintr_ks_cookie.value.ui64 = 0; 908 } 909 return (0); 910 } 911 912 void 913 px_create_intr_kstats(px_ih_t *ih_p) 914 { 915 msiq_rec_type_t rec_type = ih_p->ih_rec_type; 916 917 ASSERT(ih_p->ih_ksp == NULL); 918 919 /* 920 * Create pci_intrs::: kstats for all ih types except messages, 921 * which represent unusual conditions and don't need to be tracked. 922 */ 923 if (rec_type == 0 || rec_type == MSI32_REC || rec_type == MSI64_REC) { 924 ih_p->ih_ksp = kstat_create("pci_intrs", 925 atomic_inc_32_nv(&pxintr_ks_instance), "config", 926 "interrupts", KSTAT_TYPE_NAMED, 927 sizeof (pxintr_ks_template) / sizeof (kstat_named_t), 928 KSTAT_FLAG_VIRTUAL); 929 } 930 if (ih_p->ih_ksp != NULL) { 931 ih_p->ih_ksp->ks_data_size += MAXPATHLEN * 2; 932 ih_p->ih_ksp->ks_lock = &pxintr_ks_template_lock; 933 ih_p->ih_ksp->ks_data = &pxintr_ks_template; 934 ih_p->ih_ksp->ks_private = ih_p; 935 ih_p->ih_ksp->ks_update = px_ks_update; 936 } 937 } 938 939 /* 940 * px_add_intx_intr: 941 * 942 * This function is called to register INTx and legacy hardware 943 * interrupt pins interrupts. 944 */ 945 int 946 px_add_intx_intr(dev_info_t *dip, dev_info_t *rdip, 947 ddi_intr_handle_impl_t *hdlp) 948 { 949 px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 950 px_ib_t *ib_p = px_p->px_ib_p; 951 devino_t ino; 952 px_ih_t *ih_p; 953 px_ib_ino_info_t *ino_p; 954 int32_t weight; 955 int ret = DDI_SUCCESS; 956 957 ino = hdlp->ih_vector; 958 959 DBG(DBG_A_INTX, dip, "px_add_intx_intr: rdip=%s%d ino=%x " 960 "handler=%x arg1=%x arg2=%x\n", ddi_driver_name(rdip), 961 ddi_get_instance(rdip), ino, hdlp->ih_cb_func, 962 hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 963 964 ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, 965 hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, 0, 0); 966 967 mutex_enter(&ib_p->ib_ino_lst_mutex); 968 969 if (ino_p = px_ib_locate_ino(ib_p, ino)) { /* sharing ino */ 970 uint32_t intr_index = hdlp->ih_inum; 971 if (px_ib_ino_locate_intr(ino_p, rdip, intr_index, 0, 0)) { 972 DBG(DBG_A_INTX, dip, "px_add_intx_intr: " 973 "dup intr #%d\n", intr_index); 974 975 ret = DDI_FAILURE; 976 goto fail1; 977 } 978 979 /* Save mondo value in hdlp */ 980 hdlp->ih_vector = ino_p->ino_sysino; 981 982 if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p)) 983 != DDI_SUCCESS) 984 goto fail1; 985 } else { 986 ino_p = px_ib_new_ino(ib_p, ino, ih_p); 987 988 if (hdlp->ih_pri == 0) 989 hdlp->ih_pri = px_class_to_pil(rdip); 990 991 /* Save mondo value in hdlp */ 992 hdlp->ih_vector = ino_p->ino_sysino; 993 994 DBG(DBG_A_INTX, dip, "px_add_intx_intr: pil=0x%x mondo=0x%x\n", 995 hdlp->ih_pri, hdlp->ih_vector); 996 997 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 998 (ddi_intr_handler_t *)px_intx_intr, (caddr_t)ino_p, NULL); 999 1000 ret = i_ddi_add_ivintr(hdlp); 1001 1002 /* 1003 * Restore original interrupt handler 1004 * and arguments in interrupt handle. 1005 */ 1006 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 1007 ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 1008 1009 if (ret != DDI_SUCCESS) 1010 goto fail2; 1011 1012 /* Save the pil for this ino */ 1013 ino_p->ino_pil = hdlp->ih_pri; 1014 1015 /* select cpu, saving it for sharing and removal */ 1016 ino_p->ino_cpuid = intr_dist_cpuid(); 1017 1018 /* Enable interrupt */ 1019 px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino); 1020 } 1021 1022 /* add weight to the cpu that we are already targeting */ 1023 weight = px_class_to_intr_weight(rdip); 1024 intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 1025 1026 ih_p->ih_ino_p = ino_p; 1027 px_create_intr_kstats(ih_p); 1028 if (ih_p->ih_ksp) 1029 kstat_install(ih_p->ih_ksp); 1030 mutex_exit(&ib_p->ib_ino_lst_mutex); 1031 1032 DBG(DBG_A_INTX, dip, "px_add_intx_intr: done! Interrupt 0x%x pil=%x\n", 1033 ino_p->ino_sysino, hdlp->ih_pri); 1034 1035 return (ret); 1036 fail2: 1037 px_ib_delete_ino(ib_p, ino_p); 1038 fail1: 1039 if (ih_p->ih_config_handle) 1040 pci_config_teardown(&ih_p->ih_config_handle); 1041 1042 mutex_exit(&ib_p->ib_ino_lst_mutex); 1043 kmem_free(ih_p, sizeof (px_ih_t)); 1044 1045 DBG(DBG_A_INTX, dip, "px_add_intx_intr: Failed! Interrupt 0x%x " 1046 "pil=%x\n", ino_p->ino_sysino, hdlp->ih_pri); 1047 1048 return (ret); 1049 } 1050 1051 /* 1052 * px_rem_intx_intr: 1053 * 1054 * This function is called to unregister INTx and legacy hardware 1055 * interrupt pins interrupts. 1056 */ 1057 int 1058 px_rem_intx_intr(dev_info_t *dip, dev_info_t *rdip, 1059 ddi_intr_handle_impl_t *hdlp) 1060 { 1061 px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 1062 px_ib_t *ib_p = px_p->px_ib_p; 1063 devino_t ino; 1064 cpuid_t curr_cpu; 1065 px_ib_ino_info_t *ino_p; 1066 px_ih_t *ih_p; 1067 int ret = DDI_SUCCESS; 1068 1069 ino = hdlp->ih_vector; 1070 1071 DBG(DBG_R_INTX, dip, "px_rem_intx_intr: rdip=%s%d ino=%x\n", 1072 ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 1073 1074 mutex_enter(&ib_p->ib_ino_lst_mutex); 1075 1076 ino_p = px_ib_locate_ino(ib_p, ino); 1077 ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 0, 0); 1078 1079 /* Get the current cpu */ 1080 if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 1081 &curr_cpu)) != DDI_SUCCESS) 1082 goto fail; 1083 1084 if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS) 1085 goto fail; 1086 1087 intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 1088 1089 if (ino_p->ino_ih_size == 0) { 1090 if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 1091 INTR_DELIVERED_STATE)) != DDI_SUCCESS) 1092 goto fail; 1093 1094 hdlp->ih_vector = ino_p->ino_sysino; 1095 i_ddi_rem_ivintr(hdlp); 1096 1097 px_ib_delete_ino(ib_p, ino_p); 1098 kmem_free(ino_p, sizeof (px_ib_ino_info_t)); 1099 } else { 1100 /* Re-enable interrupt only if mapping regsiter still shared */ 1101 PX_INTR_ENABLE(px_p->px_dip, ino_p->ino_sysino, curr_cpu); 1102 } 1103 1104 fail: 1105 mutex_exit(&ib_p->ib_ino_lst_mutex); 1106 return (ret); 1107 } 1108 1109 /* 1110 * px_add_msiq_intr: 1111 * 1112 * This function is called to register MSI/Xs and PCIe message interrupts. 1113 */ 1114 int 1115 px_add_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 1116 ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 1117 msgcode_t msg_code, msiqid_t *msiq_id_p) 1118 { 1119 px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 1120 px_ib_t *ib_p = px_p->px_ib_p; 1121 px_msiq_state_t *msiq_state_p = &ib_p->ib_msiq_state; 1122 devino_t ino; 1123 px_ih_t *ih_p; 1124 px_ib_ino_info_t *ino_p; 1125 int32_t weight; 1126 int ret = DDI_SUCCESS; 1127 1128 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=%x " 1129 "arg1=%x arg2=%x\n", ddi_driver_name(rdip), ddi_get_instance(rdip), 1130 hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 1131 1132 if ((ret = px_msiq_alloc(px_p, rec_type, msiq_id_p)) != DDI_SUCCESS) { 1133 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 1134 "msiq allocation failed\n"); 1135 return (ret); 1136 } 1137 1138 ino = px_msiqid_to_devino(px_p, *msiq_id_p); 1139 1140 ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, hdlp->ih_cb_func, 1141 hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, rec_type, msg_code); 1142 1143 mutex_enter(&ib_p->ib_ino_lst_mutex); 1144 1145 if (ino_p = px_ib_locate_ino(ib_p, ino)) { /* sharing ino */ 1146 uint32_t intr_index = hdlp->ih_inum; 1147 if (px_ib_ino_locate_intr(ino_p, rdip, 1148 intr_index, rec_type, msg_code)) { 1149 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 1150 "dup intr #%d\n", intr_index); 1151 1152 ret = DDI_FAILURE; 1153 goto fail1; 1154 } 1155 1156 if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p)) 1157 != DDI_SUCCESS) 1158 goto fail1; 1159 } else { 1160 ino_p = px_ib_new_ino(ib_p, ino, ih_p); 1161 1162 ino_p->ino_msiq_p = msiq_state_p->msiq_p + 1163 (*msiq_id_p - msiq_state_p->msiq_1st_msiq_id); 1164 1165 if (hdlp->ih_pri == 0) 1166 hdlp->ih_pri = px_class_to_pil(rdip); 1167 1168 /* Save mondo value in hdlp */ 1169 hdlp->ih_vector = ino_p->ino_sysino; 1170 1171 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n", 1172 hdlp->ih_pri, hdlp->ih_vector); 1173 1174 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 1175 (ddi_intr_handler_t *)px_msiq_intr, (caddr_t)ino_p, NULL); 1176 1177 ret = i_ddi_add_ivintr(hdlp); 1178 1179 /* 1180 * Restore original interrupt handler 1181 * and arguments in interrupt handle. 1182 */ 1183 DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 1184 ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 1185 1186 if (ret != DDI_SUCCESS) 1187 goto fail2; 1188 1189 /* Save the pil for this ino */ 1190 ino_p->ino_pil = hdlp->ih_pri; 1191 1192 /* Enable MSIQ */ 1193 px_lib_msiq_setstate(dip, *msiq_id_p, PCI_MSIQ_STATE_IDLE); 1194 px_lib_msiq_setvalid(dip, *msiq_id_p, PCI_MSIQ_VALID); 1195 1196 /* select cpu, saving it for sharing and removal */ 1197 ino_p->ino_cpuid = intr_dist_cpuid(); 1198 1199 /* Enable interrupt */ 1200 px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino_p->ino_ino); 1201 } 1202 1203 /* add weight to the cpu that we are already targeting */ 1204 weight = px_class_to_intr_weight(rdip); 1205 intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 1206 1207 ih_p->ih_ino_p = ino_p; 1208 px_create_intr_kstats(ih_p); 1209 if (ih_p->ih_ksp) 1210 kstat_install(ih_p->ih_ksp); 1211 mutex_exit(&ib_p->ib_ino_lst_mutex); 1212 1213 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n", 1214 ino_p->ino_sysino, hdlp->ih_pri); 1215 1216 return (ret); 1217 fail2: 1218 px_ib_delete_ino(ib_p, ino_p); 1219 fail1: 1220 if (ih_p->ih_config_handle) 1221 pci_config_teardown(&ih_p->ih_config_handle); 1222 1223 mutex_exit(&ib_p->ib_ino_lst_mutex); 1224 kmem_free(ih_p, sizeof (px_ih_t)); 1225 1226 DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n", 1227 ino_p->ino_sysino, hdlp->ih_pri); 1228 1229 return (ret); 1230 } 1231 1232 /* 1233 * px_rem_msiq_intr: 1234 * 1235 * This function is called to unregister MSI/Xs and PCIe message interrupts. 1236 */ 1237 int 1238 px_rem_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 1239 ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 1240 msgcode_t msg_code, msiqid_t msiq_id) 1241 { 1242 px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 1243 px_ib_t *ib_p = px_p->px_ib_p; 1244 devino_t ino = px_msiqid_to_devino(px_p, msiq_id); 1245 cpuid_t curr_cpu; 1246 px_ib_ino_info_t *ino_p; 1247 px_ih_t *ih_p; 1248 int ret = DDI_SUCCESS; 1249 1250 DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n", 1251 ddi_driver_name(rdip), ddi_get_instance(rdip), msiq_id, ino); 1252 1253 mutex_enter(&ib_p->ib_ino_lst_mutex); 1254 1255 ino_p = px_ib_locate_ino(ib_p, ino); 1256 ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 1257 rec_type, msg_code); 1258 1259 /* Get the current cpu */ 1260 if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 1261 &curr_cpu)) != DDI_SUCCESS) 1262 goto fail; 1263 1264 if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS) 1265 goto fail; 1266 1267 intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 1268 1269 if (ino_p->ino_ih_size == 0) { 1270 if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 1271 INTR_DELIVERED_STATE)) != DDI_SUCCESS) 1272 goto fail; 1273 1274 px_lib_msiq_setvalid(dip, px_devino_to_msiqid(px_p, ino), 1275 PCI_MSIQ_INVALID); 1276 1277 hdlp->ih_vector = ino_p->ino_sysino; 1278 i_ddi_rem_ivintr(hdlp); 1279 1280 px_ib_delete_ino(ib_p, ino_p); 1281 1282 (void) px_msiq_free(px_p, msiq_id); 1283 kmem_free(ino_p, sizeof (px_ib_ino_info_t)); 1284 } else { 1285 /* Re-enable interrupt only if mapping regsiter still shared */ 1286 PX_INTR_ENABLE(px_p->px_dip, ino_p->ino_sysino, curr_cpu); 1287 } 1288 1289 fail: 1290 mutex_exit(&ib_p->ib_ino_lst_mutex); 1291 return (ret); 1292 } 1293