1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_IB_H 27 #define _SYS_PX_IB_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/ddi_subrdefs.h> 36 #include <sys/pci_tools.h> 37 38 typedef struct px_ib px_ib_t; 39 typedef struct px_ino px_ino_t; 40 typedef struct px_ino_pil px_ino_pil_t; 41 typedef struct px_ih px_ih_t; 42 43 /* 44 * interrupt block soft state structure: 45 * 46 * Each px node may share an interrupt block structure with its peer 47 * node or have its own private interrupt block structure. 48 */ 49 struct px_ib { 50 px_t *ib_px_p; /* link back to px soft state */ 51 px_ino_t *ib_ino_lst; /* ino link list */ 52 kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 53 kmutex_t ib_intr_lock; /* lock for internal intr */ 54 55 px_msiq_state_t ib_msiq_state; /* MSIQ soft state */ 56 px_msi_state_t ib_msi_state; /* MSI soft state */ 57 }; 58 59 /* 60 * ih structure: one per every consumer of each ino and pil pair with interrupt 61 * registered. 62 */ 63 struct px_ih { 64 dev_info_t *ih_dip; /* devinfo structure */ 65 uint32_t ih_inum; /* interrupt number for this device */ 66 uint_t (*ih_handler)(); /* interrupt handler */ 67 caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 68 caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 69 ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 70 uint_t ih_intr_state; /* only used for fixed interrupts */ 71 msiq_rec_type_t ih_rec_type; /* MSI or PCIe record type */ 72 msgcode_t ih_msg_code; /* MSI number or PCIe message code */ 73 px_ih_t *ih_next; /* Next entry in list */ 74 uint64_t ih_ticks; /* ticks spent in this handler */ 75 uint64_t ih_nsec; /* nsec spent in this handler */ 76 kstat_t *ih_ksp; /* pointer to kstat information */ 77 px_ino_pil_t *ih_ipil_p; /* only for use by kstat */ 78 }; 79 80 /* Only used for fixed or legacy interrupts */ 81 #define PX_INTR_STATE_DISABLE 0 /* disabled */ 82 #define PX_INTR_STATE_ENABLE 1 /* enabled */ 83 84 /* 85 * ino_pil structure: one per each ino and pil pair with interrupt registered 86 */ 87 struct px_ino_pil { 88 ushort_t ipil_pil; /* pil for this ino */ 89 ushort_t ipil_ih_size; /* size of px_ih_t list */ 90 px_ih_t *ipil_ih_head; /* px_ih_t list head */ 91 px_ih_t *ipil_ih_tail; /* px_ih_t list tail */ 92 px_ih_t *ipil_ih_start; /* starting point in px_ih_t list */ 93 px_ino_t *ipil_ino_p; /* pointer to px_ino_t structure */ 94 px_ino_pil_t *ipil_next_p; /* pointer to next px_ino_pil_t */ 95 }; 96 97 /* 98 * ino structure: one per each ino with interrupt registered 99 */ 100 struct px_ino { 101 devino_t ino_ino; /* INO number - 8 bit */ 102 sysino_t ino_sysino; /* Virtual inumber */ 103 px_ib_t *ino_ib_p; /* link back to interrupt block state */ 104 uint_t ino_unclaimed_intrs; /* number of unclaimed intrs */ 105 clock_t ino_spurintr_begin; /* begin time of spurious intr */ 106 cpuid_t ino_cpuid; /* cpu that ino is targeting */ 107 int32_t ino_intr_weight; /* intr wt of devices sharing ino */ 108 ushort_t ino_ipil_size; /* no of px_ino_pil_t sharing ino */ 109 ushort_t ino_lopil; /* lowest pil sharing ino */ 110 ushort_t ino_claimed; /* pil bit masks, who claimed intr */ 111 px_msiq_t *ino_msiq_p; /* pointer to MSIQ used */ 112 px_ino_pil_t *ino_ipil_p; /* pointer to first px_ino_pil_t */ 113 px_ino_t *ino_next_p; /* pointer to next px_ino_t */ 114 }; 115 116 #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 117 #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 118 119 #define PX_INTR_ENABLE(dip, sysino, cpuid) \ 120 (void) px_lib_intr_settarget(dip, sysino, cpuid); \ 121 (void) px_lib_intr_setvalid(dip, sysino, INTR_VALID); 122 123 #define PX_INTR_DISABLE(dip, sysino) \ 124 (void) px_lib_intr_setvalid(dip, sysino, INTR_NOTVALID); 125 126 extern int px_ib_attach(px_t *px_p); 127 extern void px_ib_detach(px_t *px_p); 128 extern void px_ib_intr_enable(px_t *px_p, cpuid_t cpuid, devino_t ino); 129 extern void px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait); 130 extern void px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino, 131 boolean_t wait_flag); 132 133 extern px_ino_t *px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num); 134 extern void px_ib_free_ino_all(px_ib_t *ib_p); 135 136 extern px_ino_pil_t *px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil); 137 extern px_ino_pil_t *px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num, 138 uint_t pil, px_ih_t *ih_p); 139 extern void px_ib_delete_ino_pil(px_ib_t *ib_p, px_ino_pil_t *ipil_p); 140 extern int px_ib_ino_add_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p); 141 extern int px_ib_ino_rem_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p); 142 143 extern px_ih_t *px_ib_intr_locate_ih(px_ino_pil_t *ipil_p, dev_info_t *dip, 144 uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code); 145 extern px_ih_t *px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum, 146 uint_t (*int_handler)(caddr_t int_handler_arg1, 147 caddr_t int_handler_arg2), caddr_t int_handler_arg1, 148 caddr_t int_handler_arg2, msiq_rec_type_t rec_type, msgcode_t msg_code); 149 extern void px_ib_free_ih(px_ih_t *ih_p); 150 extern int px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum, 151 devino_t ino, uint_t pil, uint_t new_intr_state, 152 msiq_rec_type_t rec_type, msgcode_t msg_code); 153 154 extern uint8_t pxtool_ib_get_ino_devs(px_t *px_p, uint32_t ino, 155 uint8_t *devs_ret, pcitool_intr_dev_t *devs); 156 extern void px_ib_log_new_cpu(px_ib_t *ib_p, uint32_t old_cpu_id, 157 uint32_t new_cpu_id, uint32_t ino); 158 159 160 #ifdef __cplusplus 161 } 162 #endif 163 164 #endif /* _SYS_PX_IB_H */ 165