1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI Express nexus DVMA and DMA core routines: 30 * dma_map/dma_bind_handle implementation 31 * bypass and peer-to-peer support 32 * fast track DVMA space allocation 33 * runtime DVMA debug 34 */ 35 #include <sys/types.h> 36 #include <sys/kmem.h> 37 #include <sys/async.h> 38 #include <sys/sysmacros.h> 39 #include <sys/sunddi.h> 40 #include <sys/ddi_impldefs.h> 41 #include "px_obj.h" 42 43 /*LINTLIBRARY*/ 44 45 /* 46 * px_dma_allocmp - Allocate a pci dma implementation structure 47 * 48 * An extra ddi_dma_attr structure is bundled with the usual ddi_dma_impl 49 * to hold unmodified device limits. The ddi_dma_attr inside the 50 * ddi_dma_impl structure is augumented with system limits to enhance 51 * DVMA performance at runtime. The unaugumented device limits saved 52 * right after (accessed through (ddi_dma_attr_t *)(mp + 1)) is used 53 * strictly for peer-to-peer transfers which do not obey system limits. 54 * 55 * return: DDI_SUCCESS DDI_DMA_NORESOURCES 56 */ 57 ddi_dma_impl_t * 58 px_dma_allocmp(dev_info_t *dip, dev_info_t *rdip, int (*waitfp)(caddr_t), 59 caddr_t arg) 60 { 61 register ddi_dma_impl_t *mp; 62 int sleep = (waitfp == DDI_DMA_SLEEP) ? KM_SLEEP : KM_NOSLEEP; 63 64 /* Caution: we don't use zalloc to enhance performance! */ 65 if ((mp = kmem_alloc(sizeof (px_dma_hdl_t), sleep)) == 0) { 66 DBG(DBG_DMA_MAP, dip, "can't alloc dma_handle\n"); 67 if (waitfp != DDI_DMA_DONTWAIT) { 68 DBG(DBG_DMA_MAP, dip, "alloc_mp kmem cb\n"); 69 ddi_set_callback(waitfp, arg, &px_kmem_clid); 70 } 71 return (mp); 72 } 73 74 mp->dmai_rdip = rdip; 75 mp->dmai_flags = 0; 76 mp->dmai_pfnlst = NULL; 77 mp->dmai_winlst = NULL; 78 79 /* 80 * kmem_alloc debug: the following fields are not zero-ed 81 * mp->dmai_mapping = 0; 82 * mp->dmai_size = 0; 83 * mp->dmai_offset = 0; 84 * mp->dmai_minxfer = 0; 85 * mp->dmai_burstsizes = 0; 86 * mp->dmai_ndvmapages = 0; 87 * mp->dmai_pool/roffset = 0; 88 * mp->dmai_rflags = 0; 89 * mp->dmai_inuse/flags 90 * mp->dmai_nwin = 0; 91 * mp->dmai_winsize = 0; 92 * mp->dmai_nexus_private/tte = 0; 93 * mp->dmai_iopte/pfnlst 94 * mp->dmai_sbi/pfn0 = 0; 95 * mp->dmai_minfo/winlst/fdvma 96 * mp->dmai_rdip 97 * bzero(&mp->dmai_object, sizeof (ddi_dma_obj_t)); 98 * bzero(&mp->dmai_attr, sizeof (ddi_dma_attr_t)); 99 * mp->dmai_cookie = 0; 100 */ 101 102 mp->dmai_attr.dma_attr_version = (uint_t)DMA_ATTR_VERSION; 103 mp->dmai_attr.dma_attr_flags = (uint_t)0; 104 mp->dmai_fault = 0; 105 mp->dmai_fault_check = NULL; 106 mp->dmai_fault_notify = NULL; 107 108 mp->dmai_error.err_ena = 0; 109 mp->dmai_error.err_status = DDI_FM_OK; 110 mp->dmai_error.err_expected = DDI_FM_ERR_UNEXPECTED; 111 mp->dmai_error.err_ontrap = NULL; 112 mp->dmai_error.err_fep = NULL; 113 mp->dmai_error.err_cf = NULL; 114 115 return (mp); 116 } 117 118 void 119 px_dma_freemp(ddi_dma_impl_t *mp) 120 { 121 if (mp->dmai_ndvmapages > 1) 122 px_dma_freepfn(mp); 123 if (mp->dmai_winlst) 124 px_dma_freewin(mp); 125 kmem_free(mp, sizeof (px_dma_hdl_t)); 126 } 127 128 void 129 px_dma_freepfn(ddi_dma_impl_t *mp) 130 { 131 void *addr = mp->dmai_pfnlst; 132 if (addr) { 133 size_t npages = mp->dmai_ndvmapages; 134 if (npages > 1) 135 kmem_free(addr, npages * sizeof (px_iopfn_t)); 136 mp->dmai_pfnlst = NULL; 137 } 138 mp->dmai_ndvmapages = 0; 139 } 140 141 /* 142 * px_dma_lmts2hdl - alloate a ddi_dma_impl_t, validate practical limits 143 * and convert dmareq->dmar_limits to mp->dmai_attr 144 * 145 * ddi_dma_impl_t member modified input 146 * ------------------------------------------------------------------------ 147 * mp->dmai_minxfer - dev 148 * mp->dmai_burstsizes - dev 149 * mp->dmai_flags - no limit? peer-to-peer only? 150 * 151 * ddi_dma_attr member modified input 152 * ------------------------------------------------------------------------ 153 * mp->dmai_attr.dma_attr_addr_lo - dev lo, sys lo 154 * mp->dmai_attr.dma_attr_addr_hi - dev hi, sys hi 155 * mp->dmai_attr.dma_attr_count_max - dev count max, dev/sys lo/hi delta 156 * mp->dmai_attr.dma_attr_seg - 0 (no nocross restriction) 157 * mp->dmai_attr.dma_attr_align - 1 (no alignment restriction) 158 * 159 * The dlim_dmaspeed member of dmareq->dmar_limits is ignored. 160 */ 161 ddi_dma_impl_t * 162 px_dma_lmts2hdl(dev_info_t *dip, dev_info_t *rdip, px_mmu_t *mmu_p, 163 ddi_dma_req_t *dmareq) 164 { 165 ddi_dma_impl_t *mp; 166 ddi_dma_attr_t *attr_p; 167 uint64_t syslo = mmu_p->mmu_dvma_base; 168 uint64_t syshi = mmu_p->mmu_dvma_end; 169 uint64_t fasthi = mmu_p->mmu_dvma_fast_end; 170 ddi_dma_lim_t *lim_p = dmareq->dmar_limits; 171 uint32_t count_max = lim_p->dlim_cntr_max; 172 uint64_t lo = lim_p->dlim_addr_lo; 173 uint64_t hi = lim_p->dlim_addr_hi; 174 if (hi <= lo) { 175 DBG(DBG_DMA_MAP, dip, "Bad limits\n"); 176 return ((ddi_dma_impl_t *)DDI_DMA_NOMAPPING); 177 } 178 if (!count_max) 179 count_max--; 180 181 if (!(mp = px_dma_allocmp(dip, rdip, dmareq->dmar_fp, 182 dmareq->dmar_arg))) 183 return (NULL); 184 185 /* store original dev input at the 2nd ddi_dma_attr */ 186 attr_p = PX_DEV_ATTR(mp); 187 SET_DMAATTR(attr_p, lo, hi, -1, count_max); 188 SET_DMAALIGN(attr_p, 1); 189 190 lo = MAX(lo, syslo); 191 hi = MIN(hi, syshi); 192 if (hi <= lo) 193 mp->dmai_flags |= PX_DMAI_FLAGS_PEER_ONLY; 194 count_max = MIN(count_max, hi - lo); 195 196 if (PX_DEV_NOSYSLIMIT(lo, hi, syslo, fasthi, 1)) 197 mp->dmai_flags |= PX_DMAI_FLAGS_NOFASTLIMIT | 198 PX_DMAI_FLAGS_NOSYSLIMIT; 199 else { 200 if (PX_DEV_NOFASTLIMIT(lo, hi, syslo, syshi, 1)) 201 mp->dmai_flags |= PX_DMAI_FLAGS_NOFASTLIMIT; 202 } 203 if (PX_DMA_NOCTX(rdip)) 204 mp->dmai_flags |= PX_DMAI_FLAGS_NOCTX; 205 206 /* store augumented dev input to mp->dmai_attr */ 207 mp->dmai_minxfer = lim_p->dlim_minxfer; 208 mp->dmai_burstsizes = lim_p->dlim_burstsizes; 209 attr_p = &mp->dmai_attr; 210 SET_DMAATTR(attr_p, lo, hi, -1, count_max); 211 SET_DMAALIGN(attr_p, 1); 212 return (mp); 213 } 214 215 /* 216 * Called from px_attach to check for bypass dma support and set 217 * flags accordingly. 218 */ 219 int 220 px_dma_attach(px_t *px_p) 221 { 222 uint64_t baddr; 223 224 if (px_lib_iommu_getbypass(px_p->px_dip, 0ull, 225 PCI_MAP_ATTR_WRITE|PCI_MAP_ATTR_READ, 226 &baddr) != DDI_ENOTSUP) 227 /* ignore all other errors */ 228 px_p->px_dev_caps |= PX_BYPASS_DMA_ALLOWED; 229 230 return (DDI_SUCCESS); 231 } 232 233 /* 234 * px_dma_attr2hdl 235 * 236 * This routine is called from the alloc handle entry point to sanity check the 237 * dma attribute structure. 238 * 239 * use by: px_dma_allochdl() 240 * 241 * return value: 242 * 243 * DDI_SUCCESS - on success 244 * DDI_DMA_BADATTR - attribute has invalid version number 245 * or address limits exclude dvma space 246 */ 247 int 248 px_dma_attr2hdl(px_t *px_p, ddi_dma_impl_t *mp) 249 { 250 px_mmu_t *mmu_p = px_p->px_mmu_p; 251 uint64_t syslo, syshi; 252 int ret; 253 ddi_dma_attr_t *attrp = PX_DEV_ATTR(mp); 254 uint64_t hi = attrp->dma_attr_addr_hi; 255 uint64_t lo = attrp->dma_attr_addr_lo; 256 uint64_t align = attrp->dma_attr_align; 257 uint64_t nocross = attrp->dma_attr_seg; 258 uint64_t count_max = attrp->dma_attr_count_max; 259 260 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "attrp=%p cntr_max=%x.%08x\n", 261 attrp, HI32(count_max), LO32(count_max)); 262 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "hi=%x.%08x lo=%x.%08x\n", 263 HI32(hi), LO32(hi), HI32(lo), LO32(lo)); 264 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "seg=%x.%08x align=%x.%08x\n", 265 HI32(nocross), LO32(nocross), HI32(align), LO32(align)); 266 267 if (!nocross) 268 nocross--; 269 if (attrp->dma_attr_flags & DDI_DMA_FORCE_PHYSICAL) { /* BYPASS */ 270 271 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "bypass mode\n"); 272 /* 273 * If Bypass DMA is not supported, return error so that 274 * target driver can fall back to dvma mode of operation 275 */ 276 if (!(px_p->px_dev_caps & PX_BYPASS_DMA_ALLOWED)) 277 return (DDI_DMA_BADATTR); 278 mp->dmai_flags |= PX_DMAI_FLAGS_BYPASSREQ; 279 if (nocross != UINT64_MAX) 280 return (DDI_DMA_BADATTR); 281 if (align && (align > MMU_PAGE_SIZE)) 282 return (DDI_DMA_BADATTR); 283 align = 1; /* align on 1 page boundary */ 284 285 /* do a range check and get the limits */ 286 ret = px_lib_dma_bypass_rngchk(px_p->px_dip, attrp, 287 &syslo, &syshi); 288 if (ret != DDI_SUCCESS) 289 return (ret); 290 } else { /* MMU_XLATE or PEER_TO_PEER */ 291 align = MAX(align, MMU_PAGE_SIZE) - 1; 292 if ((align & nocross) != align) { 293 dev_info_t *rdip = mp->dmai_rdip; 294 cmn_err(CE_WARN, "%s%d dma_attr_seg not aligned", 295 NAMEINST(rdip)); 296 return (DDI_DMA_BADATTR); 297 } 298 align = MMU_BTOP(align + 1); 299 syslo = mmu_p->mmu_dvma_base; 300 syshi = mmu_p->mmu_dvma_end; 301 } 302 if (hi <= lo) { 303 dev_info_t *rdip = mp->dmai_rdip; 304 cmn_err(CE_WARN, "%s%d limits out of range", NAMEINST(rdip)); 305 return (DDI_DMA_BADATTR); 306 } 307 lo = MAX(lo, syslo); 308 hi = MIN(hi, syshi); 309 if (!count_max) 310 count_max--; 311 312 DBG(DBG_DMA_ALLOCH, px_p->px_dip, "hi=%x.%08x, lo=%x.%08x\n", 313 HI32(hi), LO32(hi), HI32(lo), LO32(lo)); 314 if (hi <= lo) { 315 /* 316 * If this is an IOMMU bypass access, the caller can't use 317 * the required addresses, so fail it. Otherwise, it's 318 * peer-to-peer; ensure that the caller has no alignment or 319 * segment size restrictions. 320 */ 321 if ((mp->dmai_flags & PX_DMAI_FLAGS_BYPASSREQ) || 322 (nocross < UINT32_MAX) || (align > 1)) 323 return (DDI_DMA_BADATTR); 324 325 mp->dmai_flags |= PX_DMAI_FLAGS_PEER_ONLY; 326 } else /* set practical counter_max value */ 327 count_max = MIN(count_max, hi - lo); 328 329 if (PX_DEV_NOSYSLIMIT(lo, hi, syslo, syshi, align)) 330 mp->dmai_flags |= PX_DMAI_FLAGS_NOSYSLIMIT | 331 PX_DMAI_FLAGS_NOFASTLIMIT; 332 else { 333 syshi = mmu_p->mmu_dvma_fast_end; 334 if (PX_DEV_NOFASTLIMIT(lo, hi, syslo, syshi, align)) 335 mp->dmai_flags |= PX_DMAI_FLAGS_NOFASTLIMIT; 336 } 337 if (PX_DMA_NOCTX(mp->dmai_rdip)) 338 mp->dmai_flags |= PX_DMAI_FLAGS_NOCTX; 339 340 mp->dmai_minxfer = attrp->dma_attr_minxfer; 341 mp->dmai_burstsizes = attrp->dma_attr_burstsizes; 342 attrp = &mp->dmai_attr; 343 SET_DMAATTR(attrp, lo, hi, nocross, count_max); 344 return (DDI_SUCCESS); 345 } 346 347 #define TGT_PFN_INBETWEEN(pfn, bgn, end) ((pfn >= bgn) && (pfn <= end)) 348 349 /* 350 * px_dma_type - determine which of the three types DMA (peer-to-peer, 351 * mmu bypass, or mmu translate) we are asked to do. 352 * Also checks pfn0 and rejects any non-peer-to-peer 353 * requests for peer-only devices. 354 * 355 * return values: 356 * DDI_DMA_NOMAPPING - can't get valid pfn0, or bad dma type 357 * DDI_SUCCESS 358 * 359 * dma handle members affected (set on exit): 360 * mp->dmai_object - dmareq->dmar_object 361 * mp->dmai_rflags - consistent?, nosync?, dmareq->dmar_flags 362 * mp->dmai_flags - DMA type 363 * mp->dmai_pfn0 - 1st page pfn (if va/size pair and not shadow) 364 * mp->dmai_roffset - initialized to starting MMU page offset 365 * mp->dmai_ndvmapages - # of total MMU pages of entire object 366 */ 367 int 368 px_dma_type(px_t *px_p, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp) 369 { 370 dev_info_t *dip = px_p->px_dip; 371 ddi_dma_obj_t *dobj_p = &dmareq->dmar_object; 372 px_pec_t *pec_p = px_p->px_pec_p; 373 uint32_t offset; 374 pfn_t pfn0; 375 uint_t redzone; 376 377 mp->dmai_rflags = dmareq->dmar_flags & DMP_DDIFLAGS | DMP_NOSYNC; 378 379 switch (dobj_p->dmao_type) { 380 case DMA_OTYP_BUFVADDR: 381 case DMA_OTYP_VADDR: { 382 page_t **pplist = dobj_p->dmao_obj.virt_obj.v_priv; 383 caddr_t vaddr = dobj_p->dmao_obj.virt_obj.v_addr; 384 385 DBG(DBG_DMA_MAP, dip, "vaddr=%p pplist=%p\n", vaddr, pplist); 386 offset = (ulong_t)vaddr & MMU_PAGE_OFFSET; 387 if (pplist) { /* shadow list */ 388 mp->dmai_flags |= PX_DMAI_FLAGS_PGPFN; 389 pfn0 = page_pptonum(*pplist); 390 } else { 391 struct as *as_p = dobj_p->dmao_obj.virt_obj.v_as; 392 struct hat *hat_p = as_p ? as_p->a_hat : kas.a_hat; 393 pfn0 = hat_getpfnum(hat_p, vaddr); 394 } 395 } 396 break; 397 398 case DMA_OTYP_PAGES: 399 offset = dobj_p->dmao_obj.pp_obj.pp_offset; 400 mp->dmai_flags |= PX_DMAI_FLAGS_PGPFN; 401 pfn0 = page_pptonum(dobj_p->dmao_obj.pp_obj.pp_pp); 402 break; 403 404 case DMA_OTYP_PADDR: 405 default: 406 cmn_err(CE_WARN, "%s%d requested unsupported dma type %x", 407 NAMEINST(mp->dmai_rdip), dobj_p->dmao_type); 408 return (DDI_DMA_NOMAPPING); 409 } 410 if (pfn0 == PFN_INVALID) { 411 cmn_err(CE_WARN, "%s%d: invalid pfn0 for DMA object %p", 412 NAMEINST(dip), dobj_p); 413 return (DDI_DMA_NOMAPPING); 414 } 415 if (TGT_PFN_INBETWEEN(pfn0, pec_p->pec_base32_pfn, 416 pec_p->pec_last32_pfn)) { 417 mp->dmai_flags |= PX_DMAI_FLAGS_PTP|PX_DMAI_FLAGS_PTP32; 418 goto done; /* leave bypass and dvma flag as 0 */ 419 } else if (TGT_PFN_INBETWEEN(pfn0, pec_p->pec_base64_pfn, 420 pec_p->pec_last64_pfn)) { 421 mp->dmai_flags |= PX_DMAI_FLAGS_PTP|PX_DMAI_FLAGS_PTP64; 422 goto done; /* leave bypass and dvma flag as 0 */ 423 } 424 if (PX_DMA_ISPEERONLY(mp)) { 425 dev_info_t *rdip = mp->dmai_rdip; 426 cmn_err(CE_WARN, "Bad peer-to-peer req %s%d", NAMEINST(rdip)); 427 return (DDI_DMA_NOMAPPING); 428 } 429 430 redzone = (mp->dmai_rflags & DDI_DMA_REDZONE) || 431 (mp->dmai_flags & PX_DMAI_FLAGS_MAP_BUFZONE) ? 432 PX_DMAI_FLAGS_REDZONE : 0; 433 434 mp->dmai_flags |= (mp->dmai_flags & PX_DMAI_FLAGS_BYPASSREQ) ? 435 PX_DMAI_FLAGS_BYPASS : (PX_DMAI_FLAGS_DVMA | redzone); 436 done: 437 mp->dmai_object = *dobj_p; /* whole object */ 438 mp->dmai_pfn0 = (void *)pfn0; /* cache pfn0 */ 439 mp->dmai_roffset = offset; /* win0 pg0 offset */ 440 mp->dmai_ndvmapages = MMU_BTOPR(offset + mp->dmai_object.dmao_size); 441 return (DDI_SUCCESS); 442 } 443 444 /* 445 * px_dma_pgpfn - set up pfnlst array according to pages 446 * VA/size pair: <shadow IO, bypass, peer-to-peer>, or OTYP_PAGES 447 */ 448 /*ARGSUSED*/ 449 static int 450 px_dma_pgpfn(px_t *px_p, ddi_dma_impl_t *mp, uint_t npages) 451 { 452 int i; 453 dev_info_t *dip = px_p->px_dip; 454 455 switch (mp->dmai_object.dmao_type) { 456 case DMA_OTYP_BUFVADDR: 457 case DMA_OTYP_VADDR: { 458 page_t **pplist = mp->dmai_object.dmao_obj.virt_obj.v_priv; 459 DBG(DBG_DMA_MAP, dip, "shadow pplist=%p, %x pages, pfns=", 460 pplist, npages); 461 for (i = 1; i < npages; i++) { 462 px_iopfn_t pfn = page_pptonum(pplist[i]); 463 PX_SET_MP_PFN1(mp, i, pfn); 464 DBG(DBG_DMA_MAP|DBG_CONT, dip, "%x ", pfn); 465 } 466 DBG(DBG_DMA_MAP|DBG_CONT, dip, "\n"); 467 } 468 break; 469 470 case DMA_OTYP_PAGES: { 471 page_t *pp = mp->dmai_object.dmao_obj.pp_obj.pp_pp->p_next; 472 DBG(DBG_DMA_MAP, dip, "pp=%p pfns=", pp); 473 for (i = 1; i < npages; i++, pp = pp->p_next) { 474 px_iopfn_t pfn = page_pptonum(pp); 475 PX_SET_MP_PFN1(mp, i, pfn); 476 DBG(DBG_DMA_MAP|DBG_CONT, dip, "%x ", pfn); 477 } 478 DBG(DBG_DMA_MAP|DBG_CONT, dip, "\n"); 479 } 480 break; 481 482 default: /* check is already done by px_dma_type */ 483 ASSERT(0); 484 break; 485 } 486 return (DDI_SUCCESS); 487 } 488 489 /* 490 * px_dma_vapfn - set up pfnlst array according to VA 491 * VA/size pair: <normal, bypass, peer-to-peer> 492 * pfn0 is skipped as it is already done. 493 * In this case, the cached pfn0 is used to fill pfnlst[0] 494 */ 495 static int 496 px_dma_vapfn(px_t *px_p, ddi_dma_impl_t *mp, uint_t npages) 497 { 498 dev_info_t *dip = px_p->px_dip; 499 int i; 500 caddr_t vaddr = (caddr_t)mp->dmai_object.dmao_obj.virt_obj.v_as; 501 struct hat *hat_p = vaddr ? ((struct as *)vaddr)->a_hat : kas.a_hat; 502 503 vaddr = mp->dmai_object.dmao_obj.virt_obj.v_addr + MMU_PAGE_SIZE; 504 for (i = 1; i < npages; i++, vaddr += MMU_PAGE_SIZE) { 505 px_iopfn_t pfn = hat_getpfnum(hat_p, vaddr); 506 if (pfn == PFN_INVALID) 507 goto err_badpfn; 508 PX_SET_MP_PFN1(mp, i, pfn); 509 DBG(DBG_DMA_BINDH, dip, "px_dma_vapfn: mp=%p pfnlst[%x]=%x\n", 510 mp, i, pfn); 511 } 512 return (DDI_SUCCESS); 513 err_badpfn: 514 cmn_err(CE_WARN, "%s%d: bad page frame vaddr=%p", NAMEINST(dip), vaddr); 515 return (DDI_DMA_NOMAPPING); 516 } 517 518 /* 519 * px_dma_pfn - Fills pfn list for all pages being DMA-ed. 520 * 521 * dependencies: 522 * mp->dmai_ndvmapages - set to total # of dma pages 523 * 524 * return value: 525 * DDI_SUCCESS 526 * DDI_DMA_NOMAPPING 527 */ 528 int 529 px_dma_pfn(px_t *px_p, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp) 530 { 531 uint32_t npages = mp->dmai_ndvmapages; 532 int (*waitfp)(caddr_t) = dmareq->dmar_fp; 533 int i, ret, peer = PX_DMA_ISPTP(mp); 534 int peer32 = PX_DMA_ISPTP32(mp); 535 dev_info_t *dip = px_p->px_dip; 536 537 px_pec_t *pec_p = px_p->px_pec_p; 538 px_iopfn_t pfn_base = peer32 ? pec_p->pec_base32_pfn : 539 pec_p->pec_base64_pfn; 540 px_iopfn_t pfn_last = peer32 ? pec_p->pec_last32_pfn : 541 pec_p->pec_last64_pfn; 542 px_iopfn_t pfn_adj = peer ? pfn_base : 0; 543 544 DBG(DBG_DMA_BINDH, dip, "px_dma_pfn: mp=%p pfn0=%x\n", 545 mp, PX_MP_PFN0(mp) - pfn_adj); 546 /* 1 page: no array alloc/fill, no mixed mode check */ 547 if (npages == 1) { 548 PX_SET_MP_PFN(mp, 0, PX_MP_PFN0(mp) - pfn_adj); 549 return (DDI_SUCCESS); 550 } 551 /* allocate pfn array */ 552 if (!(mp->dmai_pfnlst = kmem_alloc(npages * sizeof (px_iopfn_t), 553 waitfp == DDI_DMA_SLEEP ? KM_SLEEP : KM_NOSLEEP))) { 554 if (waitfp != DDI_DMA_DONTWAIT) 555 ddi_set_callback(waitfp, dmareq->dmar_arg, 556 &px_kmem_clid); 557 return (DDI_DMA_NORESOURCES); 558 } 559 /* fill pfn array */ 560 PX_SET_MP_PFN(mp, 0, PX_MP_PFN0(mp) - pfn_adj); /* pfnlst[0] */ 561 if ((ret = PX_DMA_ISPGPFN(mp) ? px_dma_pgpfn(px_p, mp, npages) : 562 px_dma_vapfn(px_p, mp, npages)) != DDI_SUCCESS) 563 goto err; 564 565 /* skip pfn0, check mixed mode and adjust peer to peer pfn */ 566 for (i = 1; i < npages; i++) { 567 px_iopfn_t pfn = PX_GET_MP_PFN1(mp, i); 568 if (peer ^ TGT_PFN_INBETWEEN(pfn, pfn_base, pfn_last)) { 569 cmn_err(CE_WARN, "%s%d mixed mode DMA %lx %lx", 570 NAMEINST(mp->dmai_rdip), PX_MP_PFN0(mp), pfn); 571 ret = DDI_DMA_NOMAPPING; /* mixed mode */ 572 goto err; 573 } 574 DBG(DBG_DMA_MAP, dip, 575 "px_dma_pfn: pfnlst[%x]=%x-%x\n", i, pfn, pfn_adj); 576 if (pfn_adj) 577 PX_SET_MP_PFN1(mp, i, pfn - pfn_adj); 578 } 579 return (DDI_SUCCESS); 580 err: 581 px_dma_freepfn(mp); 582 return (ret); 583 } 584 585 /* 586 * px_dvma_win() - trim requested DVMA size down to window size 587 * The 1st window starts from offset and ends at page-aligned boundary. 588 * From the 2nd window on, each window starts and ends at page-aligned 589 * boundary except the last window ends at wherever requested. 590 * 591 * accesses the following mp-> members: 592 * mp->dmai_attr.dma_attr_count_max 593 * mp->dmai_attr.dma_attr_seg 594 * mp->dmai_roffset - start offset of 1st window 595 * mp->dmai_rflags (redzone) 596 * mp->dmai_ndvmapages (for 1 page fast path) 597 * 598 * sets the following mp-> members: 599 * mp->dmai_size - xfer size, != winsize if 1st/last win (not fixed) 600 * mp->dmai_winsize - window size (no redzone), n * page size (fixed) 601 * mp->dmai_nwin - # of DMA windows of entire object (fixed) 602 * mp->dmai_rflags - remove partial flag if nwin == 1 (fixed) 603 * mp->dmai_winlst - NULL, window objects not used for DVMA (fixed) 604 * 605 * fixed - not changed across different DMA windows 606 */ 607 /*ARGSUSED*/ 608 int 609 px_dvma_win(px_t *px_p, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp) 610 { 611 uint32_t redzone_sz = PX_HAS_REDZONE(mp) ? MMU_PAGE_SIZE : 0; 612 size_t obj_sz = mp->dmai_object.dmao_size; 613 size_t xfer_sz; 614 ulong_t pg_off; 615 616 if ((mp->dmai_ndvmapages == 1) && !redzone_sz) { 617 mp->dmai_rflags &= ~DDI_DMA_PARTIAL; 618 mp->dmai_size = obj_sz; 619 mp->dmai_winsize = MMU_PAGE_SIZE; 620 mp->dmai_nwin = 1; 621 goto done; 622 } 623 624 pg_off = mp->dmai_roffset; 625 xfer_sz = obj_sz + redzone_sz; 626 627 /* include redzone in nocross check */ { 628 uint64_t nocross = mp->dmai_attr.dma_attr_seg; 629 if (xfer_sz + pg_off - 1 > nocross) 630 xfer_sz = nocross - pg_off + 1; 631 if (redzone_sz && (xfer_sz <= redzone_sz)) { 632 DBG(DBG_DMA_MAP, px_p->px_dip, 633 "nocross too small: " 634 "%lx(%lx)+%lx+%lx < %llx\n", 635 xfer_sz, obj_sz, pg_off, redzone_sz, nocross); 636 return (DDI_DMA_TOOBIG); 637 } 638 } 639 xfer_sz -= redzone_sz; /* restore transfer size */ 640 /* check counter max */ { 641 uint32_t count_max = mp->dmai_attr.dma_attr_count_max; 642 if (xfer_sz - 1 > count_max) 643 xfer_sz = count_max + 1; 644 } 645 if (xfer_sz >= obj_sz) { 646 mp->dmai_rflags &= ~DDI_DMA_PARTIAL; 647 mp->dmai_size = xfer_sz; 648 mp->dmai_winsize = P2ROUNDUP(xfer_sz + pg_off, MMU_PAGE_SIZE); 649 mp->dmai_nwin = 1; 650 goto done; 651 } 652 if (!(dmareq->dmar_flags & DDI_DMA_PARTIAL)) { 653 DBG(DBG_DMA_MAP, px_p->px_dip, "too big: %lx+%lx+%lx > %lx\n", 654 obj_sz, pg_off, redzone_sz, xfer_sz); 655 return (DDI_DMA_TOOBIG); 656 } 657 658 xfer_sz = MMU_PTOB(MMU_BTOP(xfer_sz + pg_off)); /* page align */ 659 mp->dmai_size = xfer_sz - pg_off; /* 1st window xferrable size */ 660 mp->dmai_winsize = xfer_sz; /* redzone not in winsize */ 661 mp->dmai_nwin = (obj_sz + pg_off + xfer_sz - 1) / xfer_sz; 662 done: 663 mp->dmai_winlst = NULL; 664 px_dump_dma_handle(DBG_DMA_MAP, px_p->px_dip, mp); 665 return (DDI_SUCCESS); 666 } 667 668 /* 669 * fast track cache entry to mmu context, inserts 3 0 bits between 670 * upper 6-bits and lower 3-bits of the 9-bit cache entry 671 */ 672 #define MMU_FCE_TO_CTX(i) (((i) << 3) | ((i) & 0x7) | 0x38) 673 674 /* 675 * px_dvma_map_fast - attempts to map fast trackable DVMA 676 */ 677 /*ARGSUSED*/ 678 int 679 px_dvma_map_fast(px_mmu_t *mmu_p, ddi_dma_impl_t *mp) 680 { 681 uint_t clustsz = px_dvma_page_cache_clustsz; 682 uint_t entries = px_dvma_page_cache_entries; 683 io_attributes_t attr = PX_GET_TTE_ATTR(mp->dmai_rflags, 684 mp->dmai_attr.dma_attr_flags); 685 int i = mmu_p->mmu_dvma_addr_scan_start; 686 uint8_t *lock_addr = mmu_p->mmu_dvma_cache_locks + i; 687 px_dvma_addr_t dvma_pg; 688 size_t npages = MMU_BTOP(mp->dmai_winsize); 689 dev_info_t *dip = mmu_p->mmu_px_p->px_dip; 690 691 extern uint8_t ldstub(uint8_t *); 692 ASSERT(MMU_PTOB(npages) == mp->dmai_winsize); 693 ASSERT(npages + PX_HAS_REDZONE(mp) <= clustsz); 694 695 for (; i < entries && ldstub(lock_addr); i++, lock_addr++); 696 if (i >= entries) { 697 lock_addr = mmu_p->mmu_dvma_cache_locks; 698 i = 0; 699 for (; i < entries && ldstub(lock_addr); i++, lock_addr++); 700 if (i >= entries) { 701 #ifdef PX_DMA_PROF 702 px_dvmaft_exhaust++; 703 #endif /* PX_DMA_PROF */ 704 return (DDI_DMA_NORESOURCES); 705 } 706 } 707 mmu_p->mmu_dvma_addr_scan_start = (i + 1) & (entries - 1); 708 709 i *= clustsz; 710 dvma_pg = mmu_p->dvma_base_pg + i; 711 712 if (px_lib_iommu_map(dip, PCI_TSBID(0, i), npages, attr, 713 (void *)mp, 0, MMU_MAP_PFN) != DDI_SUCCESS) { 714 DBG(DBG_MAP_WIN, dip, "px_dvma_map_fast: " 715 "px_lib_iommu_map failed\n"); 716 717 return (DDI_FAILURE); 718 } 719 720 if (!PX_MAP_BUFZONE(mp)) 721 goto done; 722 723 DBG(DBG_MAP_WIN, dip, "px_dvma_map_fast: redzone pg=%x\n", i + npages); 724 725 ASSERT(PX_HAS_REDZONE(mp)); 726 727 if (px_lib_iommu_map(dip, PCI_TSBID(0, i + npages), 1, attr, 728 (void *)mp, npages - 1, MMU_MAP_PFN) != DDI_SUCCESS) { 729 DBG(DBG_MAP_WIN, dip, "px_dvma_map_fast: " 730 "mapping REDZONE page failed\n"); 731 732 (void) px_lib_iommu_demap(dip, PCI_TSBID(0, i), npages); 733 return (DDI_FAILURE); 734 } 735 736 done: 737 #ifdef PX_DMA_PROF 738 px_dvmaft_success++; 739 #endif 740 mp->dmai_mapping = mp->dmai_roffset | MMU_PTOB(dvma_pg); 741 mp->dmai_offset = 0; 742 mp->dmai_flags |= PX_DMAI_FLAGS_FASTTRACK; 743 PX_SAVE_MP_TTE(mp, attr); /* save TTE template for unmapping */ 744 if (PX_DVMA_DBG_ON(mmu_p)) 745 px_dvma_alloc_debug(mmu_p, (char *)mp->dmai_mapping, 746 mp->dmai_size, mp); 747 return (DDI_SUCCESS); 748 } 749 750 /* 751 * px_dvma_map: map non-fasttrack DMA 752 * Use quantum cache if single page DMA. 753 */ 754 int 755 px_dvma_map(ddi_dma_impl_t *mp, ddi_dma_req_t *dmareq, px_mmu_t *mmu_p) 756 { 757 uint_t npages = PX_DMA_WINNPGS(mp); 758 px_dvma_addr_t dvma_pg, dvma_pg_index; 759 void *dvma_addr; 760 uint64_t tte = PX_GET_TTE_ATTR(mp->dmai_rflags, 761 mp->dmai_attr.dma_attr_flags); 762 int sleep = dmareq->dmar_fp == DDI_DMA_SLEEP ? VM_SLEEP : VM_NOSLEEP; 763 dev_info_t *dip = mp->dmai_rdip; 764 int ret = DDI_SUCCESS; 765 766 /* 767 * allocate dvma space resource and map in the first window. 768 * (vmem_t *vmp, size_t size, 769 * size_t align, size_t phase, size_t nocross, 770 * void *minaddr, void *maxaddr, int vmflag) 771 */ 772 if ((npages == 1) && !PX_HAS_REDZONE(mp) && PX_HAS_NOSYSLIMIT(mp)) { 773 dvma_addr = vmem_alloc(mmu_p->mmu_dvma_map, 774 MMU_PAGE_SIZE, sleep); 775 mp->dmai_flags |= PX_DMAI_FLAGS_VMEMCACHE; 776 #ifdef PX_DMA_PROF 777 px_dvma_vmem_alloc++; 778 #endif /* PX_DMA_PROF */ 779 } else { 780 dvma_addr = vmem_xalloc(mmu_p->mmu_dvma_map, 781 MMU_PTOB(npages + PX_HAS_REDZONE(mp)), 782 MAX(mp->dmai_attr.dma_attr_align, MMU_PAGE_SIZE), 783 0, 784 mp->dmai_attr.dma_attr_seg + 1, 785 (void *)mp->dmai_attr.dma_attr_addr_lo, 786 (void *)(mp->dmai_attr.dma_attr_addr_hi + 1), 787 sleep); 788 #ifdef PX_DMA_PROF 789 px_dvma_vmem_xalloc++; 790 #endif /* PX_DMA_PROF */ 791 } 792 dvma_pg = MMU_BTOP((ulong_t)dvma_addr); 793 dvma_pg_index = dvma_pg - mmu_p->dvma_base_pg; 794 DBG(DBG_DMA_MAP, dip, "fallback dvma_pages: dvma_pg=%x index=%x\n", 795 dvma_pg, dvma_pg_index); 796 if (dvma_pg == 0) 797 goto noresource; 798 799 mp->dmai_mapping = mp->dmai_roffset | MMU_PTOB(dvma_pg); 800 mp->dmai_offset = 0; 801 PX_SAVE_MP_TTE(mp, tte); /* mp->dmai_tte = tte */ 802 803 if ((ret = px_mmu_map_pages(mmu_p, 804 mp, dvma_pg, npages, 0)) != DDI_SUCCESS) { 805 if (mp->dmai_flags & PX_DMAI_FLAGS_VMEMCACHE) { 806 vmem_free(mmu_p->mmu_dvma_map, (void *)dvma_addr, 807 MMU_PAGE_SIZE); 808 #ifdef PX_DMA_PROF 809 px_dvma_vmem_free++; 810 #endif /* PX_DMA_PROF */ 811 } else { 812 vmem_xfree(mmu_p->mmu_dvma_map, (void *)dvma_addr, 813 MMU_PTOB(npages + PX_HAS_REDZONE(mp))); 814 #ifdef PX_DMA_PROF 815 px_dvma_vmem_xfree++; 816 #endif /* PX_DMA_PROF */ 817 } 818 } 819 820 return (ret); 821 noresource: 822 if (dmareq->dmar_fp != DDI_DMA_DONTWAIT) { 823 DBG(DBG_DMA_MAP, dip, "dvma_pg 0 - set callback\n"); 824 ddi_set_callback(dmareq->dmar_fp, dmareq->dmar_arg, 825 &mmu_p->mmu_dvma_clid); 826 } 827 DBG(DBG_DMA_MAP, dip, "vmem_xalloc - DDI_DMA_NORESOURCES\n"); 828 return (DDI_DMA_NORESOURCES); 829 } 830 831 void 832 px_dvma_unmap(px_mmu_t *mmu_p, ddi_dma_impl_t *mp) 833 { 834 px_dvma_addr_t dvma_addr = (px_dvma_addr_t)mp->dmai_mapping; 835 px_dvma_addr_t dvma_pg = MMU_BTOP(dvma_addr); 836 dvma_addr = MMU_PTOB(dvma_pg); 837 838 if (mp->dmai_flags & PX_DMAI_FLAGS_FASTTRACK) { 839 px_iopfn_t index = dvma_pg - mmu_p->dvma_base_pg; 840 ASSERT(index % px_dvma_page_cache_clustsz == 0); 841 index /= px_dvma_page_cache_clustsz; 842 ASSERT(index < px_dvma_page_cache_entries); 843 mmu_p->mmu_dvma_cache_locks[index] = 0; 844 #ifdef PX_DMA_PROF 845 px_dvmaft_free++; 846 #endif /* PX_DMA_PROF */ 847 return; 848 } 849 850 if (mp->dmai_flags & PX_DMAI_FLAGS_VMEMCACHE) { 851 vmem_free(mmu_p->mmu_dvma_map, (void *)dvma_addr, 852 MMU_PAGE_SIZE); 853 #ifdef PX_DMA_PROF 854 px_dvma_vmem_free++; 855 #endif /* PX_DMA_PROF */ 856 } else { 857 size_t npages = MMU_BTOP(mp->dmai_winsize) + PX_HAS_REDZONE(mp); 858 vmem_xfree(mmu_p->mmu_dvma_map, (void *)dvma_addr, 859 MMU_PTOB(npages)); 860 #ifdef PX_DMA_PROF 861 px_dvma_vmem_xfree++; 862 #endif /* PX_DMA_PROF */ 863 } 864 } 865 866 /* 867 * DVMA mappings may have multiple windows, but each window always have 868 * one segment. 869 */ 870 int 871 px_dvma_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_impl_t *mp, 872 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 873 uint_t cache_flags) 874 { 875 switch (cmd) { 876 case DDI_DMA_SYNC: 877 return (px_lib_dma_sync(dip, rdip, (ddi_dma_handle_t)mp, 878 *offp, *lenp, cache_flags)); 879 880 case DDI_DMA_HTOC: { 881 int ret; 882 off_t wo_off, off = *offp; /* wo_off: wnd's obj offset */ 883 uint_t win_size = mp->dmai_winsize; 884 ddi_dma_cookie_t *cp = (ddi_dma_cookie_t *)objp; 885 886 if (off >= mp->dmai_object.dmao_size) { 887 cmn_err(CE_WARN, "%s%d invalid dma_htoc offset %lx", 888 NAMEINST(mp->dmai_rdip), off); 889 return (DDI_FAILURE); 890 } 891 off += mp->dmai_roffset; 892 ret = px_dma_win(dip, rdip, (ddi_dma_handle_t)mp, 893 off / win_size, &wo_off, NULL, cp, NULL); /* lenp == NULL */ 894 if (ret) 895 return (ret); 896 DBG(DBG_DMA_CTL, dip, "HTOC:cookie=%x+%lx off=%lx,%lx\n", 897 cp->dmac_address, cp->dmac_size, off, *offp); 898 899 /* adjust cookie addr/len if we are not on window boundary */ 900 ASSERT((off % win_size) == (off - 901 (PX_DMA_CURWIN(mp) ? mp->dmai_roffset : 0) - wo_off)); 902 off = PX_DMA_CURWIN(mp) ? off % win_size : *offp; 903 ASSERT(cp->dmac_size > off); 904 cp->dmac_laddress += off; 905 cp->dmac_size -= off; 906 DBG(DBG_DMA_CTL, dip, "HTOC:mp=%p cookie=%x+%lx off=%lx,%lx\n", 907 mp, cp->dmac_address, cp->dmac_size, off, wo_off); 908 } 909 return (DDI_SUCCESS); 910 911 case DDI_DMA_REPWIN: 912 *offp = mp->dmai_offset; 913 *lenp = mp->dmai_size; 914 return (DDI_SUCCESS); 915 916 case DDI_DMA_MOVWIN: { 917 off_t off = *offp; 918 if (off >= mp->dmai_object.dmao_size) 919 return (DDI_FAILURE); 920 off += mp->dmai_roffset; 921 return (px_dma_win(dip, rdip, (ddi_dma_handle_t)mp, 922 off / mp->dmai_winsize, offp, lenp, 923 (ddi_dma_cookie_t *)objp, NULL)); 924 } 925 926 case DDI_DMA_NEXTWIN: { 927 px_window_t win = PX_DMA_CURWIN(mp); 928 if (offp) { 929 if (*(px_window_t *)offp != win) { 930 /* window not active */ 931 *(px_window_t *)objp = win; /* return cur win */ 932 return (DDI_DMA_STALE); 933 } 934 win++; 935 } else /* map win 0 */ 936 win = 0; 937 if (win >= mp->dmai_nwin) { 938 *(px_window_t *)objp = win - 1; 939 return (DDI_DMA_DONE); 940 } 941 if (px_dma_win(dip, rdip, (ddi_dma_handle_t)mp, 942 win, 0, 0, 0, 0)) { 943 *(px_window_t *)objp = win - 1; 944 return (DDI_FAILURE); 945 } 946 *(px_window_t *)objp = win; 947 } 948 return (DDI_SUCCESS); 949 950 case DDI_DMA_NEXTSEG: 951 if (*(px_window_t *)offp != PX_DMA_CURWIN(mp)) 952 return (DDI_DMA_STALE); 953 if (lenp) /* only 1 seg allowed */ 954 return (DDI_DMA_DONE); 955 956 /* return mp as seg 0 */ 957 *(ddi_dma_seg_t *)objp = (ddi_dma_seg_t)mp; 958 return (DDI_SUCCESS); 959 960 case DDI_DMA_SEGTOC: 961 MAKE_DMA_COOKIE((ddi_dma_cookie_t *)objp, mp->dmai_mapping, 962 mp->dmai_size); 963 *offp = mp->dmai_offset; 964 *lenp = mp->dmai_size; 965 return (DDI_SUCCESS); 966 967 case DDI_DMA_COFF: { 968 ddi_dma_cookie_t *cp = (ddi_dma_cookie_t *)offp; 969 if (cp->dmac_address < mp->dmai_mapping || 970 (cp->dmac_address + cp->dmac_size) > 971 (mp->dmai_mapping + mp->dmai_size)) 972 return (DDI_FAILURE); 973 *objp = (caddr_t)(cp->dmac_address - mp->dmai_mapping + 974 mp->dmai_offset); 975 } 976 return (DDI_SUCCESS); 977 default: 978 DBG(DBG_DMA_CTL, dip, "unknown command (%x): rdip=%s%d\n", 979 cmd, ddi_driver_name(rdip), ddi_get_instance(rdip)); 980 break; 981 } 982 return (DDI_FAILURE); 983 } 984 985 void 986 px_dma_freewin(ddi_dma_impl_t *mp) 987 { 988 px_dma_win_t *win_p = mp->dmai_winlst, *win2_p; 989 for (win2_p = win_p; win_p; win2_p = win_p) { 990 win_p = win2_p->win_next; 991 kmem_free(win2_p, sizeof (px_dma_win_t) + 992 sizeof (ddi_dma_cookie_t) * win2_p->win_ncookies); 993 } 994 mp->dmai_nwin = 0; 995 mp->dmai_winlst = NULL; 996 } 997 998 /* 999 * px_dma_newwin - create a dma window object and cookies 1000 * 1001 * After the initial scan in px_dma_physwin(), which identifies 1002 * a portion of the pfn array that belongs to a dma window, 1003 * we are called to allocate and initialize representing memory 1004 * resources. We know from the 1st scan the number of cookies 1005 * or dma segment in this window so we can allocate a contiguous 1006 * memory array for the dma cookies (The implementation of 1007 * ddi_dma_nextcookie(9f) dictates dma cookies be contiguous). 1008 * 1009 * A second round scan is done on the pfn array to identify 1010 * each dma segment and initialize its corresponding dma cookie. 1011 * We don't need to do all the safety checking and we know they 1012 * all belong to the same dma window. 1013 * 1014 * Input: cookie_no - # of cookies identified by the 1st scan 1015 * start_idx - subscript of the pfn array for the starting pfn 1016 * end_idx - subscript of the last pfn in dma window 1017 * win_pp - pointer to win_next member of previous window 1018 * Return: DDI_SUCCESS - with **win_pp as newly created window object 1019 * DDI_DMA_NORESROUCE - caller frees all previous window objs 1020 * Note: Each cookie and window size are all initialized on page 1021 * boundary. This is not true for the 1st cookie of the 1st 1022 * window and the last cookie of the last window. 1023 * We fix that later in upper layer which has access to size 1024 * and offset info. 1025 * 1026 */ 1027 /*ARGSUSED*/ 1028 static int 1029 px_dma_newwin(dev_info_t *dip, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp, 1030 uint32_t cookie_no, uint32_t start_idx, uint32_t end_idx, 1031 px_dma_win_t **win_pp, uint64_t count_max, uint64_t bypass) 1032 { 1033 int (*waitfp)(caddr_t) = dmareq->dmar_fp; 1034 ddi_dma_cookie_t *cookie_p; 1035 uint32_t pfn_no = 1; 1036 px_iopfn_t pfn = PX_GET_MP_PFN(mp, start_idx); 1037 px_iopfn_t prev_pfn = pfn; 1038 uint64_t baddr, seg_pfn0 = pfn; 1039 size_t sz = cookie_no * sizeof (ddi_dma_cookie_t); 1040 px_dma_win_t *win_p = kmem_zalloc(sizeof (px_dma_win_t) + sz, 1041 waitfp == DDI_DMA_SLEEP ? KM_SLEEP : KM_NOSLEEP); 1042 io_attributes_t attr = PX_GET_TTE_ATTR(mp->dmai_rflags, 1043 mp->dmai_attr.dma_attr_flags); 1044 1045 if (!win_p) 1046 goto noresource; 1047 1048 win_p->win_next = NULL; 1049 win_p->win_ncookies = cookie_no; 1050 win_p->win_curseg = 0; /* start from segment 0 */ 1051 win_p->win_size = MMU_PTOB(end_idx - start_idx + 1); 1052 /* win_p->win_offset is left uninitialized */ 1053 1054 cookie_p = (ddi_dma_cookie_t *)(win_p + 1); 1055 start_idx++; 1056 for (; start_idx <= end_idx; start_idx++, prev_pfn = pfn, pfn_no++) { 1057 pfn = PX_GET_MP_PFN1(mp, start_idx); 1058 if ((pfn == prev_pfn + 1) && 1059 (MMU_PTOB(pfn_no + 1) - 1 <= count_max)) 1060 continue; 1061 1062 /* close up the cookie up to (including) prev_pfn */ 1063 baddr = MMU_PTOB(seg_pfn0); 1064 if (bypass && (px_lib_iommu_getbypass(dip, 1065 baddr, attr, &baddr) != DDI_SUCCESS)) 1066 return (DDI_FAILURE); 1067 1068 MAKE_DMA_COOKIE(cookie_p, baddr, MMU_PTOB(pfn_no)); 1069 DBG(DBG_BYPASS, mp->dmai_rdip, "cookie %p (%x pages)\n", 1070 MMU_PTOB(seg_pfn0), pfn_no); 1071 1072 cookie_p++; /* advance to next available cookie cell */ 1073 pfn_no = 0; 1074 seg_pfn0 = pfn; /* start a new segment from current pfn */ 1075 } 1076 1077 baddr = MMU_PTOB(seg_pfn0); 1078 if (bypass && (px_lib_iommu_getbypass(dip, 1079 baddr, attr, &baddr) != DDI_SUCCESS)) 1080 return (DDI_FAILURE); 1081 1082 MAKE_DMA_COOKIE(cookie_p, baddr, MMU_PTOB(pfn_no)); 1083 DBG(DBG_BYPASS, mp->dmai_rdip, "cookie %p (%x pages) of total %x\n", 1084 MMU_PTOB(seg_pfn0), pfn_no, cookie_no); 1085 #ifdef DEBUG 1086 cookie_p++; 1087 ASSERT((cookie_p - (ddi_dma_cookie_t *)(win_p + 1)) == cookie_no); 1088 #endif /* DEBUG */ 1089 *win_pp = win_p; 1090 return (DDI_SUCCESS); 1091 noresource: 1092 if (waitfp != DDI_DMA_DONTWAIT) 1093 ddi_set_callback(waitfp, dmareq->dmar_arg, &px_kmem_clid); 1094 return (DDI_DMA_NORESOURCES); 1095 } 1096 1097 /* 1098 * px_dma_adjust - adjust 1st and last cookie and window sizes 1099 * remove initial dma page offset from 1st cookie and window size 1100 * remove last dma page remainder from last cookie and window size 1101 * fill win_offset of each dma window according to just fixed up 1102 * each window sizes 1103 * px_dma_win_t members modified: 1104 * win_p->win_offset - this window's offset within entire DMA object 1105 * win_p->win_size - xferrable size (in bytes) for this window 1106 * 1107 * ddi_dma_impl_t members modified: 1108 * mp->dmai_size - 1st window xferrable size 1109 * mp->dmai_offset - 0, which is the dma offset of the 1st window 1110 * 1111 * ddi_dma_cookie_t members modified: 1112 * cookie_p->dmac_size - 1st and last cookie remove offset or remainder 1113 * cookie_p->dmac_laddress - 1st cookie add page offset 1114 */ 1115 static void 1116 px_dma_adjust(ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp, px_dma_win_t *win_p) 1117 { 1118 ddi_dma_cookie_t *cookie_p = (ddi_dma_cookie_t *)(win_p + 1); 1119 size_t pg_offset = mp->dmai_roffset; 1120 size_t win_offset = 0; 1121 1122 cookie_p->dmac_size -= pg_offset; 1123 cookie_p->dmac_laddress |= pg_offset; 1124 win_p->win_size -= pg_offset; 1125 DBG(DBG_BYPASS, mp->dmai_rdip, "pg0 adjust %lx\n", pg_offset); 1126 1127 mp->dmai_size = win_p->win_size; 1128 mp->dmai_offset = 0; 1129 1130 pg_offset += mp->dmai_object.dmao_size; 1131 pg_offset &= MMU_PAGE_OFFSET; 1132 if (pg_offset) 1133 pg_offset = MMU_PAGE_SIZE - pg_offset; 1134 DBG(DBG_BYPASS, mp->dmai_rdip, "last pg adjust %lx\n", pg_offset); 1135 1136 for (; win_p->win_next; win_p = win_p->win_next) { 1137 DBG(DBG_BYPASS, mp->dmai_rdip, "win off %p\n", win_offset); 1138 win_p->win_offset = win_offset; 1139 win_offset += win_p->win_size; 1140 } 1141 /* last window */ 1142 win_p->win_offset = win_offset; 1143 cookie_p = (ddi_dma_cookie_t *)(win_p + 1); 1144 cookie_p[win_p->win_ncookies - 1].dmac_size -= pg_offset; 1145 win_p->win_size -= pg_offset; 1146 ASSERT((win_offset + win_p->win_size) == mp->dmai_object.dmao_size); 1147 } 1148 1149 /* 1150 * px_dma_physwin() - carve up dma windows using physical addresses. 1151 * Called to handle mmu bypass and pci peer-to-peer transfers. 1152 * Calls px_dma_newwin() to allocate window objects. 1153 * 1154 * Dependency: mp->dmai_pfnlst points to an array of pfns 1155 * 1156 * 1. Each dma window is represented by a px_dma_win_t object. 1157 * The object will be casted to ddi_dma_win_t and returned 1158 * to leaf driver through the DDI interface. 1159 * 2. Each dma window can have several dma segments with each 1160 * segment representing a physically contiguous either memory 1161 * space (if we are doing an mmu bypass transfer) or pci address 1162 * space (if we are doing a peer-to-peer transfer). 1163 * 3. Each segment has a DMA cookie to program the DMA engine. 1164 * The cookies within each DMA window must be located in a 1165 * contiguous array per ddi_dma_nextcookie(9f). 1166 * 4. The number of DMA segments within each DMA window cannot exceed 1167 * mp->dmai_attr.dma_attr_sgllen. If the transfer size is 1168 * too large to fit in the sgllen, the rest needs to be 1169 * relocated to the next dma window. 1170 * 5. Peer-to-peer DMA segment follows device hi, lo, count_max, 1171 * and nocross restrictions while bypass DMA follows the set of 1172 * restrictions with system limits factored in. 1173 * 1174 * Return: 1175 * mp->dmai_winlst - points to a link list of px_dma_win_t objects. 1176 * Each px_dma_win_t object on the link list contains 1177 * infomation such as its window size (# of pages), 1178 * starting offset (also see Restriction), an array of 1179 * DMA cookies, and # of cookies in the array. 1180 * mp->dmai_pfnlst - NULL, the pfn list is freed to conserve memory. 1181 * mp->dmai_nwin - # of total DMA windows on mp->dmai_winlst. 1182 * mp->dmai_mapping - starting cookie address 1183 * mp->dmai_rflags - consistent, nosync, no redzone 1184 * mp->dmai_cookie - start of cookie table of the 1st DMA window 1185 * 1186 * Restriction: 1187 * Each px_dma_win_t object can theoratically start from any offset 1188 * since the mmu is not involved. However, this implementation 1189 * always make windows start from page aligned offset (except 1190 * the 1st window, which follows the requested offset) due to the 1191 * fact that we are handed a pfn list. This does require device's 1192 * count_max and attr_seg to be at least MMU_PAGE_SIZE aligned. 1193 */ 1194 int 1195 px_dma_physwin(px_t *px_p, ddi_dma_req_t *dmareq, ddi_dma_impl_t *mp) 1196 { 1197 uint_t npages = mp->dmai_ndvmapages; 1198 int ret, sgllen = mp->dmai_attr.dma_attr_sgllen; 1199 px_iopfn_t pfn_lo, pfn_hi, prev_pfn; 1200 px_iopfn_t pfn = PX_GET_MP_PFN(mp, 0); 1201 uint32_t i, win_no = 0, pfn_no = 1, win_pfn0_index = 0, cookie_no = 0; 1202 uint64_t count_max, bypass_addr = 0; 1203 px_dma_win_t **win_pp = (px_dma_win_t **)&mp->dmai_winlst; 1204 ddi_dma_cookie_t *cookie0_p; 1205 io_attributes_t attr = PX_GET_TTE_ATTR(mp->dmai_rflags, 1206 mp->dmai_attr.dma_attr_flags); 1207 dev_info_t *dip = px_p->px_dip; 1208 1209 ASSERT(PX_DMA_ISPTP(mp) || PX_DMA_ISBYPASS(mp)); 1210 if (PX_DMA_ISPTP(mp)) { /* ignore sys limits for peer-to-peer */ 1211 ddi_dma_attr_t *dev_attr_p = PX_DEV_ATTR(mp); 1212 uint64_t nocross = dev_attr_p->dma_attr_seg; 1213 px_pec_t *pec_p = px_p->px_pec_p; 1214 px_iopfn_t pfn_last = PX_DMA_ISPTP32(mp) ? 1215 pec_p->pec_last32_pfn - pec_p->pec_base32_pfn : 1216 pec_p->pec_last64_pfn - pec_p->pec_base64_pfn; 1217 1218 if (nocross && (nocross < UINT32_MAX)) 1219 return (DDI_DMA_NOMAPPING); 1220 if (dev_attr_p->dma_attr_align > MMU_PAGE_SIZE) 1221 return (DDI_DMA_NOMAPPING); 1222 pfn_lo = MMU_BTOP(dev_attr_p->dma_attr_addr_lo); 1223 pfn_hi = MMU_BTOP(dev_attr_p->dma_attr_addr_hi); 1224 pfn_hi = MIN(pfn_hi, pfn_last); 1225 if ((pfn_lo > pfn_hi) || (pfn < pfn_lo)) 1226 return (DDI_DMA_NOMAPPING); 1227 1228 count_max = dev_attr_p->dma_attr_count_max; 1229 count_max = MIN(count_max, nocross); 1230 /* 1231 * the following count_max trim is not done because we are 1232 * making sure pfn_lo <= pfn <= pfn_hi inside the loop 1233 * count_max=MIN(count_max, MMU_PTOB(pfn_hi - pfn_lo + 1)-1); 1234 */ 1235 } else { /* bypass hi/lo/count_max have been processed by attr2hdl() */ 1236 count_max = mp->dmai_attr.dma_attr_count_max; 1237 pfn_lo = MMU_BTOP(mp->dmai_attr.dma_attr_addr_lo); 1238 pfn_hi = MMU_BTOP(mp->dmai_attr.dma_attr_addr_hi); 1239 1240 if (px_lib_iommu_getbypass(dip, MMU_PTOB(pfn), 1241 attr, &bypass_addr) != DDI_SUCCESS) { 1242 cmn_err(CE_WARN, "bypass cookie failure %lx\n", pfn); 1243 return (DDI_DMA_NOMAPPING); 1244 } 1245 pfn = MMU_BTOP(bypass_addr); 1246 } 1247 1248 /* pfn: absolute (bypass mode) or relative (p2p mode) */ 1249 for (prev_pfn = pfn, i = 1; i < npages; 1250 i++, prev_pfn = pfn, pfn_no++) { 1251 pfn = PX_GET_MP_PFN1(mp, i); 1252 if (bypass_addr) { 1253 if (px_lib_iommu_getbypass(dip, MMU_PTOB(pfn), attr, 1254 &bypass_addr) != DDI_SUCCESS) { 1255 ret = DDI_DMA_NOMAPPING; 1256 goto err; 1257 } 1258 pfn = MMU_BTOP(bypass_addr); 1259 } 1260 if ((pfn == prev_pfn + 1) && 1261 (MMU_PTOB(pfn_no + 1) - 1 <= count_max)) 1262 continue; 1263 if ((pfn < pfn_lo) || (prev_pfn > pfn_hi)) { 1264 ret = DDI_DMA_NOMAPPING; 1265 goto err; 1266 } 1267 cookie_no++; 1268 pfn_no = 0; 1269 if (cookie_no < sgllen) 1270 continue; 1271 1272 DBG(DBG_BYPASS, mp->dmai_rdip, "newwin pfn[%x-%x] %x cks\n", 1273 win_pfn0_index, i - 1, cookie_no); 1274 if (ret = px_dma_newwin(dip, dmareq, mp, cookie_no, 1275 win_pfn0_index, i - 1, win_pp, count_max, bypass_addr)) 1276 goto err; 1277 1278 win_pp = &(*win_pp)->win_next; /* win_pp = *(win_pp) */ 1279 win_no++; 1280 win_pfn0_index = i; 1281 cookie_no = 0; 1282 } 1283 if (pfn > pfn_hi) { 1284 ret = DDI_DMA_NOMAPPING; 1285 goto err; 1286 } 1287 cookie_no++; 1288 DBG(DBG_BYPASS, mp->dmai_rdip, "newwin pfn[%x-%x] %x cks\n", 1289 win_pfn0_index, i - 1, cookie_no); 1290 if (ret = px_dma_newwin(dip, dmareq, mp, cookie_no, win_pfn0_index, 1291 i - 1, win_pp, count_max, bypass_addr)) 1292 goto err; 1293 win_no++; 1294 px_dma_adjust(dmareq, mp, mp->dmai_winlst); 1295 mp->dmai_nwin = win_no; 1296 mp->dmai_rflags |= DDI_DMA_CONSISTENT | DMP_NOSYNC; 1297 mp->dmai_rflags &= ~DDI_DMA_REDZONE; 1298 mp->dmai_flags |= PX_DMAI_FLAGS_NOSYNC; 1299 cookie0_p = (ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); 1300 mp->dmai_cookie = PX_WINLST(mp)->win_ncookies > 1 ? cookie0_p + 1 : 0; 1301 mp->dmai_mapping = cookie0_p->dmac_laddress; 1302 1303 px_dma_freepfn(mp); 1304 return (DDI_DMA_MAPPED); 1305 err: 1306 px_dma_freewin(mp); 1307 return (ret); 1308 } 1309 1310 int 1311 px_dma_ctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_impl_t *mp, 1312 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1313 uint_t cache_flags) 1314 { 1315 switch (cmd) { 1316 case DDI_DMA_SYNC: 1317 return (DDI_SUCCESS); 1318 1319 case DDI_DMA_HTOC: { 1320 off_t off = *offp; 1321 ddi_dma_cookie_t *loop_cp, *cp; 1322 px_dma_win_t *win_p = mp->dmai_winlst; 1323 1324 if (off >= mp->dmai_object.dmao_size) 1325 return (DDI_FAILURE); 1326 1327 /* locate window */ 1328 while (win_p->win_offset + win_p->win_size <= off) 1329 win_p = win_p->win_next; 1330 1331 loop_cp = cp = (ddi_dma_cookie_t *)(win_p + 1); 1332 mp->dmai_offset = win_p->win_offset; 1333 mp->dmai_size = win_p->win_size; 1334 mp->dmai_mapping = cp->dmac_laddress; /* cookie0 start addr */ 1335 1336 /* adjust cookie addr/len if we are not on cookie boundary */ 1337 off -= win_p->win_offset; /* offset within window */ 1338 for (; off >= loop_cp->dmac_size; loop_cp++) 1339 off -= loop_cp->dmac_size; /* offset within cookie */ 1340 1341 mp->dmai_cookie = loop_cp + 1; 1342 win_p->win_curseg = loop_cp - cp; 1343 cp = (ddi_dma_cookie_t *)objp; 1344 MAKE_DMA_COOKIE(cp, loop_cp->dmac_laddress + off, 1345 loop_cp->dmac_size - off); 1346 1347 DBG(DBG_DMA_CTL, dip, 1348 "HTOC: cookie - dmac_laddress=%p dmac_size=%x\n", 1349 cp->dmac_laddress, cp->dmac_size); 1350 } 1351 return (DDI_SUCCESS); 1352 1353 case DDI_DMA_REPWIN: 1354 *offp = mp->dmai_offset; 1355 *lenp = mp->dmai_size; 1356 return (DDI_SUCCESS); 1357 1358 case DDI_DMA_MOVWIN: { 1359 off_t off = *offp; 1360 ddi_dma_cookie_t *cp; 1361 px_dma_win_t *win_p = mp->dmai_winlst; 1362 1363 if (off >= mp->dmai_object.dmao_size) 1364 return (DDI_FAILURE); 1365 1366 /* locate window */ 1367 while (win_p->win_offset + win_p->win_size <= off) 1368 win_p = win_p->win_next; 1369 1370 cp = (ddi_dma_cookie_t *)(win_p + 1); 1371 mp->dmai_offset = win_p->win_offset; 1372 mp->dmai_size = win_p->win_size; 1373 mp->dmai_mapping = cp->dmac_laddress; /* cookie0 star addr */ 1374 mp->dmai_cookie = cp + 1; 1375 win_p->win_curseg = 0; 1376 1377 *(ddi_dma_cookie_t *)objp = *cp; 1378 *offp = win_p->win_offset; 1379 *lenp = win_p->win_size; 1380 DBG(DBG_DMA_CTL, dip, 1381 "HTOC: cookie - dmac_laddress=%p dmac_size=%x\n", 1382 cp->dmac_laddress, cp->dmac_size); 1383 } 1384 return (DDI_SUCCESS); 1385 1386 case DDI_DMA_NEXTWIN: { 1387 px_dma_win_t *win_p = *(px_dma_win_t **)offp; 1388 px_dma_win_t **nw_pp = (px_dma_win_t **)objp; 1389 ddi_dma_cookie_t *cp; 1390 if (!win_p) { 1391 *nw_pp = mp->dmai_winlst; 1392 return (DDI_SUCCESS); 1393 } 1394 1395 if (win_p->win_offset != mp->dmai_offset) 1396 return (DDI_DMA_STALE); 1397 if (!win_p->win_next) 1398 return (DDI_DMA_DONE); 1399 win_p = win_p->win_next; 1400 cp = (ddi_dma_cookie_t *)(win_p + 1); 1401 mp->dmai_offset = win_p->win_offset; 1402 mp->dmai_size = win_p->win_size; 1403 mp->dmai_mapping = cp->dmac_laddress; /* cookie0 star addr */ 1404 mp->dmai_cookie = cp + 1; 1405 win_p->win_curseg = 0; 1406 *nw_pp = win_p; 1407 } 1408 return (DDI_SUCCESS); 1409 1410 case DDI_DMA_NEXTSEG: { 1411 px_dma_win_t *w_p = *(px_dma_win_t **)offp; 1412 if (w_p->win_offset != mp->dmai_offset) 1413 return (DDI_DMA_STALE); 1414 if (w_p->win_curseg + 1 >= w_p->win_ncookies) 1415 return (DDI_DMA_DONE); 1416 w_p->win_curseg++; 1417 } 1418 *(ddi_dma_seg_t *)objp = (ddi_dma_seg_t)mp; 1419 return (DDI_SUCCESS); 1420 1421 case DDI_DMA_SEGTOC: { 1422 px_dma_win_t *win_p = mp->dmai_winlst; 1423 off_t off = mp->dmai_offset; 1424 ddi_dma_cookie_t *cp; 1425 int i; 1426 1427 /* locate active window */ 1428 for (; win_p->win_offset != off; win_p = win_p->win_next); 1429 cp = (ddi_dma_cookie_t *)(win_p + 1); 1430 for (i = 0; i < win_p->win_curseg; i++, cp++) 1431 off += cp->dmac_size; 1432 *offp = off; 1433 *lenp = cp->dmac_size; 1434 *(ddi_dma_cookie_t *)objp = *cp; /* copy cookie */ 1435 } 1436 return (DDI_SUCCESS); 1437 1438 case DDI_DMA_COFF: { 1439 px_dma_win_t *win_p; 1440 ddi_dma_cookie_t *cp; 1441 uint64_t addr, key = ((ddi_dma_cookie_t *)offp)->dmac_laddress; 1442 size_t win_off; 1443 1444 for (win_p = mp->dmai_winlst; win_p; win_p = win_p->win_next) { 1445 int i; 1446 win_off = 0; 1447 cp = (ddi_dma_cookie_t *)(win_p + 1); 1448 for (i = 0; i < win_p->win_ncookies; i++, cp++) { 1449 size_t sz = cp->dmac_size; 1450 1451 addr = cp->dmac_laddress; 1452 if ((addr <= key) && (addr + sz >= key)) 1453 goto found; 1454 win_off += sz; 1455 } 1456 } 1457 return (DDI_FAILURE); 1458 found: 1459 *objp = (caddr_t)(win_p->win_offset + win_off + (key - addr)); 1460 return (DDI_SUCCESS); 1461 } 1462 default: 1463 DBG(DBG_DMA_CTL, dip, "unknown command (%x): rdip=%s%d\n", 1464 cmd, ddi_driver_name(rdip), ddi_get_instance(rdip)); 1465 break; 1466 } 1467 return (DDI_FAILURE); 1468 } 1469 1470 static void 1471 px_dvma_debug_init(px_mmu_t *mmu_p) 1472 { 1473 size_t sz = sizeof (struct px_dvma_rec) * px_dvma_debug_rec; 1474 ASSERT(MUTEX_HELD(&mmu_p->dvma_debug_lock)); 1475 cmn_err(CE_NOTE, "PCI Express DVMA %p stat ON", mmu_p); 1476 1477 mmu_p->dvma_alloc_rec = kmem_alloc(sz, KM_SLEEP); 1478 mmu_p->dvma_free_rec = kmem_alloc(sz, KM_SLEEP); 1479 1480 mmu_p->dvma_active_list = NULL; 1481 mmu_p->dvma_alloc_rec_index = 0; 1482 mmu_p->dvma_free_rec_index = 0; 1483 mmu_p->dvma_active_count = 0; 1484 } 1485 1486 void 1487 px_dvma_debug_fini(px_mmu_t *mmu_p) 1488 { 1489 struct px_dvma_rec *prev, *ptr; 1490 size_t sz = sizeof (struct px_dvma_rec) * px_dvma_debug_rec; 1491 uint64_t mask = ~(1ull << mmu_p->mmu_inst); 1492 cmn_err(CE_NOTE, "PCI Express DVMA %p stat OFF", mmu_p); 1493 1494 kmem_free(mmu_p->dvma_alloc_rec, sz); 1495 kmem_free(mmu_p->dvma_free_rec, sz); 1496 mmu_p->dvma_alloc_rec = mmu_p->dvma_free_rec = NULL; 1497 1498 prev = mmu_p->dvma_active_list; 1499 if (!prev) 1500 return; 1501 for (ptr = prev->next; ptr; prev = ptr, ptr = ptr->next) 1502 kmem_free(prev, sizeof (struct px_dvma_rec)); 1503 kmem_free(prev, sizeof (struct px_dvma_rec)); 1504 1505 mmu_p->dvma_active_list = NULL; 1506 mmu_p->dvma_alloc_rec_index = 0; 1507 mmu_p->dvma_free_rec_index = 0; 1508 mmu_p->dvma_active_count = 0; 1509 1510 px_dvma_debug_off &= mask; 1511 px_dvma_debug_on &= mask; 1512 } 1513 1514 void 1515 px_dvma_alloc_debug(px_mmu_t *mmu_p, char *address, uint_t len, 1516 ddi_dma_impl_t *mp) 1517 { 1518 struct px_dvma_rec *ptr; 1519 mutex_enter(&mmu_p->dvma_debug_lock); 1520 1521 if (!mmu_p->dvma_alloc_rec) 1522 px_dvma_debug_init(mmu_p); 1523 if (PX_DVMA_DBG_OFF(mmu_p)) { 1524 px_dvma_debug_fini(mmu_p); 1525 goto done; 1526 } 1527 1528 ptr = &mmu_p->dvma_alloc_rec[mmu_p->dvma_alloc_rec_index]; 1529 ptr->dvma_addr = address; 1530 ptr->len = len; 1531 ptr->mp = mp; 1532 if (++mmu_p->dvma_alloc_rec_index == px_dvma_debug_rec) 1533 mmu_p->dvma_alloc_rec_index = 0; 1534 1535 ptr = kmem_alloc(sizeof (struct px_dvma_rec), KM_SLEEP); 1536 ptr->dvma_addr = address; 1537 ptr->len = len; 1538 ptr->mp = mp; 1539 1540 ptr->next = mmu_p->dvma_active_list; 1541 mmu_p->dvma_active_list = ptr; 1542 mmu_p->dvma_active_count++; 1543 done: 1544 mutex_exit(&mmu_p->dvma_debug_lock); 1545 } 1546 1547 void 1548 px_dvma_free_debug(px_mmu_t *mmu_p, char *address, uint_t len, 1549 ddi_dma_impl_t *mp) 1550 { 1551 struct px_dvma_rec *ptr, *ptr_save; 1552 mutex_enter(&mmu_p->dvma_debug_lock); 1553 1554 if (!mmu_p->dvma_alloc_rec) 1555 px_dvma_debug_init(mmu_p); 1556 if (PX_DVMA_DBG_OFF(mmu_p)) { 1557 px_dvma_debug_fini(mmu_p); 1558 goto done; 1559 } 1560 1561 ptr = &mmu_p->dvma_free_rec[mmu_p->dvma_free_rec_index]; 1562 ptr->dvma_addr = address; 1563 ptr->len = len; 1564 ptr->mp = mp; 1565 if (++mmu_p->dvma_free_rec_index == px_dvma_debug_rec) 1566 mmu_p->dvma_free_rec_index = 0; 1567 1568 ptr_save = mmu_p->dvma_active_list; 1569 for (ptr = ptr_save; ptr; ptr = ptr->next) { 1570 if ((ptr->dvma_addr == address) && (ptr->len = len)) 1571 break; 1572 ptr_save = ptr; 1573 } 1574 if (!ptr) { 1575 cmn_err(CE_WARN, "bad dvma free addr=%lx len=%x", 1576 (long)address, len); 1577 goto done; 1578 } 1579 if (ptr == mmu_p->dvma_active_list) 1580 mmu_p->dvma_active_list = ptr->next; 1581 else 1582 ptr_save->next = ptr->next; 1583 kmem_free(ptr, sizeof (struct px_dvma_rec)); 1584 mmu_p->dvma_active_count--; 1585 done: 1586 mutex_exit(&mmu_p->dvma_debug_lock); 1587 } 1588 1589 #ifdef DEBUG 1590 void 1591 px_dump_dma_handle(uint64_t flag, dev_info_t *dip, ddi_dma_impl_t *hp) 1592 { 1593 DBG(flag, dip, "mp(%p): flags=%x mapping=%lx xfer_size=%x\n", 1594 hp, hp->dmai_inuse, hp->dmai_mapping, hp->dmai_size); 1595 DBG(flag|DBG_CONT, dip, "\tnpages=%x roffset=%x rflags=%x nwin=%x\n", 1596 hp->dmai_ndvmapages, hp->dmai_roffset, hp->dmai_rflags, 1597 hp->dmai_nwin); 1598 DBG(flag|DBG_CONT, dip, "\twinsize=%x tte=%p pfnlst=%p pfn0=%p\n", 1599 hp->dmai_winsize, hp->dmai_tte, hp->dmai_pfnlst, hp->dmai_pfn0); 1600 DBG(flag|DBG_CONT, dip, "\twinlst=%x obj=%p attr=%p ckp=%p\n", 1601 hp->dmai_winlst, &hp->dmai_object, &hp->dmai_attr, 1602 hp->dmai_cookie); 1603 } 1604 #endif /* DEBUG */ 1605