1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI Express nexus driver interface 30 */ 31 32 #include <sys/types.h> 33 #include <sys/conf.h> /* nulldev */ 34 #include <sys/stat.h> /* devctl */ 35 #include <sys/kmem.h> 36 #include <sys/sunddi.h> 37 #include <sys/sunndi.h> 38 #include <sys/hotplug/pci/pcihp.h> 39 #include <sys/ddi_impldefs.h> 40 #include <sys/ddi_subrdefs.h> 41 #include <sys/spl.h> 42 #include <sys/epm.h> 43 #include <sys/iommutsb.h> 44 #include <sys/hotplug/pci/pcihp.h> 45 #include <sys/hotplug/pci/pciehpc.h> 46 #include "px_obj.h" 47 #include <sys/pci_tools.h> 48 #include "px_tools_ext.h" 49 #include "pcie_pwr.h" 50 51 /*LINTLIBRARY*/ 52 53 /* 54 * function prototypes for dev ops routines: 55 */ 56 static int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 57 static int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 58 static int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 59 void *arg, void **result); 60 static int px_cb_attach(px_t *); 61 static void px_cb_detach(px_t *); 62 static int px_pwr_setup(dev_info_t *dip); 63 static void px_pwr_teardown(dev_info_t *dip); 64 65 /* 66 * function prototypes for hotplug routines: 67 */ 68 static uint_t px_init_hotplug(px_t *px_p); 69 static uint_t px_uninit_hotplug(dev_info_t *dip); 70 71 /* 72 * bus ops and dev ops structures: 73 */ 74 static struct bus_ops px_bus_ops = { 75 BUSO_REV, 76 px_map, 77 0, 78 0, 79 0, 80 i_ddi_map_fault, 81 px_dma_setup, 82 px_dma_allochdl, 83 px_dma_freehdl, 84 px_dma_bindhdl, 85 px_dma_unbindhdl, 86 px_lib_dma_sync, 87 px_dma_win, 88 px_dma_ctlops, 89 px_ctlops, 90 ddi_bus_prop_op, 91 ndi_busop_get_eventcookie, 92 ndi_busop_add_eventcall, 93 ndi_busop_remove_eventcall, 94 ndi_post_event, 95 NULL, 96 NULL, /* (*bus_config)(); */ 97 NULL, /* (*bus_unconfig)(); */ 98 px_fm_init_child, /* (*bus_fm_init)(); */ 99 NULL, /* (*bus_fm_fini)(); */ 100 px_bus_enter, /* (*bus_fm_access_enter)(); */ 101 px_bus_exit, /* (*bus_fm_access_fini)(); */ 102 pcie_bus_power, /* (*bus_power)(); */ 103 px_intr_ops /* (*bus_intr_op)(); */ 104 }; 105 106 extern struct cb_ops px_cb_ops; 107 108 static struct dev_ops px_ops = { 109 DEVO_REV, 110 0, 111 px_info, 112 nulldev, 113 0, 114 px_attach, 115 px_detach, 116 nodev, 117 &px_cb_ops, 118 &px_bus_ops, 119 nulldev 120 }; 121 122 /* 123 * module definitions: 124 */ 125 #include <sys/modctl.h> 126 extern struct mod_ops mod_driverops; 127 128 static struct modldrv modldrv = { 129 &mod_driverops, /* Type of module - driver */ 130 "PCI Express nexus driver %I%", /* Name of module. */ 131 &px_ops, /* driver ops */ 132 }; 133 134 static struct modlinkage modlinkage = { 135 MODREV_1, (void *)&modldrv, NULL 136 }; 137 138 /* driver soft state */ 139 void *px_state_p; 140 141 int 142 _init(void) 143 { 144 int e; 145 146 /* 147 * Initialize per-px bus soft state pointer. 148 */ 149 e = ddi_soft_state_init(&px_state_p, sizeof (px_t), 1); 150 if (e != DDI_SUCCESS) 151 return (e); 152 153 /* 154 * Install the module. 155 */ 156 e = mod_install(&modlinkage); 157 if (e != DDI_SUCCESS) 158 ddi_soft_state_fini(&px_state_p); 159 return (e); 160 } 161 162 int 163 _fini(void) 164 { 165 int e; 166 167 /* 168 * Remove the module. 169 */ 170 e = mod_remove(&modlinkage); 171 if (e != DDI_SUCCESS) 172 return (e); 173 174 /* Free px soft state */ 175 ddi_soft_state_fini(&px_state_p); 176 177 return (e); 178 } 179 180 int 181 _info(struct modinfo *modinfop) 182 { 183 return (mod_info(&modlinkage, modinfop)); 184 } 185 186 /* ARGSUSED */ 187 static int 188 px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 189 { 190 int instance = getminor((dev_t)arg); 191 px_t *px_p = INST_TO_STATE(instance); 192 193 /* 194 * Allow hotplug to deal with ones it manages 195 * Hot Plug will be done later. 196 */ 197 if (px_p && (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)) 198 return (pcihp_info(dip, infocmd, arg, result)); 199 200 /* non-hotplug or not attached */ 201 switch (infocmd) { 202 case DDI_INFO_DEVT2INSTANCE: 203 *result = (void *)(intptr_t)instance; 204 return (DDI_SUCCESS); 205 206 case DDI_INFO_DEVT2DEVINFO: 207 if (px_p == NULL) 208 return (DDI_FAILURE); 209 *result = (void *)px_p->px_dip; 210 return (DDI_SUCCESS); 211 212 default: 213 return (DDI_FAILURE); 214 } 215 } 216 217 /* device driver entry points */ 218 /* 219 * attach entry point: 220 */ 221 /*ARGSUSED*/ 222 static int 223 px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 224 { 225 px_t *px_p; /* per bus state pointer */ 226 int instance = DIP_TO_INST(dip); 227 int ret = DDI_SUCCESS; 228 devhandle_t dev_hdl = NULL; 229 230 switch (cmd) { 231 case DDI_ATTACH: 232 DBG(DBG_ATTACH, dip, "DDI_ATTACH\n"); 233 234 /* 235 * Allocate and get the per-px soft state structure. 236 */ 237 if (ddi_soft_state_zalloc(px_state_p, instance) 238 != DDI_SUCCESS) { 239 cmn_err(CE_WARN, "%s%d: can't allocate px state", 240 ddi_driver_name(dip), instance); 241 goto err_bad_px_softstate; 242 } 243 px_p = INST_TO_STATE(instance); 244 px_p->px_dip = dip; 245 mutex_init(&px_p->px_mutex, NULL, MUTEX_DRIVER, NULL); 246 px_p->px_soft_state = PX_SOFT_STATE_CLOSED; 247 px_p->px_open_count = 0; 248 249 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, 250 "device_type", "pciex"); 251 /* 252 * Get key properties of the pci bridge node and 253 * determine it's type (psycho, schizo, etc ...). 254 */ 255 if (px_get_props(px_p, dip) == DDI_FAILURE) 256 goto err_bad_px_prop; 257 258 if ((px_fm_attach(px_p)) != DDI_SUCCESS) 259 goto err_bad_fm; 260 261 if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS) 262 goto err_bad_dev_init; 263 264 /* Initilize device handle */ 265 px_p->px_dev_hdl = dev_hdl; 266 267 /* 268 * Initialize interrupt block. Note that this 269 * initialize error handling for the PEC as well. 270 */ 271 if ((ret = px_ib_attach(px_p)) != DDI_SUCCESS) 272 goto err_bad_ib; 273 274 if (px_cb_attach(px_p) != DDI_SUCCESS) 275 goto err_bad_cb; 276 277 /* 278 * Start creating the modules. 279 * Note that attach() routines should 280 * register and enable their own interrupts. 281 */ 282 283 if ((px_mmu_attach(px_p)) != DDI_SUCCESS) 284 goto err_bad_mmu; 285 286 if ((px_msiq_attach(px_p)) != DDI_SUCCESS) 287 goto err_bad_msiq; 288 289 if ((px_msi_attach(px_p)) != DDI_SUCCESS) 290 goto err_bad_msi; 291 292 if ((px_pec_attach(px_p)) != DDI_SUCCESS) 293 goto err_bad_pec; 294 295 if ((px_dma_attach(px_p)) != DDI_SUCCESS) 296 goto err_bad_pec; /* nothing to uninitialize on DMA */ 297 298 /* 299 * All of the error handlers have been registered 300 * by now so it's time to activate the interrupt. 301 */ 302 if ((ret = px_err_add_intr(&px_p->px_fault)) != DDI_SUCCESS) 303 goto err_bad_pec_add_intr; 304 305 (void) px_init_hotplug(px_p); 306 307 /* 308 * Create the "devctl" node for hotplug and pcitool support. 309 * For non-hotplug bus, we still need ":devctl" to 310 * support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls. 311 */ 312 if (ddi_create_minor_node(dip, "devctl", S_IFCHR, 313 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 314 DDI_NT_NEXUS, 0) != DDI_SUCCESS) { 315 goto err_bad_devctl_node; 316 } 317 318 if (pxtool_init(dip) != DDI_SUCCESS) 319 goto err_bad_pcitool_node; 320 321 /* 322 * power management setup. Even if it fails, attach will 323 * succeed as this is a optional feature. Since we are 324 * always at full power, this is not critical. 325 */ 326 if (pwr_common_setup(dip) != DDI_SUCCESS) { 327 DBG(DBG_PWR, dip, "pwr_common_setup failed\n"); 328 } else if (px_pwr_setup(dip) != DDI_SUCCESS) { 329 DBG(DBG_PWR, dip, "px_pwr_setup failed \n"); 330 pwr_common_teardown(dip); 331 } 332 333 /* 334 * add cpr callback 335 */ 336 px_cpr_add_callb(px_p); 337 338 ddi_report_dev(dip); 339 340 px_p->px_state = PX_ATTACHED; 341 DBG(DBG_ATTACH, dip, "attach success\n"); 342 break; 343 344 err_bad_pcitool_node: 345 ddi_remove_minor_node(dip, "devctl"); 346 err_bad_devctl_node: 347 px_err_rem_intr(&px_p->px_fault); 348 err_bad_pec_add_intr: 349 px_pec_detach(px_p); 350 err_bad_pec: 351 px_msi_detach(px_p); 352 err_bad_msi: 353 px_msiq_detach(px_p); 354 err_bad_msiq: 355 px_mmu_detach(px_p); 356 err_bad_mmu: 357 px_cb_detach(px_p); 358 err_bad_cb: 359 px_ib_detach(px_p); 360 err_bad_ib: 361 (void) px_lib_dev_fini(dip); 362 err_bad_dev_init: 363 px_fm_detach(px_p); 364 err_bad_fm: 365 px_free_props(px_p); 366 err_bad_px_prop: 367 mutex_destroy(&px_p->px_mutex); 368 ddi_soft_state_free(px_state_p, instance); 369 err_bad_px_softstate: 370 ret = DDI_FAILURE; 371 break; 372 373 case DDI_RESUME: 374 DBG(DBG_ATTACH, dip, "DDI_RESUME\n"); 375 376 px_p = INST_TO_STATE(instance); 377 378 mutex_enter(&px_p->px_mutex); 379 380 /* suspend might have not succeeded */ 381 if (px_p->px_state != PX_SUSPENDED) { 382 DBG(DBG_ATTACH, px_p->px_dip, 383 "instance NOT suspended\n"); 384 ret = DDI_FAILURE; 385 break; 386 } 387 388 px_lib_resume(dip); 389 (void) pcie_pwr_resume(dip); 390 px_p->px_state = PX_ATTACHED; 391 392 mutex_exit(&px_p->px_mutex); 393 394 break; 395 default: 396 DBG(DBG_ATTACH, dip, "unsupported attach op\n"); 397 ret = DDI_FAILURE; 398 break; 399 } 400 401 return (ret); 402 } 403 404 /* 405 * detach entry point: 406 */ 407 /*ARGSUSED*/ 408 static int 409 px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 410 { 411 int instance = ddi_get_instance(dip); 412 px_t *px_p = INST_TO_STATE(instance); 413 int ret; 414 415 /* 416 * Make sure we are currently attached 417 */ 418 if (px_p->px_state != PX_ATTACHED) { 419 DBG(DBG_DETACH, dip, "Instance not attached\n"); 420 return (DDI_FAILURE); 421 } 422 423 mutex_enter(&px_p->px_mutex); 424 425 switch (cmd) { 426 case DDI_DETACH: 427 DBG(DBG_DETACH, dip, "DDI_DETACH\n"); 428 429 /* 430 * remove cpr callback 431 */ 432 px_cpr_rem_callb(px_p); 433 434 if (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE) 435 if (px_uninit_hotplug(dip) != DDI_SUCCESS) { 436 mutex_exit(&px_p->px_mutex); 437 return (DDI_FAILURE); 438 } 439 440 /* 441 * things which used to be done in obj_destroy 442 * are now in-lined here. 443 */ 444 445 px_p->px_state = PX_DETACHED; 446 447 pxtool_uninit(dip); 448 449 ddi_remove_minor_node(dip, "devctl"); 450 px_err_rem_intr(&px_p->px_fault); 451 px_pec_detach(px_p); 452 px_pwr_teardown(dip); 453 pwr_common_teardown(dip); 454 px_msi_detach(px_p); 455 px_msiq_detach(px_p); 456 px_mmu_detach(px_p); 457 px_cb_detach(px_p); 458 px_ib_detach(px_p); 459 (void) px_lib_dev_fini(dip); 460 px_fm_detach(px_p); 461 462 /* 463 * Free the px soft state structure and the rest of the 464 * resources it's using. 465 */ 466 px_free_props(px_p); 467 mutex_exit(&px_p->px_mutex); 468 mutex_destroy(&px_p->px_mutex); 469 470 /* Free the interrupt-priorities prop if we created it. */ { 471 int len; 472 473 if (ddi_getproplen(DDI_DEV_T_ANY, dip, 474 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS, 475 "interrupt-priorities", &len) == DDI_PROP_SUCCESS) 476 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 477 "interrupt-priorities"); 478 } 479 480 px_p->px_dev_hdl = NULL; 481 ddi_soft_state_free(px_state_p, instance); 482 483 return (DDI_SUCCESS); 484 485 case DDI_SUSPEND: 486 if (pcie_pwr_suspend(dip) != DDI_SUCCESS) { 487 mutex_exit(&px_p->px_mutex); 488 return (DDI_FAILURE); 489 } 490 if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS) 491 px_p->px_state = PX_SUSPENDED; 492 mutex_exit(&px_p->px_mutex); 493 494 return (ret); 495 496 default: 497 DBG(DBG_DETACH, dip, "unsupported detach op\n"); 498 mutex_exit(&px_p->px_mutex); 499 return (DDI_FAILURE); 500 } 501 } 502 503 int 504 px_cb_attach(px_t *px_p) 505 { 506 px_fault_t *fault_p = &px_p->px_cb_fault; 507 dev_info_t *dip = px_p->px_dip; 508 sysino_t sysino; 509 510 if (px_lib_intr_devino_to_sysino(dip, 511 px_p->px_inos[PX_INTR_XBC], &sysino) != DDI_SUCCESS) 512 return (DDI_FAILURE); 513 514 fault_p->px_fh_dip = dip; 515 fault_p->px_fh_sysino = sysino; 516 fault_p->px_err_func = px_err_cb_intr; 517 fault_p->px_intr_ino = px_p->px_inos[PX_INTR_XBC]; 518 519 return (px_cb_add_intr(fault_p)); 520 } 521 522 void 523 px_cb_detach(px_t *px_p) 524 { 525 px_cb_rem_intr(&px_p->px_cb_fault); 526 } 527 528 /* 529 * power management related initialization specific to px 530 * called by px_attach() 531 */ 532 static int 533 px_pwr_setup(dev_info_t *dip) 534 { 535 pcie_pwr_t *pwr_p; 536 int instance = ddi_get_instance(dip); 537 px_t *px_p = INST_TO_STATE(instance); 538 ddi_intr_handle_impl_t hdl; 539 540 ASSERT(PCIE_PMINFO(dip)); 541 pwr_p = PCIE_NEXUS_PMINFO(dip); 542 ASSERT(pwr_p); 543 544 /* 545 * indicate support LDI (Layered Driver Interface) 546 * Create the property, if it is not already there 547 */ 548 if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 549 DDI_KERNEL_IOCTL)) { 550 if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 551 DDI_KERNEL_IOCTL, NULL, 0) != DDI_PROP_SUCCESS) { 552 DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n"); 553 return (DDI_FAILURE); 554 } 555 } 556 /* No support for device PM. We are always at full power */ 557 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 558 559 mutex_init(&px_p->px_l23ready_lock, NULL, MUTEX_DRIVER, 560 DDI_INTR_PRI(px_pwr_pil)); 561 cv_init(&px_p->px_l23ready_cv, NULL, CV_DRIVER, NULL); 562 563 564 565 /* Initilize handle */ 566 hdl.ih_cb_arg1 = px_p; 567 hdl.ih_cb_arg2 = NULL; 568 hdl.ih_ver = DDI_INTR_VERSION; 569 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 570 hdl.ih_dip = dip; 571 hdl.ih_inum = 0; 572 hdl.ih_pri = px_pwr_pil; 573 574 /* Add PME_TO_ACK message handler */ 575 hdl.ih_cb_func = (ddi_intr_handler_t *)px_pmeq_intr; 576 if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC, 577 (msgcode_t)PCIE_PME_ACK_MSG, &px_p->px_pm_msiq_id) != DDI_SUCCESS) { 578 DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add " 579 " PME_TO_ACK intr\n"); 580 goto pwr_setup_err1; 581 } 582 px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id); 583 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID); 584 585 if (px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 586 px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), 587 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) { 588 DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt" 589 " state failed\n"); 590 goto px_pwrsetup_err_state; 591 } 592 593 return (DDI_SUCCESS); 594 595 px_pwrsetup_err_state: 596 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 597 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 598 px_p->px_pm_msiq_id); 599 pwr_setup_err1: 600 mutex_destroy(&px_p->px_l23ready_lock); 601 cv_destroy(&px_p->px_l23ready_cv); 602 603 return (DDI_FAILURE); 604 } 605 606 /* 607 * undo whatever is done in px_pwr_setup. called by px_detach() 608 */ 609 static void 610 px_pwr_teardown(dev_info_t *dip) 611 { 612 int instance = ddi_get_instance(dip); 613 px_t *px_p = INST_TO_STATE(instance); 614 ddi_intr_handle_impl_t hdl; 615 616 if (!PCIE_PMINFO(dip) || !PCIE_NEXUS_PMINFO(dip)) 617 return; 618 619 /* Initilize handle */ 620 hdl.ih_ver = DDI_INTR_VERSION; 621 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 622 hdl.ih_dip = dip; 623 hdl.ih_inum = 0; 624 625 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 626 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 627 px_p->px_pm_msiq_id); 628 629 (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 630 px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), 631 PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG); 632 633 px_p->px_pm_msiq_id = -1; 634 635 cv_destroy(&px_p->px_l23ready_cv); 636 mutex_destroy(&px_p->px_l23ready_lock); 637 } 638 639 /* bus driver entry points */ 640 641 /* 642 * bus map entry point: 643 * 644 * if map request is for an rnumber 645 * get the corresponding regspec from device node 646 * build a new regspec in our parent's format 647 * build a new map_req with the new regspec 648 * call up the tree to complete the mapping 649 */ 650 int 651 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 652 off_t off, off_t len, caddr_t *addrp) 653 { 654 px_t *px_p = DIP_TO_STATE(dip); 655 struct regspec p_regspec; 656 ddi_map_req_t p_mapreq; 657 int reglen, rval, r_no; 658 pci_regspec_t reloc_reg, *rp = &reloc_reg; 659 660 DBG(DBG_MAP, dip, "rdip=%s%d:", 661 ddi_driver_name(rdip), ddi_get_instance(rdip)); 662 663 if (mp->map_flags & DDI_MF_USER_MAPPING) 664 return (DDI_ME_UNIMPLEMENTED); 665 666 switch (mp->map_type) { 667 case DDI_MT_REGSPEC: 668 reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */ 669 break; 670 671 case DDI_MT_RNUMBER: 672 r_no = mp->map_obj.rnumber; 673 DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no); 674 675 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 676 "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS) 677 return (DDI_ME_RNUMBER_RANGE); 678 679 if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) { 680 kmem_free(rp, reglen); 681 return (DDI_ME_RNUMBER_RANGE); 682 } 683 rp += r_no; 684 break; 685 686 default: 687 return (DDI_ME_INVAL); 688 } 689 DBG(DBG_MAP | DBG_CONT, dip, "\n"); 690 691 if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) { 692 /* 693 * There may be a need to differentiate between PCI 694 * and PCI-Ex devices so the following range check is 695 * done correctly, depending on the implementation of 696 * px_pci bridge nexus driver. 697 */ 698 if ((off >= PCIE_CONF_HDR_SIZE) || 699 (len > PCIE_CONF_HDR_SIZE) || 700 (off + len > PCIE_CONF_HDR_SIZE)) 701 return (DDI_ME_INVAL); 702 /* 703 * the following function returning a DDI_FAILURE assumes 704 * that there are no virtual config space access services 705 * defined in this layer. Otherwise it is availed right 706 * here and we return. 707 */ 708 rval = px_lib_map_vconfig(dip, mp, off, rp, addrp); 709 if (rval == DDI_SUCCESS) 710 goto done; 711 } 712 713 /* 714 * No virtual config space services or we are mapping 715 * a region of memory mapped config/IO/memory space, so proceed 716 * to the parent. 717 */ 718 719 /* relocate within 64-bit pci space through "assigned-addresses" */ 720 if (rval = px_reloc_reg(dip, rdip, px_p, rp)) 721 goto done; 722 723 if (len) /* adjust regspec according to mapping request */ 724 rp->pci_size_low = len; /* MIN ? */ 725 rp->pci_phys_low += off; 726 727 /* translate relocated pci regspec into parent space through "ranges" */ 728 if (rval = px_xlate_reg(px_p, rp, &p_regspec)) 729 goto done; 730 731 p_mapreq = *mp; /* dup the whole structure */ 732 p_mapreq.map_type = DDI_MT_REGSPEC; 733 p_mapreq.map_obj.rp = &p_regspec; 734 px_lib_map_attr_check(&p_mapreq); 735 rval = ddi_map(dip, &p_mapreq, 0, 0, addrp); 736 737 if (rval == DDI_SUCCESS) { 738 /* 739 * Set-up access functions for FM access error capable drivers. 740 */ 741 if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)) && 742 mp->map_handlep->ah_acc.devacc_attr_access != 743 DDI_DEFAULT_ACC) 744 px_fm_acc_setup(mp, rdip); 745 } 746 747 done: 748 if (mp->map_type == DDI_MT_RNUMBER) 749 kmem_free(rp - r_no, reglen); 750 751 return (rval); 752 } 753 754 /* 755 * bus dma map entry point 756 * return value: 757 * DDI_DMA_PARTIAL_MAP 1 758 * DDI_DMA_MAPOK 0 759 * DDI_DMA_MAPPED 0 760 * DDI_DMA_NORESOURCES -1 761 * DDI_DMA_NOMAPPING -2 762 * DDI_DMA_TOOBIG -3 763 */ 764 int 765 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq, 766 ddi_dma_handle_t *handlep) 767 { 768 px_t *px_p = DIP_TO_STATE(dip); 769 px_mmu_t *mmu_p = px_p->px_mmu_p; 770 ddi_dma_impl_t *mp; 771 int ret; 772 773 DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n", 774 ddi_driver_name(rdip), ddi_get_instance(rdip), 775 handlep ? "alloc" : "advisory"); 776 777 if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq))) 778 return (DDI_DMA_NORESOURCES); 779 if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING) 780 return (DDI_DMA_NOMAPPING); 781 if (ret = px_dma_type(px_p, dmareq, mp)) 782 goto freehandle; 783 if (ret = px_dma_pfn(px_p, dmareq, mp)) 784 goto freehandle; 785 786 switch (PX_DMA_TYPE(mp)) { 787 case PX_DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 788 if ((ret = px_dvma_win(px_p, dmareq, mp)) || !handlep) 789 goto freehandle; 790 if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 791 if (PX_DMA_CANFAST(mp)) { 792 if (!px_dvma_map_fast(mmu_p, mp)) 793 break; 794 /* LINTED E_NOP_ELSE_STMT */ 795 } else { 796 PX_DVMA_FASTTRAK_PROF(mp); 797 } 798 } 799 if (ret = px_dvma_map(mp, dmareq, mmu_p)) 800 goto freehandle; 801 break; 802 case PX_DMAI_FLAGS_PTP: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 803 if ((ret = px_dma_physwin(px_p, dmareq, mp)) || !handlep) 804 goto freehandle; 805 break; 806 case PX_DMAI_FLAGS_BYPASS: 807 default: 808 cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x", 809 ddi_driver_name(rdip), ddi_get_instance(rdip), 810 PX_DMA_TYPE(mp)); 811 /*NOTREACHED*/ 812 } 813 *handlep = (ddi_dma_handle_t)mp; 814 mp->dmai_flags |= PX_DMAI_FLAGS_INUSE; 815 px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 816 817 return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 818 freehandle: 819 if (ret == DDI_DMA_NORESOURCES) 820 px_dma_freemp(mp); /* don't run_callback() */ 821 else 822 (void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 823 return (ret); 824 } 825 826 827 /* 828 * bus dma alloc handle entry point: 829 */ 830 int 831 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 832 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 833 { 834 px_t *px_p = DIP_TO_STATE(dip); 835 ddi_dma_impl_t *mp; 836 int rval; 837 838 DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", 839 ddi_driver_name(rdip), ddi_get_instance(rdip)); 840 841 if (attrp->dma_attr_version != DMA_ATTR_V0) 842 return (DDI_DMA_BADATTR); 843 844 if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg))) 845 return (DDI_DMA_NORESOURCES); 846 847 /* 848 * Save requestor's information 849 */ 850 mp->dmai_attr = *attrp; /* whole object - augmented later */ 851 *PX_DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */ 852 DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp); 853 854 /* check and convert dma attributes to handle parameters */ 855 if (rval = px_dma_attr2hdl(px_p, mp)) { 856 px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 857 *handlep = NULL; 858 return (rval); 859 } 860 *handlep = (ddi_dma_handle_t)mp; 861 return (DDI_SUCCESS); 862 } 863 864 865 /* 866 * bus dma free handle entry point: 867 */ 868 /*ARGSUSED*/ 869 int 870 px_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 871 { 872 DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n", 873 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 874 px_dma_freemp((ddi_dma_impl_t *)handle); 875 876 if (px_kmem_clid) { 877 DBG(DBG_DMA_FREEH, dip, "run handle callback\n"); 878 ddi_run_callback(&px_kmem_clid); 879 } 880 return (DDI_SUCCESS); 881 } 882 883 884 /* 885 * bus dma bind handle entry point: 886 */ 887 int 888 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 889 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 890 ddi_dma_cookie_t *cookiep, uint_t *ccountp) 891 { 892 px_t *px_p = DIP_TO_STATE(dip); 893 px_mmu_t *mmu_p = px_p->px_mmu_p; 894 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 895 int ret; 896 897 DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n", 898 ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq); 899 900 if (mp->dmai_flags & PX_DMAI_FLAGS_INUSE) 901 return (DDI_DMA_INUSE); 902 903 ASSERT((mp->dmai_flags & ~PX_DMAI_FLAGS_PRESERVE) == 0); 904 mp->dmai_flags |= PX_DMAI_FLAGS_INUSE; 905 906 if (ret = px_dma_type(px_p, dmareq, mp)) 907 goto err; 908 if (ret = px_dma_pfn(px_p, dmareq, mp)) 909 goto err; 910 911 switch (PX_DMA_TYPE(mp)) { 912 case PX_DMAI_FLAGS_DVMA: 913 if (ret = px_dvma_win(px_p, dmareq, mp)) 914 goto map_err; 915 if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 916 if (PX_DMA_CANFAST(mp)) { 917 if (!px_dvma_map_fast(mmu_p, mp)) 918 goto mapped; /*LINTED E_NOP_ELSE_STMT*/ 919 } else { 920 PX_DVMA_FASTTRAK_PROF(mp); 921 } 922 } 923 if (ret = px_dvma_map(mp, dmareq, mmu_p)) 924 goto map_err; 925 mapped: 926 *ccountp = 1; 927 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size); 928 break; 929 case PX_DMAI_FLAGS_BYPASS: 930 case PX_DMAI_FLAGS_PTP: 931 if (ret = px_dma_physwin(px_p, dmareq, mp)) 932 goto map_err; 933 *ccountp = PX_WINLST(mp)->win_ncookies; 934 *cookiep = 935 *(ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); /* wholeobj */ 936 break; 937 default: 938 cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type", 939 ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 940 /*NOTREACHED*/ 941 } 942 DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n", 943 cookiep->dmac_address, cookiep->dmac_size); 944 px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 945 946 /* insert dma handle into FMA cache */ 947 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) 948 (void) ndi_fmc_insert(rdip, DMA_HANDLE, mp, NULL); 949 950 return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 951 map_err: 952 px_dma_freepfn(mp); 953 err: 954 mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE; 955 return (ret); 956 } 957 958 959 /* 960 * bus dma unbind handle entry point: 961 */ 962 /*ARGSUSED*/ 963 int 964 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 965 { 966 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 967 px_t *px_p = DIP_TO_STATE(dip); 968 px_mmu_t *mmu_p = px_p->px_mmu_p; 969 970 DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n", 971 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 972 if ((mp->dmai_flags & PX_DMAI_FLAGS_INUSE) == 0) { 973 DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n"); 974 return (DDI_FAILURE); 975 } 976 977 /* remove dma handle from FMA cache */ 978 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) { 979 if (DEVI(rdip)->devi_fmhdl != NULL && 980 DDI_FM_DMA_ERR_CAP(DEVI(rdip)->devi_fmhdl->fh_cap)) { 981 (void) ndi_fmc_remove(rdip, DMA_HANDLE, mp); 982 } 983 } 984 985 /* 986 * Here if the handle is using the iommu. Unload all the iommu 987 * translations. 988 */ 989 switch (PX_DMA_TYPE(mp)) { 990 case PX_DMAI_FLAGS_DVMA: 991 px_mmu_unmap_window(mmu_p, mp); 992 px_dvma_unmap(mmu_p, mp); 993 px_dma_freepfn(mp); 994 break; 995 case PX_DMAI_FLAGS_BYPASS: 996 case PX_DMAI_FLAGS_PTP: 997 px_dma_freewin(mp); 998 break; 999 default: 1000 cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p", 1001 ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 1002 /*NOTREACHED*/ 1003 } 1004 if (mmu_p->mmu_dvma_clid != 0) { 1005 DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n"); 1006 ddi_run_callback(&mmu_p->mmu_dvma_clid); 1007 } 1008 if (px_kmem_clid) { 1009 DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n"); 1010 ddi_run_callback(&px_kmem_clid); 1011 } 1012 mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE; 1013 1014 return (DDI_SUCCESS); 1015 } 1016 1017 /* 1018 * bus dma win entry point: 1019 */ 1020 int 1021 px_dma_win(dev_info_t *dip, dev_info_t *rdip, 1022 ddi_dma_handle_t handle, uint_t win, off_t *offp, 1023 size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp) 1024 { 1025 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 1026 int ret; 1027 1028 DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n", 1029 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1030 1031 px_dump_dma_handle(DBG_DMA_WIN, dip, mp); 1032 if (win >= mp->dmai_nwin) { 1033 DBG(DBG_DMA_WIN, dip, "%x out of range\n", win); 1034 return (DDI_FAILURE); 1035 } 1036 1037 switch (PX_DMA_TYPE(mp)) { 1038 case PX_DMAI_FLAGS_DVMA: 1039 if (win != PX_DMA_CURWIN(mp)) { 1040 px_t *px_p = DIP_TO_STATE(dip); 1041 px_mmu_t *mmu_p = px_p->px_mmu_p; 1042 px_mmu_unmap_window(mmu_p, mp); 1043 1044 /* map_window sets dmai_mapping/size/offset */ 1045 px_mmu_map_window(mmu_p, mp, win); 1046 if ((ret = px_mmu_map_window(mmu_p, 1047 mp, win)) != DDI_SUCCESS) 1048 return (ret); 1049 } 1050 if (cookiep) 1051 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, 1052 mp->dmai_size); 1053 if (ccountp) 1054 *ccountp = 1; 1055 break; 1056 case PX_DMAI_FLAGS_PTP: 1057 case PX_DMAI_FLAGS_BYPASS: { 1058 int i; 1059 ddi_dma_cookie_t *ck_p; 1060 px_dma_win_t *win_p = mp->dmai_winlst; 1061 1062 for (i = 0; i < win; win_p = win_p->win_next, i++); 1063 ck_p = (ddi_dma_cookie_t *)(win_p + 1); 1064 *cookiep = *ck_p; 1065 mp->dmai_offset = win_p->win_offset; 1066 mp->dmai_size = win_p->win_size; 1067 mp->dmai_mapping = ck_p->dmac_laddress; 1068 mp->dmai_cookie = ck_p + 1; 1069 win_p->win_curseg = 0; 1070 if (ccountp) 1071 *ccountp = win_p->win_ncookies; 1072 } 1073 break; 1074 default: 1075 cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x", 1076 ddi_driver_name(rdip), ddi_get_instance(rdip), 1077 PX_DMA_TYPE(mp)); 1078 return (DDI_FAILURE); 1079 } 1080 if (cookiep) 1081 DBG(DBG_DMA_WIN, dip, 1082 "cookie - dmac_address=%x dmac_size=%x\n", 1083 cookiep->dmac_address, cookiep->dmac_size); 1084 if (offp) 1085 *offp = (off_t)mp->dmai_offset; 1086 if (lenp) 1087 *lenp = mp->dmai_size; 1088 return (DDI_SUCCESS); 1089 } 1090 1091 #ifdef DEBUG 1092 static char *px_dmactl_str[] = { 1093 "DDI_DMA_FREE", 1094 "DDI_DMA_SYNC", 1095 "DDI_DMA_HTOC", 1096 "DDI_DMA_KVADDR", 1097 "DDI_DMA_MOVWIN", 1098 "DDI_DMA_REPWIN", 1099 "DDI_DMA_GETERR", 1100 "DDI_DMA_COFF", 1101 "DDI_DMA_NEXTWIN", 1102 "DDI_DMA_NEXTSEG", 1103 "DDI_DMA_SEGTOC", 1104 "DDI_DMA_RESERVE", 1105 "DDI_DMA_RELEASE", 1106 "DDI_DMA_RESETH", 1107 "DDI_DMA_CKSYNC", 1108 "DDI_DMA_IOPB_ALLOC", 1109 "DDI_DMA_IOPB_FREE", 1110 "DDI_DMA_SMEM_ALLOC", 1111 "DDI_DMA_SMEM_FREE", 1112 "DDI_DMA_SET_SBUS64" 1113 }; 1114 #endif /* DEBUG */ 1115 1116 /* 1117 * bus dma control entry point: 1118 */ 1119 /*ARGSUSED*/ 1120 int 1121 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 1122 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1123 uint_t cache_flags) 1124 { 1125 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 1126 1127 #ifdef DEBUG 1128 DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd], 1129 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1130 #endif /* DEBUG */ 1131 1132 switch (cmd) { 1133 case DDI_DMA_FREE: 1134 (void) px_dma_unbindhdl(dip, rdip, handle); 1135 (void) px_dma_freehdl(dip, rdip, handle); 1136 return (DDI_SUCCESS); 1137 case DDI_DMA_RESERVE: { 1138 px_t *px_p = DIP_TO_STATE(dip); 1139 return (px_fdvma_reserve(dip, rdip, px_p, 1140 (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp)); 1141 } 1142 case DDI_DMA_RELEASE: { 1143 px_t *px_p = DIP_TO_STATE(dip); 1144 return (px_fdvma_release(dip, px_p, mp)); 1145 } 1146 default: 1147 break; 1148 } 1149 1150 switch (PX_DMA_TYPE(mp)) { 1151 case PX_DMAI_FLAGS_DVMA: 1152 return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 1153 cache_flags)); 1154 case PX_DMAI_FLAGS_PTP: 1155 case PX_DMAI_FLAGS_BYPASS: 1156 return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 1157 cache_flags)); 1158 default: 1159 cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x", 1160 ddi_driver_name(rdip), ddi_get_instance(rdip), cmd, 1161 mp->dmai_flags); 1162 /*NOTREACHED*/ 1163 } 1164 return (0); 1165 } 1166 1167 /* 1168 * control ops entry point: 1169 * 1170 * Requests handled completely: 1171 * DDI_CTLOPS_INITCHILD see init_child() for details 1172 * DDI_CTLOPS_UNINITCHILD 1173 * DDI_CTLOPS_REPORTDEV see report_dev() for details 1174 * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1 1175 * DDI_CTLOPS_REGSIZE 1176 * DDI_CTLOPS_NREGS 1177 * DDI_CTLOPS_DVMAPAGESIZE 1178 * DDI_CTLOPS_POKE 1179 * DDI_CTLOPS_PEEK 1180 * 1181 * All others passed to parent. 1182 */ 1183 int 1184 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 1185 ddi_ctl_enum_t op, void *arg, void *result) 1186 { 1187 px_t *px_p = DIP_TO_STATE(dip); 1188 struct detachspec *ds; 1189 struct attachspec *as; 1190 1191 switch (op) { 1192 case DDI_CTLOPS_INITCHILD: 1193 return (px_init_child(px_p, (dev_info_t *)arg)); 1194 1195 case DDI_CTLOPS_UNINITCHILD: 1196 return (px_uninit_child(px_p, (dev_info_t *)arg)); 1197 1198 case DDI_CTLOPS_ATTACH: 1199 as = (struct attachspec *)arg; 1200 switch (as->when) { 1201 case DDI_PRE: 1202 if (as->cmd == DDI_ATTACH) { 1203 DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n", 1204 ddi_driver_name(rdip), 1205 ddi_get_instance(rdip)); 1206 return (pcie_pm_hold(dip)); 1207 } 1208 if (as->cmd == DDI_RESUME) { 1209 ddi_acc_handle_t config_handle; 1210 DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n", 1211 ddi_driver_name(rdip), 1212 ddi_get_instance(rdip)); 1213 1214 if (pci_config_setup(rdip, &config_handle) == 1215 DDI_SUCCESS) { 1216 pcie_clear_errors(rdip, config_handle); 1217 pci_config_teardown(&config_handle); 1218 } 1219 } 1220 return (DDI_SUCCESS); 1221 1222 case DDI_POST: 1223 DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n", 1224 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1225 if (as->cmd == DDI_ATTACH && as->result != DDI_SUCCESS) 1226 pcie_pm_release(dip); 1227 return (DDI_SUCCESS); 1228 default: 1229 break; 1230 } 1231 break; 1232 1233 case DDI_CTLOPS_DETACH: 1234 ds = (struct detachspec *)arg; 1235 switch (ds->when) { 1236 case DDI_POST: 1237 if (ds->cmd == DDI_DETACH && 1238 ds->result == DDI_SUCCESS) { 1239 DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n", 1240 ddi_driver_name(rdip), 1241 ddi_get_instance(rdip)); 1242 return (pcie_pm_remove_child(dip, rdip)); 1243 } 1244 return (DDI_SUCCESS); 1245 default: 1246 break; 1247 } 1248 break; 1249 1250 case DDI_CTLOPS_REPORTDEV: 1251 return (px_report_dev(rdip)); 1252 1253 case DDI_CTLOPS_IOMIN: 1254 return (DDI_SUCCESS); 1255 1256 case DDI_CTLOPS_REGSIZE: 1257 *((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg)); 1258 return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS); 1259 1260 case DDI_CTLOPS_NREGS: 1261 *((uint_t *)result) = px_get_nreg_set(rdip); 1262 return (DDI_SUCCESS); 1263 1264 case DDI_CTLOPS_DVMAPAGESIZE: 1265 *((ulong_t *)result) = MMU_PAGE_SIZE; 1266 return (DDI_SUCCESS); 1267 1268 case DDI_CTLOPS_POKE: /* platform dependent implementation. */ 1269 return (px_lib_ctlops_poke(dip, rdip, 1270 (peekpoke_ctlops_t *)arg)); 1271 1272 case DDI_CTLOPS_PEEK: /* platform dependent implementation. */ 1273 return (px_lib_ctlops_peek(dip, rdip, 1274 (peekpoke_ctlops_t *)arg, result)); 1275 1276 case DDI_CTLOPS_POWER: 1277 default: 1278 break; 1279 } 1280 1281 /* 1282 * Now pass the request up to our parent. 1283 */ 1284 DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n", 1285 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1286 return (ddi_ctlops(dip, rdip, op, arg, result)); 1287 } 1288 1289 /* ARGSUSED */ 1290 int 1291 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1292 ddi_intr_handle_impl_t *hdlp, void *result) 1293 { 1294 int intr_types, ret = DDI_SUCCESS; 1295 1296 DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n", 1297 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1298 1299 /* Process DDI_INTROP_SUPPORTED_TYPES request here */ 1300 if (intr_op == DDI_INTROP_SUPPORTED_TYPES) { 1301 *(int *)result = i_ddi_get_nintrs(rdip) ? 1302 DDI_INTR_TYPE_FIXED : 0; 1303 1304 if ((pci_msi_get_supported_type(rdip, 1305 &intr_types)) == DDI_SUCCESS) { 1306 /* 1307 * Double check supported interrupt types vs. 1308 * what the host bridge supports. 1309 * 1310 * NOTE: 1311 * Currently MSI-X is disabled since px driver 1312 * don't fully support this feature. 1313 */ 1314 *(int *)result |= (intr_types & DDI_INTR_TYPE_MSI); 1315 } 1316 1317 return (ret); 1318 } 1319 1320 /* 1321 * PCI-E nexus driver supports fixed, MSI and MSI-X interrupts. 1322 * Return failure if interrupt type is not supported. 1323 */ 1324 switch (hdlp->ih_type) { 1325 case DDI_INTR_TYPE_FIXED: 1326 ret = px_intx_ops(dip, rdip, intr_op, hdlp, result); 1327 break; 1328 case DDI_INTR_TYPE_MSI: 1329 case DDI_INTR_TYPE_MSIX: 1330 ret = px_msix_ops(dip, rdip, intr_op, hdlp, result); 1331 break; 1332 default: 1333 ret = DDI_ENOTSUP; 1334 break; 1335 } 1336 1337 return (ret); 1338 } 1339 1340 static uint_t 1341 px_init_hotplug(px_t *px_p) 1342 { 1343 px_bus_range_t bus_range; 1344 dev_info_t *dip; 1345 pciehpc_regops_t regops; 1346 1347 dip = px_p->px_dip; 1348 1349 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1350 "hotplug-capable") == 0) 1351 return (DDI_FAILURE); 1352 1353 /* 1354 * Before initializing hotplug - open up bus range. The busra 1355 * module will initialize its pool of bus numbers from this. 1356 * "busra" will be the agent that keeps track of them during 1357 * hotplug. Also, note, that busra will remove any bus numbers 1358 * already in use from boot time. 1359 */ 1360 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1361 "bus-range") == 0) { 1362 cmn_err(CE_WARN, "%s%d: bus-range not found\n", 1363 ddi_driver_name(dip), ddi_get_instance(dip)); 1364 #ifdef DEBUG 1365 bus_range.lo = 0x0; 1366 bus_range.hi = 0xff; 1367 1368 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 1369 dip, "bus-range", (int *)&bus_range, 2) 1370 != DDI_PROP_SUCCESS) { 1371 return (DDI_FAILURE); 1372 } 1373 #else 1374 return (DDI_FAILURE); 1375 #endif 1376 } 1377 1378 if (px_lib_hotplug_init(dip, (void *)®ops) != DDI_SUCCESS) 1379 return (DDI_FAILURE); 1380 1381 if (pciehpc_init(dip, ®ops) != DDI_SUCCESS) { 1382 px_lib_hotplug_uninit(dip); 1383 return (DDI_FAILURE); 1384 } 1385 1386 if (pcihp_init(dip) != DDI_SUCCESS) { 1387 (void) pciehpc_uninit(dip); 1388 px_lib_hotplug_uninit(dip); 1389 return (DDI_FAILURE); 1390 } 1391 1392 if (pcihp_get_cb_ops() != NULL) { 1393 DBG(DBG_ATTACH, dip, "%s%d hotplug enabled", 1394 ddi_driver_name(dip), ddi_get_instance(dip)); 1395 px_p->px_dev_caps |= PX_HOTPLUG_CAPABLE; 1396 } 1397 1398 return (DDI_SUCCESS); 1399 } 1400 1401 static uint_t 1402 px_uninit_hotplug(dev_info_t *dip) 1403 { 1404 if (pcihp_uninit(dip) != DDI_SUCCESS) 1405 return (DDI_FAILURE); 1406 1407 if (pciehpc_uninit(dip) != DDI_SUCCESS) 1408 return (DDI_FAILURE); 1409 1410 px_lib_hotplug_uninit(dip); 1411 1412 return (DDI_SUCCESS); 1413 } 1414