1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI Express nexus driver interface 31 */ 32 33 #include <sys/types.h> 34 #include <sys/conf.h> /* nulldev */ 35 #include <sys/stat.h> /* devctl */ 36 #include <sys/kmem.h> 37 #include <sys/sunddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/hotplug/pci/pcihp.h> 40 #include <sys/ddi_impldefs.h> 41 #include <sys/ddi_subrdefs.h> 42 #include <sys/spl.h> 43 #include <sys/epm.h> 44 #include <sys/iommutsb.h> 45 #include "px_obj.h" 46 #include <sys/pci_tools.h> 47 #include "px_tools_ext.h" 48 #include "pcie_pwr.h" 49 50 /*LINTLIBRARY*/ 51 52 /* 53 * function prototypes for dev ops routines: 54 */ 55 static int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 56 static int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 57 static int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 58 void *arg, void **result); 59 static int px_pwr_setup(dev_info_t *dip); 60 static void px_pwr_teardown(dev_info_t *dip); 61 62 /* 63 * bus ops and dev ops structures: 64 */ 65 static struct bus_ops px_bus_ops = { 66 BUSO_REV, 67 px_map, 68 0, 69 0, 70 0, 71 i_ddi_map_fault, 72 px_dma_setup, 73 px_dma_allochdl, 74 px_dma_freehdl, 75 px_dma_bindhdl, 76 px_dma_unbindhdl, 77 px_lib_dma_sync, 78 px_dma_win, 79 px_dma_ctlops, 80 px_ctlops, 81 ddi_bus_prop_op, 82 ndi_busop_get_eventcookie, 83 ndi_busop_add_eventcall, 84 ndi_busop_remove_eventcall, 85 ndi_post_event, 86 NULL, 87 NULL, /* (*bus_config)(); */ 88 NULL, /* (*bus_unconfig)(); */ 89 px_fm_init_child, /* (*bus_fm_init)(); */ 90 NULL, /* (*bus_fm_fini)(); */ 91 px_bus_enter, /* (*bus_fm_access_enter)(); */ 92 px_bus_exit, /* (*bus_fm_access_fini)(); */ 93 pcie_bus_power, /* (*bus_power)(); */ 94 px_intr_ops /* (*bus_intr_op)(); */ 95 }; 96 97 extern struct cb_ops px_cb_ops; 98 99 static struct dev_ops px_ops = { 100 DEVO_REV, 101 0, 102 px_info, 103 nulldev, 104 0, 105 px_attach, 106 px_detach, 107 nodev, 108 &px_cb_ops, 109 &px_bus_ops, 110 nulldev 111 }; 112 113 /* 114 * module definitions: 115 */ 116 #include <sys/modctl.h> 117 extern struct mod_ops mod_driverops; 118 119 static struct modldrv modldrv = { 120 &mod_driverops, /* Type of module - driver */ 121 "PCI Express nexus driver %I%", /* Name of module. */ 122 &px_ops, /* driver ops */ 123 }; 124 125 static struct modlinkage modlinkage = { 126 MODREV_1, (void *)&modldrv, NULL 127 }; 128 129 /* driver soft state */ 130 void *px_state_p; 131 132 int 133 _init(void) 134 { 135 int e; 136 137 /* 138 * Initialize per-px bus soft state pointer. 139 */ 140 e = ddi_soft_state_init(&px_state_p, sizeof (px_t), 1); 141 if (e != DDI_SUCCESS) 142 return (e); 143 144 /* 145 * Install the module. 146 */ 147 e = mod_install(&modlinkage); 148 if (e != DDI_SUCCESS) 149 ddi_soft_state_fini(&px_state_p); 150 return (e); 151 } 152 153 int 154 _fini(void) 155 { 156 int e; 157 158 /* 159 * Remove the module. 160 */ 161 e = mod_remove(&modlinkage); 162 if (e != DDI_SUCCESS) 163 return (e); 164 165 /* Free px soft state */ 166 ddi_soft_state_fini(&px_state_p); 167 168 return (e); 169 } 170 171 int 172 _info(struct modinfo *modinfop) 173 { 174 return (mod_info(&modlinkage, modinfop)); 175 } 176 177 /* ARGSUSED */ 178 static int 179 px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 180 { 181 int instance = getminor((dev_t)arg); 182 px_t *px_p = INST_TO_STATE(instance); 183 184 #ifdef HOTPLUG 185 /* 186 * Allow hotplug to deal with ones it manages 187 * Hot Plug will be done later. 188 */ 189 if (px_p && (px_p->hotplug_capable == B_TRUE)) 190 return (pcihp_info(dip, infocmd, arg, result)); 191 #endif /* HOTPLUG */ 192 193 /* non-hotplug or not attached */ 194 switch (infocmd) { 195 case DDI_INFO_DEVT2INSTANCE: 196 *result = (void *)(intptr_t)instance; 197 return (DDI_SUCCESS); 198 199 case DDI_INFO_DEVT2DEVINFO: 200 if (px_p == NULL) 201 return (DDI_FAILURE); 202 *result = (void *)px_p->px_dip; 203 return (DDI_SUCCESS); 204 205 default: 206 return (DDI_FAILURE); 207 } 208 } 209 210 /* device driver entry points */ 211 /* 212 * attach entry point: 213 */ 214 /*ARGSUSED*/ 215 static int 216 px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 217 { 218 px_t *px_p; /* per bus state pointer */ 219 int instance = DIP_TO_INST(dip); 220 int ret = DDI_SUCCESS; 221 devhandle_t dev_hdl = NULL; 222 223 switch (cmd) { 224 case DDI_ATTACH: 225 DBG(DBG_ATTACH, dip, "DDI_ATTACH\n"); 226 227 /* 228 * Allocate and get the per-px soft state structure. 229 */ 230 if (ddi_soft_state_zalloc(px_state_p, instance) 231 != DDI_SUCCESS) { 232 cmn_err(CE_WARN, "%s%d: can't allocate px state", 233 ddi_driver_name(dip), instance); 234 goto err_bad_px_softstate; 235 } 236 px_p = INST_TO_STATE(instance); 237 px_p->px_dip = dip; 238 mutex_init(&px_p->px_mutex, NULL, MUTEX_DRIVER, NULL); 239 px_p->px_soft_state = PX_SOFT_STATE_CLOSED; 240 px_p->px_open_count = 0; 241 242 /* 243 * Get key properties of the pci bridge node and 244 * determine it's type (psycho, schizo, etc ...). 245 */ 246 if (px_get_props(px_p, dip) == DDI_FAILURE) 247 goto err_bad_px_prop; 248 249 if ((px_fm_attach(px_p)) != DDI_SUCCESS) 250 goto err_bad_fm; 251 252 if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS) 253 goto err_bad_dev_init; 254 255 /* Initilize device handle */ 256 px_p->px_dev_hdl = dev_hdl; 257 258 /* 259 * Initialize interrupt block. Note that this 260 * initialize error handling for the PEC as well. 261 */ 262 if ((ret = px_ib_attach(px_p)) != DDI_SUCCESS) 263 goto err_bad_ib; 264 265 if (px_cb_attach(px_p) != DDI_SUCCESS) 266 goto err_bad_cb; 267 268 /* 269 * Start creating the modules. 270 * Note that attach() routines should 271 * register and enable their own interrupts. 272 */ 273 274 if ((px_mmu_attach(px_p)) != DDI_SUCCESS) 275 goto err_bad_mmu; 276 277 if ((px_msiq_attach(px_p)) != DDI_SUCCESS) 278 goto err_bad_msiq; 279 280 if ((px_msi_attach(px_p)) != DDI_SUCCESS) 281 goto err_bad_msi; 282 283 if ((px_pec_attach(px_p)) != DDI_SUCCESS) 284 goto err_bad_pec; 285 286 if ((px_dma_attach(px_p)) != DDI_SUCCESS) 287 goto err_bad_pec; /* nothing to uninitialize on DMA */ 288 289 /* 290 * All of the error handlers have been registered 291 * by now so it's time to activate the interrupt. 292 */ 293 if ((ret = px_err_add_intr(&px_p->px_fault)) != DDI_SUCCESS) 294 goto err_bad_pec_add_intr; 295 296 /* 297 * Create the "devctl" node for hotplug and pcitool support. 298 * For non-hotplug bus, we still need ":devctl" to 299 * support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls. 300 */ 301 if (ddi_create_minor_node(dip, "devctl", S_IFCHR, 302 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 303 DDI_NT_NEXUS, 0) != DDI_SUCCESS) { 304 goto err_bad_devctl_node; 305 } 306 307 if (pxtool_init(dip) != DDI_SUCCESS) 308 goto err_bad_pcitool_node; 309 310 /* 311 * power management setup. Even if it fails, attach will 312 * succeed as this is a optional feature. Since we are 313 * always at full power, this is not critical. 314 */ 315 if (pwr_common_setup(dip) != DDI_SUCCESS) { 316 DBG(DBG_PWR, dip, "pwr_common_setup failed\n"); 317 } else if (px_pwr_setup(dip) != DDI_SUCCESS) { 318 DBG(DBG_PWR, dip, "px_pwr_setup failed \n"); 319 pwr_common_teardown(dip); 320 } 321 322 /* 323 * add cpr callback 324 */ 325 px_cpr_add_callb(px_p); 326 327 ddi_report_dev(dip); 328 329 px_p->px_state = PX_ATTACHED; 330 DBG(DBG_ATTACH, dip, "attach success\n"); 331 break; 332 333 err_bad_pcitool_node: 334 ddi_remove_minor_node(dip, "devctl"); 335 err_bad_devctl_node: 336 px_err_rem_intr(&px_p->px_fault); 337 err_bad_pec_add_intr: 338 px_pec_detach(px_p); 339 err_bad_pec: 340 px_msi_detach(px_p); 341 err_bad_msi: 342 px_msiq_detach(px_p); 343 err_bad_msiq: 344 px_mmu_detach(px_p); 345 err_bad_mmu: 346 px_cb_detach(px_p); 347 err_bad_cb: 348 px_ib_detach(px_p); 349 err_bad_ib: 350 (void) px_lib_dev_fini(dip); 351 err_bad_dev_init: 352 px_fm_detach(px_p); 353 err_bad_fm: 354 px_free_props(px_p); 355 err_bad_px_prop: 356 mutex_destroy(&px_p->px_mutex); 357 ddi_soft_state_free(px_state_p, instance); 358 err_bad_px_softstate: 359 ret = DDI_FAILURE; 360 break; 361 362 case DDI_RESUME: 363 DBG(DBG_ATTACH, dip, "DDI_RESUME\n"); 364 365 px_p = INST_TO_STATE(instance); 366 367 mutex_enter(&px_p->px_mutex); 368 369 /* suspend might have not succeeded */ 370 if (px_p->px_state != PX_SUSPENDED) { 371 DBG(DBG_ATTACH, px_p->px_dip, 372 "instance NOT suspended\n"); 373 ret = DDI_FAILURE; 374 break; 375 } 376 377 px_lib_resume(dip); 378 (void) pcie_pwr_resume(dip); 379 px_p->px_state = PX_ATTACHED; 380 381 mutex_exit(&px_p->px_mutex); 382 383 break; 384 default: 385 DBG(DBG_ATTACH, dip, "unsupported attach op\n"); 386 ret = DDI_FAILURE; 387 break; 388 } 389 390 return (ret); 391 } 392 393 /* 394 * detach entry point: 395 */ 396 /*ARGSUSED*/ 397 static int 398 px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 399 { 400 int instance = ddi_get_instance(dip); 401 px_t *px_p = INST_TO_STATE(instance); 402 int ret; 403 404 /* 405 * Make sure we are currently attached 406 */ 407 if (px_p->px_state != PX_ATTACHED) { 408 DBG(DBG_DETACH, dip, "failed - instance not attached\n"); 409 return (DDI_FAILURE); 410 } 411 412 mutex_enter(&px_p->px_mutex); 413 414 switch (cmd) { 415 case DDI_DETACH: 416 DBG(DBG_DETACH, dip, "DDI_DETACH\n"); 417 418 /* 419 * remove cpr callback 420 */ 421 px_cpr_rem_callb(px_p); 422 423 #ifdef HOTPLUG 424 /* 425 * Hot plug will be done later. 426 */ 427 if (px_p->hotplug_capable == B_TRUE) { 428 if (pxhp_uninit(dip) == DDI_FAILURE) { 429 mutex_exit(&px_p->px_mutex); 430 return (DDI_FAILURE); 431 } 432 } 433 #endif /* HOTPLUG */ 434 435 /* 436 * things which used to be done in obj_destroy 437 * are now in-lined here. 438 */ 439 440 px_p->px_state = PX_DETACHED; 441 442 pxtool_uninit(dip); 443 444 ddi_remove_minor_node(dip, "devctl"); 445 px_err_rem_intr(&px_p->px_fault); 446 px_pec_detach(px_p); 447 px_pwr_teardown(dip); 448 pwr_common_teardown(dip); 449 px_msi_detach(px_p); 450 px_msiq_detach(px_p); 451 px_mmu_detach(px_p); 452 px_cb_detach(px_p); 453 px_ib_detach(px_p); 454 (void) px_lib_dev_fini(dip); 455 px_fm_detach(px_p); 456 457 /* 458 * Free the px soft state structure and the rest of the 459 * resources it's using. 460 */ 461 px_free_props(px_p); 462 mutex_exit(&px_p->px_mutex); 463 mutex_destroy(&px_p->px_mutex); 464 465 /* Free the interrupt-priorities prop if we created it. */ { 466 int len; 467 468 if (ddi_getproplen(DDI_DEV_T_ANY, dip, 469 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS, 470 "interrupt-priorities", &len) == DDI_PROP_SUCCESS) 471 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 472 "interrupt-priorities"); 473 } 474 475 px_p->px_dev_hdl = NULL; 476 ddi_soft_state_free(px_state_p, instance); 477 478 return (DDI_SUCCESS); 479 480 case DDI_SUSPEND: 481 if (pcie_pwr_suspend(dip) != DDI_SUCCESS) { 482 mutex_exit(&px_p->px_mutex); 483 return (DDI_FAILURE); 484 } 485 if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS) 486 px_p->px_state = PX_SUSPENDED; 487 mutex_exit(&px_p->px_mutex); 488 489 return (ret); 490 491 default: 492 DBG(DBG_DETACH, dip, "unsupported detach op\n"); 493 mutex_exit(&px_p->px_mutex); 494 return (DDI_FAILURE); 495 } 496 } 497 498 /* 499 * power management related initialization specific to px 500 * called by px_attach() 501 */ 502 static int 503 px_pwr_setup(dev_info_t *dip) 504 { 505 pcie_pwr_t *pwr_p; 506 int instance = ddi_get_instance(dip); 507 px_t *px_p = INST_TO_STATE(instance); 508 ddi_intr_handle_impl_t hdl; 509 510 ASSERT(PCIE_PMINFO(dip)); 511 pwr_p = PCIE_NEXUS_PMINFO(dip); 512 ASSERT(pwr_p); 513 514 /* 515 * indicate support LDI (Layered Driver Interface) 516 * Create the property, if it is not already there 517 */ 518 if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 519 DDI_KERNEL_IOCTL)) { 520 if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 521 DDI_KERNEL_IOCTL, NULL, 0) != DDI_PROP_SUCCESS) { 522 DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n"); 523 return (DDI_FAILURE); 524 } 525 } 526 /* No support for device PM. We are always at full power */ 527 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 528 529 mutex_init(&px_p->px_l23ready_lock, NULL, MUTEX_DRIVER, 530 DDI_INTR_PRI(px_pwr_pil)); 531 cv_init(&px_p->px_l23ready_cv, NULL, CV_DRIVER, NULL); 532 533 /* Initilize handle */ 534 hdl.ih_cb_arg1 = px_p; 535 hdl.ih_cb_arg2 = NULL; 536 hdl.ih_ver = DDI_INTR_VERSION; 537 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 538 hdl.ih_dip = dip; 539 hdl.ih_inum = 0; 540 hdl.ih_pri = px_pwr_pil; 541 542 /* Add PME_TO_ACK message handler */ 543 hdl.ih_cb_func = (ddi_intr_handler_t *)px_pmeq_intr; 544 if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC, 545 (msgcode_t)PCIE_PME_ACK_MSG, &px_p->px_pm_msiq_id) != DDI_SUCCESS) { 546 DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add " 547 " PME_TO_ACK intr\n"); 548 goto pwr_setup_err1; 549 } 550 px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id); 551 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID); 552 553 if (px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 554 px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), 555 PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) { 556 DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt" 557 " state failed\n"); 558 goto px_pwrsetup_err_state; 559 } 560 561 return (DDI_SUCCESS); 562 563 px_pwrsetup_err_state: 564 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 565 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 566 px_p->px_pm_msiq_id); 567 pwr_setup_err1: 568 mutex_destroy(&px_p->px_l23ready_lock); 569 cv_destroy(&px_p->px_l23ready_cv); 570 571 return (DDI_FAILURE); 572 } 573 574 /* 575 * undo whatever is done in px_pwr_setup. called by px_detach() 576 */ 577 static void 578 px_pwr_teardown(dev_info_t *dip) 579 { 580 int instance = ddi_get_instance(dip); 581 px_t *px_p = INST_TO_STATE(instance); 582 ddi_intr_handle_impl_t hdl; 583 584 if (!PCIE_PMINFO(dip) || !PCIE_NEXUS_PMINFO(dip)) 585 return; 586 587 /* Initilize handle */ 588 hdl.ih_ver = DDI_INTR_VERSION; 589 hdl.ih_state = DDI_IHDL_STATE_ALLOC; 590 hdl.ih_dip = dip; 591 hdl.ih_inum = 0; 592 593 px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 594 (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 595 px_p->px_pm_msiq_id); 596 597 (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 598 px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), 599 PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG); 600 601 px_p->px_pm_msiq_id = -1; 602 603 cv_destroy(&px_p->px_l23ready_cv); 604 mutex_destroy(&px_p->px_l23ready_lock); 605 } 606 607 /* bus driver entry points */ 608 609 /* 610 * bus map entry point: 611 * 612 * if map request is for an rnumber 613 * get the corresponding regspec from device node 614 * build a new regspec in our parent's format 615 * build a new map_req with the new regspec 616 * call up the tree to complete the mapping 617 */ 618 int 619 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 620 off_t off, off_t len, caddr_t *addrp) 621 { 622 px_t *px_p = DIP_TO_STATE(dip); 623 struct regspec p_regspec; 624 ddi_map_req_t p_mapreq; 625 int reglen, rval, r_no; 626 pci_regspec_t reloc_reg, *rp = &reloc_reg; 627 628 DBG(DBG_MAP, dip, "rdip=%s%d:", 629 ddi_driver_name(rdip), ddi_get_instance(rdip)); 630 631 if (mp->map_flags & DDI_MF_USER_MAPPING) 632 return (DDI_ME_UNIMPLEMENTED); 633 634 switch (mp->map_type) { 635 case DDI_MT_REGSPEC: 636 reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */ 637 break; 638 639 case DDI_MT_RNUMBER: 640 r_no = mp->map_obj.rnumber; 641 DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no); 642 643 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 644 "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS) 645 return (DDI_ME_RNUMBER_RANGE); 646 647 if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) { 648 kmem_free(rp, reglen); 649 return (DDI_ME_RNUMBER_RANGE); 650 } 651 rp += r_no; 652 break; 653 654 default: 655 return (DDI_ME_INVAL); 656 } 657 DBG(DBG_MAP | DBG_CONT, dip, "\n"); 658 659 if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) { 660 /* 661 * There may be a need to differentiate between PCI 662 * and PCI-Ex devices so the following range check is 663 * done correctly, depending on the implementation of 664 * px_pci bridge nexus driver. 665 */ 666 if ((off >= PCIE_CONF_HDR_SIZE) || 667 (len > PCIE_CONF_HDR_SIZE) || 668 (off + len > PCIE_CONF_HDR_SIZE)) 669 return (DDI_ME_INVAL); 670 /* 671 * the following function returning a DDI_FAILURE assumes 672 * that there are no virtual config space access services 673 * defined in this layer. Otherwise it is availed right 674 * here and we return. 675 */ 676 rval = px_lib_map_vconfig(dip, mp, off, rp, addrp); 677 if (rval == DDI_SUCCESS) 678 goto done; 679 } 680 681 /* 682 * No virtual config space services or we are mapping 683 * a region of memory mapped config/IO/memory space, so proceed 684 * to the parent. 685 */ 686 687 /* relocate within 64-bit pci space through "assigned-addresses" */ 688 if (rval = px_reloc_reg(dip, rdip, px_p, rp)) 689 goto done; 690 691 if (len) /* adjust regspec according to mapping request */ 692 rp->pci_size_low = len; /* MIN ? */ 693 rp->pci_phys_low += off; 694 695 /* translate relocated pci regspec into parent space through "ranges" */ 696 if (rval = px_xlate_reg(px_p, rp, &p_regspec)) 697 goto done; 698 699 p_mapreq = *mp; /* dup the whole structure */ 700 p_mapreq.map_type = DDI_MT_REGSPEC; 701 p_mapreq.map_obj.rp = &p_regspec; 702 px_lib_map_attr_check(&p_mapreq); 703 rval = ddi_map(dip, &p_mapreq, 0, 0, addrp); 704 705 if (rval == DDI_SUCCESS) { 706 /* 707 * Set-up access functions for FM access error capable drivers. 708 */ 709 if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip)) && 710 mp->map_handlep->ah_acc.devacc_attr_access != 711 DDI_DEFAULT_ACC) 712 px_fm_acc_setup(mp, rdip); 713 } 714 715 done: 716 if (mp->map_type == DDI_MT_RNUMBER) 717 kmem_free(rp - r_no, reglen); 718 719 return (rval); 720 } 721 722 /* 723 * bus dma map entry point 724 * return value: 725 * DDI_DMA_PARTIAL_MAP 1 726 * DDI_DMA_MAPOK 0 727 * DDI_DMA_MAPPED 0 728 * DDI_DMA_NORESOURCES -1 729 * DDI_DMA_NOMAPPING -2 730 * DDI_DMA_TOOBIG -3 731 */ 732 int 733 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq, 734 ddi_dma_handle_t *handlep) 735 { 736 px_t *px_p = DIP_TO_STATE(dip); 737 px_mmu_t *mmu_p = px_p->px_mmu_p; 738 ddi_dma_impl_t *mp; 739 int ret; 740 741 DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n", 742 ddi_driver_name(rdip), ddi_get_instance(rdip), 743 handlep ? "alloc" : "advisory"); 744 745 if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq))) 746 return (DDI_DMA_NORESOURCES); 747 if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING) 748 return (DDI_DMA_NOMAPPING); 749 if (ret = px_dma_type(px_p, dmareq, mp)) 750 goto freehandle; 751 if (ret = px_dma_pfn(px_p, dmareq, mp)) 752 goto freehandle; 753 754 switch (PX_DMA_TYPE(mp)) { 755 case PX_DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 756 if ((ret = px_dvma_win(px_p, dmareq, mp)) || !handlep) 757 goto freehandle; 758 if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 759 if (PX_DMA_CANFAST(mp)) { 760 if (!px_dvma_map_fast(mmu_p, mp)) 761 break; 762 /* LINTED E_NOP_ELSE_STMT */ 763 } else { 764 PX_DVMA_FASTTRAK_PROF(mp); 765 } 766 } 767 if (ret = px_dvma_map(mp, dmareq, mmu_p)) 768 goto freehandle; 769 break; 770 case PX_DMAI_FLAGS_PTP: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 771 if ((ret = px_dma_physwin(px_p, dmareq, mp)) || !handlep) 772 goto freehandle; 773 break; 774 case PX_DMAI_FLAGS_BYPASS: 775 default: 776 cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x", 777 ddi_driver_name(rdip), ddi_get_instance(rdip), 778 PX_DMA_TYPE(mp)); 779 /*NOTREACHED*/ 780 } 781 *handlep = (ddi_dma_handle_t)mp; 782 mp->dmai_flags |= PX_DMAI_FLAGS_INUSE; 783 px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 784 785 return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 786 freehandle: 787 if (ret == DDI_DMA_NORESOURCES) 788 px_dma_freemp(mp); /* don't run_callback() */ 789 else 790 (void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 791 return (ret); 792 } 793 794 795 /* 796 * bus dma alloc handle entry point: 797 */ 798 int 799 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 800 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 801 { 802 px_t *px_p = DIP_TO_STATE(dip); 803 ddi_dma_impl_t *mp; 804 int rval; 805 806 DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", 807 ddi_driver_name(rdip), ddi_get_instance(rdip)); 808 809 if (attrp->dma_attr_version != DMA_ATTR_V0) 810 return (DDI_DMA_BADATTR); 811 812 if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg))) 813 return (DDI_DMA_NORESOURCES); 814 815 /* 816 * Save requestor's information 817 */ 818 mp->dmai_attr = *attrp; /* whole object - augmented later */ 819 *PX_DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */ 820 DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp); 821 822 /* check and convert dma attributes to handle parameters */ 823 if (rval = px_dma_attr2hdl(px_p, mp)) { 824 px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 825 *handlep = NULL; 826 return (rval); 827 } 828 *handlep = (ddi_dma_handle_t)mp; 829 return (DDI_SUCCESS); 830 } 831 832 833 /* 834 * bus dma free handle entry point: 835 */ 836 /*ARGSUSED*/ 837 int 838 px_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 839 { 840 DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n", 841 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 842 px_dma_freemp((ddi_dma_impl_t *)handle); 843 844 if (px_kmem_clid) { 845 DBG(DBG_DMA_FREEH, dip, "run handle callback\n"); 846 ddi_run_callback(&px_kmem_clid); 847 } 848 return (DDI_SUCCESS); 849 } 850 851 852 /* 853 * bus dma bind handle entry point: 854 */ 855 int 856 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 857 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 858 ddi_dma_cookie_t *cookiep, uint_t *ccountp) 859 { 860 px_t *px_p = DIP_TO_STATE(dip); 861 px_mmu_t *mmu_p = px_p->px_mmu_p; 862 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 863 int ret; 864 865 DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n", 866 ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq); 867 868 if (mp->dmai_flags & PX_DMAI_FLAGS_INUSE) 869 return (DDI_DMA_INUSE); 870 871 ASSERT((mp->dmai_flags & ~PX_DMAI_FLAGS_PRESERVE) == 0); 872 mp->dmai_flags |= PX_DMAI_FLAGS_INUSE; 873 874 if (ret = px_dma_type(px_p, dmareq, mp)) 875 goto err; 876 if (ret = px_dma_pfn(px_p, dmareq, mp)) 877 goto err; 878 879 switch (PX_DMA_TYPE(mp)) { 880 case PX_DMAI_FLAGS_DVMA: 881 if (ret = px_dvma_win(px_p, dmareq, mp)) 882 goto map_err; 883 if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 884 if (PX_DMA_CANFAST(mp)) { 885 if (!px_dvma_map_fast(mmu_p, mp)) 886 goto mapped; /*LINTED E_NOP_ELSE_STMT*/ 887 } else { 888 PX_DVMA_FASTTRAK_PROF(mp); 889 } 890 } 891 if (ret = px_dvma_map(mp, dmareq, mmu_p)) 892 goto map_err; 893 mapped: 894 *ccountp = 1; 895 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size); 896 break; 897 case PX_DMAI_FLAGS_BYPASS: 898 case PX_DMAI_FLAGS_PTP: 899 if (ret = px_dma_physwin(px_p, dmareq, mp)) 900 goto map_err; 901 *ccountp = PX_WINLST(mp)->win_ncookies; 902 *cookiep = 903 *(ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); /* wholeobj */ 904 break; 905 default: 906 cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type", 907 ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 908 /*NOTREACHED*/ 909 } 910 DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n", 911 cookiep->dmac_address, cookiep->dmac_size); 912 px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 913 914 /* insert dma handle into FMA cache */ 915 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) 916 (void) ndi_fmc_insert(rdip, DMA_HANDLE, mp, NULL); 917 918 return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 919 map_err: 920 px_dma_freepfn(mp); 921 err: 922 mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE; 923 return (ret); 924 } 925 926 927 /* 928 * bus dma unbind handle entry point: 929 */ 930 /*ARGSUSED*/ 931 int 932 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 933 { 934 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 935 px_t *px_p = DIP_TO_STATE(dip); 936 px_mmu_t *mmu_p = px_p->px_mmu_p; 937 938 DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n", 939 ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 940 if ((mp->dmai_flags & PX_DMAI_FLAGS_INUSE) == 0) { 941 DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n"); 942 return (DDI_FAILURE); 943 } 944 945 /* remove dma handle from FMA cache */ 946 if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) { 947 if (DEVI(rdip)->devi_fmhdl != NULL && 948 DDI_FM_DMA_ERR_CAP(DEVI(rdip)->devi_fmhdl->fh_cap)) { 949 (void) ndi_fmc_remove(rdip, DMA_HANDLE, mp); 950 } 951 } 952 953 /* 954 * Here if the handle is using the iommu. Unload all the iommu 955 * translations. 956 */ 957 switch (PX_DMA_TYPE(mp)) { 958 case PX_DMAI_FLAGS_DVMA: 959 px_mmu_unmap_window(mmu_p, mp); 960 px_dvma_unmap(mmu_p, mp); 961 px_dma_freepfn(mp); 962 break; 963 case PX_DMAI_FLAGS_BYPASS: 964 case PX_DMAI_FLAGS_PTP: 965 px_dma_freewin(mp); 966 break; 967 default: 968 cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p", 969 ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 970 /*NOTREACHED*/ 971 } 972 if (mmu_p->mmu_dvma_clid != 0) { 973 DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n"); 974 ddi_run_callback(&mmu_p->mmu_dvma_clid); 975 } 976 if (px_kmem_clid) { 977 DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n"); 978 ddi_run_callback(&px_kmem_clid); 979 } 980 mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE; 981 982 return (DDI_SUCCESS); 983 } 984 985 /* 986 * bus dma win entry point: 987 */ 988 int 989 px_dma_win(dev_info_t *dip, dev_info_t *rdip, 990 ddi_dma_handle_t handle, uint_t win, off_t *offp, 991 size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp) 992 { 993 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 994 int ret; 995 996 DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n", 997 ddi_driver_name(rdip), ddi_get_instance(rdip)); 998 999 px_dump_dma_handle(DBG_DMA_WIN, dip, mp); 1000 if (win >= mp->dmai_nwin) { 1001 DBG(DBG_DMA_WIN, dip, "%x out of range\n", win); 1002 return (DDI_FAILURE); 1003 } 1004 1005 switch (PX_DMA_TYPE(mp)) { 1006 case PX_DMAI_FLAGS_DVMA: 1007 if (win != PX_DMA_CURWIN(mp)) { 1008 px_t *px_p = DIP_TO_STATE(dip); 1009 px_mmu_t *mmu_p = px_p->px_mmu_p; 1010 px_mmu_unmap_window(mmu_p, mp); 1011 1012 /* map_window sets dmai_mapping/size/offset */ 1013 px_mmu_map_window(mmu_p, mp, win); 1014 if ((ret = px_mmu_map_window(mmu_p, 1015 mp, win)) != DDI_SUCCESS) 1016 return (ret); 1017 } 1018 if (cookiep) 1019 MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, 1020 mp->dmai_size); 1021 if (ccountp) 1022 *ccountp = 1; 1023 break; 1024 case PX_DMAI_FLAGS_PTP: 1025 case PX_DMAI_FLAGS_BYPASS: { 1026 int i; 1027 ddi_dma_cookie_t *ck_p; 1028 px_dma_win_t *win_p = mp->dmai_winlst; 1029 1030 for (i = 0; i < win; win_p = win_p->win_next, i++); 1031 ck_p = (ddi_dma_cookie_t *)(win_p + 1); 1032 *cookiep = *ck_p; 1033 mp->dmai_offset = win_p->win_offset; 1034 mp->dmai_size = win_p->win_size; 1035 mp->dmai_mapping = ck_p->dmac_laddress; 1036 mp->dmai_cookie = ck_p + 1; 1037 win_p->win_curseg = 0; 1038 if (ccountp) 1039 *ccountp = win_p->win_ncookies; 1040 } 1041 break; 1042 default: 1043 cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x", 1044 ddi_driver_name(rdip), ddi_get_instance(rdip), 1045 PX_DMA_TYPE(mp)); 1046 return (DDI_FAILURE); 1047 } 1048 if (cookiep) 1049 DBG(DBG_DMA_WIN, dip, 1050 "cookie - dmac_address=%x dmac_size=%x\n", 1051 cookiep->dmac_address, cookiep->dmac_size); 1052 if (offp) 1053 *offp = (off_t)mp->dmai_offset; 1054 if (lenp) 1055 *lenp = mp->dmai_size; 1056 return (DDI_SUCCESS); 1057 } 1058 1059 #ifdef DEBUG 1060 static char *px_dmactl_str[] = { 1061 "DDI_DMA_FREE", 1062 "DDI_DMA_SYNC", 1063 "DDI_DMA_HTOC", 1064 "DDI_DMA_KVADDR", 1065 "DDI_DMA_MOVWIN", 1066 "DDI_DMA_REPWIN", 1067 "DDI_DMA_GETERR", 1068 "DDI_DMA_COFF", 1069 "DDI_DMA_NEXTWIN", 1070 "DDI_DMA_NEXTSEG", 1071 "DDI_DMA_SEGTOC", 1072 "DDI_DMA_RESERVE", 1073 "DDI_DMA_RELEASE", 1074 "DDI_DMA_RESETH", 1075 "DDI_DMA_CKSYNC", 1076 "DDI_DMA_IOPB_ALLOC", 1077 "DDI_DMA_IOPB_FREE", 1078 "DDI_DMA_SMEM_ALLOC", 1079 "DDI_DMA_SMEM_FREE", 1080 "DDI_DMA_SET_SBUS64" 1081 }; 1082 #endif /* DEBUG */ 1083 1084 /* 1085 * bus dma control entry point: 1086 */ 1087 /*ARGSUSED*/ 1088 int 1089 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 1090 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1091 uint_t cache_flags) 1092 { 1093 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 1094 1095 #ifdef DEBUG 1096 DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd], 1097 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1098 #endif /* DEBUG */ 1099 1100 switch (cmd) { 1101 case DDI_DMA_FREE: 1102 (void) px_dma_unbindhdl(dip, rdip, handle); 1103 (void) px_dma_freehdl(dip, rdip, handle); 1104 return (DDI_SUCCESS); 1105 case DDI_DMA_RESERVE: { 1106 px_t *px_p = DIP_TO_STATE(dip); 1107 return (px_fdvma_reserve(dip, rdip, px_p, 1108 (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp)); 1109 } 1110 case DDI_DMA_RELEASE: { 1111 px_t *px_p = DIP_TO_STATE(dip); 1112 return (px_fdvma_release(dip, px_p, mp)); 1113 } 1114 default: 1115 break; 1116 } 1117 1118 switch (PX_DMA_TYPE(mp)) { 1119 case PX_DMAI_FLAGS_DVMA: 1120 return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 1121 cache_flags)); 1122 case PX_DMAI_FLAGS_PTP: 1123 case PX_DMAI_FLAGS_BYPASS: 1124 return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 1125 cache_flags)); 1126 default: 1127 cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x", 1128 ddi_driver_name(rdip), ddi_get_instance(rdip), cmd, 1129 mp->dmai_flags); 1130 /*NOTREACHED*/ 1131 } 1132 return (0); 1133 } 1134 1135 /* 1136 * control ops entry point: 1137 * 1138 * Requests handled completely: 1139 * DDI_CTLOPS_INITCHILD see init_child() for details 1140 * DDI_CTLOPS_UNINITCHILD 1141 * DDI_CTLOPS_REPORTDEV see report_dev() for details 1142 * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1 1143 * DDI_CTLOPS_REGSIZE 1144 * DDI_CTLOPS_NREGS 1145 * DDI_CTLOPS_DVMAPAGESIZE 1146 * DDI_CTLOPS_POKE 1147 * DDI_CTLOPS_PEEK 1148 * 1149 * All others passed to parent. 1150 */ 1151 int 1152 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 1153 ddi_ctl_enum_t op, void *arg, void *result) 1154 { 1155 px_t *px_p = DIP_TO_STATE(dip); 1156 struct detachspec *ds; 1157 struct attachspec *as; 1158 1159 switch (op) { 1160 case DDI_CTLOPS_INITCHILD: 1161 return (px_init_child(px_p, (dev_info_t *)arg)); 1162 1163 case DDI_CTLOPS_UNINITCHILD: 1164 return (px_uninit_child(px_p, (dev_info_t *)arg)); 1165 1166 case DDI_CTLOPS_ATTACH: 1167 as = (struct attachspec *)arg; 1168 switch (as->when) { 1169 case DDI_PRE: 1170 if (as->cmd == DDI_ATTACH) { 1171 DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n", 1172 ddi_driver_name(rdip), 1173 ddi_get_instance(rdip)); 1174 return (pcie_pm_hold(dip)); 1175 } 1176 if (as->cmd == DDI_RESUME) { 1177 ddi_acc_handle_t config_handle; 1178 DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n", 1179 ddi_driver_name(rdip), 1180 ddi_get_instance(rdip)); 1181 1182 if (pci_config_setup(rdip, &config_handle) == 1183 DDI_SUCCESS) { 1184 pcie_clear_errors(rdip, config_handle); 1185 pci_config_teardown(&config_handle); 1186 } 1187 } 1188 return (DDI_SUCCESS); 1189 1190 case DDI_POST: 1191 DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n", 1192 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1193 if (as->cmd == DDI_ATTACH && as->result != DDI_SUCCESS) 1194 pcie_pm_release(dip); 1195 return (DDI_SUCCESS); 1196 default: 1197 break; 1198 } 1199 break; 1200 1201 case DDI_CTLOPS_DETACH: 1202 ds = (struct detachspec *)arg; 1203 switch (ds->when) { 1204 case DDI_POST: 1205 if (ds->cmd == DDI_DETACH && 1206 ds->result == DDI_SUCCESS) { 1207 DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n", 1208 ddi_driver_name(rdip), 1209 ddi_get_instance(rdip)); 1210 return (pcie_pm_remove_child(dip, rdip)); 1211 } 1212 return (DDI_SUCCESS); 1213 default: 1214 break; 1215 } 1216 break; 1217 1218 case DDI_CTLOPS_REPORTDEV: 1219 return (px_report_dev(rdip)); 1220 1221 case DDI_CTLOPS_IOMIN: 1222 return (DDI_SUCCESS); 1223 1224 case DDI_CTLOPS_REGSIZE: 1225 *((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg)); 1226 return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS); 1227 1228 case DDI_CTLOPS_NREGS: 1229 *((uint_t *)result) = px_get_nreg_set(rdip); 1230 return (DDI_SUCCESS); 1231 1232 case DDI_CTLOPS_DVMAPAGESIZE: 1233 *((ulong_t *)result) = MMU_PAGE_SIZE; 1234 return (DDI_SUCCESS); 1235 1236 case DDI_CTLOPS_POKE: /* platform dependent implementation. */ 1237 return (px_lib_ctlops_poke(dip, rdip, 1238 (peekpoke_ctlops_t *)arg)); 1239 1240 case DDI_CTLOPS_PEEK: /* platform dependent implementation. */ 1241 return (px_lib_ctlops_peek(dip, rdip, 1242 (peekpoke_ctlops_t *)arg, result)); 1243 1244 case DDI_CTLOPS_POWER: 1245 default: 1246 break; 1247 } 1248 1249 /* 1250 * Now pass the request up to our parent. 1251 */ 1252 DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n", 1253 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1254 return (ddi_ctlops(dip, rdip, op, arg, result)); 1255 } 1256 1257 /* ARGSUSED */ 1258 int 1259 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1260 ddi_intr_handle_impl_t *hdlp, void *result) 1261 { 1262 int intr_types, ret = DDI_SUCCESS; 1263 1264 DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n", 1265 ddi_driver_name(rdip), ddi_get_instance(rdip)); 1266 1267 /* Process DDI_INTROP_SUPPORTED_TYPES request here */ 1268 if (intr_op == DDI_INTROP_SUPPORTED_TYPES) { 1269 *(int *)result = i_ddi_get_nintrs(rdip) ? 1270 DDI_INTR_TYPE_FIXED : 0; 1271 1272 if ((pci_msi_get_supported_type(rdip, 1273 &intr_types)) == DDI_SUCCESS) { 1274 /* 1275 * Double check supported interrupt types vs. 1276 * what the host bridge supports. 1277 * 1278 * NOTE: 1279 * Currently MSI-X is disabled since px driver 1280 * don't fully support this feature. 1281 */ 1282 *(int *)result |= (intr_types & DDI_INTR_TYPE_MSI); 1283 } 1284 1285 return (ret); 1286 } 1287 1288 /* 1289 * PCI-E nexus driver supports fixed, MSI and MSI-X interrupts. 1290 * Return failure if interrupt type is not supported. 1291 */ 1292 switch (hdlp->ih_type) { 1293 case DDI_INTR_TYPE_FIXED: 1294 ret = px_intx_ops(dip, rdip, intr_op, hdlp, result); 1295 break; 1296 case DDI_INTR_TYPE_MSI: 1297 case DDI_INTR_TYPE_MSIX: 1298 ret = px_msix_ops(dip, rdip, intr_op, hdlp, result); 1299 break; 1300 default: 1301 ret = DDI_ENOTSUP; 1302 break; 1303 } 1304 1305 return (ret); 1306 } 1307