17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57aadd8d4Skini * Common Development and Distribution License (the "License"). 67aadd8d4Skini * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 21788cfa89SDavid Woods 227c478bd9Sstevel@tonic-gate /* 23788cfa89SDavid Woods * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate /* 2726947304SEvan Yan * SPARC Host to PCI Express nexus driver 287c478bd9Sstevel@tonic-gate */ 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #include <sys/types.h> 317c478bd9Sstevel@tonic-gate #include <sys/conf.h> /* nulldev */ 327c478bd9Sstevel@tonic-gate #include <sys/stat.h> /* devctl */ 337c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 347c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 357c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 367c478bd9Sstevel@tonic-gate #include <sys/ddi_subrdefs.h> 371a887b2eSjchu #include <sys/spl.h> 387c478bd9Sstevel@tonic-gate #include <sys/epm.h> 397c478bd9Sstevel@tonic-gate #include <sys/iommutsb.h> 407c478bd9Sstevel@tonic-gate #include "px_obj.h" 4126947304SEvan Yan #include <sys/hotplug/pci/pcie_hp.h> 4269cd775fSschwartz #include <sys/pci_tools.h> 43d4476ccbSschwartz #include "px_tools_ext.h" 44d4bc0535SKrishna Elango #include <sys/pcie_pwr.h> 45c0da6274SZhi-Jun Robin Fu #include <sys/pci_cfgacc.h> 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 487c478bd9Sstevel@tonic-gate 497c478bd9Sstevel@tonic-gate /* 507c478bd9Sstevel@tonic-gate * function prototypes for dev ops routines: 517c478bd9Sstevel@tonic-gate */ 527c478bd9Sstevel@tonic-gate static int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 537c478bd9Sstevel@tonic-gate static int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 54*e6b21d58SErwin T Tsaur static int px_enable_err_intr(px_t *px_p); 55*e6b21d58SErwin T Tsaur static void px_disable_err_intr(px_t *px_p); 567c478bd9Sstevel@tonic-gate static int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 577c478bd9Sstevel@tonic-gate void *arg, void **result); 5801689544Sjchu static int px_cb_attach(px_t *); 597c478bd9Sstevel@tonic-gate static int px_pwr_setup(dev_info_t *dip); 607c478bd9Sstevel@tonic-gate static void px_pwr_teardown(dev_info_t *dip); 610114761dSAlan Adamson, SD OSSD static void px_set_mps(px_t *px_p); 620114761dSAlan Adamson, SD OSSD 63c0da6274SZhi-Jun Robin Fu extern void pci_cfgacc_acc(pci_cfgacc_req_t *); 640114761dSAlan Adamson, SD OSSD extern int pcie_max_mps; 65c0da6274SZhi-Jun Robin Fu extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *); 667c478bd9Sstevel@tonic-gate /* 677c478bd9Sstevel@tonic-gate * bus ops and dev ops structures: 687c478bd9Sstevel@tonic-gate */ 697c478bd9Sstevel@tonic-gate static struct bus_ops px_bus_ops = { 707c478bd9Sstevel@tonic-gate BUSO_REV, 717c478bd9Sstevel@tonic-gate px_map, 727c478bd9Sstevel@tonic-gate 0, 737c478bd9Sstevel@tonic-gate 0, 747c478bd9Sstevel@tonic-gate 0, 757c478bd9Sstevel@tonic-gate i_ddi_map_fault, 767c478bd9Sstevel@tonic-gate px_dma_setup, 777c478bd9Sstevel@tonic-gate px_dma_allochdl, 787c478bd9Sstevel@tonic-gate px_dma_freehdl, 797c478bd9Sstevel@tonic-gate px_dma_bindhdl, 807c478bd9Sstevel@tonic-gate px_dma_unbindhdl, 817c478bd9Sstevel@tonic-gate px_lib_dma_sync, 827c478bd9Sstevel@tonic-gate px_dma_win, 837c478bd9Sstevel@tonic-gate px_dma_ctlops, 847c478bd9Sstevel@tonic-gate px_ctlops, 857c478bd9Sstevel@tonic-gate ddi_bus_prop_op, 867c478bd9Sstevel@tonic-gate ndi_busop_get_eventcookie, 877c478bd9Sstevel@tonic-gate ndi_busop_add_eventcall, 887c478bd9Sstevel@tonic-gate ndi_busop_remove_eventcall, 897c478bd9Sstevel@tonic-gate ndi_post_event, 907c478bd9Sstevel@tonic-gate NULL, 917c478bd9Sstevel@tonic-gate NULL, /* (*bus_config)(); */ 927c478bd9Sstevel@tonic-gate NULL, /* (*bus_unconfig)(); */ 937c478bd9Sstevel@tonic-gate px_fm_init_child, /* (*bus_fm_init)(); */ 947c478bd9Sstevel@tonic-gate NULL, /* (*bus_fm_fini)(); */ 95f8d2de6bSjchu px_bus_enter, /* (*bus_fm_access_enter)(); */ 96f8d2de6bSjchu px_bus_exit, /* (*bus_fm_access_fini)(); */ 977c478bd9Sstevel@tonic-gate pcie_bus_power, /* (*bus_power)(); */ 9826947304SEvan Yan px_intr_ops, /* (*bus_intr_op)(); */ 9926947304SEvan Yan pcie_hp_common_ops /* (*bus_hp_op)(); */ 1007c478bd9Sstevel@tonic-gate }; 1017c478bd9Sstevel@tonic-gate 1027c478bd9Sstevel@tonic-gate extern struct cb_ops px_cb_ops; 1037c478bd9Sstevel@tonic-gate 1047c478bd9Sstevel@tonic-gate static struct dev_ops px_ops = { 1057c478bd9Sstevel@tonic-gate DEVO_REV, 1067c478bd9Sstevel@tonic-gate 0, 1077c478bd9Sstevel@tonic-gate px_info, 1087c478bd9Sstevel@tonic-gate nulldev, 1097c478bd9Sstevel@tonic-gate 0, 1107c478bd9Sstevel@tonic-gate px_attach, 1117c478bd9Sstevel@tonic-gate px_detach, 1127c478bd9Sstevel@tonic-gate nodev, 1137c478bd9Sstevel@tonic-gate &px_cb_ops, 1147c478bd9Sstevel@tonic-gate &px_bus_ops, 11519397407SSherry Moore nulldev, 11619397407SSherry Moore ddi_quiesce_not_needed, /* quiesce */ 1177c478bd9Sstevel@tonic-gate }; 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate /* 1207c478bd9Sstevel@tonic-gate * module definitions: 1217c478bd9Sstevel@tonic-gate */ 1227c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 1237c478bd9Sstevel@tonic-gate extern struct mod_ops mod_driverops; 1247c478bd9Sstevel@tonic-gate 1257c478bd9Sstevel@tonic-gate static struct modldrv modldrv = { 1267c478bd9Sstevel@tonic-gate &mod_driverops, /* Type of module - driver */ 12726947304SEvan Yan #if defined(sun4u) 12826947304SEvan Yan "Sun4u Host to PCIe nexus driver", /* Name of module. */ 12926947304SEvan Yan #elif defined(sun4v) 13026947304SEvan Yan "Sun4v Host to PCIe nexus driver", /* Name of module. */ 13126947304SEvan Yan #endif 1327c478bd9Sstevel@tonic-gate &px_ops, /* driver ops */ 1337c478bd9Sstevel@tonic-gate }; 1347c478bd9Sstevel@tonic-gate 1357c478bd9Sstevel@tonic-gate static struct modlinkage modlinkage = { 1367c478bd9Sstevel@tonic-gate MODREV_1, (void *)&modldrv, NULL 1377c478bd9Sstevel@tonic-gate }; 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate /* driver soft state */ 1407c478bd9Sstevel@tonic-gate void *px_state_p; 1417c478bd9Sstevel@tonic-gate 142788cfa89SDavid Woods int px_force_intx_support = 1; 143788cfa89SDavid Woods 1447c478bd9Sstevel@tonic-gate int 1457c478bd9Sstevel@tonic-gate _init(void) 1467c478bd9Sstevel@tonic-gate { 1477c478bd9Sstevel@tonic-gate int e; 1487c478bd9Sstevel@tonic-gate 1497c478bd9Sstevel@tonic-gate /* 1507c478bd9Sstevel@tonic-gate * Initialize per-px bus soft state pointer. 1517c478bd9Sstevel@tonic-gate */ 1527c478bd9Sstevel@tonic-gate e = ddi_soft_state_init(&px_state_p, sizeof (px_t), 1); 1537c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS) 1547c478bd9Sstevel@tonic-gate return (e); 1557c478bd9Sstevel@tonic-gate 1567c478bd9Sstevel@tonic-gate /* 1577c478bd9Sstevel@tonic-gate * Install the module. 1587c478bd9Sstevel@tonic-gate */ 1597c478bd9Sstevel@tonic-gate e = mod_install(&modlinkage); 1607c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS) 1617c478bd9Sstevel@tonic-gate ddi_soft_state_fini(&px_state_p); 1627c478bd9Sstevel@tonic-gate return (e); 1637c478bd9Sstevel@tonic-gate } 1647c478bd9Sstevel@tonic-gate 1657c478bd9Sstevel@tonic-gate int 1667c478bd9Sstevel@tonic-gate _fini(void) 1677c478bd9Sstevel@tonic-gate { 1687c478bd9Sstevel@tonic-gate int e; 1697c478bd9Sstevel@tonic-gate 1707c478bd9Sstevel@tonic-gate /* 1717c478bd9Sstevel@tonic-gate * Remove the module. 1727c478bd9Sstevel@tonic-gate */ 1737c478bd9Sstevel@tonic-gate e = mod_remove(&modlinkage); 1747c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS) 1757c478bd9Sstevel@tonic-gate return (e); 1767c478bd9Sstevel@tonic-gate 1777c478bd9Sstevel@tonic-gate /* Free px soft state */ 1787c478bd9Sstevel@tonic-gate ddi_soft_state_fini(&px_state_p); 1797c478bd9Sstevel@tonic-gate 1807c478bd9Sstevel@tonic-gate return (e); 1817c478bd9Sstevel@tonic-gate } 1827c478bd9Sstevel@tonic-gate 1837c478bd9Sstevel@tonic-gate int 1847c478bd9Sstevel@tonic-gate _info(struct modinfo *modinfop) 1857c478bd9Sstevel@tonic-gate { 1867c478bd9Sstevel@tonic-gate return (mod_info(&modlinkage, modinfop)); 1877c478bd9Sstevel@tonic-gate } 1887c478bd9Sstevel@tonic-gate 1897c478bd9Sstevel@tonic-gate /* ARGSUSED */ 1907c478bd9Sstevel@tonic-gate static int 1917c478bd9Sstevel@tonic-gate px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 1927c478bd9Sstevel@tonic-gate { 19326947304SEvan Yan minor_t minor = getminor((dev_t)arg); 19426947304SEvan Yan int instance = PCI_MINOR_NUM_TO_INSTANCE(minor); 1957c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(instance); 19626947304SEvan Yan int ret = DDI_SUCCESS; 1977c478bd9Sstevel@tonic-gate 1987c478bd9Sstevel@tonic-gate switch (infocmd) { 1997c478bd9Sstevel@tonic-gate case DDI_INFO_DEVT2INSTANCE: 200b40cec45Skrishnae *result = (void *)(intptr_t)instance; 20126947304SEvan Yan break; 2027c478bd9Sstevel@tonic-gate case DDI_INFO_DEVT2DEVINFO: 20326947304SEvan Yan if (px_p == NULL) { 20426947304SEvan Yan ret = DDI_FAILURE; 20526947304SEvan Yan break; 2067c478bd9Sstevel@tonic-gate } 20726947304SEvan Yan 20826947304SEvan Yan *result = (void *)px_p->px_dip; 20926947304SEvan Yan break; 21026947304SEvan Yan default: 21126947304SEvan Yan ret = DDI_FAILURE; 21226947304SEvan Yan break; 21326947304SEvan Yan } 21426947304SEvan Yan 21526947304SEvan Yan return (ret); 2167c478bd9Sstevel@tonic-gate } 2177c478bd9Sstevel@tonic-gate 2187c478bd9Sstevel@tonic-gate /* device driver entry points */ 2197c478bd9Sstevel@tonic-gate /* 2207c478bd9Sstevel@tonic-gate * attach entry point: 2217c478bd9Sstevel@tonic-gate */ 2227c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 2237c478bd9Sstevel@tonic-gate static int 2247c478bd9Sstevel@tonic-gate px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 2257c478bd9Sstevel@tonic-gate { 2267c478bd9Sstevel@tonic-gate px_t *px_p; /* per bus state pointer */ 2277c478bd9Sstevel@tonic-gate int instance = DIP_TO_INST(dip); 2287c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 2297c478bd9Sstevel@tonic-gate devhandle_t dev_hdl = NULL; 23026947304SEvan Yan pcie_hp_regops_t regops; 231c0da6274SZhi-Jun Robin Fu pcie_bus_t *bus_p; 2327c478bd9Sstevel@tonic-gate 2337c478bd9Sstevel@tonic-gate switch (cmd) { 2347c478bd9Sstevel@tonic-gate case DDI_ATTACH: 2357c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "DDI_ATTACH\n"); 2367c478bd9Sstevel@tonic-gate 237c0da6274SZhi-Jun Robin Fu /* See pci_cfgacc.c */ 238c0da6274SZhi-Jun Robin Fu pci_cfgacc_acc_p = pci_cfgacc_acc; 239c0da6274SZhi-Jun Robin Fu 2407c478bd9Sstevel@tonic-gate /* 2417c478bd9Sstevel@tonic-gate * Allocate and get the per-px soft state structure. 2427c478bd9Sstevel@tonic-gate */ 2437c478bd9Sstevel@tonic-gate if (ddi_soft_state_zalloc(px_state_p, instance) 2447c478bd9Sstevel@tonic-gate != DDI_SUCCESS) { 2457c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: can't allocate px state", 2467c478bd9Sstevel@tonic-gate ddi_driver_name(dip), instance); 2477c478bd9Sstevel@tonic-gate goto err_bad_px_softstate; 2487c478bd9Sstevel@tonic-gate } 2497c478bd9Sstevel@tonic-gate px_p = INST_TO_STATE(instance); 2507c478bd9Sstevel@tonic-gate px_p->px_dip = dip; 2517c478bd9Sstevel@tonic-gate mutex_init(&px_p->px_mutex, NULL, MUTEX_DRIVER, NULL); 25226947304SEvan Yan px_p->px_soft_state = PCI_SOFT_STATE_CLOSED; 2537c478bd9Sstevel@tonic-gate 254b65731f1Skini (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, 255b65731f1Skini "device_type", "pciex"); 256bf8fc234Set142600 257bf8fc234Set142600 /* Initialize px_dbg for high pil printing */ 258bf8fc234Set142600 px_dbg_attach(dip, &px_p->px_dbg_hdl); 25926947304SEvan Yan pcie_rc_init_bus(dip); 260bf8fc234Set142600 2617c478bd9Sstevel@tonic-gate /* 2627c478bd9Sstevel@tonic-gate * Get key properties of the pci bridge node and 2637c478bd9Sstevel@tonic-gate * determine it's type (psycho, schizo, etc ...). 2647c478bd9Sstevel@tonic-gate */ 2657c478bd9Sstevel@tonic-gate if (px_get_props(px_p, dip) == DDI_FAILURE) 2667c478bd9Sstevel@tonic-gate goto err_bad_px_prop; 2677c478bd9Sstevel@tonic-gate 2687c478bd9Sstevel@tonic-gate if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS) 2697c478bd9Sstevel@tonic-gate goto err_bad_dev_init; 2707c478bd9Sstevel@tonic-gate 27120036fe5Segillett /* Initialize device handle */ 2727c478bd9Sstevel@tonic-gate px_p->px_dev_hdl = dev_hdl; 2737c478bd9Sstevel@tonic-gate 2747ea9b230Set142600 /* Cache the BDF of the root port nexus */ 2757ea9b230Set142600 px_p->px_bdf = px_lib_get_bdf(px_p); 2767ea9b230Set142600 2777c478bd9Sstevel@tonic-gate /* 2787c478bd9Sstevel@tonic-gate * Initialize interrupt block. Note that this 2797c478bd9Sstevel@tonic-gate * initialize error handling for the PEC as well. 2807c478bd9Sstevel@tonic-gate */ 2817c478bd9Sstevel@tonic-gate if ((ret = px_ib_attach(px_p)) != DDI_SUCCESS) 2827c478bd9Sstevel@tonic-gate goto err_bad_ib; 2837c478bd9Sstevel@tonic-gate 2847c478bd9Sstevel@tonic-gate if (px_cb_attach(px_p) != DDI_SUCCESS) 2857c478bd9Sstevel@tonic-gate goto err_bad_cb; 2867c478bd9Sstevel@tonic-gate 2877c478bd9Sstevel@tonic-gate /* 2887c478bd9Sstevel@tonic-gate * Start creating the modules. 2897c478bd9Sstevel@tonic-gate * Note that attach() routines should 2907c478bd9Sstevel@tonic-gate * register and enable their own interrupts. 2917c478bd9Sstevel@tonic-gate */ 2927c478bd9Sstevel@tonic-gate 2937c478bd9Sstevel@tonic-gate if ((px_mmu_attach(px_p)) != DDI_SUCCESS) 2947c478bd9Sstevel@tonic-gate goto err_bad_mmu; 2957c478bd9Sstevel@tonic-gate 2967c478bd9Sstevel@tonic-gate if ((px_msiq_attach(px_p)) != DDI_SUCCESS) 2977c478bd9Sstevel@tonic-gate goto err_bad_msiq; 2987c478bd9Sstevel@tonic-gate 2997c478bd9Sstevel@tonic-gate if ((px_msi_attach(px_p)) != DDI_SUCCESS) 3007c478bd9Sstevel@tonic-gate goto err_bad_msi; 3017c478bd9Sstevel@tonic-gate 3027c478bd9Sstevel@tonic-gate if ((px_pec_attach(px_p)) != DDI_SUCCESS) 3037c478bd9Sstevel@tonic-gate goto err_bad_pec; 3047c478bd9Sstevel@tonic-gate 3057c478bd9Sstevel@tonic-gate if ((px_dma_attach(px_p)) != DDI_SUCCESS) 3069c81f298Sjchu goto err_bad_dma; /* nothing to uninitialize on DMA */ 3077c478bd9Sstevel@tonic-gate 3083c4226f9Spjha if ((px_fm_attach(px_p)) != DDI_SUCCESS) 3093c4226f9Spjha goto err_bad_dma; 3103c4226f9Spjha 3117c478bd9Sstevel@tonic-gate /* 3127c478bd9Sstevel@tonic-gate * All of the error handlers have been registered 313*e6b21d58SErwin T Tsaur * by now so it's time to activate all the interrupt. 3147c478bd9Sstevel@tonic-gate */ 315*e6b21d58SErwin T Tsaur if ((px_enable_err_intr(px_p)) != DDI_SUCCESS) 3163c4226f9Spjha goto err_bad_intr; 3177c478bd9Sstevel@tonic-gate 31826947304SEvan Yan if (px_lib_hotplug_init(dip, (void *)®ops) == DDI_SUCCESS) { 31926947304SEvan Yan pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 32026947304SEvan Yan 32126947304SEvan Yan bus_p->bus_hp_sup_modes |= PCIE_NATIVE_HP_MODE; 32226947304SEvan Yan } 323b65731f1Skini 3240114761dSAlan Adamson, SD OSSD (void) px_set_mps(px_p); 3250114761dSAlan Adamson, SD OSSD 32626947304SEvan Yan if (pcie_init(dip, (caddr_t)®ops) != DDI_SUCCESS) 32726947304SEvan Yan goto err_bad_hotplug; 32869cd775fSschwartz 32970f83219SEvan Yan (void) pcie_hpintr_enable(dip); 33070f83219SEvan Yan 33169cd775fSschwartz if (pxtool_init(dip) != DDI_SUCCESS) 33269cd775fSschwartz goto err_bad_pcitool_node; 33369cd775fSschwartz 3347c478bd9Sstevel@tonic-gate /* 3357c478bd9Sstevel@tonic-gate * power management setup. Even if it fails, attach will 3367c478bd9Sstevel@tonic-gate * succeed as this is a optional feature. Since we are 3377c478bd9Sstevel@tonic-gate * always at full power, this is not critical. 3387c478bd9Sstevel@tonic-gate */ 3397c478bd9Sstevel@tonic-gate if (pwr_common_setup(dip) != DDI_SUCCESS) { 3407c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "pwr_common_setup failed\n"); 3417c478bd9Sstevel@tonic-gate } else if (px_pwr_setup(dip) != DDI_SUCCESS) { 3427c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "px_pwr_setup failed \n"); 3437c478bd9Sstevel@tonic-gate pwr_common_teardown(dip); 3447c478bd9Sstevel@tonic-gate } 3457c478bd9Sstevel@tonic-gate 346817a6df8Sjchu /* 347817a6df8Sjchu * add cpr callback 348817a6df8Sjchu */ 349817a6df8Sjchu px_cpr_add_callb(px_p); 350817a6df8Sjchu 351fc256490SJason Beloro /* 352fc256490SJason Beloro * do fabric sync in case we don't need to wait for 353fc256490SJason Beloro * any bridge driver to be ready 354fc256490SJason Beloro */ 355fc256490SJason Beloro (void) px_lib_fabric_sync(dip); 356fc256490SJason Beloro 3577c478bd9Sstevel@tonic-gate ddi_report_dev(dip); 3587c478bd9Sstevel@tonic-gate 3597c478bd9Sstevel@tonic-gate px_p->px_state = PX_ATTACHED; 360c0da6274SZhi-Jun Robin Fu 361c0da6274SZhi-Jun Robin Fu /* 362c0da6274SZhi-Jun Robin Fu * save base addr in bus_t for pci_cfgacc_xxx(), this 363c0da6274SZhi-Jun Robin Fu * depends of px structure being properly initialized. 364c0da6274SZhi-Jun Robin Fu */ 365c0da6274SZhi-Jun Robin Fu bus_p = PCIE_DIP2BUS(dip); 366c0da6274SZhi-Jun Robin Fu bus_p->bus_cfgacc_base = px_lib_get_cfgacc_base(dip); 367c0da6274SZhi-Jun Robin Fu 368c0da6274SZhi-Jun Robin Fu /* 369c0da6274SZhi-Jun Robin Fu * Partially populate bus_t for all devices in this fabric 370c0da6274SZhi-Jun Robin Fu * for device type macros to work. 371c0da6274SZhi-Jun Robin Fu */ 372c0da6274SZhi-Jun Robin Fu /* 373c0da6274SZhi-Jun Robin Fu * Populate bus_t for all devices in this fabric, after FMA 374c0da6274SZhi-Jun Robin Fu * is initializated, so that config access errors could 375c0da6274SZhi-Jun Robin Fu * trigger panic. 376c0da6274SZhi-Jun Robin Fu */ 377c0da6274SZhi-Jun Robin Fu pcie_fab_init_bus(dip, PCIE_BUS_ALL); 378c0da6274SZhi-Jun Robin Fu 3797c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "attach success\n"); 3807c478bd9Sstevel@tonic-gate break; 3817c478bd9Sstevel@tonic-gate 38269cd775fSschwartz err_bad_pcitool_node: 38370f83219SEvan Yan (void) pcie_hpintr_disable(dip); 38426947304SEvan Yan (void) pcie_uninit(dip); 38526947304SEvan Yan err_bad_hotplug: 38626947304SEvan Yan (void) px_lib_hotplug_uninit(dip); 387*e6b21d58SErwin T Tsaur px_disable_err_intr(px_p); 3883c4226f9Spjha err_bad_intr: 3893c4226f9Spjha px_fm_detach(px_p); 3909c81f298Sjchu err_bad_dma: 3917c478bd9Sstevel@tonic-gate px_pec_detach(px_p); 3927c478bd9Sstevel@tonic-gate err_bad_pec: 3937c478bd9Sstevel@tonic-gate px_msi_detach(px_p); 3947c478bd9Sstevel@tonic-gate err_bad_msi: 3957c478bd9Sstevel@tonic-gate px_msiq_detach(px_p); 3967c478bd9Sstevel@tonic-gate err_bad_msiq: 3977c478bd9Sstevel@tonic-gate px_mmu_detach(px_p); 3987c478bd9Sstevel@tonic-gate err_bad_mmu: 3997c478bd9Sstevel@tonic-gate err_bad_cb: 4007c478bd9Sstevel@tonic-gate px_ib_detach(px_p); 4017c478bd9Sstevel@tonic-gate err_bad_ib: 402d8d130aeSanbui if (px_lib_dev_fini(dip) != DDI_SUCCESS) { 403d8d130aeSanbui DBG(DBG_ATTACH, dip, "px_lib_dev_fini failed\n"); 404d8d130aeSanbui } 4057c478bd9Sstevel@tonic-gate err_bad_dev_init: 4067c478bd9Sstevel@tonic-gate px_free_props(px_p); 4077c478bd9Sstevel@tonic-gate err_bad_px_prop: 40826947304SEvan Yan pcie_rc_fini_bus(dip); 409bf8fc234Set142600 px_dbg_detach(dip, &px_p->px_dbg_hdl); 4107c478bd9Sstevel@tonic-gate mutex_destroy(&px_p->px_mutex); 4117c478bd9Sstevel@tonic-gate ddi_soft_state_free(px_state_p, instance); 4127c478bd9Sstevel@tonic-gate err_bad_px_softstate: 4137c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 4147c478bd9Sstevel@tonic-gate break; 4157c478bd9Sstevel@tonic-gate 4167c478bd9Sstevel@tonic-gate case DDI_RESUME: 4177c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "DDI_RESUME\n"); 4187c478bd9Sstevel@tonic-gate 4197c478bd9Sstevel@tonic-gate px_p = INST_TO_STATE(instance); 4207c478bd9Sstevel@tonic-gate 4217c478bd9Sstevel@tonic-gate mutex_enter(&px_p->px_mutex); 4227c478bd9Sstevel@tonic-gate 4237c478bd9Sstevel@tonic-gate /* suspend might have not succeeded */ 4247c478bd9Sstevel@tonic-gate if (px_p->px_state != PX_SUSPENDED) { 4257c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, px_p->px_dip, 4267c478bd9Sstevel@tonic-gate "instance NOT suspended\n"); 4277c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 4287c478bd9Sstevel@tonic-gate break; 4297c478bd9Sstevel@tonic-gate } 4307c478bd9Sstevel@tonic-gate 431023ccc1eSegillett px_msiq_resume(px_p); 4327c478bd9Sstevel@tonic-gate px_lib_resume(dip); 4337c478bd9Sstevel@tonic-gate (void) pcie_pwr_resume(dip); 4347c478bd9Sstevel@tonic-gate px_p->px_state = PX_ATTACHED; 4357c478bd9Sstevel@tonic-gate 4367c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 4377c478bd9Sstevel@tonic-gate 4387c478bd9Sstevel@tonic-gate break; 4397c478bd9Sstevel@tonic-gate default: 4407c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "unsupported attach op\n"); 4417c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 4427c478bd9Sstevel@tonic-gate break; 4437c478bd9Sstevel@tonic-gate } 4447c478bd9Sstevel@tonic-gate 4457c478bd9Sstevel@tonic-gate return (ret); 4467c478bd9Sstevel@tonic-gate } 4477c478bd9Sstevel@tonic-gate 4487c478bd9Sstevel@tonic-gate /* 4497c478bd9Sstevel@tonic-gate * detach entry point: 4507c478bd9Sstevel@tonic-gate */ 4517c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 4527c478bd9Sstevel@tonic-gate static int 4537c478bd9Sstevel@tonic-gate px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 4547c478bd9Sstevel@tonic-gate { 4557c478bd9Sstevel@tonic-gate int instance = ddi_get_instance(dip); 4567c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(instance); 45726947304SEvan Yan pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 4587c478bd9Sstevel@tonic-gate int ret; 4597c478bd9Sstevel@tonic-gate 4607c478bd9Sstevel@tonic-gate /* 4617c478bd9Sstevel@tonic-gate * Make sure we are currently attached 4627c478bd9Sstevel@tonic-gate */ 4637c478bd9Sstevel@tonic-gate if (px_p->px_state != PX_ATTACHED) { 46401689544Sjchu DBG(DBG_DETACH, dip, "Instance not attached\n"); 4657c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 4667c478bd9Sstevel@tonic-gate } 4677c478bd9Sstevel@tonic-gate 4687c478bd9Sstevel@tonic-gate mutex_enter(&px_p->px_mutex); 4697c478bd9Sstevel@tonic-gate 4707c478bd9Sstevel@tonic-gate switch (cmd) { 4717c478bd9Sstevel@tonic-gate case DDI_DETACH: 4727c478bd9Sstevel@tonic-gate DBG(DBG_DETACH, dip, "DDI_DETACH\n"); 4737c478bd9Sstevel@tonic-gate 474817a6df8Sjchu /* 475817a6df8Sjchu * remove cpr callback 476817a6df8Sjchu */ 477817a6df8Sjchu px_cpr_rem_callb(px_p); 478817a6df8Sjchu 47970f83219SEvan Yan (void) pcie_hpintr_disable(dip); 48070f83219SEvan Yan 48126947304SEvan Yan if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) 48226947304SEvan Yan (void) px_lib_hotplug_uninit(dip); 48326947304SEvan Yan 48426947304SEvan Yan if (pcie_uninit(dip) != DDI_SUCCESS) { 4857c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 4867c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 4877c478bd9Sstevel@tonic-gate } 4887c478bd9Sstevel@tonic-gate 489c0da6274SZhi-Jun Robin Fu /* Destroy bus_t for the whole fabric */ 490c0da6274SZhi-Jun Robin Fu pcie_fab_fini_bus(dip, PCIE_BUS_ALL); 491c0da6274SZhi-Jun Robin Fu 4927c478bd9Sstevel@tonic-gate /* 4937c478bd9Sstevel@tonic-gate * things which used to be done in obj_destroy 4947c478bd9Sstevel@tonic-gate * are now in-lined here. 4957c478bd9Sstevel@tonic-gate */ 4967c478bd9Sstevel@tonic-gate 4977c478bd9Sstevel@tonic-gate px_p->px_state = PX_DETACHED; 4987c478bd9Sstevel@tonic-gate 49969cd775fSschwartz pxtool_uninit(dip); 50069cd775fSschwartz 501*e6b21d58SErwin T Tsaur px_disable_err_intr(px_p); 5023c4226f9Spjha px_fm_detach(px_p); 5037c478bd9Sstevel@tonic-gate px_pec_detach(px_p); 5049c75c6bfSgovinda px_pwr_teardown(dip); 5059c75c6bfSgovinda pwr_common_teardown(dip); 5067c478bd9Sstevel@tonic-gate px_msi_detach(px_p); 5077c478bd9Sstevel@tonic-gate px_msiq_detach(px_p); 5087c478bd9Sstevel@tonic-gate px_mmu_detach(px_p); 5097c478bd9Sstevel@tonic-gate px_ib_detach(px_p); 510d8d130aeSanbui if (px_lib_dev_fini(dip) != DDI_SUCCESS) { 511d8d130aeSanbui DBG(DBG_DETACH, dip, "px_lib_dev_fini failed\n"); 512d8d130aeSanbui } 5137c478bd9Sstevel@tonic-gate 5147c478bd9Sstevel@tonic-gate /* 5157c478bd9Sstevel@tonic-gate * Free the px soft state structure and the rest of the 5167c478bd9Sstevel@tonic-gate * resources it's using. 5177c478bd9Sstevel@tonic-gate */ 5187c478bd9Sstevel@tonic-gate px_free_props(px_p); 51926947304SEvan Yan pcie_rc_fini_bus(dip); 520bf8fc234Set142600 px_dbg_detach(dip, &px_p->px_dbg_hdl); 5217c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 5227c478bd9Sstevel@tonic-gate mutex_destroy(&px_p->px_mutex); 5237c478bd9Sstevel@tonic-gate 5247c478bd9Sstevel@tonic-gate px_p->px_dev_hdl = NULL; 525dabea0dbSschwartz ddi_soft_state_free(px_state_p, instance); 5267c478bd9Sstevel@tonic-gate 5277c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5287c478bd9Sstevel@tonic-gate 5297c478bd9Sstevel@tonic-gate case DDI_SUSPEND: 5307c478bd9Sstevel@tonic-gate if (pcie_pwr_suspend(dip) != DDI_SUCCESS) { 5317c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 5327c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 5337c478bd9Sstevel@tonic-gate } 5347c478bd9Sstevel@tonic-gate if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS) 5357c478bd9Sstevel@tonic-gate px_p->px_state = PX_SUSPENDED; 5367c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 5377c478bd9Sstevel@tonic-gate 5387c478bd9Sstevel@tonic-gate return (ret); 5397c478bd9Sstevel@tonic-gate 5407c478bd9Sstevel@tonic-gate default: 5417c478bd9Sstevel@tonic-gate DBG(DBG_DETACH, dip, "unsupported detach op\n"); 5427c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 5437c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 5447c478bd9Sstevel@tonic-gate } 5457c478bd9Sstevel@tonic-gate } 5467c478bd9Sstevel@tonic-gate 547*e6b21d58SErwin T Tsaur static int 548*e6b21d58SErwin T Tsaur px_enable_err_intr(px_t *px_p) 549*e6b21d58SErwin T Tsaur { 550*e6b21d58SErwin T Tsaur /* Add FMA Callback handler for failed PIO Loads */ 551*e6b21d58SErwin T Tsaur px_fm_cb_enable(px_p); 552*e6b21d58SErwin T Tsaur 553*e6b21d58SErwin T Tsaur /* Add Common Block mondo handler */ 554*e6b21d58SErwin T Tsaur if (px_cb_add_intr(&px_p->px_cb_fault) != DDI_SUCCESS) 555*e6b21d58SErwin T Tsaur goto cb_bad; 556*e6b21d58SErwin T Tsaur 557*e6b21d58SErwin T Tsaur /* Add PEU Block Mondo Handler */ 558*e6b21d58SErwin T Tsaur if (px_err_add_intr(&px_p->px_fault) != DDI_SUCCESS) 559*e6b21d58SErwin T Tsaur goto peu_bad; 560*e6b21d58SErwin T Tsaur 561*e6b21d58SErwin T Tsaur /* Enable interrupt handler for PCIE Fabric Error Messages */ 562*e6b21d58SErwin T Tsaur if (px_pec_msg_add_intr(px_p) != DDI_SUCCESS) 563*e6b21d58SErwin T Tsaur goto msg_bad; 564*e6b21d58SErwin T Tsaur 565*e6b21d58SErwin T Tsaur return (DDI_SUCCESS); 566*e6b21d58SErwin T Tsaur 567*e6b21d58SErwin T Tsaur msg_bad: 568*e6b21d58SErwin T Tsaur px_err_rem_intr(&px_p->px_fault); 569*e6b21d58SErwin T Tsaur peu_bad: 570*e6b21d58SErwin T Tsaur px_cb_rem_intr(&px_p->px_cb_fault); 571*e6b21d58SErwin T Tsaur cb_bad: 572*e6b21d58SErwin T Tsaur px_fm_cb_disable(px_p); 573*e6b21d58SErwin T Tsaur 574*e6b21d58SErwin T Tsaur return (DDI_FAILURE); 575*e6b21d58SErwin T Tsaur } 576*e6b21d58SErwin T Tsaur 577*e6b21d58SErwin T Tsaur static void 578*e6b21d58SErwin T Tsaur px_disable_err_intr(px_t *px_p) 579*e6b21d58SErwin T Tsaur { 580*e6b21d58SErwin T Tsaur px_pec_msg_rem_intr(px_p); 581*e6b21d58SErwin T Tsaur px_err_rem_intr(&px_p->px_fault); 582*e6b21d58SErwin T Tsaur px_cb_rem_intr(&px_p->px_cb_fault); 583*e6b21d58SErwin T Tsaur px_fm_cb_disable(px_p); 584*e6b21d58SErwin T Tsaur } 585*e6b21d58SErwin T Tsaur 58601689544Sjchu int 58701689544Sjchu px_cb_attach(px_t *px_p) 58801689544Sjchu { 58901689544Sjchu px_fault_t *fault_p = &px_p->px_cb_fault; 59001689544Sjchu dev_info_t *dip = px_p->px_dip; 59101689544Sjchu sysino_t sysino; 59201689544Sjchu 59301689544Sjchu if (px_lib_intr_devino_to_sysino(dip, 59401689544Sjchu px_p->px_inos[PX_INTR_XBC], &sysino) != DDI_SUCCESS) 59501689544Sjchu return (DDI_FAILURE); 59601689544Sjchu 59701689544Sjchu fault_p->px_fh_dip = dip; 59801689544Sjchu fault_p->px_fh_sysino = sysino; 59901689544Sjchu fault_p->px_err_func = px_err_cb_intr; 60001689544Sjchu fault_p->px_intr_ino = px_p->px_inos[PX_INTR_XBC]; 60101689544Sjchu 602*e6b21d58SErwin T Tsaur return (DDI_SUCCESS); 60301689544Sjchu } 60401689544Sjchu 6057c478bd9Sstevel@tonic-gate /* 6067c478bd9Sstevel@tonic-gate * power management related initialization specific to px 6077c478bd9Sstevel@tonic-gate * called by px_attach() 6087c478bd9Sstevel@tonic-gate */ 6097c478bd9Sstevel@tonic-gate static int 6107c478bd9Sstevel@tonic-gate px_pwr_setup(dev_info_t *dip) 6117c478bd9Sstevel@tonic-gate { 6127c478bd9Sstevel@tonic-gate pcie_pwr_t *pwr_p; 6131a887b2eSjchu int instance = ddi_get_instance(dip); 6141a887b2eSjchu px_t *px_p = INST_TO_STATE(instance); 6157c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t hdl; 6167c478bd9Sstevel@tonic-gate 6177c478bd9Sstevel@tonic-gate ASSERT(PCIE_PMINFO(dip)); 6187c478bd9Sstevel@tonic-gate pwr_p = PCIE_NEXUS_PMINFO(dip); 6197c478bd9Sstevel@tonic-gate ASSERT(pwr_p); 6207c478bd9Sstevel@tonic-gate 6217c478bd9Sstevel@tonic-gate /* 6227c478bd9Sstevel@tonic-gate * indicate support LDI (Layered Driver Interface) 6237c478bd9Sstevel@tonic-gate * Create the property, if it is not already there 6247c478bd9Sstevel@tonic-gate */ 6257c478bd9Sstevel@tonic-gate if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 6267c478bd9Sstevel@tonic-gate DDI_KERNEL_IOCTL)) { 6277c478bd9Sstevel@tonic-gate if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 6287c478bd9Sstevel@tonic-gate DDI_KERNEL_IOCTL, NULL, 0) != DDI_PROP_SUCCESS) { 6297c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n"); 6307c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 6317c478bd9Sstevel@tonic-gate } 6327c478bd9Sstevel@tonic-gate } 6337c478bd9Sstevel@tonic-gate /* No support for device PM. We are always at full power */ 6347c478bd9Sstevel@tonic-gate pwr_p->pwr_func_lvl = PM_LEVEL_D0; 6357c478bd9Sstevel@tonic-gate 6361a887b2eSjchu mutex_init(&px_p->px_l23ready_lock, NULL, MUTEX_DRIVER, 637a195726fSgovinda DDI_INTR_PRI(px_pwr_pil)); 6381a887b2eSjchu cv_init(&px_p->px_l23ready_cv, NULL, CV_DRIVER, NULL); 6391a887b2eSjchu 64020036fe5Segillett /* Initialize handle */ 64120036fe5Segillett bzero(&hdl, sizeof (ddi_intr_handle_impl_t)); 6421a887b2eSjchu hdl.ih_cb_arg1 = px_p; 6437c478bd9Sstevel@tonic-gate hdl.ih_ver = DDI_INTR_VERSION; 6447c478bd9Sstevel@tonic-gate hdl.ih_state = DDI_IHDL_STATE_ALLOC; 6457c478bd9Sstevel@tonic-gate hdl.ih_dip = dip; 6467c478bd9Sstevel@tonic-gate hdl.ih_pri = px_pwr_pil; 6477c478bd9Sstevel@tonic-gate 6487c478bd9Sstevel@tonic-gate /* Add PME_TO_ACK message handler */ 6491a887b2eSjchu hdl.ih_cb_func = (ddi_intr_handler_t *)px_pmeq_intr; 6507c478bd9Sstevel@tonic-gate if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC, 65109b1eac2SEvan Yan (msgcode_t)PCIE_PME_ACK_MSG, -1, 65209b1eac2SEvan Yan &px_p->px_pm_msiq_id) != DDI_SUCCESS) { 6531a887b2eSjchu DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add " 6541a887b2eSjchu " PME_TO_ACK intr\n"); 655f9721e07Sjchu goto pwr_setup_err1; 6567c478bd9Sstevel@tonic-gate } 6571a887b2eSjchu px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id); 6587c478bd9Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID); 6597c478bd9Sstevel@tonic-gate 66036fe4a92Segillett if (px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 661b0fc0e77Sgovinda px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), px_pwr_pil, 66236fe4a92Segillett PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) { 66336fe4a92Segillett DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt" 66436fe4a92Segillett " state failed\n"); 66536fe4a92Segillett goto px_pwrsetup_err_state; 66636fe4a92Segillett } 66736fe4a92Segillett 6687c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 6697c478bd9Sstevel@tonic-gate 67036fe4a92Segillett px_pwrsetup_err_state: 67136fe4a92Segillett px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 67236fe4a92Segillett (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 67336fe4a92Segillett px_p->px_pm_msiq_id); 6741a887b2eSjchu pwr_setup_err1: 6751a887b2eSjchu mutex_destroy(&px_p->px_l23ready_lock); 6761a887b2eSjchu cv_destroy(&px_p->px_l23ready_cv); 6771a887b2eSjchu 6787c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 6797c478bd9Sstevel@tonic-gate } 6807c478bd9Sstevel@tonic-gate 6817c478bd9Sstevel@tonic-gate /* 6827c478bd9Sstevel@tonic-gate * undo whatever is done in px_pwr_setup. called by px_detach() 6837c478bd9Sstevel@tonic-gate */ 6847c478bd9Sstevel@tonic-gate static void 6857c478bd9Sstevel@tonic-gate px_pwr_teardown(dev_info_t *dip) 6867c478bd9Sstevel@tonic-gate { 6871a887b2eSjchu int instance = ddi_get_instance(dip); 6881a887b2eSjchu px_t *px_p = INST_TO_STATE(instance); 6897c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t hdl; 6907c478bd9Sstevel@tonic-gate 6911a887b2eSjchu if (!PCIE_PMINFO(dip) || !PCIE_NEXUS_PMINFO(dip)) 6927c478bd9Sstevel@tonic-gate return; 6937c478bd9Sstevel@tonic-gate 69420036fe5Segillett /* Initialize handle */ 69520036fe5Segillett bzero(&hdl, sizeof (ddi_intr_handle_impl_t)); 6967c478bd9Sstevel@tonic-gate hdl.ih_ver = DDI_INTR_VERSION; 6977c478bd9Sstevel@tonic-gate hdl.ih_state = DDI_IHDL_STATE_ALLOC; 6987c478bd9Sstevel@tonic-gate hdl.ih_dip = dip; 699665a7fcaSgovinda hdl.ih_pri = px_pwr_pil; 7007c478bd9Sstevel@tonic-gate 7017c478bd9Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 7027c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 7031a887b2eSjchu px_p->px_pm_msiq_id); 7047c478bd9Sstevel@tonic-gate 70536fe4a92Segillett (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 706b0fc0e77Sgovinda px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), px_pwr_pil, 70736fe4a92Segillett PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG); 70836fe4a92Segillett 709055d7c80Scarlsonj px_p->px_pm_msiq_id = (msiqid_t)-1; 7107c478bd9Sstevel@tonic-gate 7111a887b2eSjchu cv_destroy(&px_p->px_l23ready_cv); 7121a887b2eSjchu mutex_destroy(&px_p->px_l23ready_lock); 7137c478bd9Sstevel@tonic-gate } 7147c478bd9Sstevel@tonic-gate 7157c478bd9Sstevel@tonic-gate /* bus driver entry points */ 7167c478bd9Sstevel@tonic-gate 7177c478bd9Sstevel@tonic-gate /* 7187c478bd9Sstevel@tonic-gate * bus map entry point: 7197c478bd9Sstevel@tonic-gate * 7207c478bd9Sstevel@tonic-gate * if map request is for an rnumber 7217c478bd9Sstevel@tonic-gate * get the corresponding regspec from device node 7227c478bd9Sstevel@tonic-gate * build a new regspec in our parent's format 7237c478bd9Sstevel@tonic-gate * build a new map_req with the new regspec 7247c478bd9Sstevel@tonic-gate * call up the tree to complete the mapping 7257c478bd9Sstevel@tonic-gate */ 7267c478bd9Sstevel@tonic-gate int 7277c478bd9Sstevel@tonic-gate px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 7287c478bd9Sstevel@tonic-gate off_t off, off_t len, caddr_t *addrp) 7297c478bd9Sstevel@tonic-gate { 7307c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 7317c478bd9Sstevel@tonic-gate struct regspec p_regspec; 7327c478bd9Sstevel@tonic-gate ddi_map_req_t p_mapreq; 7337c478bd9Sstevel@tonic-gate int reglen, rval, r_no; 7347c478bd9Sstevel@tonic-gate pci_regspec_t reloc_reg, *rp = &reloc_reg; 7357c478bd9Sstevel@tonic-gate 7367c478bd9Sstevel@tonic-gate DBG(DBG_MAP, dip, "rdip=%s%d:", 7377c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 7387c478bd9Sstevel@tonic-gate 7397c478bd9Sstevel@tonic-gate if (mp->map_flags & DDI_MF_USER_MAPPING) 7407c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED); 7417c478bd9Sstevel@tonic-gate 7427c478bd9Sstevel@tonic-gate switch (mp->map_type) { 7437c478bd9Sstevel@tonic-gate case DDI_MT_REGSPEC: 7447c478bd9Sstevel@tonic-gate reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */ 7457c478bd9Sstevel@tonic-gate break; 7467c478bd9Sstevel@tonic-gate 7477c478bd9Sstevel@tonic-gate case DDI_MT_RNUMBER: 7487c478bd9Sstevel@tonic-gate r_no = mp->map_obj.rnumber; 7497c478bd9Sstevel@tonic-gate DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no); 7507c478bd9Sstevel@tonic-gate 751a3282898Scth if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 7527c478bd9Sstevel@tonic-gate "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS) 7537c478bd9Sstevel@tonic-gate return (DDI_ME_RNUMBER_RANGE); 7547c478bd9Sstevel@tonic-gate 7557c478bd9Sstevel@tonic-gate if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) { 7567c478bd9Sstevel@tonic-gate kmem_free(rp, reglen); 7577c478bd9Sstevel@tonic-gate return (DDI_ME_RNUMBER_RANGE); 7587c478bd9Sstevel@tonic-gate } 7597c478bd9Sstevel@tonic-gate rp += r_no; 7607c478bd9Sstevel@tonic-gate break; 7617c478bd9Sstevel@tonic-gate 7627c478bd9Sstevel@tonic-gate default: 7637c478bd9Sstevel@tonic-gate return (DDI_ME_INVAL); 7647c478bd9Sstevel@tonic-gate } 7657c478bd9Sstevel@tonic-gate DBG(DBG_MAP | DBG_CONT, dip, "\n"); 7667c478bd9Sstevel@tonic-gate 7677c478bd9Sstevel@tonic-gate if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) { 7687c478bd9Sstevel@tonic-gate /* 7697c478bd9Sstevel@tonic-gate * There may be a need to differentiate between PCI 7707c478bd9Sstevel@tonic-gate * and PCI-Ex devices so the following range check is 7717c478bd9Sstevel@tonic-gate * done correctly, depending on the implementation of 772d4bc0535SKrishna Elango * pcieb bridge nexus driver. 7737c478bd9Sstevel@tonic-gate */ 7747c478bd9Sstevel@tonic-gate if ((off >= PCIE_CONF_HDR_SIZE) || 7757c478bd9Sstevel@tonic-gate (len > PCIE_CONF_HDR_SIZE) || 7767c478bd9Sstevel@tonic-gate (off + len > PCIE_CONF_HDR_SIZE)) 7777c478bd9Sstevel@tonic-gate return (DDI_ME_INVAL); 7787c478bd9Sstevel@tonic-gate /* 7797c478bd9Sstevel@tonic-gate * the following function returning a DDI_FAILURE assumes 7807c478bd9Sstevel@tonic-gate * that there are no virtual config space access services 7817c478bd9Sstevel@tonic-gate * defined in this layer. Otherwise it is availed right 7827c478bd9Sstevel@tonic-gate * here and we return. 7837c478bd9Sstevel@tonic-gate */ 7847c478bd9Sstevel@tonic-gate rval = px_lib_map_vconfig(dip, mp, off, rp, addrp); 7857c478bd9Sstevel@tonic-gate if (rval == DDI_SUCCESS) 7867c478bd9Sstevel@tonic-gate goto done; 7877c478bd9Sstevel@tonic-gate } 7887c478bd9Sstevel@tonic-gate 7897c478bd9Sstevel@tonic-gate /* 7907c478bd9Sstevel@tonic-gate * No virtual config space services or we are mapping 7917c478bd9Sstevel@tonic-gate * a region of memory mapped config/IO/memory space, so proceed 7927c478bd9Sstevel@tonic-gate * to the parent. 7937c478bd9Sstevel@tonic-gate */ 7947c478bd9Sstevel@tonic-gate 7957c478bd9Sstevel@tonic-gate /* relocate within 64-bit pci space through "assigned-addresses" */ 7967c478bd9Sstevel@tonic-gate if (rval = px_reloc_reg(dip, rdip, px_p, rp)) 7977c478bd9Sstevel@tonic-gate goto done; 7987c478bd9Sstevel@tonic-gate 7997c478bd9Sstevel@tonic-gate if (len) /* adjust regspec according to mapping request */ 8007c478bd9Sstevel@tonic-gate rp->pci_size_low = len; /* MIN ? */ 8017c478bd9Sstevel@tonic-gate rp->pci_phys_low += off; 8027c478bd9Sstevel@tonic-gate 8037c478bd9Sstevel@tonic-gate /* translate relocated pci regspec into parent space through "ranges" */ 8047c478bd9Sstevel@tonic-gate if (rval = px_xlate_reg(px_p, rp, &p_regspec)) 8057c478bd9Sstevel@tonic-gate goto done; 8067c478bd9Sstevel@tonic-gate 8077c478bd9Sstevel@tonic-gate p_mapreq = *mp; /* dup the whole structure */ 8087c478bd9Sstevel@tonic-gate p_mapreq.map_type = DDI_MT_REGSPEC; 8097c478bd9Sstevel@tonic-gate p_mapreq.map_obj.rp = &p_regspec; 8104fbb58f6Sjchu px_lib_map_attr_check(&p_mapreq); 8117c478bd9Sstevel@tonic-gate rval = ddi_map(dip, &p_mapreq, 0, 0, addrp); 8127c478bd9Sstevel@tonic-gate 8137c478bd9Sstevel@tonic-gate if (rval == DDI_SUCCESS) { 8147c478bd9Sstevel@tonic-gate /* 8157c478bd9Sstevel@tonic-gate * Set-up access functions for FM access error capable drivers. 8167c478bd9Sstevel@tonic-gate */ 817eae2e508Skrishnae if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip))) 818eae2e508Skrishnae px_fm_acc_setup(mp, rdip, rp); 8197c478bd9Sstevel@tonic-gate } 8207c478bd9Sstevel@tonic-gate 8217c478bd9Sstevel@tonic-gate done: 8227c478bd9Sstevel@tonic-gate if (mp->map_type == DDI_MT_RNUMBER) 8237c478bd9Sstevel@tonic-gate kmem_free(rp - r_no, reglen); 8247c478bd9Sstevel@tonic-gate 8257c478bd9Sstevel@tonic-gate return (rval); 8267c478bd9Sstevel@tonic-gate } 8277c478bd9Sstevel@tonic-gate 8287c478bd9Sstevel@tonic-gate /* 8297c478bd9Sstevel@tonic-gate * bus dma map entry point 8307c478bd9Sstevel@tonic-gate * return value: 8317c478bd9Sstevel@tonic-gate * DDI_DMA_PARTIAL_MAP 1 8327c478bd9Sstevel@tonic-gate * DDI_DMA_MAPOK 0 8337c478bd9Sstevel@tonic-gate * DDI_DMA_MAPPED 0 8347c478bd9Sstevel@tonic-gate * DDI_DMA_NORESOURCES -1 8357c478bd9Sstevel@tonic-gate * DDI_DMA_NOMAPPING -2 8367c478bd9Sstevel@tonic-gate * DDI_DMA_TOOBIG -3 8377c478bd9Sstevel@tonic-gate */ 8387c478bd9Sstevel@tonic-gate int 8397c478bd9Sstevel@tonic-gate px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq, 8407c478bd9Sstevel@tonic-gate ddi_dma_handle_t *handlep) 8417c478bd9Sstevel@tonic-gate { 8427c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 8437c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p; 8447c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp; 8457c478bd9Sstevel@tonic-gate int ret; 8467c478bd9Sstevel@tonic-gate 8477c478bd9Sstevel@tonic-gate DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n", 8487c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), 8497c478bd9Sstevel@tonic-gate handlep ? "alloc" : "advisory"); 8507c478bd9Sstevel@tonic-gate 8517c478bd9Sstevel@tonic-gate if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq))) 8527c478bd9Sstevel@tonic-gate return (DDI_DMA_NORESOURCES); 8537c478bd9Sstevel@tonic-gate if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING) 8547c478bd9Sstevel@tonic-gate return (DDI_DMA_NOMAPPING); 8557c478bd9Sstevel@tonic-gate if (ret = px_dma_type(px_p, dmareq, mp)) 8567c478bd9Sstevel@tonic-gate goto freehandle; 8577c478bd9Sstevel@tonic-gate if (ret = px_dma_pfn(px_p, dmareq, mp)) 8587c478bd9Sstevel@tonic-gate goto freehandle; 8597c478bd9Sstevel@tonic-gate 8607c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 86136fe4a92Segillett case PX_DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 8627c478bd9Sstevel@tonic-gate if ((ret = px_dvma_win(px_p, dmareq, mp)) || !handlep) 8637c478bd9Sstevel@tonic-gate goto freehandle; 8647c478bd9Sstevel@tonic-gate if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 8657c478bd9Sstevel@tonic-gate if (PX_DMA_CANFAST(mp)) { 8667c478bd9Sstevel@tonic-gate if (!px_dvma_map_fast(mmu_p, mp)) 8677c478bd9Sstevel@tonic-gate break; 8687c478bd9Sstevel@tonic-gate /* LINTED E_NOP_ELSE_STMT */ 8697c478bd9Sstevel@tonic-gate } else { 8707c478bd9Sstevel@tonic-gate PX_DVMA_FASTTRAK_PROF(mp); 8717c478bd9Sstevel@tonic-gate } 8727c478bd9Sstevel@tonic-gate } 8737c478bd9Sstevel@tonic-gate if (ret = px_dvma_map(mp, dmareq, mmu_p)) 8747c478bd9Sstevel@tonic-gate goto freehandle; 8757c478bd9Sstevel@tonic-gate break; 87636fe4a92Segillett case PX_DMAI_FLAGS_PTP: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 8777c478bd9Sstevel@tonic-gate if ((ret = px_dma_physwin(px_p, dmareq, mp)) || !handlep) 8787c478bd9Sstevel@tonic-gate goto freehandle; 8797c478bd9Sstevel@tonic-gate break; 88036fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: 8817c478bd9Sstevel@tonic-gate default: 8827c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x", 8837c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), 8847c478bd9Sstevel@tonic-gate PX_DMA_TYPE(mp)); 8857c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 8867c478bd9Sstevel@tonic-gate } 8877c478bd9Sstevel@tonic-gate *handlep = (ddi_dma_handle_t)mp; 88836fe4a92Segillett mp->dmai_flags |= PX_DMAI_FLAGS_INUSE; 8897c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 8907c478bd9Sstevel@tonic-gate 8917c478bd9Sstevel@tonic-gate return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 8927c478bd9Sstevel@tonic-gate freehandle: 8937c478bd9Sstevel@tonic-gate if (ret == DDI_DMA_NORESOURCES) 8947c478bd9Sstevel@tonic-gate px_dma_freemp(mp); /* don't run_callback() */ 8957c478bd9Sstevel@tonic-gate else 8967c478bd9Sstevel@tonic-gate (void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 8977c478bd9Sstevel@tonic-gate return (ret); 8987c478bd9Sstevel@tonic-gate } 8997c478bd9Sstevel@tonic-gate 9007c478bd9Sstevel@tonic-gate 9017c478bd9Sstevel@tonic-gate /* 9027c478bd9Sstevel@tonic-gate * bus dma alloc handle entry point: 9037c478bd9Sstevel@tonic-gate */ 9047c478bd9Sstevel@tonic-gate int 9057c478bd9Sstevel@tonic-gate px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 9067c478bd9Sstevel@tonic-gate int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 9077c478bd9Sstevel@tonic-gate { 9087c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 9097c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp; 9107c478bd9Sstevel@tonic-gate int rval; 9117c478bd9Sstevel@tonic-gate 9127c478bd9Sstevel@tonic-gate DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", 9137c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 9147c478bd9Sstevel@tonic-gate 9157c478bd9Sstevel@tonic-gate if (attrp->dma_attr_version != DMA_ATTR_V0) 9167c478bd9Sstevel@tonic-gate return (DDI_DMA_BADATTR); 9177c478bd9Sstevel@tonic-gate 9187c478bd9Sstevel@tonic-gate if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg))) 9197c478bd9Sstevel@tonic-gate return (DDI_DMA_NORESOURCES); 9207c478bd9Sstevel@tonic-gate 9217c478bd9Sstevel@tonic-gate /* 9227c478bd9Sstevel@tonic-gate * Save requestor's information 9237c478bd9Sstevel@tonic-gate */ 9247c478bd9Sstevel@tonic-gate mp->dmai_attr = *attrp; /* whole object - augmented later */ 92536fe4a92Segillett *PX_DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */ 9267c478bd9Sstevel@tonic-gate DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp); 9277c478bd9Sstevel@tonic-gate 9287c478bd9Sstevel@tonic-gate /* check and convert dma attributes to handle parameters */ 9297c478bd9Sstevel@tonic-gate if (rval = px_dma_attr2hdl(px_p, mp)) { 9307c478bd9Sstevel@tonic-gate px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 9317c478bd9Sstevel@tonic-gate *handlep = NULL; 9327c478bd9Sstevel@tonic-gate return (rval); 9337c478bd9Sstevel@tonic-gate } 9347c478bd9Sstevel@tonic-gate *handlep = (ddi_dma_handle_t)mp; 9357c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 9367c478bd9Sstevel@tonic-gate } 9377c478bd9Sstevel@tonic-gate 9387c478bd9Sstevel@tonic-gate 9397c478bd9Sstevel@tonic-gate /* 9407c478bd9Sstevel@tonic-gate * bus dma free handle entry point: 9417c478bd9Sstevel@tonic-gate */ 9427c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 9437c478bd9Sstevel@tonic-gate int 9447c478bd9Sstevel@tonic-gate px_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 9457c478bd9Sstevel@tonic-gate { 9467c478bd9Sstevel@tonic-gate DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n", 9477c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 9487c478bd9Sstevel@tonic-gate px_dma_freemp((ddi_dma_impl_t *)handle); 9497c478bd9Sstevel@tonic-gate 9507c478bd9Sstevel@tonic-gate if (px_kmem_clid) { 9517c478bd9Sstevel@tonic-gate DBG(DBG_DMA_FREEH, dip, "run handle callback\n"); 9527c478bd9Sstevel@tonic-gate ddi_run_callback(&px_kmem_clid); 9537c478bd9Sstevel@tonic-gate } 9547c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 9557c478bd9Sstevel@tonic-gate } 9567c478bd9Sstevel@tonic-gate 9577c478bd9Sstevel@tonic-gate 9587c478bd9Sstevel@tonic-gate /* 9597c478bd9Sstevel@tonic-gate * bus dma bind handle entry point: 9607c478bd9Sstevel@tonic-gate */ 9617c478bd9Sstevel@tonic-gate int 9627c478bd9Sstevel@tonic-gate px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 9637c478bd9Sstevel@tonic-gate ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 9647c478bd9Sstevel@tonic-gate ddi_dma_cookie_t *cookiep, uint_t *ccountp) 9657c478bd9Sstevel@tonic-gate { 9667c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 9677c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p; 9687c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 9697c478bd9Sstevel@tonic-gate int ret; 9707c478bd9Sstevel@tonic-gate 9717c478bd9Sstevel@tonic-gate DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n", 9727c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq); 9737c478bd9Sstevel@tonic-gate 97436fe4a92Segillett if (mp->dmai_flags & PX_DMAI_FLAGS_INUSE) 9757c478bd9Sstevel@tonic-gate return (DDI_DMA_INUSE); 9767c478bd9Sstevel@tonic-gate 97736fe4a92Segillett ASSERT((mp->dmai_flags & ~PX_DMAI_FLAGS_PRESERVE) == 0); 97836fe4a92Segillett mp->dmai_flags |= PX_DMAI_FLAGS_INUSE; 9797c478bd9Sstevel@tonic-gate 9807c478bd9Sstevel@tonic-gate if (ret = px_dma_type(px_p, dmareq, mp)) 9817c478bd9Sstevel@tonic-gate goto err; 9827c478bd9Sstevel@tonic-gate if (ret = px_dma_pfn(px_p, dmareq, mp)) 9837c478bd9Sstevel@tonic-gate goto err; 9847c478bd9Sstevel@tonic-gate 9857c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 98636fe4a92Segillett case PX_DMAI_FLAGS_DVMA: 9877c478bd9Sstevel@tonic-gate if (ret = px_dvma_win(px_p, dmareq, mp)) 9887c478bd9Sstevel@tonic-gate goto map_err; 9897c478bd9Sstevel@tonic-gate if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 9907c478bd9Sstevel@tonic-gate if (PX_DMA_CANFAST(mp)) { 9917c478bd9Sstevel@tonic-gate if (!px_dvma_map_fast(mmu_p, mp)) 9927c478bd9Sstevel@tonic-gate goto mapped; /*LINTED E_NOP_ELSE_STMT*/ 9937c478bd9Sstevel@tonic-gate } else { 9947c478bd9Sstevel@tonic-gate PX_DVMA_FASTTRAK_PROF(mp); 9957c478bd9Sstevel@tonic-gate } 9967c478bd9Sstevel@tonic-gate } 9977c478bd9Sstevel@tonic-gate if (ret = px_dvma_map(mp, dmareq, mmu_p)) 9987c478bd9Sstevel@tonic-gate goto map_err; 9997c478bd9Sstevel@tonic-gate mapped: 10007c478bd9Sstevel@tonic-gate *ccountp = 1; 10017c478bd9Sstevel@tonic-gate MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size); 10027c478bd9Sstevel@tonic-gate break; 100336fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: 100436fe4a92Segillett case PX_DMAI_FLAGS_PTP: 10057c478bd9Sstevel@tonic-gate if (ret = px_dma_physwin(px_p, dmareq, mp)) 10067c478bd9Sstevel@tonic-gate goto map_err; 100736fe4a92Segillett *ccountp = PX_WINLST(mp)->win_ncookies; 100836fe4a92Segillett *cookiep = 100936fe4a92Segillett *(ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); /* wholeobj */ 10107c478bd9Sstevel@tonic-gate break; 10117c478bd9Sstevel@tonic-gate default: 10127c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type", 10137c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 10147c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 10157c478bd9Sstevel@tonic-gate } 101669cd775fSschwartz DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n", 101769cd775fSschwartz cookiep->dmac_address, cookiep->dmac_size); 10187c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 1019f8d2de6bSjchu 1020f8d2de6bSjchu /* insert dma handle into FMA cache */ 1021567c0b92SStephen Hanson if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) 1022eae2e508Skrishnae mp->dmai_error.err_cf = px_err_dma_hdl_check; 1023f8d2de6bSjchu 10247c478bd9Sstevel@tonic-gate return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 10257c478bd9Sstevel@tonic-gate map_err: 10267c478bd9Sstevel@tonic-gate px_dma_freepfn(mp); 10277c478bd9Sstevel@tonic-gate err: 102836fe4a92Segillett mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE; 10297c478bd9Sstevel@tonic-gate return (ret); 10307c478bd9Sstevel@tonic-gate } 10317c478bd9Sstevel@tonic-gate 10327c478bd9Sstevel@tonic-gate 10337c478bd9Sstevel@tonic-gate /* 10347c478bd9Sstevel@tonic-gate * bus dma unbind handle entry point: 10357c478bd9Sstevel@tonic-gate */ 10367c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 10377c478bd9Sstevel@tonic-gate int 10387c478bd9Sstevel@tonic-gate px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 10397c478bd9Sstevel@tonic-gate { 10407c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 10417c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 10427c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p; 10437c478bd9Sstevel@tonic-gate 10447c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n", 10457c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 104636fe4a92Segillett if ((mp->dmai_flags & PX_DMAI_FLAGS_INUSE) == 0) { 10477c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n"); 10487c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 10497c478bd9Sstevel@tonic-gate } 10507c478bd9Sstevel@tonic-gate 1051567c0b92SStephen Hanson mp->dmai_error.err_cf = NULL; 1052f8d2de6bSjchu 10537c478bd9Sstevel@tonic-gate /* 10547c478bd9Sstevel@tonic-gate * Here if the handle is using the iommu. Unload all the iommu 10557c478bd9Sstevel@tonic-gate * translations. 10567c478bd9Sstevel@tonic-gate */ 10577c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 105836fe4a92Segillett case PX_DMAI_FLAGS_DVMA: 10597c478bd9Sstevel@tonic-gate px_mmu_unmap_window(mmu_p, mp); 10607c478bd9Sstevel@tonic-gate px_dvma_unmap(mmu_p, mp); 10617c478bd9Sstevel@tonic-gate px_dma_freepfn(mp); 10627c478bd9Sstevel@tonic-gate break; 106336fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: 106436fe4a92Segillett case PX_DMAI_FLAGS_PTP: 10657c478bd9Sstevel@tonic-gate px_dma_freewin(mp); 10667c478bd9Sstevel@tonic-gate break; 10677c478bd9Sstevel@tonic-gate default: 10687c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p", 10697c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 10707c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 10717c478bd9Sstevel@tonic-gate } 10727c478bd9Sstevel@tonic-gate if (mmu_p->mmu_dvma_clid != 0) { 10737c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n"); 10747c478bd9Sstevel@tonic-gate ddi_run_callback(&mmu_p->mmu_dvma_clid); 10757c478bd9Sstevel@tonic-gate } 10767c478bd9Sstevel@tonic-gate if (px_kmem_clid) { 10777c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n"); 10787c478bd9Sstevel@tonic-gate ddi_run_callback(&px_kmem_clid); 10797c478bd9Sstevel@tonic-gate } 108036fe4a92Segillett mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE; 1081f8d2de6bSjchu 10827c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 10837c478bd9Sstevel@tonic-gate } 10847c478bd9Sstevel@tonic-gate 10857c478bd9Sstevel@tonic-gate /* 10867c478bd9Sstevel@tonic-gate * bus dma win entry point: 10877c478bd9Sstevel@tonic-gate */ 10887c478bd9Sstevel@tonic-gate int 10897c478bd9Sstevel@tonic-gate px_dma_win(dev_info_t *dip, dev_info_t *rdip, 10907c478bd9Sstevel@tonic-gate ddi_dma_handle_t handle, uint_t win, off_t *offp, 10917c478bd9Sstevel@tonic-gate size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp) 10927c478bd9Sstevel@tonic-gate { 10937c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 10947c478bd9Sstevel@tonic-gate int ret; 10957c478bd9Sstevel@tonic-gate 10967c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n", 10977c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 10987c478bd9Sstevel@tonic-gate 10997c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_WIN, dip, mp); 11007c478bd9Sstevel@tonic-gate if (win >= mp->dmai_nwin) { 11017c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip, "%x out of range\n", win); 11027c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 11037c478bd9Sstevel@tonic-gate } 11047c478bd9Sstevel@tonic-gate 11057c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 110636fe4a92Segillett case PX_DMAI_FLAGS_DVMA: 11077c478bd9Sstevel@tonic-gate if (win != PX_DMA_CURWIN(mp)) { 11087c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 11097c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p; 11107c478bd9Sstevel@tonic-gate px_mmu_unmap_window(mmu_p, mp); 11117c478bd9Sstevel@tonic-gate 11127c478bd9Sstevel@tonic-gate /* map_window sets dmai_mapping/size/offset */ 11137c478bd9Sstevel@tonic-gate px_mmu_map_window(mmu_p, mp, win); 11147c478bd9Sstevel@tonic-gate if ((ret = px_mmu_map_window(mmu_p, 11157c478bd9Sstevel@tonic-gate mp, win)) != DDI_SUCCESS) 11167c478bd9Sstevel@tonic-gate return (ret); 11177c478bd9Sstevel@tonic-gate } 11187c478bd9Sstevel@tonic-gate if (cookiep) 11197c478bd9Sstevel@tonic-gate MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, 11207c478bd9Sstevel@tonic-gate mp->dmai_size); 11217c478bd9Sstevel@tonic-gate if (ccountp) 11227c478bd9Sstevel@tonic-gate *ccountp = 1; 11237c478bd9Sstevel@tonic-gate break; 112436fe4a92Segillett case PX_DMAI_FLAGS_PTP: 112536fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: { 11267c478bd9Sstevel@tonic-gate int i; 11277c478bd9Sstevel@tonic-gate ddi_dma_cookie_t *ck_p; 11287c478bd9Sstevel@tonic-gate px_dma_win_t *win_p = mp->dmai_winlst; 11297c478bd9Sstevel@tonic-gate 1130eae2e508Skrishnae for (i = 0; i < win; win_p = win_p->win_next, i++) {}; 11317c478bd9Sstevel@tonic-gate ck_p = (ddi_dma_cookie_t *)(win_p + 1); 11327c478bd9Sstevel@tonic-gate *cookiep = *ck_p; 11337c478bd9Sstevel@tonic-gate mp->dmai_offset = win_p->win_offset; 11347c478bd9Sstevel@tonic-gate mp->dmai_size = win_p->win_size; 11357c478bd9Sstevel@tonic-gate mp->dmai_mapping = ck_p->dmac_laddress; 11367c478bd9Sstevel@tonic-gate mp->dmai_cookie = ck_p + 1; 11377c478bd9Sstevel@tonic-gate win_p->win_curseg = 0; 11387c478bd9Sstevel@tonic-gate if (ccountp) 11397c478bd9Sstevel@tonic-gate *ccountp = win_p->win_ncookies; 11407c478bd9Sstevel@tonic-gate } 11417c478bd9Sstevel@tonic-gate break; 11427c478bd9Sstevel@tonic-gate default: 11437c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x", 11447c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), 11457c478bd9Sstevel@tonic-gate PX_DMA_TYPE(mp)); 11467c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 11477c478bd9Sstevel@tonic-gate } 11487c478bd9Sstevel@tonic-gate if (cookiep) 11497c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip, 11507c478bd9Sstevel@tonic-gate "cookie - dmac_address=%x dmac_size=%x\n", 11517c478bd9Sstevel@tonic-gate cookiep->dmac_address, cookiep->dmac_size); 11527c478bd9Sstevel@tonic-gate if (offp) 11537c478bd9Sstevel@tonic-gate *offp = (off_t)mp->dmai_offset; 11547c478bd9Sstevel@tonic-gate if (lenp) 11557c478bd9Sstevel@tonic-gate *lenp = mp->dmai_size; 11567c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 11577c478bd9Sstevel@tonic-gate } 11587c478bd9Sstevel@tonic-gate 11597c478bd9Sstevel@tonic-gate #ifdef DEBUG 11607c478bd9Sstevel@tonic-gate static char *px_dmactl_str[] = { 11617c478bd9Sstevel@tonic-gate "DDI_DMA_FREE", 11627c478bd9Sstevel@tonic-gate "DDI_DMA_SYNC", 11637c478bd9Sstevel@tonic-gate "DDI_DMA_HTOC", 11647c478bd9Sstevel@tonic-gate "DDI_DMA_KVADDR", 11657c478bd9Sstevel@tonic-gate "DDI_DMA_MOVWIN", 11667c478bd9Sstevel@tonic-gate "DDI_DMA_REPWIN", 11677c478bd9Sstevel@tonic-gate "DDI_DMA_GETERR", 11687c478bd9Sstevel@tonic-gate "DDI_DMA_COFF", 11697c478bd9Sstevel@tonic-gate "DDI_DMA_NEXTWIN", 11707c478bd9Sstevel@tonic-gate "DDI_DMA_NEXTSEG", 11717c478bd9Sstevel@tonic-gate "DDI_DMA_SEGTOC", 11727c478bd9Sstevel@tonic-gate "DDI_DMA_RESERVE", 11737c478bd9Sstevel@tonic-gate "DDI_DMA_RELEASE", 11747c478bd9Sstevel@tonic-gate "DDI_DMA_RESETH", 11757c478bd9Sstevel@tonic-gate "DDI_DMA_CKSYNC", 11767c478bd9Sstevel@tonic-gate "DDI_DMA_IOPB_ALLOC", 11777c478bd9Sstevel@tonic-gate "DDI_DMA_IOPB_FREE", 11787c478bd9Sstevel@tonic-gate "DDI_DMA_SMEM_ALLOC", 11797c478bd9Sstevel@tonic-gate "DDI_DMA_SMEM_FREE", 11807c478bd9Sstevel@tonic-gate "DDI_DMA_SET_SBUS64" 11817c478bd9Sstevel@tonic-gate }; 11827c478bd9Sstevel@tonic-gate #endif /* DEBUG */ 11837c478bd9Sstevel@tonic-gate 11847c478bd9Sstevel@tonic-gate /* 11857c478bd9Sstevel@tonic-gate * bus dma control entry point: 11867c478bd9Sstevel@tonic-gate */ 11877c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 11887c478bd9Sstevel@tonic-gate int 11897c478bd9Sstevel@tonic-gate px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 11907c478bd9Sstevel@tonic-gate enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 11917c478bd9Sstevel@tonic-gate uint_t cache_flags) 11927c478bd9Sstevel@tonic-gate { 11937c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 11947c478bd9Sstevel@tonic-gate 11957c478bd9Sstevel@tonic-gate #ifdef DEBUG 11967c478bd9Sstevel@tonic-gate DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd], 11977c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 11987c478bd9Sstevel@tonic-gate #endif /* DEBUG */ 11997c478bd9Sstevel@tonic-gate 12007c478bd9Sstevel@tonic-gate switch (cmd) { 12017c478bd9Sstevel@tonic-gate case DDI_DMA_FREE: 12027c478bd9Sstevel@tonic-gate (void) px_dma_unbindhdl(dip, rdip, handle); 12037c478bd9Sstevel@tonic-gate (void) px_dma_freehdl(dip, rdip, handle); 12047c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12057c478bd9Sstevel@tonic-gate case DDI_DMA_RESERVE: { 12067c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 12077c478bd9Sstevel@tonic-gate return (px_fdvma_reserve(dip, rdip, px_p, 12087c478bd9Sstevel@tonic-gate (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp)); 12097c478bd9Sstevel@tonic-gate } 12107c478bd9Sstevel@tonic-gate case DDI_DMA_RELEASE: { 12117c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 12127c478bd9Sstevel@tonic-gate return (px_fdvma_release(dip, px_p, mp)); 12137c478bd9Sstevel@tonic-gate } 12147c478bd9Sstevel@tonic-gate default: 12157c478bd9Sstevel@tonic-gate break; 12167c478bd9Sstevel@tonic-gate } 12177c478bd9Sstevel@tonic-gate 12187c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 121936fe4a92Segillett case PX_DMAI_FLAGS_DVMA: 12207c478bd9Sstevel@tonic-gate return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 12217c478bd9Sstevel@tonic-gate cache_flags)); 122236fe4a92Segillett case PX_DMAI_FLAGS_PTP: 122336fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: 12247c478bd9Sstevel@tonic-gate return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 12257c478bd9Sstevel@tonic-gate cache_flags)); 12267c478bd9Sstevel@tonic-gate default: 12277c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x", 12287c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), cmd, 12297c478bd9Sstevel@tonic-gate mp->dmai_flags); 12307c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 12317c478bd9Sstevel@tonic-gate } 1232b40cec45Skrishnae return (0); 12337c478bd9Sstevel@tonic-gate } 12347c478bd9Sstevel@tonic-gate 12357c478bd9Sstevel@tonic-gate /* 12367c478bd9Sstevel@tonic-gate * control ops entry point: 12377c478bd9Sstevel@tonic-gate * 12387c478bd9Sstevel@tonic-gate * Requests handled completely: 12397c478bd9Sstevel@tonic-gate * DDI_CTLOPS_INITCHILD see init_child() for details 12407c478bd9Sstevel@tonic-gate * DDI_CTLOPS_UNINITCHILD 12417c478bd9Sstevel@tonic-gate * DDI_CTLOPS_REPORTDEV see report_dev() for details 12427c478bd9Sstevel@tonic-gate * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1 12437c478bd9Sstevel@tonic-gate * DDI_CTLOPS_REGSIZE 12447c478bd9Sstevel@tonic-gate * DDI_CTLOPS_NREGS 12457c478bd9Sstevel@tonic-gate * DDI_CTLOPS_DVMAPAGESIZE 12467c478bd9Sstevel@tonic-gate * DDI_CTLOPS_POKE 12477c478bd9Sstevel@tonic-gate * DDI_CTLOPS_PEEK 12487c478bd9Sstevel@tonic-gate * 12497c478bd9Sstevel@tonic-gate * All others passed to parent. 12507c478bd9Sstevel@tonic-gate */ 12517c478bd9Sstevel@tonic-gate int 12527c478bd9Sstevel@tonic-gate px_ctlops(dev_info_t *dip, dev_info_t *rdip, 12537c478bd9Sstevel@tonic-gate ddi_ctl_enum_t op, void *arg, void *result) 12547c478bd9Sstevel@tonic-gate { 12557c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 12567c478bd9Sstevel@tonic-gate struct detachspec *ds; 12577c478bd9Sstevel@tonic-gate struct attachspec *as; 12587c478bd9Sstevel@tonic-gate 12597c478bd9Sstevel@tonic-gate switch (op) { 12607c478bd9Sstevel@tonic-gate case DDI_CTLOPS_INITCHILD: 12617c478bd9Sstevel@tonic-gate return (px_init_child(px_p, (dev_info_t *)arg)); 12627c478bd9Sstevel@tonic-gate 12637c478bd9Sstevel@tonic-gate case DDI_CTLOPS_UNINITCHILD: 12647c478bd9Sstevel@tonic-gate return (px_uninit_child(px_p, (dev_info_t *)arg)); 12657c478bd9Sstevel@tonic-gate 12667c478bd9Sstevel@tonic-gate case DDI_CTLOPS_ATTACH: 12676e8a7b44Sjchu if (!pcie_is_child(dip, rdip)) 12686e8a7b44Sjchu return (DDI_SUCCESS); 12696e8a7b44Sjchu 12707c478bd9Sstevel@tonic-gate as = (struct attachspec *)arg; 12717c478bd9Sstevel@tonic-gate switch (as->when) { 12727c478bd9Sstevel@tonic-gate case DDI_PRE: 12737c478bd9Sstevel@tonic-gate if (as->cmd == DDI_ATTACH) { 12747c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n", 12757c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), 12767c478bd9Sstevel@tonic-gate ddi_get_instance(rdip)); 12777c478bd9Sstevel@tonic-gate return (pcie_pm_hold(dip)); 12787c478bd9Sstevel@tonic-gate } 12798bc7d88aSet142600 if (as->cmd == DDI_RESUME) { 12808bc7d88aSet142600 DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n", 12818bc7d88aSet142600 ddi_driver_name(rdip), 12828bc7d88aSet142600 ddi_get_instance(rdip)); 12838bc7d88aSet142600 1284eae2e508Skrishnae pcie_clear_errors(rdip); 12858bc7d88aSet142600 } 12867c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12877c478bd9Sstevel@tonic-gate 12887c478bd9Sstevel@tonic-gate case DDI_POST: 12897c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n", 12907c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 1291c2cc6e07SRamesh Chitrothu if (as->cmd == DDI_ATTACH && 1292c2cc6e07SRamesh Chitrothu as->result != DDI_SUCCESS) { 1293c2cc6e07SRamesh Chitrothu /* 1294c2cc6e07SRamesh Chitrothu * Attach failed for the child device. The child 1295c2cc6e07SRamesh Chitrothu * driver may have made PM calls before the 1296c2cc6e07SRamesh Chitrothu * attach failed. pcie_pm_remove_child() should 1297c2cc6e07SRamesh Chitrothu * cleanup PM state and holds (if any) 1298c2cc6e07SRamesh Chitrothu * associated with the child device. 1299c2cc6e07SRamesh Chitrothu */ 1300c2cc6e07SRamesh Chitrothu return (pcie_pm_remove_child(dip, rdip)); 1301c2cc6e07SRamesh Chitrothu } 130213683ea2Skrishnae 1303e0d05aa9Skrishnae if (as->result == DDI_SUCCESS) 13040c5eba8cSkrishnae pf_init(rdip, (void *)px_p->px_fm_ibc, as->cmd); 1305bf8fc234Set142600 130613683ea2Skrishnae (void) pcie_postattach_child(rdip); 130713683ea2Skrishnae 13087c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 13097c478bd9Sstevel@tonic-gate default: 13107c478bd9Sstevel@tonic-gate break; 13117c478bd9Sstevel@tonic-gate } 13127c478bd9Sstevel@tonic-gate break; 13137c478bd9Sstevel@tonic-gate 13147c478bd9Sstevel@tonic-gate case DDI_CTLOPS_DETACH: 1315025c5d04Sjchu if (!pcie_is_child(dip, rdip)) 1316025c5d04Sjchu return (DDI_SUCCESS); 1317025c5d04Sjchu 13187c478bd9Sstevel@tonic-gate ds = (struct detachspec *)arg; 13197c478bd9Sstevel@tonic-gate switch (ds->when) { 13207c478bd9Sstevel@tonic-gate case DDI_POST: 13217c478bd9Sstevel@tonic-gate if (ds->cmd == DDI_DETACH && 13227c478bd9Sstevel@tonic-gate ds->result == DDI_SUCCESS) { 13237c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n", 13247c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), 13257c478bd9Sstevel@tonic-gate ddi_get_instance(rdip)); 13267c478bd9Sstevel@tonic-gate return (pcie_pm_remove_child(dip, rdip)); 13277c478bd9Sstevel@tonic-gate } 13287c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 1329bf8fc234Set142600 case DDI_PRE: 13300c5eba8cSkrishnae pf_fini(rdip, ds->cmd); 1331bf8fc234Set142600 return (DDI_SUCCESS); 13327c478bd9Sstevel@tonic-gate default: 13337c478bd9Sstevel@tonic-gate break; 13347c478bd9Sstevel@tonic-gate } 13357c478bd9Sstevel@tonic-gate break; 13367c478bd9Sstevel@tonic-gate 13377c478bd9Sstevel@tonic-gate case DDI_CTLOPS_REPORTDEV: 1338fc256490SJason Beloro if (ddi_get_parent(rdip) == dip) 13397c478bd9Sstevel@tonic-gate return (px_report_dev(rdip)); 13407c478bd9Sstevel@tonic-gate 1341fc256490SJason Beloro (void) px_lib_fabric_sync(rdip); 1342fc256490SJason Beloro return (DDI_SUCCESS); 1343fc256490SJason Beloro 13447c478bd9Sstevel@tonic-gate case DDI_CTLOPS_IOMIN: 13457c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 13467c478bd9Sstevel@tonic-gate 13477c478bd9Sstevel@tonic-gate case DDI_CTLOPS_REGSIZE: 13487c478bd9Sstevel@tonic-gate *((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg)); 1349f8d2de6bSjchu return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS); 13507c478bd9Sstevel@tonic-gate 13517c478bd9Sstevel@tonic-gate case DDI_CTLOPS_NREGS: 13527c478bd9Sstevel@tonic-gate *((uint_t *)result) = px_get_nreg_set(rdip); 13537c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 13547c478bd9Sstevel@tonic-gate 13557c478bd9Sstevel@tonic-gate case DDI_CTLOPS_DVMAPAGESIZE: 13567c478bd9Sstevel@tonic-gate *((ulong_t *)result) = MMU_PAGE_SIZE; 13577c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 13587c478bd9Sstevel@tonic-gate 13597c478bd9Sstevel@tonic-gate case DDI_CTLOPS_POKE: /* platform dependent implementation. */ 13607c478bd9Sstevel@tonic-gate return (px_lib_ctlops_poke(dip, rdip, 13617c478bd9Sstevel@tonic-gate (peekpoke_ctlops_t *)arg)); 13627c478bd9Sstevel@tonic-gate 13637c478bd9Sstevel@tonic-gate case DDI_CTLOPS_PEEK: /* platform dependent implementation. */ 13647c478bd9Sstevel@tonic-gate return (px_lib_ctlops_peek(dip, rdip, 13657c478bd9Sstevel@tonic-gate (peekpoke_ctlops_t *)arg, result)); 13667c478bd9Sstevel@tonic-gate 13677c478bd9Sstevel@tonic-gate case DDI_CTLOPS_POWER: 13687c478bd9Sstevel@tonic-gate default: 13697c478bd9Sstevel@tonic-gate break; 13707c478bd9Sstevel@tonic-gate } 13717c478bd9Sstevel@tonic-gate 13727c478bd9Sstevel@tonic-gate /* 13737c478bd9Sstevel@tonic-gate * Now pass the request up to our parent. 13747c478bd9Sstevel@tonic-gate */ 13757c478bd9Sstevel@tonic-gate DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n", 13767c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 13777c478bd9Sstevel@tonic-gate return (ddi_ctlops(dip, rdip, op, arg, result)); 13787c478bd9Sstevel@tonic-gate } 13797c478bd9Sstevel@tonic-gate 13807c478bd9Sstevel@tonic-gate /* ARGSUSED */ 13817c478bd9Sstevel@tonic-gate int 13827c478bd9Sstevel@tonic-gate px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 13837c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 13847c478bd9Sstevel@tonic-gate { 13857c478bd9Sstevel@tonic-gate int intr_types, ret = DDI_SUCCESS; 1386fc256490SJason Beloro px_t *px_p = DIP_TO_STATE(dip); 13877c478bd9Sstevel@tonic-gate 13887c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n", 13897c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 13907c478bd9Sstevel@tonic-gate 13917c478bd9Sstevel@tonic-gate /* Process DDI_INTROP_SUPPORTED_TYPES request here */ 13927c478bd9Sstevel@tonic-gate if (intr_op == DDI_INTROP_SUPPORTED_TYPES) { 1393a54f81fbSanish *(int *)result = i_ddi_get_intx_nintrs(rdip) ? 13947c478bd9Sstevel@tonic-gate DDI_INTR_TYPE_FIXED : 0; 13957c478bd9Sstevel@tonic-gate 13967c478bd9Sstevel@tonic-gate if ((pci_msi_get_supported_type(rdip, 13977c478bd9Sstevel@tonic-gate &intr_types)) == DDI_SUCCESS) { 13987c478bd9Sstevel@tonic-gate /* 13997c478bd9Sstevel@tonic-gate * Double check supported interrupt types vs. 14007c478bd9Sstevel@tonic-gate * what the host bridge supports. 14017c478bd9Sstevel@tonic-gate */ 140220036fe5Segillett *(int *)result |= intr_types; 14037c478bd9Sstevel@tonic-gate } 14047c478bd9Sstevel@tonic-gate 1405788cfa89SDavid Woods *(int *)result &= 1406788cfa89SDavid Woods (px_force_intx_support ? 1407788cfa89SDavid Woods (px_p->px_supp_intr_types | DDI_INTR_TYPE_FIXED) : 1408788cfa89SDavid Woods px_p->px_supp_intr_types); 1409fc256490SJason Beloro return (*(int *)result ? DDI_SUCCESS : DDI_FAILURE); 14107c478bd9Sstevel@tonic-gate } 14117c478bd9Sstevel@tonic-gate 14127c478bd9Sstevel@tonic-gate /* 14137c478bd9Sstevel@tonic-gate * PCI-E nexus driver supports fixed, MSI and MSI-X interrupts. 14147c478bd9Sstevel@tonic-gate * Return failure if interrupt type is not supported. 14157c478bd9Sstevel@tonic-gate */ 14167c478bd9Sstevel@tonic-gate switch (hdlp->ih_type) { 14177c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_FIXED: 14187c478bd9Sstevel@tonic-gate ret = px_intx_ops(dip, rdip, intr_op, hdlp, result); 14197c478bd9Sstevel@tonic-gate break; 14207c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_MSI: 14217c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_MSIX: 14227c478bd9Sstevel@tonic-gate ret = px_msix_ops(dip, rdip, intr_op, hdlp, result); 14237c478bd9Sstevel@tonic-gate break; 14247c478bd9Sstevel@tonic-gate default: 14257c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 14267c478bd9Sstevel@tonic-gate break; 14277c478bd9Sstevel@tonic-gate } 14287c478bd9Sstevel@tonic-gate 14297c478bd9Sstevel@tonic-gate return (ret); 14307c478bd9Sstevel@tonic-gate } 1431b65731f1Skini 14320114761dSAlan Adamson, SD OSSD static void 14330114761dSAlan Adamson, SD OSSD px_set_mps(px_t *px_p) 14340114761dSAlan Adamson, SD OSSD { 14350114761dSAlan Adamson, SD OSSD dev_info_t *dip; 14360114761dSAlan Adamson, SD OSSD pcie_bus_t *bus_p; 14370114761dSAlan Adamson, SD OSSD int max_supported; 14380114761dSAlan Adamson, SD OSSD 14390114761dSAlan Adamson, SD OSSD dip = px_p->px_dip; 14400114761dSAlan Adamson, SD OSSD bus_p = PCIE_DIP2BUS(dip); 14410114761dSAlan Adamson, SD OSSD 14420114761dSAlan Adamson, SD OSSD bus_p->bus_mps = -1; 14430114761dSAlan Adamson, SD OSSD 14440114761dSAlan Adamson, SD OSSD if (pcie_root_port(dip) == DDI_FAILURE) { 14450114761dSAlan Adamson, SD OSSD if (px_lib_get_root_complex_mps(px_p, dip, 14460114761dSAlan Adamson, SD OSSD &max_supported) < 0) { 14470114761dSAlan Adamson, SD OSSD 14480114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Can not get RC MPS\n"); 14490114761dSAlan Adamson, SD OSSD return; 14500114761dSAlan Adamson, SD OSSD } 14510114761dSAlan Adamson, SD OSSD 14520114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Root Complex MPS Cap of = %x\n", 14530114761dSAlan Adamson, SD OSSD max_supported); 14540114761dSAlan Adamson, SD OSSD 14550114761dSAlan Adamson, SD OSSD if (pcie_max_mps < max_supported) 14560114761dSAlan Adamson, SD OSSD max_supported = pcie_max_mps; 14570114761dSAlan Adamson, SD OSSD 14580114761dSAlan Adamson, SD OSSD (void) pcie_get_fabric_mps(dip, ddi_get_child(dip), 14590114761dSAlan Adamson, SD OSSD &max_supported); 14600114761dSAlan Adamson, SD OSSD 14610114761dSAlan Adamson, SD OSSD bus_p->bus_mps = max_supported; 14620114761dSAlan Adamson, SD OSSD 14630114761dSAlan Adamson, SD OSSD (void) px_lib_set_root_complex_mps(px_p, dip, bus_p->bus_mps); 14640114761dSAlan Adamson, SD OSSD 14650114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Root Complex MPS Set to = %x\n", 14660114761dSAlan Adamson, SD OSSD bus_p->bus_mps); 14670114761dSAlan Adamson, SD OSSD } 14680114761dSAlan Adamson, SD OSSD } 1469