17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57aadd8d4Skini * Common Development and Distribution License (the "License"). 67aadd8d4Skini * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 2209b1eac2SEvan Yan * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate /* 27*26947304SEvan Yan * SPARC Host to PCI Express nexus driver 287c478bd9Sstevel@tonic-gate */ 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #include <sys/types.h> 317c478bd9Sstevel@tonic-gate #include <sys/conf.h> /* nulldev */ 327c478bd9Sstevel@tonic-gate #include <sys/stat.h> /* devctl */ 337c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 347c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 357c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 367c478bd9Sstevel@tonic-gate #include <sys/ddi_subrdefs.h> 371a887b2eSjchu #include <sys/spl.h> 387c478bd9Sstevel@tonic-gate #include <sys/epm.h> 397c478bd9Sstevel@tonic-gate #include <sys/iommutsb.h> 407c478bd9Sstevel@tonic-gate #include "px_obj.h" 41*26947304SEvan Yan #include <sys/hotplug/pci/pcie_hp.h> 4269cd775fSschwartz #include <sys/pci_tools.h> 43d4476ccbSschwartz #include "px_tools_ext.h" 44d4bc0535SKrishna Elango #include <sys/pcie_pwr.h> 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 477c478bd9Sstevel@tonic-gate 487c478bd9Sstevel@tonic-gate /* 497c478bd9Sstevel@tonic-gate * function prototypes for dev ops routines: 507c478bd9Sstevel@tonic-gate */ 517c478bd9Sstevel@tonic-gate static int px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 527c478bd9Sstevel@tonic-gate static int px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 537c478bd9Sstevel@tonic-gate static int px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 547c478bd9Sstevel@tonic-gate void *arg, void **result); 5501689544Sjchu static int px_cb_attach(px_t *); 5601689544Sjchu static void px_cb_detach(px_t *); 577c478bd9Sstevel@tonic-gate static int px_pwr_setup(dev_info_t *dip); 587c478bd9Sstevel@tonic-gate static void px_pwr_teardown(dev_info_t *dip); 597c478bd9Sstevel@tonic-gate 600114761dSAlan Adamson, SD OSSD static void px_set_mps(px_t *px_p); 610114761dSAlan Adamson, SD OSSD 620114761dSAlan Adamson, SD OSSD extern int pcie_max_mps; 630114761dSAlan Adamson, SD OSSD 647c478bd9Sstevel@tonic-gate /* 657c478bd9Sstevel@tonic-gate * bus ops and dev ops structures: 667c478bd9Sstevel@tonic-gate */ 677c478bd9Sstevel@tonic-gate static struct bus_ops px_bus_ops = { 687c478bd9Sstevel@tonic-gate BUSO_REV, 697c478bd9Sstevel@tonic-gate px_map, 707c478bd9Sstevel@tonic-gate 0, 717c478bd9Sstevel@tonic-gate 0, 727c478bd9Sstevel@tonic-gate 0, 737c478bd9Sstevel@tonic-gate i_ddi_map_fault, 747c478bd9Sstevel@tonic-gate px_dma_setup, 757c478bd9Sstevel@tonic-gate px_dma_allochdl, 767c478bd9Sstevel@tonic-gate px_dma_freehdl, 777c478bd9Sstevel@tonic-gate px_dma_bindhdl, 787c478bd9Sstevel@tonic-gate px_dma_unbindhdl, 797c478bd9Sstevel@tonic-gate px_lib_dma_sync, 807c478bd9Sstevel@tonic-gate px_dma_win, 817c478bd9Sstevel@tonic-gate px_dma_ctlops, 827c478bd9Sstevel@tonic-gate px_ctlops, 837c478bd9Sstevel@tonic-gate ddi_bus_prop_op, 847c478bd9Sstevel@tonic-gate ndi_busop_get_eventcookie, 857c478bd9Sstevel@tonic-gate ndi_busop_add_eventcall, 867c478bd9Sstevel@tonic-gate ndi_busop_remove_eventcall, 877c478bd9Sstevel@tonic-gate ndi_post_event, 887c478bd9Sstevel@tonic-gate NULL, 897c478bd9Sstevel@tonic-gate NULL, /* (*bus_config)(); */ 907c478bd9Sstevel@tonic-gate NULL, /* (*bus_unconfig)(); */ 917c478bd9Sstevel@tonic-gate px_fm_init_child, /* (*bus_fm_init)(); */ 927c478bd9Sstevel@tonic-gate NULL, /* (*bus_fm_fini)(); */ 93f8d2de6bSjchu px_bus_enter, /* (*bus_fm_access_enter)(); */ 94f8d2de6bSjchu px_bus_exit, /* (*bus_fm_access_fini)(); */ 957c478bd9Sstevel@tonic-gate pcie_bus_power, /* (*bus_power)(); */ 96*26947304SEvan Yan px_intr_ops, /* (*bus_intr_op)(); */ 97*26947304SEvan Yan pcie_hp_common_ops /* (*bus_hp_op)(); */ 987c478bd9Sstevel@tonic-gate }; 997c478bd9Sstevel@tonic-gate 1007c478bd9Sstevel@tonic-gate extern struct cb_ops px_cb_ops; 1017c478bd9Sstevel@tonic-gate 1027c478bd9Sstevel@tonic-gate static struct dev_ops px_ops = { 1037c478bd9Sstevel@tonic-gate DEVO_REV, 1047c478bd9Sstevel@tonic-gate 0, 1057c478bd9Sstevel@tonic-gate px_info, 1067c478bd9Sstevel@tonic-gate nulldev, 1077c478bd9Sstevel@tonic-gate 0, 1087c478bd9Sstevel@tonic-gate px_attach, 1097c478bd9Sstevel@tonic-gate px_detach, 1107c478bd9Sstevel@tonic-gate nodev, 1117c478bd9Sstevel@tonic-gate &px_cb_ops, 1127c478bd9Sstevel@tonic-gate &px_bus_ops, 11319397407SSherry Moore nulldev, 11419397407SSherry Moore ddi_quiesce_not_needed, /* quiesce */ 1157c478bd9Sstevel@tonic-gate }; 1167c478bd9Sstevel@tonic-gate 1177c478bd9Sstevel@tonic-gate /* 1187c478bd9Sstevel@tonic-gate * module definitions: 1197c478bd9Sstevel@tonic-gate */ 1207c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 1217c478bd9Sstevel@tonic-gate extern struct mod_ops mod_driverops; 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate static struct modldrv modldrv = { 1247c478bd9Sstevel@tonic-gate &mod_driverops, /* Type of module - driver */ 125*26947304SEvan Yan #if defined(sun4u) 126*26947304SEvan Yan "Sun4u Host to PCIe nexus driver", /* Name of module. */ 127*26947304SEvan Yan #elif defined(sun4v) 128*26947304SEvan Yan "Sun4v Host to PCIe nexus driver", /* Name of module. */ 129*26947304SEvan Yan #endif 1307c478bd9Sstevel@tonic-gate &px_ops, /* driver ops */ 1317c478bd9Sstevel@tonic-gate }; 1327c478bd9Sstevel@tonic-gate 1337c478bd9Sstevel@tonic-gate static struct modlinkage modlinkage = { 1347c478bd9Sstevel@tonic-gate MODREV_1, (void *)&modldrv, NULL 1357c478bd9Sstevel@tonic-gate }; 1367c478bd9Sstevel@tonic-gate 1377c478bd9Sstevel@tonic-gate /* driver soft state */ 1387c478bd9Sstevel@tonic-gate void *px_state_p; 1397c478bd9Sstevel@tonic-gate 1407c478bd9Sstevel@tonic-gate int 1417c478bd9Sstevel@tonic-gate _init(void) 1427c478bd9Sstevel@tonic-gate { 1437c478bd9Sstevel@tonic-gate int e; 1447c478bd9Sstevel@tonic-gate 1457c478bd9Sstevel@tonic-gate /* 1467c478bd9Sstevel@tonic-gate * Initialize per-px bus soft state pointer. 1477c478bd9Sstevel@tonic-gate */ 1487c478bd9Sstevel@tonic-gate e = ddi_soft_state_init(&px_state_p, sizeof (px_t), 1); 1497c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS) 1507c478bd9Sstevel@tonic-gate return (e); 1517c478bd9Sstevel@tonic-gate 1527c478bd9Sstevel@tonic-gate /* 1537c478bd9Sstevel@tonic-gate * Install the module. 1547c478bd9Sstevel@tonic-gate */ 1557c478bd9Sstevel@tonic-gate e = mod_install(&modlinkage); 1567c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS) 1577c478bd9Sstevel@tonic-gate ddi_soft_state_fini(&px_state_p); 1587c478bd9Sstevel@tonic-gate return (e); 1597c478bd9Sstevel@tonic-gate } 1607c478bd9Sstevel@tonic-gate 1617c478bd9Sstevel@tonic-gate int 1627c478bd9Sstevel@tonic-gate _fini(void) 1637c478bd9Sstevel@tonic-gate { 1647c478bd9Sstevel@tonic-gate int e; 1657c478bd9Sstevel@tonic-gate 1667c478bd9Sstevel@tonic-gate /* 1677c478bd9Sstevel@tonic-gate * Remove the module. 1687c478bd9Sstevel@tonic-gate */ 1697c478bd9Sstevel@tonic-gate e = mod_remove(&modlinkage); 1707c478bd9Sstevel@tonic-gate if (e != DDI_SUCCESS) 1717c478bd9Sstevel@tonic-gate return (e); 1727c478bd9Sstevel@tonic-gate 1737c478bd9Sstevel@tonic-gate /* Free px soft state */ 1747c478bd9Sstevel@tonic-gate ddi_soft_state_fini(&px_state_p); 1757c478bd9Sstevel@tonic-gate 1767c478bd9Sstevel@tonic-gate return (e); 1777c478bd9Sstevel@tonic-gate } 1787c478bd9Sstevel@tonic-gate 1797c478bd9Sstevel@tonic-gate int 1807c478bd9Sstevel@tonic-gate _info(struct modinfo *modinfop) 1817c478bd9Sstevel@tonic-gate { 1827c478bd9Sstevel@tonic-gate return (mod_info(&modlinkage, modinfop)); 1837c478bd9Sstevel@tonic-gate } 1847c478bd9Sstevel@tonic-gate 1857c478bd9Sstevel@tonic-gate /* ARGSUSED */ 1867c478bd9Sstevel@tonic-gate static int 1877c478bd9Sstevel@tonic-gate px_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 1887c478bd9Sstevel@tonic-gate { 189*26947304SEvan Yan minor_t minor = getminor((dev_t)arg); 190*26947304SEvan Yan int instance = PCI_MINOR_NUM_TO_INSTANCE(minor); 1917c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(instance); 192*26947304SEvan Yan int ret = DDI_SUCCESS; 1937c478bd9Sstevel@tonic-gate 1947c478bd9Sstevel@tonic-gate switch (infocmd) { 1957c478bd9Sstevel@tonic-gate case DDI_INFO_DEVT2INSTANCE: 196b40cec45Skrishnae *result = (void *)(intptr_t)instance; 197*26947304SEvan Yan break; 1987c478bd9Sstevel@tonic-gate case DDI_INFO_DEVT2DEVINFO: 199*26947304SEvan Yan if (px_p == NULL) { 200*26947304SEvan Yan ret = DDI_FAILURE; 201*26947304SEvan Yan break; 2027c478bd9Sstevel@tonic-gate } 203*26947304SEvan Yan 204*26947304SEvan Yan *result = (void *)px_p->px_dip; 205*26947304SEvan Yan break; 206*26947304SEvan Yan default: 207*26947304SEvan Yan ret = DDI_FAILURE; 208*26947304SEvan Yan break; 209*26947304SEvan Yan } 210*26947304SEvan Yan 211*26947304SEvan Yan return (ret); 2127c478bd9Sstevel@tonic-gate } 2137c478bd9Sstevel@tonic-gate 2147c478bd9Sstevel@tonic-gate /* device driver entry points */ 2157c478bd9Sstevel@tonic-gate /* 2167c478bd9Sstevel@tonic-gate * attach entry point: 2177c478bd9Sstevel@tonic-gate */ 2187c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 2197c478bd9Sstevel@tonic-gate static int 2207c478bd9Sstevel@tonic-gate px_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 2217c478bd9Sstevel@tonic-gate { 2227c478bd9Sstevel@tonic-gate px_t *px_p; /* per bus state pointer */ 2237c478bd9Sstevel@tonic-gate int instance = DIP_TO_INST(dip); 2247c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 2257c478bd9Sstevel@tonic-gate devhandle_t dev_hdl = NULL; 226*26947304SEvan Yan pcie_hp_regops_t regops; 2277c478bd9Sstevel@tonic-gate 2287c478bd9Sstevel@tonic-gate switch (cmd) { 2297c478bd9Sstevel@tonic-gate case DDI_ATTACH: 2307c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "DDI_ATTACH\n"); 2317c478bd9Sstevel@tonic-gate 2327c478bd9Sstevel@tonic-gate /* 2337c478bd9Sstevel@tonic-gate * Allocate and get the per-px soft state structure. 2347c478bd9Sstevel@tonic-gate */ 2357c478bd9Sstevel@tonic-gate if (ddi_soft_state_zalloc(px_state_p, instance) 2367c478bd9Sstevel@tonic-gate != DDI_SUCCESS) { 2377c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: can't allocate px state", 2387c478bd9Sstevel@tonic-gate ddi_driver_name(dip), instance); 2397c478bd9Sstevel@tonic-gate goto err_bad_px_softstate; 2407c478bd9Sstevel@tonic-gate } 2417c478bd9Sstevel@tonic-gate px_p = INST_TO_STATE(instance); 2427c478bd9Sstevel@tonic-gate px_p->px_dip = dip; 2437c478bd9Sstevel@tonic-gate mutex_init(&px_p->px_mutex, NULL, MUTEX_DRIVER, NULL); 244*26947304SEvan Yan px_p->px_soft_state = PCI_SOFT_STATE_CLOSED; 2457c478bd9Sstevel@tonic-gate 246b65731f1Skini (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, 247b65731f1Skini "device_type", "pciex"); 248bf8fc234Set142600 249bf8fc234Set142600 /* Initialize px_dbg for high pil printing */ 250bf8fc234Set142600 px_dbg_attach(dip, &px_p->px_dbg_hdl); 251*26947304SEvan Yan pcie_rc_init_bus(dip); 252bf8fc234Set142600 2537c478bd9Sstevel@tonic-gate /* 2547c478bd9Sstevel@tonic-gate * Get key properties of the pci bridge node and 2557c478bd9Sstevel@tonic-gate * determine it's type (psycho, schizo, etc ...). 2567c478bd9Sstevel@tonic-gate */ 2577c478bd9Sstevel@tonic-gate if (px_get_props(px_p, dip) == DDI_FAILURE) 2587c478bd9Sstevel@tonic-gate goto err_bad_px_prop; 2597c478bd9Sstevel@tonic-gate 2607c478bd9Sstevel@tonic-gate if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS) 2617c478bd9Sstevel@tonic-gate goto err_bad_dev_init; 2627c478bd9Sstevel@tonic-gate 26320036fe5Segillett /* Initialize device handle */ 2647c478bd9Sstevel@tonic-gate px_p->px_dev_hdl = dev_hdl; 2657c478bd9Sstevel@tonic-gate 2667ea9b230Set142600 /* Cache the BDF of the root port nexus */ 2677ea9b230Set142600 px_p->px_bdf = px_lib_get_bdf(px_p); 2687ea9b230Set142600 2697c478bd9Sstevel@tonic-gate /* 2707c478bd9Sstevel@tonic-gate * Initialize interrupt block. Note that this 2717c478bd9Sstevel@tonic-gate * initialize error handling for the PEC as well. 2727c478bd9Sstevel@tonic-gate */ 2737c478bd9Sstevel@tonic-gate if ((ret = px_ib_attach(px_p)) != DDI_SUCCESS) 2747c478bd9Sstevel@tonic-gate goto err_bad_ib; 2757c478bd9Sstevel@tonic-gate 2767c478bd9Sstevel@tonic-gate if (px_cb_attach(px_p) != DDI_SUCCESS) 2777c478bd9Sstevel@tonic-gate goto err_bad_cb; 2787c478bd9Sstevel@tonic-gate 2797c478bd9Sstevel@tonic-gate /* 2807c478bd9Sstevel@tonic-gate * Start creating the modules. 2817c478bd9Sstevel@tonic-gate * Note that attach() routines should 2827c478bd9Sstevel@tonic-gate * register and enable their own interrupts. 2837c478bd9Sstevel@tonic-gate */ 2847c478bd9Sstevel@tonic-gate 2857c478bd9Sstevel@tonic-gate if ((px_mmu_attach(px_p)) != DDI_SUCCESS) 2867c478bd9Sstevel@tonic-gate goto err_bad_mmu; 2877c478bd9Sstevel@tonic-gate 2887c478bd9Sstevel@tonic-gate if ((px_msiq_attach(px_p)) != DDI_SUCCESS) 2897c478bd9Sstevel@tonic-gate goto err_bad_msiq; 2907c478bd9Sstevel@tonic-gate 2917c478bd9Sstevel@tonic-gate if ((px_msi_attach(px_p)) != DDI_SUCCESS) 2927c478bd9Sstevel@tonic-gate goto err_bad_msi; 2937c478bd9Sstevel@tonic-gate 2947c478bd9Sstevel@tonic-gate if ((px_pec_attach(px_p)) != DDI_SUCCESS) 2957c478bd9Sstevel@tonic-gate goto err_bad_pec; 2967c478bd9Sstevel@tonic-gate 2977c478bd9Sstevel@tonic-gate if ((px_dma_attach(px_p)) != DDI_SUCCESS) 2989c81f298Sjchu goto err_bad_dma; /* nothing to uninitialize on DMA */ 2997c478bd9Sstevel@tonic-gate 3003c4226f9Spjha if ((px_fm_attach(px_p)) != DDI_SUCCESS) 3013c4226f9Spjha goto err_bad_dma; 3023c4226f9Spjha 3037c478bd9Sstevel@tonic-gate /* 3047c478bd9Sstevel@tonic-gate * All of the error handlers have been registered 3057c478bd9Sstevel@tonic-gate * by now so it's time to activate the interrupt. 3067c478bd9Sstevel@tonic-gate */ 307f8d2de6bSjchu if ((ret = px_err_add_intr(&px_p->px_fault)) != DDI_SUCCESS) 3083c4226f9Spjha goto err_bad_intr; 3097c478bd9Sstevel@tonic-gate 310*26947304SEvan Yan if (px_lib_hotplug_init(dip, (void *)®ops) == DDI_SUCCESS) { 311*26947304SEvan Yan pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 312*26947304SEvan Yan 313*26947304SEvan Yan bus_p->bus_hp_sup_modes |= PCIE_NATIVE_HP_MODE; 314*26947304SEvan Yan } 315b65731f1Skini 3160114761dSAlan Adamson, SD OSSD (void) px_set_mps(px_p); 3170114761dSAlan Adamson, SD OSSD 318*26947304SEvan Yan if (pcie_init(dip, (caddr_t)®ops) != DDI_SUCCESS) 319*26947304SEvan Yan goto err_bad_hotplug; 32069cd775fSschwartz 32169cd775fSschwartz if (pxtool_init(dip) != DDI_SUCCESS) 32269cd775fSschwartz goto err_bad_pcitool_node; 32369cd775fSschwartz 3247c478bd9Sstevel@tonic-gate /* 3257c478bd9Sstevel@tonic-gate * power management setup. Even if it fails, attach will 3267c478bd9Sstevel@tonic-gate * succeed as this is a optional feature. Since we are 3277c478bd9Sstevel@tonic-gate * always at full power, this is not critical. 3287c478bd9Sstevel@tonic-gate */ 3297c478bd9Sstevel@tonic-gate if (pwr_common_setup(dip) != DDI_SUCCESS) { 3307c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "pwr_common_setup failed\n"); 3317c478bd9Sstevel@tonic-gate } else if (px_pwr_setup(dip) != DDI_SUCCESS) { 3327c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "px_pwr_setup failed \n"); 3337c478bd9Sstevel@tonic-gate pwr_common_teardown(dip); 3347c478bd9Sstevel@tonic-gate } 3357c478bd9Sstevel@tonic-gate 336817a6df8Sjchu /* 337817a6df8Sjchu * add cpr callback 338817a6df8Sjchu */ 339817a6df8Sjchu px_cpr_add_callb(px_p); 340817a6df8Sjchu 3417c478bd9Sstevel@tonic-gate ddi_report_dev(dip); 3427c478bd9Sstevel@tonic-gate 3437c478bd9Sstevel@tonic-gate px_p->px_state = PX_ATTACHED; 3447c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "attach success\n"); 3457c478bd9Sstevel@tonic-gate break; 3467c478bd9Sstevel@tonic-gate 34769cd775fSschwartz err_bad_pcitool_node: 348*26947304SEvan Yan (void) pcie_uninit(dip); 349*26947304SEvan Yan err_bad_hotplug: 350*26947304SEvan Yan (void) px_lib_hotplug_uninit(dip); 351f8d2de6bSjchu px_err_rem_intr(&px_p->px_fault); 3523c4226f9Spjha err_bad_intr: 3533c4226f9Spjha px_fm_detach(px_p); 3549c81f298Sjchu err_bad_dma: 3557c478bd9Sstevel@tonic-gate px_pec_detach(px_p); 3567c478bd9Sstevel@tonic-gate err_bad_pec: 3577c478bd9Sstevel@tonic-gate px_msi_detach(px_p); 3587c478bd9Sstevel@tonic-gate err_bad_msi: 3597c478bd9Sstevel@tonic-gate px_msiq_detach(px_p); 3607c478bd9Sstevel@tonic-gate err_bad_msiq: 3617c478bd9Sstevel@tonic-gate px_mmu_detach(px_p); 3627c478bd9Sstevel@tonic-gate err_bad_mmu: 3637c478bd9Sstevel@tonic-gate px_cb_detach(px_p); 3647c478bd9Sstevel@tonic-gate err_bad_cb: 3657c478bd9Sstevel@tonic-gate px_ib_detach(px_p); 3667c478bd9Sstevel@tonic-gate err_bad_ib: 367d8d130aeSanbui if (px_lib_dev_fini(dip) != DDI_SUCCESS) { 368d8d130aeSanbui DBG(DBG_ATTACH, dip, "px_lib_dev_fini failed\n"); 369d8d130aeSanbui } 3707c478bd9Sstevel@tonic-gate err_bad_dev_init: 3717c478bd9Sstevel@tonic-gate px_free_props(px_p); 3727c478bd9Sstevel@tonic-gate err_bad_px_prop: 373*26947304SEvan Yan pcie_rc_fini_bus(dip); 374bf8fc234Set142600 px_dbg_detach(dip, &px_p->px_dbg_hdl); 3757c478bd9Sstevel@tonic-gate mutex_destroy(&px_p->px_mutex); 3767c478bd9Sstevel@tonic-gate ddi_soft_state_free(px_state_p, instance); 3777c478bd9Sstevel@tonic-gate err_bad_px_softstate: 3787c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 3797c478bd9Sstevel@tonic-gate break; 3807c478bd9Sstevel@tonic-gate 3817c478bd9Sstevel@tonic-gate case DDI_RESUME: 3827c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "DDI_RESUME\n"); 3837c478bd9Sstevel@tonic-gate 3847c478bd9Sstevel@tonic-gate px_p = INST_TO_STATE(instance); 3857c478bd9Sstevel@tonic-gate 3867c478bd9Sstevel@tonic-gate mutex_enter(&px_p->px_mutex); 3877c478bd9Sstevel@tonic-gate 3887c478bd9Sstevel@tonic-gate /* suspend might have not succeeded */ 3897c478bd9Sstevel@tonic-gate if (px_p->px_state != PX_SUSPENDED) { 3907c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, px_p->px_dip, 3917c478bd9Sstevel@tonic-gate "instance NOT suspended\n"); 3927c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 3937c478bd9Sstevel@tonic-gate break; 3947c478bd9Sstevel@tonic-gate } 3957c478bd9Sstevel@tonic-gate 396023ccc1eSegillett px_msiq_resume(px_p); 3977c478bd9Sstevel@tonic-gate px_lib_resume(dip); 3987c478bd9Sstevel@tonic-gate (void) pcie_pwr_resume(dip); 3997c478bd9Sstevel@tonic-gate px_p->px_state = PX_ATTACHED; 4007c478bd9Sstevel@tonic-gate 4017c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 4027c478bd9Sstevel@tonic-gate 4037c478bd9Sstevel@tonic-gate break; 4047c478bd9Sstevel@tonic-gate default: 4057c478bd9Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "unsupported attach op\n"); 4067c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 4077c478bd9Sstevel@tonic-gate break; 4087c478bd9Sstevel@tonic-gate } 4097c478bd9Sstevel@tonic-gate 4107c478bd9Sstevel@tonic-gate return (ret); 4117c478bd9Sstevel@tonic-gate } 4127c478bd9Sstevel@tonic-gate 4137c478bd9Sstevel@tonic-gate /* 4147c478bd9Sstevel@tonic-gate * detach entry point: 4157c478bd9Sstevel@tonic-gate */ 4167c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 4177c478bd9Sstevel@tonic-gate static int 4187c478bd9Sstevel@tonic-gate px_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 4197c478bd9Sstevel@tonic-gate { 4207c478bd9Sstevel@tonic-gate int instance = ddi_get_instance(dip); 4217c478bd9Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(instance); 422*26947304SEvan Yan pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 4237c478bd9Sstevel@tonic-gate int ret; 4247c478bd9Sstevel@tonic-gate 4257c478bd9Sstevel@tonic-gate /* 4267c478bd9Sstevel@tonic-gate * Make sure we are currently attached 4277c478bd9Sstevel@tonic-gate */ 4287c478bd9Sstevel@tonic-gate if (px_p->px_state != PX_ATTACHED) { 42901689544Sjchu DBG(DBG_DETACH, dip, "Instance not attached\n"); 4307c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 4317c478bd9Sstevel@tonic-gate } 4327c478bd9Sstevel@tonic-gate 4337c478bd9Sstevel@tonic-gate mutex_enter(&px_p->px_mutex); 4347c478bd9Sstevel@tonic-gate 4357c478bd9Sstevel@tonic-gate switch (cmd) { 4367c478bd9Sstevel@tonic-gate case DDI_DETACH: 4377c478bd9Sstevel@tonic-gate DBG(DBG_DETACH, dip, "DDI_DETACH\n"); 4387c478bd9Sstevel@tonic-gate 439817a6df8Sjchu /* 440817a6df8Sjchu * remove cpr callback 441817a6df8Sjchu */ 442817a6df8Sjchu px_cpr_rem_callb(px_p); 443817a6df8Sjchu 444*26947304SEvan Yan if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) 445*26947304SEvan Yan (void) px_lib_hotplug_uninit(dip); 446*26947304SEvan Yan 447*26947304SEvan Yan if (pcie_uninit(dip) != DDI_SUCCESS) { 4487c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 4497c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 4507c478bd9Sstevel@tonic-gate } 4517c478bd9Sstevel@tonic-gate 4527c478bd9Sstevel@tonic-gate /* 4537c478bd9Sstevel@tonic-gate * things which used to be done in obj_destroy 4547c478bd9Sstevel@tonic-gate * are now in-lined here. 4557c478bd9Sstevel@tonic-gate */ 4567c478bd9Sstevel@tonic-gate 4577c478bd9Sstevel@tonic-gate px_p->px_state = PX_DETACHED; 4587c478bd9Sstevel@tonic-gate 45969cd775fSschwartz pxtool_uninit(dip); 46069cd775fSschwartz 461f8d2de6bSjchu px_err_rem_intr(&px_p->px_fault); 4623c4226f9Spjha px_fm_detach(px_p); 4637c478bd9Sstevel@tonic-gate px_pec_detach(px_p); 4649c75c6bfSgovinda px_pwr_teardown(dip); 4659c75c6bfSgovinda pwr_common_teardown(dip); 4667c478bd9Sstevel@tonic-gate px_msi_detach(px_p); 4677c478bd9Sstevel@tonic-gate px_msiq_detach(px_p); 4687c478bd9Sstevel@tonic-gate px_mmu_detach(px_p); 4697c478bd9Sstevel@tonic-gate px_cb_detach(px_p); 4707c478bd9Sstevel@tonic-gate px_ib_detach(px_p); 471d8d130aeSanbui if (px_lib_dev_fini(dip) != DDI_SUCCESS) { 472d8d130aeSanbui DBG(DBG_DETACH, dip, "px_lib_dev_fini failed\n"); 473d8d130aeSanbui } 4747c478bd9Sstevel@tonic-gate 4757c478bd9Sstevel@tonic-gate /* 4767c478bd9Sstevel@tonic-gate * Free the px soft state structure and the rest of the 4777c478bd9Sstevel@tonic-gate * resources it's using. 4787c478bd9Sstevel@tonic-gate */ 4797c478bd9Sstevel@tonic-gate px_free_props(px_p); 480*26947304SEvan Yan pcie_rc_fini_bus(dip); 481bf8fc234Set142600 px_dbg_detach(dip, &px_p->px_dbg_hdl); 4827c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 4837c478bd9Sstevel@tonic-gate mutex_destroy(&px_p->px_mutex); 4847c478bd9Sstevel@tonic-gate 4857c478bd9Sstevel@tonic-gate px_p->px_dev_hdl = NULL; 486dabea0dbSschwartz ddi_soft_state_free(px_state_p, instance); 4877c478bd9Sstevel@tonic-gate 4887c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 4897c478bd9Sstevel@tonic-gate 4907c478bd9Sstevel@tonic-gate case DDI_SUSPEND: 4917c478bd9Sstevel@tonic-gate if (pcie_pwr_suspend(dip) != DDI_SUCCESS) { 4927c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 4937c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 4947c478bd9Sstevel@tonic-gate } 4957c478bd9Sstevel@tonic-gate if ((ret = px_lib_suspend(dip)) == DDI_SUCCESS) 4967c478bd9Sstevel@tonic-gate px_p->px_state = PX_SUSPENDED; 4977c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 4987c478bd9Sstevel@tonic-gate 4997c478bd9Sstevel@tonic-gate return (ret); 5007c478bd9Sstevel@tonic-gate 5017c478bd9Sstevel@tonic-gate default: 5027c478bd9Sstevel@tonic-gate DBG(DBG_DETACH, dip, "unsupported detach op\n"); 5037c478bd9Sstevel@tonic-gate mutex_exit(&px_p->px_mutex); 5047c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 5057c478bd9Sstevel@tonic-gate } 5067c478bd9Sstevel@tonic-gate } 5077c478bd9Sstevel@tonic-gate 50801689544Sjchu int 50901689544Sjchu px_cb_attach(px_t *px_p) 51001689544Sjchu { 51101689544Sjchu px_fault_t *fault_p = &px_p->px_cb_fault; 51201689544Sjchu dev_info_t *dip = px_p->px_dip; 51301689544Sjchu sysino_t sysino; 51401689544Sjchu 51501689544Sjchu if (px_lib_intr_devino_to_sysino(dip, 51601689544Sjchu px_p->px_inos[PX_INTR_XBC], &sysino) != DDI_SUCCESS) 51701689544Sjchu return (DDI_FAILURE); 51801689544Sjchu 51901689544Sjchu fault_p->px_fh_dip = dip; 52001689544Sjchu fault_p->px_fh_sysino = sysino; 52101689544Sjchu fault_p->px_err_func = px_err_cb_intr; 52201689544Sjchu fault_p->px_intr_ino = px_p->px_inos[PX_INTR_XBC]; 52301689544Sjchu 52401689544Sjchu return (px_cb_add_intr(fault_p)); 52501689544Sjchu } 52601689544Sjchu 52701689544Sjchu void 52801689544Sjchu px_cb_detach(px_t *px_p) 52901689544Sjchu { 53001689544Sjchu px_cb_rem_intr(&px_p->px_cb_fault); 53101689544Sjchu } 53201689544Sjchu 5337c478bd9Sstevel@tonic-gate /* 5347c478bd9Sstevel@tonic-gate * power management related initialization specific to px 5357c478bd9Sstevel@tonic-gate * called by px_attach() 5367c478bd9Sstevel@tonic-gate */ 5377c478bd9Sstevel@tonic-gate static int 5387c478bd9Sstevel@tonic-gate px_pwr_setup(dev_info_t *dip) 5397c478bd9Sstevel@tonic-gate { 5407c478bd9Sstevel@tonic-gate pcie_pwr_t *pwr_p; 5411a887b2eSjchu int instance = ddi_get_instance(dip); 5421a887b2eSjchu px_t *px_p = INST_TO_STATE(instance); 5437c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t hdl; 5447c478bd9Sstevel@tonic-gate 5457c478bd9Sstevel@tonic-gate ASSERT(PCIE_PMINFO(dip)); 5467c478bd9Sstevel@tonic-gate pwr_p = PCIE_NEXUS_PMINFO(dip); 5477c478bd9Sstevel@tonic-gate ASSERT(pwr_p); 5487c478bd9Sstevel@tonic-gate 5497c478bd9Sstevel@tonic-gate /* 5507c478bd9Sstevel@tonic-gate * indicate support LDI (Layered Driver Interface) 5517c478bd9Sstevel@tonic-gate * Create the property, if it is not already there 5527c478bd9Sstevel@tonic-gate */ 5537c478bd9Sstevel@tonic-gate if (!ddi_prop_exists(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5547c478bd9Sstevel@tonic-gate DDI_KERNEL_IOCTL)) { 5557c478bd9Sstevel@tonic-gate if (ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 5567c478bd9Sstevel@tonic-gate DDI_KERNEL_IOCTL, NULL, 0) != DDI_PROP_SUCCESS) { 5577c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "can't create kernel ioctl prop\n"); 5587c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 5597c478bd9Sstevel@tonic-gate } 5607c478bd9Sstevel@tonic-gate } 5617c478bd9Sstevel@tonic-gate /* No support for device PM. We are always at full power */ 5627c478bd9Sstevel@tonic-gate pwr_p->pwr_func_lvl = PM_LEVEL_D0; 5637c478bd9Sstevel@tonic-gate 5641a887b2eSjchu mutex_init(&px_p->px_l23ready_lock, NULL, MUTEX_DRIVER, 565a195726fSgovinda DDI_INTR_PRI(px_pwr_pil)); 5661a887b2eSjchu cv_init(&px_p->px_l23ready_cv, NULL, CV_DRIVER, NULL); 5671a887b2eSjchu 56820036fe5Segillett /* Initialize handle */ 56920036fe5Segillett bzero(&hdl, sizeof (ddi_intr_handle_impl_t)); 5701a887b2eSjchu hdl.ih_cb_arg1 = px_p; 5717c478bd9Sstevel@tonic-gate hdl.ih_ver = DDI_INTR_VERSION; 5727c478bd9Sstevel@tonic-gate hdl.ih_state = DDI_IHDL_STATE_ALLOC; 5737c478bd9Sstevel@tonic-gate hdl.ih_dip = dip; 5747c478bd9Sstevel@tonic-gate hdl.ih_pri = px_pwr_pil; 5757c478bd9Sstevel@tonic-gate 5767c478bd9Sstevel@tonic-gate /* Add PME_TO_ACK message handler */ 5771a887b2eSjchu hdl.ih_cb_func = (ddi_intr_handler_t *)px_pmeq_intr; 5787c478bd9Sstevel@tonic-gate if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC, 57909b1eac2SEvan Yan (msgcode_t)PCIE_PME_ACK_MSG, -1, 58009b1eac2SEvan Yan &px_p->px_pm_msiq_id) != DDI_SUCCESS) { 5811a887b2eSjchu DBG(DBG_PWR, dip, "px_pwr_setup: couldn't add " 5821a887b2eSjchu " PME_TO_ACK intr\n"); 583f9721e07Sjchu goto pwr_setup_err1; 5847c478bd9Sstevel@tonic-gate } 5851a887b2eSjchu px_lib_msg_setmsiq(dip, PCIE_PME_ACK_MSG, px_p->px_pm_msiq_id); 5867c478bd9Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_VALID); 5877c478bd9Sstevel@tonic-gate 58836fe4a92Segillett if (px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 589b0fc0e77Sgovinda px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), px_pwr_pil, 59036fe4a92Segillett PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) { 59136fe4a92Segillett DBG(DBG_PWR, dip, "px_pwr_setup: PME_TO_ACK update interrupt" 59236fe4a92Segillett " state failed\n"); 59336fe4a92Segillett goto px_pwrsetup_err_state; 59436fe4a92Segillett } 59536fe4a92Segillett 5967c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5977c478bd9Sstevel@tonic-gate 59836fe4a92Segillett px_pwrsetup_err_state: 59936fe4a92Segillett px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 60036fe4a92Segillett (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 60136fe4a92Segillett px_p->px_pm_msiq_id); 6021a887b2eSjchu pwr_setup_err1: 6031a887b2eSjchu mutex_destroy(&px_p->px_l23ready_lock); 6041a887b2eSjchu cv_destroy(&px_p->px_l23ready_cv); 6051a887b2eSjchu 6067c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 6077c478bd9Sstevel@tonic-gate } 6087c478bd9Sstevel@tonic-gate 6097c478bd9Sstevel@tonic-gate /* 6107c478bd9Sstevel@tonic-gate * undo whatever is done in px_pwr_setup. called by px_detach() 6117c478bd9Sstevel@tonic-gate */ 6127c478bd9Sstevel@tonic-gate static void 6137c478bd9Sstevel@tonic-gate px_pwr_teardown(dev_info_t *dip) 6147c478bd9Sstevel@tonic-gate { 6151a887b2eSjchu int instance = ddi_get_instance(dip); 6161a887b2eSjchu px_t *px_p = INST_TO_STATE(instance); 6177c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t hdl; 6187c478bd9Sstevel@tonic-gate 6191a887b2eSjchu if (!PCIE_PMINFO(dip) || !PCIE_NEXUS_PMINFO(dip)) 6207c478bd9Sstevel@tonic-gate return; 6217c478bd9Sstevel@tonic-gate 62220036fe5Segillett /* Initialize handle */ 62320036fe5Segillett bzero(&hdl, sizeof (ddi_intr_handle_impl_t)); 6247c478bd9Sstevel@tonic-gate hdl.ih_ver = DDI_INTR_VERSION; 6257c478bd9Sstevel@tonic-gate hdl.ih_state = DDI_IHDL_STATE_ALLOC; 6267c478bd9Sstevel@tonic-gate hdl.ih_dip = dip; 627665a7fcaSgovinda hdl.ih_pri = px_pwr_pil; 6287c478bd9Sstevel@tonic-gate 6297c478bd9Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_PME_ACK_MSG, PCIE_MSG_INVALID); 6307c478bd9Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG, 6311a887b2eSjchu px_p->px_pm_msiq_id); 6327c478bd9Sstevel@tonic-gate 63336fe4a92Segillett (void) px_ib_update_intr_state(px_p, px_p->px_dip, hdl.ih_inum, 634b0fc0e77Sgovinda px_msiqid_to_devino(px_p, px_p->px_pm_msiq_id), px_pwr_pil, 63536fe4a92Segillett PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG); 63636fe4a92Segillett 637055d7c80Scarlsonj px_p->px_pm_msiq_id = (msiqid_t)-1; 6387c478bd9Sstevel@tonic-gate 6391a887b2eSjchu cv_destroy(&px_p->px_l23ready_cv); 6401a887b2eSjchu mutex_destroy(&px_p->px_l23ready_lock); 6417c478bd9Sstevel@tonic-gate } 6427c478bd9Sstevel@tonic-gate 6437c478bd9Sstevel@tonic-gate /* bus driver entry points */ 6447c478bd9Sstevel@tonic-gate 6457c478bd9Sstevel@tonic-gate /* 6467c478bd9Sstevel@tonic-gate * bus map entry point: 6477c478bd9Sstevel@tonic-gate * 6487c478bd9Sstevel@tonic-gate * if map request is for an rnumber 6497c478bd9Sstevel@tonic-gate * get the corresponding regspec from device node 6507c478bd9Sstevel@tonic-gate * build a new regspec in our parent's format 6517c478bd9Sstevel@tonic-gate * build a new map_req with the new regspec 6527c478bd9Sstevel@tonic-gate * call up the tree to complete the mapping 6537c478bd9Sstevel@tonic-gate */ 6547c478bd9Sstevel@tonic-gate int 6557c478bd9Sstevel@tonic-gate px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 6567c478bd9Sstevel@tonic-gate off_t off, off_t len, caddr_t *addrp) 6577c478bd9Sstevel@tonic-gate { 6587c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 6597c478bd9Sstevel@tonic-gate struct regspec p_regspec; 6607c478bd9Sstevel@tonic-gate ddi_map_req_t p_mapreq; 6617c478bd9Sstevel@tonic-gate int reglen, rval, r_no; 6627c478bd9Sstevel@tonic-gate pci_regspec_t reloc_reg, *rp = &reloc_reg; 6637c478bd9Sstevel@tonic-gate 6647c478bd9Sstevel@tonic-gate DBG(DBG_MAP, dip, "rdip=%s%d:", 6657c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 6667c478bd9Sstevel@tonic-gate 6677c478bd9Sstevel@tonic-gate if (mp->map_flags & DDI_MF_USER_MAPPING) 6687c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED); 6697c478bd9Sstevel@tonic-gate 6707c478bd9Sstevel@tonic-gate switch (mp->map_type) { 6717c478bd9Sstevel@tonic-gate case DDI_MT_REGSPEC: 6727c478bd9Sstevel@tonic-gate reloc_reg = *(pci_regspec_t *)mp->map_obj.rp; /* dup whole */ 6737c478bd9Sstevel@tonic-gate break; 6747c478bd9Sstevel@tonic-gate 6757c478bd9Sstevel@tonic-gate case DDI_MT_RNUMBER: 6767c478bd9Sstevel@tonic-gate r_no = mp->map_obj.rnumber; 6777c478bd9Sstevel@tonic-gate DBG(DBG_MAP | DBG_CONT, dip, " r#=%x", r_no); 6787c478bd9Sstevel@tonic-gate 679a3282898Scth if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 6807c478bd9Sstevel@tonic-gate "reg", (caddr_t)&rp, ®len) != DDI_SUCCESS) 6817c478bd9Sstevel@tonic-gate return (DDI_ME_RNUMBER_RANGE); 6827c478bd9Sstevel@tonic-gate 6837c478bd9Sstevel@tonic-gate if (r_no < 0 || r_no >= reglen / sizeof (pci_regspec_t)) { 6847c478bd9Sstevel@tonic-gate kmem_free(rp, reglen); 6857c478bd9Sstevel@tonic-gate return (DDI_ME_RNUMBER_RANGE); 6867c478bd9Sstevel@tonic-gate } 6877c478bd9Sstevel@tonic-gate rp += r_no; 6887c478bd9Sstevel@tonic-gate break; 6897c478bd9Sstevel@tonic-gate 6907c478bd9Sstevel@tonic-gate default: 6917c478bd9Sstevel@tonic-gate return (DDI_ME_INVAL); 6927c478bd9Sstevel@tonic-gate } 6937c478bd9Sstevel@tonic-gate DBG(DBG_MAP | DBG_CONT, dip, "\n"); 6947c478bd9Sstevel@tonic-gate 6957c478bd9Sstevel@tonic-gate if ((rp->pci_phys_hi & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) { 6967c478bd9Sstevel@tonic-gate /* 6977c478bd9Sstevel@tonic-gate * There may be a need to differentiate between PCI 6987c478bd9Sstevel@tonic-gate * and PCI-Ex devices so the following range check is 6997c478bd9Sstevel@tonic-gate * done correctly, depending on the implementation of 700d4bc0535SKrishna Elango * pcieb bridge nexus driver. 7017c478bd9Sstevel@tonic-gate */ 7027c478bd9Sstevel@tonic-gate if ((off >= PCIE_CONF_HDR_SIZE) || 7037c478bd9Sstevel@tonic-gate (len > PCIE_CONF_HDR_SIZE) || 7047c478bd9Sstevel@tonic-gate (off + len > PCIE_CONF_HDR_SIZE)) 7057c478bd9Sstevel@tonic-gate return (DDI_ME_INVAL); 7067c478bd9Sstevel@tonic-gate /* 7077c478bd9Sstevel@tonic-gate * the following function returning a DDI_FAILURE assumes 7087c478bd9Sstevel@tonic-gate * that there are no virtual config space access services 7097c478bd9Sstevel@tonic-gate * defined in this layer. Otherwise it is availed right 7107c478bd9Sstevel@tonic-gate * here and we return. 7117c478bd9Sstevel@tonic-gate */ 7127c478bd9Sstevel@tonic-gate rval = px_lib_map_vconfig(dip, mp, off, rp, addrp); 7137c478bd9Sstevel@tonic-gate if (rval == DDI_SUCCESS) 7147c478bd9Sstevel@tonic-gate goto done; 7157c478bd9Sstevel@tonic-gate } 7167c478bd9Sstevel@tonic-gate 7177c478bd9Sstevel@tonic-gate /* 7187c478bd9Sstevel@tonic-gate * No virtual config space services or we are mapping 7197c478bd9Sstevel@tonic-gate * a region of memory mapped config/IO/memory space, so proceed 7207c478bd9Sstevel@tonic-gate * to the parent. 7217c478bd9Sstevel@tonic-gate */ 7227c478bd9Sstevel@tonic-gate 7237c478bd9Sstevel@tonic-gate /* relocate within 64-bit pci space through "assigned-addresses" */ 7247c478bd9Sstevel@tonic-gate if (rval = px_reloc_reg(dip, rdip, px_p, rp)) 7257c478bd9Sstevel@tonic-gate goto done; 7267c478bd9Sstevel@tonic-gate 7277c478bd9Sstevel@tonic-gate if (len) /* adjust regspec according to mapping request */ 7287c478bd9Sstevel@tonic-gate rp->pci_size_low = len; /* MIN ? */ 7297c478bd9Sstevel@tonic-gate rp->pci_phys_low += off; 7307c478bd9Sstevel@tonic-gate 7317c478bd9Sstevel@tonic-gate /* translate relocated pci regspec into parent space through "ranges" */ 7327c478bd9Sstevel@tonic-gate if (rval = px_xlate_reg(px_p, rp, &p_regspec)) 7337c478bd9Sstevel@tonic-gate goto done; 7347c478bd9Sstevel@tonic-gate 7357c478bd9Sstevel@tonic-gate p_mapreq = *mp; /* dup the whole structure */ 7367c478bd9Sstevel@tonic-gate p_mapreq.map_type = DDI_MT_REGSPEC; 7377c478bd9Sstevel@tonic-gate p_mapreq.map_obj.rp = &p_regspec; 7384fbb58f6Sjchu px_lib_map_attr_check(&p_mapreq); 7397c478bd9Sstevel@tonic-gate rval = ddi_map(dip, &p_mapreq, 0, 0, addrp); 7407c478bd9Sstevel@tonic-gate 7417c478bd9Sstevel@tonic-gate if (rval == DDI_SUCCESS) { 7427c478bd9Sstevel@tonic-gate /* 7437c478bd9Sstevel@tonic-gate * Set-up access functions for FM access error capable drivers. 7447c478bd9Sstevel@tonic-gate */ 745eae2e508Skrishnae if (DDI_FM_ACC_ERR_CAP(ddi_fm_capable(rdip))) 746eae2e508Skrishnae px_fm_acc_setup(mp, rdip, rp); 7477c478bd9Sstevel@tonic-gate } 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate done: 7507c478bd9Sstevel@tonic-gate if (mp->map_type == DDI_MT_RNUMBER) 7517c478bd9Sstevel@tonic-gate kmem_free(rp - r_no, reglen); 7527c478bd9Sstevel@tonic-gate 7537c478bd9Sstevel@tonic-gate return (rval); 7547c478bd9Sstevel@tonic-gate } 7557c478bd9Sstevel@tonic-gate 7567c478bd9Sstevel@tonic-gate /* 7577c478bd9Sstevel@tonic-gate * bus dma map entry point 7587c478bd9Sstevel@tonic-gate * return value: 7597c478bd9Sstevel@tonic-gate * DDI_DMA_PARTIAL_MAP 1 7607c478bd9Sstevel@tonic-gate * DDI_DMA_MAPOK 0 7617c478bd9Sstevel@tonic-gate * DDI_DMA_MAPPED 0 7627c478bd9Sstevel@tonic-gate * DDI_DMA_NORESOURCES -1 7637c478bd9Sstevel@tonic-gate * DDI_DMA_NOMAPPING -2 7647c478bd9Sstevel@tonic-gate * DDI_DMA_TOOBIG -3 7657c478bd9Sstevel@tonic-gate */ 7667c478bd9Sstevel@tonic-gate int 7677c478bd9Sstevel@tonic-gate px_dma_setup(dev_info_t *dip, dev_info_t *rdip, ddi_dma_req_t *dmareq, 7687c478bd9Sstevel@tonic-gate ddi_dma_handle_t *handlep) 7697c478bd9Sstevel@tonic-gate { 7707c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 7717c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p; 7727c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp; 7737c478bd9Sstevel@tonic-gate int ret; 7747c478bd9Sstevel@tonic-gate 7757c478bd9Sstevel@tonic-gate DBG(DBG_DMA_MAP, dip, "mapping - rdip=%s%d type=%s\n", 7767c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), 7777c478bd9Sstevel@tonic-gate handlep ? "alloc" : "advisory"); 7787c478bd9Sstevel@tonic-gate 7797c478bd9Sstevel@tonic-gate if (!(mp = px_dma_lmts2hdl(dip, rdip, mmu_p, dmareq))) 7807c478bd9Sstevel@tonic-gate return (DDI_DMA_NORESOURCES); 7817c478bd9Sstevel@tonic-gate if (mp == (ddi_dma_impl_t *)DDI_DMA_NOMAPPING) 7827c478bd9Sstevel@tonic-gate return (DDI_DMA_NOMAPPING); 7837c478bd9Sstevel@tonic-gate if (ret = px_dma_type(px_p, dmareq, mp)) 7847c478bd9Sstevel@tonic-gate goto freehandle; 7857c478bd9Sstevel@tonic-gate if (ret = px_dma_pfn(px_p, dmareq, mp)) 7867c478bd9Sstevel@tonic-gate goto freehandle; 7877c478bd9Sstevel@tonic-gate 7887c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 78936fe4a92Segillett case PX_DMAI_FLAGS_DVMA: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 7907c478bd9Sstevel@tonic-gate if ((ret = px_dvma_win(px_p, dmareq, mp)) || !handlep) 7917c478bd9Sstevel@tonic-gate goto freehandle; 7927c478bd9Sstevel@tonic-gate if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 7937c478bd9Sstevel@tonic-gate if (PX_DMA_CANFAST(mp)) { 7947c478bd9Sstevel@tonic-gate if (!px_dvma_map_fast(mmu_p, mp)) 7957c478bd9Sstevel@tonic-gate break; 7967c478bd9Sstevel@tonic-gate /* LINTED E_NOP_ELSE_STMT */ 7977c478bd9Sstevel@tonic-gate } else { 7987c478bd9Sstevel@tonic-gate PX_DVMA_FASTTRAK_PROF(mp); 7997c478bd9Sstevel@tonic-gate } 8007c478bd9Sstevel@tonic-gate } 8017c478bd9Sstevel@tonic-gate if (ret = px_dvma_map(mp, dmareq, mmu_p)) 8027c478bd9Sstevel@tonic-gate goto freehandle; 8037c478bd9Sstevel@tonic-gate break; 80436fe4a92Segillett case PX_DMAI_FLAGS_PTP: /* LINTED E_EQUALITY_NOT_ASSIGNMENT */ 8057c478bd9Sstevel@tonic-gate if ((ret = px_dma_physwin(px_p, dmareq, mp)) || !handlep) 8067c478bd9Sstevel@tonic-gate goto freehandle; 8077c478bd9Sstevel@tonic-gate break; 80836fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: 8097c478bd9Sstevel@tonic-gate default: 8107c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_setup: bad dma type 0x%x", 8117c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), 8127c478bd9Sstevel@tonic-gate PX_DMA_TYPE(mp)); 8137c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 8147c478bd9Sstevel@tonic-gate } 8157c478bd9Sstevel@tonic-gate *handlep = (ddi_dma_handle_t)mp; 81636fe4a92Segillett mp->dmai_flags |= PX_DMAI_FLAGS_INUSE; 8177c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 8187c478bd9Sstevel@tonic-gate 8197c478bd9Sstevel@tonic-gate return ((mp->dmai_nwin == 1) ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 8207c478bd9Sstevel@tonic-gate freehandle: 8217c478bd9Sstevel@tonic-gate if (ret == DDI_DMA_NORESOURCES) 8227c478bd9Sstevel@tonic-gate px_dma_freemp(mp); /* don't run_callback() */ 8237c478bd9Sstevel@tonic-gate else 8247c478bd9Sstevel@tonic-gate (void) px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 8257c478bd9Sstevel@tonic-gate return (ret); 8267c478bd9Sstevel@tonic-gate } 8277c478bd9Sstevel@tonic-gate 8287c478bd9Sstevel@tonic-gate 8297c478bd9Sstevel@tonic-gate /* 8307c478bd9Sstevel@tonic-gate * bus dma alloc handle entry point: 8317c478bd9Sstevel@tonic-gate */ 8327c478bd9Sstevel@tonic-gate int 8337c478bd9Sstevel@tonic-gate px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 8347c478bd9Sstevel@tonic-gate int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 8357c478bd9Sstevel@tonic-gate { 8367c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 8377c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp; 8387c478bd9Sstevel@tonic-gate int rval; 8397c478bd9Sstevel@tonic-gate 8407c478bd9Sstevel@tonic-gate DBG(DBG_DMA_ALLOCH, dip, "rdip=%s%d\n", 8417c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 8427c478bd9Sstevel@tonic-gate 8437c478bd9Sstevel@tonic-gate if (attrp->dma_attr_version != DMA_ATTR_V0) 8447c478bd9Sstevel@tonic-gate return (DDI_DMA_BADATTR); 8457c478bd9Sstevel@tonic-gate 8467c478bd9Sstevel@tonic-gate if (!(mp = px_dma_allocmp(dip, rdip, waitfp, arg))) 8477c478bd9Sstevel@tonic-gate return (DDI_DMA_NORESOURCES); 8487c478bd9Sstevel@tonic-gate 8497c478bd9Sstevel@tonic-gate /* 8507c478bd9Sstevel@tonic-gate * Save requestor's information 8517c478bd9Sstevel@tonic-gate */ 8527c478bd9Sstevel@tonic-gate mp->dmai_attr = *attrp; /* whole object - augmented later */ 85336fe4a92Segillett *PX_DEV_ATTR(mp) = *attrp; /* whole object - device orig attr */ 8547c478bd9Sstevel@tonic-gate DBG(DBG_DMA_ALLOCH, dip, "mp=%p\n", mp); 8557c478bd9Sstevel@tonic-gate 8567c478bd9Sstevel@tonic-gate /* check and convert dma attributes to handle parameters */ 8577c478bd9Sstevel@tonic-gate if (rval = px_dma_attr2hdl(px_p, mp)) { 8587c478bd9Sstevel@tonic-gate px_dma_freehdl(dip, rdip, (ddi_dma_handle_t)mp); 8597c478bd9Sstevel@tonic-gate *handlep = NULL; 8607c478bd9Sstevel@tonic-gate return (rval); 8617c478bd9Sstevel@tonic-gate } 8627c478bd9Sstevel@tonic-gate *handlep = (ddi_dma_handle_t)mp; 8637c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 8647c478bd9Sstevel@tonic-gate } 8657c478bd9Sstevel@tonic-gate 8667c478bd9Sstevel@tonic-gate 8677c478bd9Sstevel@tonic-gate /* 8687c478bd9Sstevel@tonic-gate * bus dma free handle entry point: 8697c478bd9Sstevel@tonic-gate */ 8707c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 8717c478bd9Sstevel@tonic-gate int 8727c478bd9Sstevel@tonic-gate px_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 8737c478bd9Sstevel@tonic-gate { 8747c478bd9Sstevel@tonic-gate DBG(DBG_DMA_FREEH, dip, "rdip=%s%d mp=%p\n", 8757c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 8767c478bd9Sstevel@tonic-gate px_dma_freemp((ddi_dma_impl_t *)handle); 8777c478bd9Sstevel@tonic-gate 8787c478bd9Sstevel@tonic-gate if (px_kmem_clid) { 8797c478bd9Sstevel@tonic-gate DBG(DBG_DMA_FREEH, dip, "run handle callback\n"); 8807c478bd9Sstevel@tonic-gate ddi_run_callback(&px_kmem_clid); 8817c478bd9Sstevel@tonic-gate } 8827c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 8837c478bd9Sstevel@tonic-gate } 8847c478bd9Sstevel@tonic-gate 8857c478bd9Sstevel@tonic-gate 8867c478bd9Sstevel@tonic-gate /* 8877c478bd9Sstevel@tonic-gate * bus dma bind handle entry point: 8887c478bd9Sstevel@tonic-gate */ 8897c478bd9Sstevel@tonic-gate int 8907c478bd9Sstevel@tonic-gate px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 8917c478bd9Sstevel@tonic-gate ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 8927c478bd9Sstevel@tonic-gate ddi_dma_cookie_t *cookiep, uint_t *ccountp) 8937c478bd9Sstevel@tonic-gate { 8947c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 8957c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p; 8967c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 8977c478bd9Sstevel@tonic-gate int ret; 8987c478bd9Sstevel@tonic-gate 8997c478bd9Sstevel@tonic-gate DBG(DBG_DMA_BINDH, dip, "rdip=%s%d mp=%p dmareq=%p\n", 9007c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), mp, dmareq); 9017c478bd9Sstevel@tonic-gate 90236fe4a92Segillett if (mp->dmai_flags & PX_DMAI_FLAGS_INUSE) 9037c478bd9Sstevel@tonic-gate return (DDI_DMA_INUSE); 9047c478bd9Sstevel@tonic-gate 90536fe4a92Segillett ASSERT((mp->dmai_flags & ~PX_DMAI_FLAGS_PRESERVE) == 0); 90636fe4a92Segillett mp->dmai_flags |= PX_DMAI_FLAGS_INUSE; 9077c478bd9Sstevel@tonic-gate 9087c478bd9Sstevel@tonic-gate if (ret = px_dma_type(px_p, dmareq, mp)) 9097c478bd9Sstevel@tonic-gate goto err; 9107c478bd9Sstevel@tonic-gate if (ret = px_dma_pfn(px_p, dmareq, mp)) 9117c478bd9Sstevel@tonic-gate goto err; 9127c478bd9Sstevel@tonic-gate 9137c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 91436fe4a92Segillett case PX_DMAI_FLAGS_DVMA: 9157c478bd9Sstevel@tonic-gate if (ret = px_dvma_win(px_p, dmareq, mp)) 9167c478bd9Sstevel@tonic-gate goto map_err; 9177c478bd9Sstevel@tonic-gate if (!PX_DMA_CANCACHE(mp)) { /* try fast track */ 9187c478bd9Sstevel@tonic-gate if (PX_DMA_CANFAST(mp)) { 9197c478bd9Sstevel@tonic-gate if (!px_dvma_map_fast(mmu_p, mp)) 9207c478bd9Sstevel@tonic-gate goto mapped; /*LINTED E_NOP_ELSE_STMT*/ 9217c478bd9Sstevel@tonic-gate } else { 9227c478bd9Sstevel@tonic-gate PX_DVMA_FASTTRAK_PROF(mp); 9237c478bd9Sstevel@tonic-gate } 9247c478bd9Sstevel@tonic-gate } 9257c478bd9Sstevel@tonic-gate if (ret = px_dvma_map(mp, dmareq, mmu_p)) 9267c478bd9Sstevel@tonic-gate goto map_err; 9277c478bd9Sstevel@tonic-gate mapped: 9287c478bd9Sstevel@tonic-gate *ccountp = 1; 9297c478bd9Sstevel@tonic-gate MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, mp->dmai_size); 9307c478bd9Sstevel@tonic-gate break; 93136fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: 93236fe4a92Segillett case PX_DMAI_FLAGS_PTP: 9337c478bd9Sstevel@tonic-gate if (ret = px_dma_physwin(px_p, dmareq, mp)) 9347c478bd9Sstevel@tonic-gate goto map_err; 93536fe4a92Segillett *ccountp = PX_WINLST(mp)->win_ncookies; 93636fe4a92Segillett *cookiep = 93736fe4a92Segillett *(ddi_dma_cookie_t *)(PX_WINLST(mp) + 1); /* wholeobj */ 9387c478bd9Sstevel@tonic-gate break; 9397c478bd9Sstevel@tonic-gate default: 9407c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_bindhdl(%p): bad dma type", 9417c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 9427c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 9437c478bd9Sstevel@tonic-gate } 94469cd775fSschwartz DBG(DBG_DMA_BINDH, dip, "cookie %" PRIx64 "+%x\n", 94569cd775fSschwartz cookiep->dmac_address, cookiep->dmac_size); 9467c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_MAP, dip, mp); 947f8d2de6bSjchu 948f8d2de6bSjchu /* insert dma handle into FMA cache */ 94900d0963fSdilpreet if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) { 950f8d2de6bSjchu (void) ndi_fmc_insert(rdip, DMA_HANDLE, mp, NULL); 951eae2e508Skrishnae mp->dmai_error.err_cf = px_err_dma_hdl_check; 95200d0963fSdilpreet } 953f8d2de6bSjchu 9547c478bd9Sstevel@tonic-gate return (mp->dmai_nwin == 1 ? DDI_DMA_MAPPED : DDI_DMA_PARTIAL_MAP); 9557c478bd9Sstevel@tonic-gate map_err: 9567c478bd9Sstevel@tonic-gate px_dma_freepfn(mp); 9577c478bd9Sstevel@tonic-gate err: 95836fe4a92Segillett mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE; 9597c478bd9Sstevel@tonic-gate return (ret); 9607c478bd9Sstevel@tonic-gate } 9617c478bd9Sstevel@tonic-gate 9627c478bd9Sstevel@tonic-gate 9637c478bd9Sstevel@tonic-gate /* 9647c478bd9Sstevel@tonic-gate * bus dma unbind handle entry point: 9657c478bd9Sstevel@tonic-gate */ 9667c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 9677c478bd9Sstevel@tonic-gate int 9687c478bd9Sstevel@tonic-gate px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 9697c478bd9Sstevel@tonic-gate { 9707c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 9717c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 9727c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p; 9737c478bd9Sstevel@tonic-gate 9747c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "rdip=%s%d, mp=%p\n", 9757c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), handle); 97636fe4a92Segillett if ((mp->dmai_flags & PX_DMAI_FLAGS_INUSE) == 0) { 9777c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "handle not inuse\n"); 9787c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 9797c478bd9Sstevel@tonic-gate } 9807c478bd9Sstevel@tonic-gate 981f8d2de6bSjchu /* remove dma handle from FMA cache */ 982f8d2de6bSjchu if (mp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) { 983f8d2de6bSjchu if (DEVI(rdip)->devi_fmhdl != NULL && 984f8d2de6bSjchu DDI_FM_DMA_ERR_CAP(DEVI(rdip)->devi_fmhdl->fh_cap)) { 985f8d2de6bSjchu (void) ndi_fmc_remove(rdip, DMA_HANDLE, mp); 986f8d2de6bSjchu } 987f8d2de6bSjchu } 988f8d2de6bSjchu 9897c478bd9Sstevel@tonic-gate /* 9907c478bd9Sstevel@tonic-gate * Here if the handle is using the iommu. Unload all the iommu 9917c478bd9Sstevel@tonic-gate * translations. 9927c478bd9Sstevel@tonic-gate */ 9937c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 99436fe4a92Segillett case PX_DMAI_FLAGS_DVMA: 9957c478bd9Sstevel@tonic-gate px_mmu_unmap_window(mmu_p, mp); 9967c478bd9Sstevel@tonic-gate px_dvma_unmap(mmu_p, mp); 9977c478bd9Sstevel@tonic-gate px_dma_freepfn(mp); 9987c478bd9Sstevel@tonic-gate break; 99936fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: 100036fe4a92Segillett case PX_DMAI_FLAGS_PTP: 10017c478bd9Sstevel@tonic-gate px_dma_freewin(mp); 10027c478bd9Sstevel@tonic-gate break; 10037c478bd9Sstevel@tonic-gate default: 10047c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_unbindhdl:bad dma type %p", 10057c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), mp); 10067c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 10077c478bd9Sstevel@tonic-gate } 10087c478bd9Sstevel@tonic-gate if (mmu_p->mmu_dvma_clid != 0) { 10097c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "run dvma callback\n"); 10107c478bd9Sstevel@tonic-gate ddi_run_callback(&mmu_p->mmu_dvma_clid); 10117c478bd9Sstevel@tonic-gate } 10127c478bd9Sstevel@tonic-gate if (px_kmem_clid) { 10137c478bd9Sstevel@tonic-gate DBG(DBG_DMA_UNBINDH, dip, "run handle callback\n"); 10147c478bd9Sstevel@tonic-gate ddi_run_callback(&px_kmem_clid); 10157c478bd9Sstevel@tonic-gate } 101636fe4a92Segillett mp->dmai_flags &= PX_DMAI_FLAGS_PRESERVE; 1017f8d2de6bSjchu 10187c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 10197c478bd9Sstevel@tonic-gate } 10207c478bd9Sstevel@tonic-gate 10217c478bd9Sstevel@tonic-gate /* 10227c478bd9Sstevel@tonic-gate * bus dma win entry point: 10237c478bd9Sstevel@tonic-gate */ 10247c478bd9Sstevel@tonic-gate int 10257c478bd9Sstevel@tonic-gate px_dma_win(dev_info_t *dip, dev_info_t *rdip, 10267c478bd9Sstevel@tonic-gate ddi_dma_handle_t handle, uint_t win, off_t *offp, 10277c478bd9Sstevel@tonic-gate size_t *lenp, ddi_dma_cookie_t *cookiep, uint_t *ccountp) 10287c478bd9Sstevel@tonic-gate { 10297c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 10307c478bd9Sstevel@tonic-gate int ret; 10317c478bd9Sstevel@tonic-gate 10327c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip, "rdip=%s%d\n", 10337c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 10347c478bd9Sstevel@tonic-gate 10357c478bd9Sstevel@tonic-gate px_dump_dma_handle(DBG_DMA_WIN, dip, mp); 10367c478bd9Sstevel@tonic-gate if (win >= mp->dmai_nwin) { 10377c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip, "%x out of range\n", win); 10387c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 10397c478bd9Sstevel@tonic-gate } 10407c478bd9Sstevel@tonic-gate 10417c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 104236fe4a92Segillett case PX_DMAI_FLAGS_DVMA: 10437c478bd9Sstevel@tonic-gate if (win != PX_DMA_CURWIN(mp)) { 10447c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 10457c478bd9Sstevel@tonic-gate px_mmu_t *mmu_p = px_p->px_mmu_p; 10467c478bd9Sstevel@tonic-gate px_mmu_unmap_window(mmu_p, mp); 10477c478bd9Sstevel@tonic-gate 10487c478bd9Sstevel@tonic-gate /* map_window sets dmai_mapping/size/offset */ 10497c478bd9Sstevel@tonic-gate px_mmu_map_window(mmu_p, mp, win); 10507c478bd9Sstevel@tonic-gate if ((ret = px_mmu_map_window(mmu_p, 10517c478bd9Sstevel@tonic-gate mp, win)) != DDI_SUCCESS) 10527c478bd9Sstevel@tonic-gate return (ret); 10537c478bd9Sstevel@tonic-gate } 10547c478bd9Sstevel@tonic-gate if (cookiep) 10557c478bd9Sstevel@tonic-gate MAKE_DMA_COOKIE(cookiep, mp->dmai_mapping, 10567c478bd9Sstevel@tonic-gate mp->dmai_size); 10577c478bd9Sstevel@tonic-gate if (ccountp) 10587c478bd9Sstevel@tonic-gate *ccountp = 1; 10597c478bd9Sstevel@tonic-gate break; 106036fe4a92Segillett case PX_DMAI_FLAGS_PTP: 106136fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: { 10627c478bd9Sstevel@tonic-gate int i; 10637c478bd9Sstevel@tonic-gate ddi_dma_cookie_t *ck_p; 10647c478bd9Sstevel@tonic-gate px_dma_win_t *win_p = mp->dmai_winlst; 10657c478bd9Sstevel@tonic-gate 1066eae2e508Skrishnae for (i = 0; i < win; win_p = win_p->win_next, i++) {}; 10677c478bd9Sstevel@tonic-gate ck_p = (ddi_dma_cookie_t *)(win_p + 1); 10687c478bd9Sstevel@tonic-gate *cookiep = *ck_p; 10697c478bd9Sstevel@tonic-gate mp->dmai_offset = win_p->win_offset; 10707c478bd9Sstevel@tonic-gate mp->dmai_size = win_p->win_size; 10717c478bd9Sstevel@tonic-gate mp->dmai_mapping = ck_p->dmac_laddress; 10727c478bd9Sstevel@tonic-gate mp->dmai_cookie = ck_p + 1; 10737c478bd9Sstevel@tonic-gate win_p->win_curseg = 0; 10747c478bd9Sstevel@tonic-gate if (ccountp) 10757c478bd9Sstevel@tonic-gate *ccountp = win_p->win_ncookies; 10767c478bd9Sstevel@tonic-gate } 10777c478bd9Sstevel@tonic-gate break; 10787c478bd9Sstevel@tonic-gate default: 10797c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: px_dma_win:bad dma type 0x%x", 10807c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), 10817c478bd9Sstevel@tonic-gate PX_DMA_TYPE(mp)); 10827c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 10837c478bd9Sstevel@tonic-gate } 10847c478bd9Sstevel@tonic-gate if (cookiep) 10857c478bd9Sstevel@tonic-gate DBG(DBG_DMA_WIN, dip, 10867c478bd9Sstevel@tonic-gate "cookie - dmac_address=%x dmac_size=%x\n", 10877c478bd9Sstevel@tonic-gate cookiep->dmac_address, cookiep->dmac_size); 10887c478bd9Sstevel@tonic-gate if (offp) 10897c478bd9Sstevel@tonic-gate *offp = (off_t)mp->dmai_offset; 10907c478bd9Sstevel@tonic-gate if (lenp) 10917c478bd9Sstevel@tonic-gate *lenp = mp->dmai_size; 10927c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 10937c478bd9Sstevel@tonic-gate } 10947c478bd9Sstevel@tonic-gate 10957c478bd9Sstevel@tonic-gate #ifdef DEBUG 10967c478bd9Sstevel@tonic-gate static char *px_dmactl_str[] = { 10977c478bd9Sstevel@tonic-gate "DDI_DMA_FREE", 10987c478bd9Sstevel@tonic-gate "DDI_DMA_SYNC", 10997c478bd9Sstevel@tonic-gate "DDI_DMA_HTOC", 11007c478bd9Sstevel@tonic-gate "DDI_DMA_KVADDR", 11017c478bd9Sstevel@tonic-gate "DDI_DMA_MOVWIN", 11027c478bd9Sstevel@tonic-gate "DDI_DMA_REPWIN", 11037c478bd9Sstevel@tonic-gate "DDI_DMA_GETERR", 11047c478bd9Sstevel@tonic-gate "DDI_DMA_COFF", 11057c478bd9Sstevel@tonic-gate "DDI_DMA_NEXTWIN", 11067c478bd9Sstevel@tonic-gate "DDI_DMA_NEXTSEG", 11077c478bd9Sstevel@tonic-gate "DDI_DMA_SEGTOC", 11087c478bd9Sstevel@tonic-gate "DDI_DMA_RESERVE", 11097c478bd9Sstevel@tonic-gate "DDI_DMA_RELEASE", 11107c478bd9Sstevel@tonic-gate "DDI_DMA_RESETH", 11117c478bd9Sstevel@tonic-gate "DDI_DMA_CKSYNC", 11127c478bd9Sstevel@tonic-gate "DDI_DMA_IOPB_ALLOC", 11137c478bd9Sstevel@tonic-gate "DDI_DMA_IOPB_FREE", 11147c478bd9Sstevel@tonic-gate "DDI_DMA_SMEM_ALLOC", 11157c478bd9Sstevel@tonic-gate "DDI_DMA_SMEM_FREE", 11167c478bd9Sstevel@tonic-gate "DDI_DMA_SET_SBUS64" 11177c478bd9Sstevel@tonic-gate }; 11187c478bd9Sstevel@tonic-gate #endif /* DEBUG */ 11197c478bd9Sstevel@tonic-gate 11207c478bd9Sstevel@tonic-gate /* 11217c478bd9Sstevel@tonic-gate * bus dma control entry point: 11227c478bd9Sstevel@tonic-gate */ 11237c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 11247c478bd9Sstevel@tonic-gate int 11257c478bd9Sstevel@tonic-gate px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 11267c478bd9Sstevel@tonic-gate enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 11277c478bd9Sstevel@tonic-gate uint_t cache_flags) 11287c478bd9Sstevel@tonic-gate { 11297c478bd9Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 11307c478bd9Sstevel@tonic-gate 11317c478bd9Sstevel@tonic-gate #ifdef DEBUG 11327c478bd9Sstevel@tonic-gate DBG(DBG_DMA_CTL, dip, "%s: rdip=%s%d\n", px_dmactl_str[cmd], 11337c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 11347c478bd9Sstevel@tonic-gate #endif /* DEBUG */ 11357c478bd9Sstevel@tonic-gate 11367c478bd9Sstevel@tonic-gate switch (cmd) { 11377c478bd9Sstevel@tonic-gate case DDI_DMA_FREE: 11387c478bd9Sstevel@tonic-gate (void) px_dma_unbindhdl(dip, rdip, handle); 11397c478bd9Sstevel@tonic-gate (void) px_dma_freehdl(dip, rdip, handle); 11407c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 11417c478bd9Sstevel@tonic-gate case DDI_DMA_RESERVE: { 11427c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 11437c478bd9Sstevel@tonic-gate return (px_fdvma_reserve(dip, rdip, px_p, 11447c478bd9Sstevel@tonic-gate (ddi_dma_req_t *)offp, (ddi_dma_handle_t *)objp)); 11457c478bd9Sstevel@tonic-gate } 11467c478bd9Sstevel@tonic-gate case DDI_DMA_RELEASE: { 11477c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 11487c478bd9Sstevel@tonic-gate return (px_fdvma_release(dip, px_p, mp)); 11497c478bd9Sstevel@tonic-gate } 11507c478bd9Sstevel@tonic-gate default: 11517c478bd9Sstevel@tonic-gate break; 11527c478bd9Sstevel@tonic-gate } 11537c478bd9Sstevel@tonic-gate 11547c478bd9Sstevel@tonic-gate switch (PX_DMA_TYPE(mp)) { 115536fe4a92Segillett case PX_DMAI_FLAGS_DVMA: 11567c478bd9Sstevel@tonic-gate return (px_dvma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 11577c478bd9Sstevel@tonic-gate cache_flags)); 115836fe4a92Segillett case PX_DMAI_FLAGS_PTP: 115936fe4a92Segillett case PX_DMAI_FLAGS_BYPASS: 11607c478bd9Sstevel@tonic-gate return (px_dma_ctl(dip, rdip, mp, cmd, offp, lenp, objp, 11617c478bd9Sstevel@tonic-gate cache_flags)); 11627c478bd9Sstevel@tonic-gate default: 11637c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: px_dma_ctlops(%x):bad dma type %x", 11647c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), cmd, 11657c478bd9Sstevel@tonic-gate mp->dmai_flags); 11667c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 11677c478bd9Sstevel@tonic-gate } 1168b40cec45Skrishnae return (0); 11697c478bd9Sstevel@tonic-gate } 11707c478bd9Sstevel@tonic-gate 11717c478bd9Sstevel@tonic-gate /* 11727c478bd9Sstevel@tonic-gate * control ops entry point: 11737c478bd9Sstevel@tonic-gate * 11747c478bd9Sstevel@tonic-gate * Requests handled completely: 11757c478bd9Sstevel@tonic-gate * DDI_CTLOPS_INITCHILD see init_child() for details 11767c478bd9Sstevel@tonic-gate * DDI_CTLOPS_UNINITCHILD 11777c478bd9Sstevel@tonic-gate * DDI_CTLOPS_REPORTDEV see report_dev() for details 11787c478bd9Sstevel@tonic-gate * DDI_CTLOPS_IOMIN cache line size if streaming otherwise 1 11797c478bd9Sstevel@tonic-gate * DDI_CTLOPS_REGSIZE 11807c478bd9Sstevel@tonic-gate * DDI_CTLOPS_NREGS 11817c478bd9Sstevel@tonic-gate * DDI_CTLOPS_DVMAPAGESIZE 11827c478bd9Sstevel@tonic-gate * DDI_CTLOPS_POKE 11837c478bd9Sstevel@tonic-gate * DDI_CTLOPS_PEEK 11847c478bd9Sstevel@tonic-gate * 11857c478bd9Sstevel@tonic-gate * All others passed to parent. 11867c478bd9Sstevel@tonic-gate */ 11877c478bd9Sstevel@tonic-gate int 11887c478bd9Sstevel@tonic-gate px_ctlops(dev_info_t *dip, dev_info_t *rdip, 11897c478bd9Sstevel@tonic-gate ddi_ctl_enum_t op, void *arg, void *result) 11907c478bd9Sstevel@tonic-gate { 11917c478bd9Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 11927c478bd9Sstevel@tonic-gate struct detachspec *ds; 11937c478bd9Sstevel@tonic-gate struct attachspec *as; 11947c478bd9Sstevel@tonic-gate 11957c478bd9Sstevel@tonic-gate switch (op) { 11967c478bd9Sstevel@tonic-gate case DDI_CTLOPS_INITCHILD: 11977c478bd9Sstevel@tonic-gate return (px_init_child(px_p, (dev_info_t *)arg)); 11987c478bd9Sstevel@tonic-gate 11997c478bd9Sstevel@tonic-gate case DDI_CTLOPS_UNINITCHILD: 12007c478bd9Sstevel@tonic-gate return (px_uninit_child(px_p, (dev_info_t *)arg)); 12017c478bd9Sstevel@tonic-gate 12027c478bd9Sstevel@tonic-gate case DDI_CTLOPS_ATTACH: 12036e8a7b44Sjchu if (!pcie_is_child(dip, rdip)) 12046e8a7b44Sjchu return (DDI_SUCCESS); 12056e8a7b44Sjchu 12067c478bd9Sstevel@tonic-gate as = (struct attachspec *)arg; 12077c478bd9Sstevel@tonic-gate switch (as->when) { 12087c478bd9Sstevel@tonic-gate case DDI_PRE: 12097c478bd9Sstevel@tonic-gate if (as->cmd == DDI_ATTACH) { 12107c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "PRE_ATTACH for %s@%d\n", 12117c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), 12127c478bd9Sstevel@tonic-gate ddi_get_instance(rdip)); 12137c478bd9Sstevel@tonic-gate return (pcie_pm_hold(dip)); 12147c478bd9Sstevel@tonic-gate } 12158bc7d88aSet142600 if (as->cmd == DDI_RESUME) { 12168bc7d88aSet142600 DBG(DBG_PWR, dip, "PRE_RESUME for %s@%d\n", 12178bc7d88aSet142600 ddi_driver_name(rdip), 12188bc7d88aSet142600 ddi_get_instance(rdip)); 12198bc7d88aSet142600 1220eae2e508Skrishnae pcie_clear_errors(rdip); 12218bc7d88aSet142600 } 12227c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12237c478bd9Sstevel@tonic-gate 12247c478bd9Sstevel@tonic-gate case DDI_POST: 12257c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "POST_ATTACH for %s@%d\n", 12267c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 1227c2cc6e07SRamesh Chitrothu if (as->cmd == DDI_ATTACH && 1228c2cc6e07SRamesh Chitrothu as->result != DDI_SUCCESS) { 1229c2cc6e07SRamesh Chitrothu /* 1230c2cc6e07SRamesh Chitrothu * Attach failed for the child device. The child 1231c2cc6e07SRamesh Chitrothu * driver may have made PM calls before the 1232c2cc6e07SRamesh Chitrothu * attach failed. pcie_pm_remove_child() should 1233c2cc6e07SRamesh Chitrothu * cleanup PM state and holds (if any) 1234c2cc6e07SRamesh Chitrothu * associated with the child device. 1235c2cc6e07SRamesh Chitrothu */ 1236c2cc6e07SRamesh Chitrothu return (pcie_pm_remove_child(dip, rdip)); 1237c2cc6e07SRamesh Chitrothu } 123813683ea2Skrishnae 1239e0d05aa9Skrishnae if (as->result == DDI_SUCCESS) 12400c5eba8cSkrishnae pf_init(rdip, (void *)px_p->px_fm_ibc, as->cmd); 1241bf8fc234Set142600 124213683ea2Skrishnae (void) pcie_postattach_child(rdip); 124313683ea2Skrishnae 12447c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12457c478bd9Sstevel@tonic-gate default: 12467c478bd9Sstevel@tonic-gate break; 12477c478bd9Sstevel@tonic-gate } 12487c478bd9Sstevel@tonic-gate break; 12497c478bd9Sstevel@tonic-gate 12507c478bd9Sstevel@tonic-gate case DDI_CTLOPS_DETACH: 1251025c5d04Sjchu if (!pcie_is_child(dip, rdip)) 1252025c5d04Sjchu return (DDI_SUCCESS); 1253025c5d04Sjchu 12547c478bd9Sstevel@tonic-gate ds = (struct detachspec *)arg; 12557c478bd9Sstevel@tonic-gate switch (ds->when) { 12567c478bd9Sstevel@tonic-gate case DDI_POST: 12577c478bd9Sstevel@tonic-gate if (ds->cmd == DDI_DETACH && 12587c478bd9Sstevel@tonic-gate ds->result == DDI_SUCCESS) { 12597c478bd9Sstevel@tonic-gate DBG(DBG_PWR, dip, "POST_DETACH for %s@%d\n", 12607c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), 12617c478bd9Sstevel@tonic-gate ddi_get_instance(rdip)); 12627c478bd9Sstevel@tonic-gate return (pcie_pm_remove_child(dip, rdip)); 12637c478bd9Sstevel@tonic-gate } 12647c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 1265bf8fc234Set142600 case DDI_PRE: 12660c5eba8cSkrishnae pf_fini(rdip, ds->cmd); 1267bf8fc234Set142600 return (DDI_SUCCESS); 12687c478bd9Sstevel@tonic-gate default: 12697c478bd9Sstevel@tonic-gate break; 12707c478bd9Sstevel@tonic-gate } 12717c478bd9Sstevel@tonic-gate break; 12727c478bd9Sstevel@tonic-gate 12737c478bd9Sstevel@tonic-gate case DDI_CTLOPS_REPORTDEV: 12747c478bd9Sstevel@tonic-gate return (px_report_dev(rdip)); 12757c478bd9Sstevel@tonic-gate 12767c478bd9Sstevel@tonic-gate case DDI_CTLOPS_IOMIN: 12777c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12787c478bd9Sstevel@tonic-gate 12797c478bd9Sstevel@tonic-gate case DDI_CTLOPS_REGSIZE: 12807c478bd9Sstevel@tonic-gate *((off_t *)result) = px_get_reg_set_size(rdip, *((int *)arg)); 1281f8d2de6bSjchu return (*((off_t *)result) == 0 ? DDI_FAILURE : DDI_SUCCESS); 12827c478bd9Sstevel@tonic-gate 12837c478bd9Sstevel@tonic-gate case DDI_CTLOPS_NREGS: 12847c478bd9Sstevel@tonic-gate *((uint_t *)result) = px_get_nreg_set(rdip); 12857c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12867c478bd9Sstevel@tonic-gate 12877c478bd9Sstevel@tonic-gate case DDI_CTLOPS_DVMAPAGESIZE: 12887c478bd9Sstevel@tonic-gate *((ulong_t *)result) = MMU_PAGE_SIZE; 12897c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12907c478bd9Sstevel@tonic-gate 12917c478bd9Sstevel@tonic-gate case DDI_CTLOPS_POKE: /* platform dependent implementation. */ 12927c478bd9Sstevel@tonic-gate return (px_lib_ctlops_poke(dip, rdip, 12937c478bd9Sstevel@tonic-gate (peekpoke_ctlops_t *)arg)); 12947c478bd9Sstevel@tonic-gate 12957c478bd9Sstevel@tonic-gate case DDI_CTLOPS_PEEK: /* platform dependent implementation. */ 12967c478bd9Sstevel@tonic-gate return (px_lib_ctlops_peek(dip, rdip, 12977c478bd9Sstevel@tonic-gate (peekpoke_ctlops_t *)arg, result)); 12987c478bd9Sstevel@tonic-gate 12997c478bd9Sstevel@tonic-gate case DDI_CTLOPS_POWER: 13007c478bd9Sstevel@tonic-gate default: 13017c478bd9Sstevel@tonic-gate break; 13027c478bd9Sstevel@tonic-gate } 13037c478bd9Sstevel@tonic-gate 13047c478bd9Sstevel@tonic-gate /* 13057c478bd9Sstevel@tonic-gate * Now pass the request up to our parent. 13067c478bd9Sstevel@tonic-gate */ 13077c478bd9Sstevel@tonic-gate DBG(DBG_CTLOPS, dip, "passing request to parent: rdip=%s%d\n", 13087c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 13097c478bd9Sstevel@tonic-gate return (ddi_ctlops(dip, rdip, op, arg, result)); 13107c478bd9Sstevel@tonic-gate } 13117c478bd9Sstevel@tonic-gate 13127c478bd9Sstevel@tonic-gate /* ARGSUSED */ 13137c478bd9Sstevel@tonic-gate int 13147c478bd9Sstevel@tonic-gate px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 13157c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 13167c478bd9Sstevel@tonic-gate { 13177c478bd9Sstevel@tonic-gate int intr_types, ret = DDI_SUCCESS; 13187c478bd9Sstevel@tonic-gate 13197c478bd9Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intr_ops: rdip=%s%d\n", 13207c478bd9Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 13217c478bd9Sstevel@tonic-gate 13227c478bd9Sstevel@tonic-gate /* Process DDI_INTROP_SUPPORTED_TYPES request here */ 13237c478bd9Sstevel@tonic-gate if (intr_op == DDI_INTROP_SUPPORTED_TYPES) { 1324a54f81fbSanish *(int *)result = i_ddi_get_intx_nintrs(rdip) ? 13257c478bd9Sstevel@tonic-gate DDI_INTR_TYPE_FIXED : 0; 13267c478bd9Sstevel@tonic-gate 13277c478bd9Sstevel@tonic-gate if ((pci_msi_get_supported_type(rdip, 13287c478bd9Sstevel@tonic-gate &intr_types)) == DDI_SUCCESS) { 13297c478bd9Sstevel@tonic-gate /* 13307c478bd9Sstevel@tonic-gate * Double check supported interrupt types vs. 13317c478bd9Sstevel@tonic-gate * what the host bridge supports. 13327c478bd9Sstevel@tonic-gate */ 133320036fe5Segillett *(int *)result |= intr_types; 13347c478bd9Sstevel@tonic-gate } 13357c478bd9Sstevel@tonic-gate 13367c478bd9Sstevel@tonic-gate return (ret); 13377c478bd9Sstevel@tonic-gate } 13387c478bd9Sstevel@tonic-gate 13397c478bd9Sstevel@tonic-gate /* 13407c478bd9Sstevel@tonic-gate * PCI-E nexus driver supports fixed, MSI and MSI-X interrupts. 13417c478bd9Sstevel@tonic-gate * Return failure if interrupt type is not supported. 13427c478bd9Sstevel@tonic-gate */ 13437c478bd9Sstevel@tonic-gate switch (hdlp->ih_type) { 13447c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_FIXED: 13457c478bd9Sstevel@tonic-gate ret = px_intx_ops(dip, rdip, intr_op, hdlp, result); 13467c478bd9Sstevel@tonic-gate break; 13477c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_MSI: 13487c478bd9Sstevel@tonic-gate case DDI_INTR_TYPE_MSIX: 13497c478bd9Sstevel@tonic-gate ret = px_msix_ops(dip, rdip, intr_op, hdlp, result); 13507c478bd9Sstevel@tonic-gate break; 13517c478bd9Sstevel@tonic-gate default: 13527c478bd9Sstevel@tonic-gate ret = DDI_ENOTSUP; 13537c478bd9Sstevel@tonic-gate break; 13547c478bd9Sstevel@tonic-gate } 13557c478bd9Sstevel@tonic-gate 13567c478bd9Sstevel@tonic-gate return (ret); 13577c478bd9Sstevel@tonic-gate } 1358b65731f1Skini 13590114761dSAlan Adamson, SD OSSD static void 13600114761dSAlan Adamson, SD OSSD px_set_mps(px_t *px_p) 13610114761dSAlan Adamson, SD OSSD { 13620114761dSAlan Adamson, SD OSSD dev_info_t *dip; 13630114761dSAlan Adamson, SD OSSD pcie_bus_t *bus_p; 13640114761dSAlan Adamson, SD OSSD int max_supported; 13650114761dSAlan Adamson, SD OSSD 13660114761dSAlan Adamson, SD OSSD dip = px_p->px_dip; 13670114761dSAlan Adamson, SD OSSD bus_p = PCIE_DIP2BUS(dip); 13680114761dSAlan Adamson, SD OSSD 13690114761dSAlan Adamson, SD OSSD bus_p->bus_mps = -1; 13700114761dSAlan Adamson, SD OSSD 13710114761dSAlan Adamson, SD OSSD if (pcie_root_port(dip) == DDI_FAILURE) { 13720114761dSAlan Adamson, SD OSSD if (px_lib_get_root_complex_mps(px_p, dip, 13730114761dSAlan Adamson, SD OSSD &max_supported) < 0) { 13740114761dSAlan Adamson, SD OSSD 13750114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Can not get RC MPS\n"); 13760114761dSAlan Adamson, SD OSSD return; 13770114761dSAlan Adamson, SD OSSD } 13780114761dSAlan Adamson, SD OSSD 13790114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Root Complex MPS Cap of = %x\n", 13800114761dSAlan Adamson, SD OSSD max_supported); 13810114761dSAlan Adamson, SD OSSD 13820114761dSAlan Adamson, SD OSSD if (pcie_max_mps < max_supported) 13830114761dSAlan Adamson, SD OSSD max_supported = pcie_max_mps; 13840114761dSAlan Adamson, SD OSSD 13850114761dSAlan Adamson, SD OSSD (void) pcie_get_fabric_mps(dip, ddi_get_child(dip), 13860114761dSAlan Adamson, SD OSSD &max_supported); 13870114761dSAlan Adamson, SD OSSD 13880114761dSAlan Adamson, SD OSSD bus_p->bus_mps = max_supported; 13890114761dSAlan Adamson, SD OSSD 13900114761dSAlan Adamson, SD OSSD (void) px_lib_set_root_complex_mps(px_p, dip, bus_p->bus_mps); 13910114761dSAlan Adamson, SD OSSD 13920114761dSAlan Adamson, SD OSSD DBG(DBG_MPS, dip, "MPS: Root Complex MPS Set to = %x\n", 13930114761dSAlan Adamson, SD OSSD bus_p->bus_mps); 13940114761dSAlan Adamson, SD OSSD } 13950114761dSAlan Adamson, SD OSSD } 1396