1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1983, 1991, by Sun Microsystems, Inc. 24 */ 25 26 #ifndef _SYS_SER_ZSCC_H 27 #define _SYS_SER_ZSCC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 /* 32 * Zilog 8530 SCC Serial Communications Controller 33 * 34 * This is a dual uart chip with on-chip baud rate generators. 35 * It is about as brain-damaged as the typical modern uart chip, 36 * but it does have a lot of features as well as the usual lot of 37 * brain damage around addressing, write-onlyness, etc. 38 */ 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* 45 * SCC registers: 46 * 47 * There are 16 write registers and 9 read registers in each channel. 48 * As usual, the two channels are ALMOST orthogonal, not exactly. Most regs 49 * can only be written to, or read, but not both. To access one, you must 50 * first write to register 0 with the number of the register you 51 * are interested in, then read/write the actual value, and hope that 52 * nobody interrupts you in between. 53 */ 54 55 /* bits in RR0 */ 56 #define ZSRR0_RX_READY 0x01 /* received character available */ 57 #define ZSRR0_TIMER 0x02 /* if R15_TIMER, timer reached 0 */ 58 #define ZSRR0_TX_READY 0x04 /* transmit buffer empty */ 59 #define ZSRR0_CD 0x08 /* CD input (latched if R15_CD) */ 60 #define ZSRR0_SYNC 0x10 /* SYNC input (latched if R15_SYNC) */ 61 #define ZSRR0_CTS 0x20 /* CTS input (latched if R15_CTS) */ 62 #define ZSRR0_TXUNDER 0x40 /* (SYNC) Xmitter underran */ 63 #define ZSRR0_BREAK 0x80 /* received break detected */ 64 65 /* bits in RR1 */ 66 #define ZSRR1_ALL_SENT 0x01 /* all chars fully transmitted */ 67 #define ZSRR1_PE 0x10 /* parity error (latched, must reset) */ 68 #define ZSRR1_DO 0x20 /* data overrun (latched, must reset) */ 69 #define ZSRR1_FE 0x40 /* framing/CRC error (not latched) */ 70 #define ZSRR1_RXEOF 0x80 /* end of recv sdlc frame */ 71 72 /* 73 * bits in R/WR2 -- interrupt vector number. 74 * 75 * NOTE that RR2 in channel A is unmodified, while in channel B it is 76 * modified by the current status of the UARTs. (This is independent 77 * of the setting of WR9_VIS.) If no interrupts are pending, the modified 78 * status is Channel B Special Receive. It can be written from 79 * either channel. 80 */ 81 82 #define ZSR2_TX_EMPTY_B 0x0 83 #define ZSR2_XSINT_B 0x2 84 #define ZSR2_RX_AVAIL_B 0x4 85 #define ZSR2_SRINT_B_OR_NONE 0x6 86 #define ZSR2_TX_EMPTY_A 0x8 87 #define ZSR2_XSINT_A 0xA 88 #define ZSR2_RX_AVAIL_A 0xC 89 #define ZSR2_SRINT_A 0xE 90 91 #define ZSR2_STATUS_ALL 0xE 92 93 94 /* 95 * bits in RR3 -- Interrupt Pending flags for both channels (this reg can 96 * only be read in Channel A, tho. Thanks guys.) 97 */ 98 #define ZSRR3_IP_B_STAT 0x01 /* Ext/status int pending, chan B */ 99 #define ZSRR3_IP_B_TX 0x02 /* Transmit int pending, chan B */ 100 #define ZSRR3_IP_B_RX 0x04 /* Receive int pending, chan B */ 101 #define ZSRR3_IP_A_STAT 0x08 /* Ditto for channel A */ 102 #define ZSRR3_IP_A_TX 0x10 103 #define ZSRR3_IP_A_RX 0x20 104 105 /* bits in RR8 -- this is the same as reading the Data port */ 106 107 /* bits in RR10 -- DPLL and SDLC Loop Mode status -- not entered */ 108 109 /* bits in R/WR12 -- lower byte of time constant for baud rate generator */ 110 /* bits in R/WR13 -- upper byte of time constant for baud rate generator */ 111 112 /* bits in R/WR15 -- interrupt enables for status conditions */ 113 #define ZSR15_TIMER 0x02 /* ie if baud rate generator = 0 */ 114 #define ZSR15_CD 0x08 /* ie transition on CD (car. det.) */ 115 #define ZSR15_SYNC 0x10 /* ie transition on SYNC (gen purp) */ 116 #define ZSR15_CTS 0x20 /* ie transition on CTS (clr to send) */ 117 #define ZSR15_TX_UNDER 0x40 /* (SYNC) ie transmit underrun */ 118 #define ZSR15_BREAK 0x80 /* ie on start, and end, of break */ 119 120 /* Write register 0 -- common commands and Register Pointers */ 121 #define ZSWR0_REG 0x0F /* mask: next reg to read/write */ 122 #define ZSWR0_RESET_STATUS 0x10 /* reset status bit latches */ 123 #define ZSWR0_SEND_ABORT 0x18 /* SDLC: send abort */ 124 #define ZSWR0_FIRST_RX 0x20 /* in WR1_RX_FIRST_IE, enab next int */ 125 #define ZSWR0_RESET_TXINT 0x28 /* reset transmitter interrupt */ 126 #define ZSWR0_RESET_ERRORS 0x30 /* reset read character errors */ 127 #define ZSWR0_CLR_INTR 0x38 /* Reset Interrupt In Service */ 128 #define ZSWR0_RESET_RXCRC 0x40 /* Reset Rx CRC generator */ 129 #define ZSWR0_RESET_TXCRC 0x80 /* Reset Tx CRC generator */ 130 #define ZSWR0_RESET_EOM 0xC0 /* Reset Tx underrun / EOM */ 131 132 /* bits in WR1 */ 133 #define ZSWR1_SIE 0x01 /* status change master int enable */ 134 /* Also see R15 for individual enabs */ 135 #define ZSWR1_TIE 0x02 /* transmitter interrupt enable */ 136 #define ZSWR1_PARITY_SPECIAL 0x04 /* parity err causes special rx int */ 137 #define ZSWR1_RIE_FIRST_SPECIAL 0x08 /* r.i.e. on 1st char of msg */ 138 #define ZSWR1_RIE 0x10 /* receiver interrupt enable */ 139 #define ZSWR1_RIE_SPECIAL_ONLY 0x18 /* rie on special only */ 140 #define ZSWR1_REQ_IS_RX 0x20 /* REQ pin is for receiver */ 141 #define ZSWR1_REQ_NOT_WAIT 0x40 /* REQ/WAIT pin is REQ */ 142 #define ZSWR1_REQ_ENABLE 0x80 /* enable REQ/WAIT */ 143 /* There are other Receive interrupt options defined, see data sheet. */ 144 145 /* bits in WR2 are defined above as R/WR2. */ 146 147 /* bits in WR3 */ 148 #define ZSWR3_RX_ENABLE 0x01 /* receiver enable */ 149 #define ZSWR3_RXCRC_ENABLE 0x08 /* receiver CRC enable */ 150 #define ZSWR3_HUNT 0x10 /* enter hunt mode */ 151 #define ZSWR3_AUTO_CD_CTS 0x20 /* auto-enable CD&CTS rcv&xmit ctl */ 152 #define ZSWR3_RX_5 0x00 /* receive 5-bit characters */ 153 #define ZSWR3_RX_6 0x80 /* receive 6 bit characters */ 154 #define ZSWR3_RX_7 0x40 /* receive 7 bit characters */ 155 #define ZSWR3_RX_8 0xC0 /* receive 8 bit characters */ 156 157 /* bits in WR4 */ 158 #define ZSWR4_PARITY_ENABLE 0x01 /* Gen/check parity bit */ 159 #define ZSWR4_PARITY_EVEN 0x02 /* Gen/check even parity */ 160 #define ZSWR4_1_STOP 0x04 /* 1 stop bit */ 161 #define ZSWR4_1_5_STOP 0x08 /* 1.5 stop bits */ 162 #define ZSWR4_2_STOP 0x0C /* 2 stop bits */ 163 #define ZSWR4_BISYNC 0x10 /* Bisync mode */ 164 #define ZSWR4_SDLC 0x20 /* SDLC mode */ 165 #define ZSWR4_X1_CLK 0x00 /* clock is 1x */ 166 #define ZSWR4_X16_CLK 0x40 /* clock is 16x */ 167 #define ZSWR4_X32_CLK 0x80 /* clock is 32x */ 168 #define ZSWR4_X64_CLK 0xC0 /* clock is 64x */ 169 170 /* bits in WR5 */ 171 #define ZSWR5_TXCRC_ENABLE 0x01 /* transmitter CRC enable */ 172 #define ZSWR5_RTS 0x02 /* RTS output */ 173 #define ZSWR5_CRC16 0x04 /* Use CRC-16 for checksum */ 174 #define ZSWR5_TX_ENABLE 0x08 /* transmitter enable */ 175 #define ZSWR5_BREAK 0x10 /* send break continuously */ 176 #define ZSWR5_TX_5 0x00 /* transmit 5 bit chars or less */ 177 #define ZSWR5_TX_6 0x40 /* transmit 6 bit characters */ 178 #define ZSWR5_TX_7 0x20 /* transmit 7 bit characters */ 179 #define ZSWR5_TX_8 0x60 /* transmit 8 bit characters */ 180 #define ZSWR5_DTR 0x80 /* DTR output */ 181 182 /* bits in WR6 -- Sync characters or SDLC address field. */ 183 184 /* bits in WR7 -- Sync character or SDLC flag */ 185 186 /* bits in WR8 -- transmit buffer. Same as writing to data port. */ 187 188 /* 189 * bits in WR9 -- Master interrupt control and reset. Accessible thru 190 * either channel, there's only one of them. 191 */ 192 #define ZSWR9_VECTOR_INCL_STAT 0x01 /* Include status bits in int vector */ 193 #define ZSWR9_NO_VECTOR 0x02 /* Do not respond to int ack cycles */ 194 #define ZSWR9_DIS_LOWER_CHAIN 0x04 /* Disable ints lower in daisy chain */ 195 #define ZSWR9_MASTER_IE 0x08 /* Master interrupt enable */ 196 #define ZSWR9_STAT_HIGH 0x10 /* Modify ivec bits 6-4, not 1-3 */ 197 #define ZSWR9_RESET_CHAN_B 0x40 /* Reset just channel B */ 198 #define ZSWR9_RESET_CHAN_A 0x80 /* Reset just channel A */ 199 #define ZSWR9_RESET_WORLD 0xC0 /* Force hardware reset */ 200 201 /* bits in WR10 -- SDLC, NRZI, FM control bits */ 202 #define ZSWR10_UNDERRUN_ABORT 0x04 /* send abort on TX underrun */ 203 #define ZSWR10_NRZI 0x20 /* NRZI mode (SDLC) */ 204 #define ZSWR10_PRESET_ONES 0x80 /* preset CRC to ones (SDLC) */ 205 206 /* bits in WR11 -- clock mode control */ 207 #define ZSWR11_TRXC_XTAL 0x00 /* TRxC output = xtal osc */ 208 #define ZSWR11_TRXC_XMIT 0x01 /* TRxC output = xmitter clk */ 209 #define ZSWR11_TRXC_BAUD 0x02 /* TRxC output = baud rate gen */ 210 #define ZSWR11_TRXC_DPLL 0x03 /* TRxC output = Phase Locked Loop */ 211 #define ZSWR11_TRXC_OUT_ENA 0x04 /* TRxC output enable (unless input) */ 212 #define ZSWR11_TXCLK_RTXC 0x00 /* Tx clock is RTxC pin */ 213 #define ZSWR11_TXCLK_TRXC 0x08 /* Tx clock is TRxC pin */ 214 #define ZSWR11_TXCLK_BAUD 0x10 /* Tx clock is baud rate gen output */ 215 #define ZSWR11_TXCLK_DPLL 0x18 /* Tx clock is Phase Locked Loop o/p */ 216 #define ZSWR11_RXCLK_RTXC 0x00 /* Rx clock is RTxC pin */ 217 #define ZSWR11_RXCLK_TRXC 0x20 /* Rx clock is TRxC pin */ 218 #define ZSWR11_RXCLK_BAUD 0x40 /* Rx clock is baud rate gen output */ 219 #define ZSWR11_RXCLK_DPLL 0x60 /* Rx clock is Phase Locked Loop o/p */ 220 #define ZSWR11_RTXC_XTAL 0x80 /* RTxC uses crystal, not TTL signal */ 221 222 /* bits in WR12 -- described above as R/WR12 */ 223 224 /* bits in WR13 -- described above as R/WR13 */ 225 226 /* bits in WR14 -- misc control bits, and DPLL control */ 227 #define ZSWR14_BAUD_ENA 0x01 /* enables baud rate counter */ 228 #define ZSWR14_BAUD_FROM_PCLK 0x02 /* Baud rate gen src = PCLK not RTxC */ 229 #define ZSWR14_DTR_IS_REQUEST 0x04 /* Changes DTR line to DMA Request */ 230 #define ZSWR14_AUTO_ECHO 0x08 /* Echoes RXD to TXD */ 231 #define ZSWR14_LOCAL_LOOPBACK 0x10 /* Echoes TX to RX in chip */ 232 #define ZSWR14_DPLL_NOP 0x00 /* These 8 commands are mut. exclu. */ 233 #define ZSWR14_DPLL_SEARCH 0x20 /* Enter search mode in DPLL */ 234 #define ZSWR14_DPLL_RESET 0x40 /* Reset missing clock in DPLL */ 235 #define ZSWR14_DPLL_DISABLE 0x60 /* Disable DPLL */ 236 #define ZSWR14_DPLL_SRC_BAUD 0x80 /* Source for DPLL is baud rate gen */ 237 #define ZSWR14_DPLL_SRC_RTXC 0xA0 /* Source for DPLL is RTxC pin */ 238 #define ZSWR14_DPLL_FM 0xC0 /* DPLL should run in FM mode */ 239 #define ZSWR14_DPLL_NRZI 0xE0 /* DPLL should run in NRZI mode */ 240 241 /* bits in WR15 -- described above as R/WR15 */ 242 243 /* 244 * UART register addressing 245 * 246 * It would be nice if they used 4 address pins to address 15 registers, 247 * but they only used 1. So you have to write to the control port then 248 * read or write it; the 2nd cycle is done to whatever register number 249 * you wrote in the first cycle. 250 * 251 * The data register can also be accessed as Read/Write register 8. 252 */ 253 254 #ifdef _KERNEL 255 struct zscc_device { 256 volatile unsigned char zscc_control; 257 volatile unsigned char :8; /* Filler */ 258 volatile unsigned char zscc_data; 259 volatile unsigned char :8; /* Filler */ 260 }; 261 262 #define ZSOFF 4 263 264 265 #endif /* _KERNEL */ 266 267 #ifdef __cplusplus 268 } 269 #endif 270 271 #endif /* !_SYS_SER_ZSCC_H */ 272