xref: /illumos-gate/usr/src/uts/sparc/sys/pcb.h (revision 07a48826732249fcd3aa8dd53c8389595e9f1fbc)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*07a48826SRoger A. Faulkner  * Common Development and Distribution License (the "License").
6*07a48826SRoger A. Faulkner  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
21*07a48826SRoger A. Faulkner 
227c478bd9Sstevel@tonic-gate /*
23*07a48826SRoger A. Faulkner  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
247c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
257c478bd9Sstevel@tonic-gate  */
267c478bd9Sstevel@tonic-gate 
277c478bd9Sstevel@tonic-gate #ifndef _SYS_PCB_H
287c478bd9Sstevel@tonic-gate #define	_SYS_PCB_H
297c478bd9Sstevel@tonic-gate 
307c478bd9Sstevel@tonic-gate #include <sys/regset.h>
317c478bd9Sstevel@tonic-gate 
327c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
337c478bd9Sstevel@tonic-gate extern "C" {
347c478bd9Sstevel@tonic-gate #endif
357c478bd9Sstevel@tonic-gate 
367c478bd9Sstevel@tonic-gate /*
377c478bd9Sstevel@tonic-gate  * Sun software process control block
387c478bd9Sstevel@tonic-gate  */
397c478bd9Sstevel@tonic-gate 
407c478bd9Sstevel@tonic-gate #ifndef _ASM
417c478bd9Sstevel@tonic-gate typedef struct pcb {
427c478bd9Sstevel@tonic-gate 	int	pcb_flags;	/* various state flags; cleared on fork */
437c478bd9Sstevel@tonic-gate 	uint32_t pcb_trap0addr;	/* addr of user level trap 0 handler */
447c478bd9Sstevel@tonic-gate 				/* deliberately restricted to 32 bits */
457c478bd9Sstevel@tonic-gate 				/* because only used for SunOS programs */
467c478bd9Sstevel@tonic-gate 	uint_t	pcb_instr;	/* /proc: instruction at stop */
477c478bd9Sstevel@tonic-gate 	enum { XREGNONE = 0, XREGPRESENT, XREGMODIFIED }
487c478bd9Sstevel@tonic-gate 		pcb_xregstat;	/* state of contents of pcb_xregs */
497c478bd9Sstevel@tonic-gate 	struct	rwindow pcb_xregs; /* locals+ins fetched/set via /proc */
507c478bd9Sstevel@tonic-gate 	int	pcb_step;	/* used while single-stepping */
517c478bd9Sstevel@tonic-gate 	caddr_t	pcb_tracepc;	/* used while single-stepping */
527c478bd9Sstevel@tonic-gate } pcb_t;
537c478bd9Sstevel@tonic-gate #endif /* ! _ASM */
547c478bd9Sstevel@tonic-gate 
557c478bd9Sstevel@tonic-gate /* pcb_flags */
56*07a48826SRoger A. Faulkner #define	PRSTOP_CALLED	0x01	/* prstop() has been called for this lwp */
577c478bd9Sstevel@tonic-gate #define	INSTR_VALID	0x02	/* value in pcb_instr is valid (/proc) */
587c478bd9Sstevel@tonic-gate #define	NORMAL_STEP	0x04	/* normal debugger requested single-step */
597c478bd9Sstevel@tonic-gate #define	WATCH_STEP	0x08	/* single-stepping in watchpoint emulation */
607c478bd9Sstevel@tonic-gate #define	CPC_OVERFLOW	0x10	/* performance counters overflowed */
617c478bd9Sstevel@tonic-gate #define	ASYNC_HWERR	0x20	/* asynchronous h/w error (e.g. parity error) */
627c478bd9Sstevel@tonic-gate #define	ASYNC_BERR	0x40	/* asynchronous bus error */
637c478bd9Sstevel@tonic-gate #define	ASYNC_BTO	0x80	/* asynchronous bus timeout */
647c478bd9Sstevel@tonic-gate #define	ASYNC_MOD_ILL	0x100	/* async module error w/ illegal instr/cycle */
657c478bd9Sstevel@tonic-gate #define	ASYNC_MOD_SEGV	0x200	/* async module error w/ address violation */
667c478bd9Sstevel@tonic-gate #define	ASYNC_ERR	(ASYNC_HWERR | ASYNC_BERR | ASYNC_BTO | \
677c478bd9Sstevel@tonic-gate 			    ASYNC_MOD_ILL | ASYNC_MOD_SEGV)
687c478bd9Sstevel@tonic-gate 
697c478bd9Sstevel@tonic-gate /* pcb_step */
707c478bd9Sstevel@tonic-gate #define	STEP_NONE	0	/* no single step */
717c478bd9Sstevel@tonic-gate #define	STEP_REQUESTED	1	/* arrange to single-step the lwp */
727c478bd9Sstevel@tonic-gate #define	STEP_ACTIVE	2	/* actively patching addr, set active flag */
737c478bd9Sstevel@tonic-gate #define	STEP_WASACTIVE	3	/* wrap up after taking single-step fault */
747c478bd9Sstevel@tonic-gate 
757c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
767c478bd9Sstevel@tonic-gate }
777c478bd9Sstevel@tonic-gate #endif
787c478bd9Sstevel@tonic-gate 
797c478bd9Sstevel@tonic-gate #endif	/* _SYS_PCB_H */
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