xref: /illumos-gate/usr/src/uts/sparc/sys/cpu.h (revision bea83d026ee1bd1b2a2419e1d0232f107a5d7d9b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_CPU_H
27 #define	_SYS_CPU_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 /*
32  * Include generic bustype cookies.
33  */
34 #include <sys/bustypes.h>
35 
36 #ifdef	__cplusplus
37 extern "C" {
38 #endif
39 
40 /*
41  * Global kernel variables of interest
42  */
43 
44 #if defined(_KERNEL) && !defined(_ASM)
45 
46 extern int dvmasize;			/* usable dvma size in pages */
47 
48 /*
49  * Cache defines
50  *
51  * Each bit represents an attribute of the system's caches that
52  * the OS must handle.  For example, VAC caches must have virtual
53  * alias detection, VTAG caches must be flushed on every demap, etc.
54  */
55 #define	CACHE_NONE		0	/* No caches of any type */
56 #define	CACHE_VAC		0x01	/* Virtual addressed cache */
57 #define	CACHE_VTAG		0x02	/* Virtual tagged cache */
58 #define	CACHE_PAC		0x04	/* Physical addressed cache */
59 #define	CACHE_PTAG		0x08	/* Physical tagged cache */
60 #define	CACHE_WRITEBACK		0x10	/* Writeback cache */
61 #define	CACHE_IOCOHERENT	0x20	/* I/O coherent cache */
62 
63 extern int cache;
64 
65 /* set this to zero if no vac */
66 extern int vac;
67 
68 /*
69  * Use to insert cpu-dependent instructions into spin loops
70  */
71 #pragma	weak	cpu_smt_pause
72 extern  void	cpu_smt_pause();
73 #define	SMT_PAUSE()	{ if (&cpu_smt_pause) cpu_smt_pause(); }
74 
75 #endif /* defined(_KERNEL) && !defined(_ASM) */
76 
77 #ifdef	__cplusplus
78 }
79 #endif
80 
81 #endif	/* _SYS_CPU_H */
82