xref: /illumos-gate/usr/src/uts/sparc/sys/cpu.h (revision 94e7edb1e6b194fffd0e7901c0b32e9fc836bc5b)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
525cf1a30Sjl139090  * Common Development and Distribution License (the "License").
625cf1a30Sjl139090  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22*94e7edb1Slucy wang - Sun Microsystems - Beijing China  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate #ifndef _SYS_CPU_H
277c478bd9Sstevel@tonic-gate #define	_SYS_CPU_H
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate /*
307c478bd9Sstevel@tonic-gate  * Include generic bustype cookies.
317c478bd9Sstevel@tonic-gate  */
327c478bd9Sstevel@tonic-gate #include <sys/bustypes.h>
337c478bd9Sstevel@tonic-gate 
34*94e7edb1Slucy wang - Sun Microsystems - Beijing China #if defined(_KERNEL)
35*94e7edb1Slucy wang - Sun Microsystems - Beijing China #if defined(__GNUC__) && defined(_ASM_INLINES)
36*94e7edb1Slucy wang - Sun Microsystems - Beijing China #include <asm/cpu.h>
37*94e7edb1Slucy wang - Sun Microsystems - Beijing China #endif
38*94e7edb1Slucy wang - Sun Microsystems - Beijing China #endif	/* _KERNEL */
39*94e7edb1Slucy wang - Sun Microsystems - Beijing China 
407c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
417c478bd9Sstevel@tonic-gate extern "C" {
427c478bd9Sstevel@tonic-gate #endif
437c478bd9Sstevel@tonic-gate 
44*94e7edb1Slucy wang - Sun Microsystems - Beijing China 
457c478bd9Sstevel@tonic-gate /*
467c478bd9Sstevel@tonic-gate  * Global kernel variables of interest
477c478bd9Sstevel@tonic-gate  */
487c478bd9Sstevel@tonic-gate 
497c478bd9Sstevel@tonic-gate #if defined(_KERNEL) && !defined(_ASM)
507c478bd9Sstevel@tonic-gate 
517c478bd9Sstevel@tonic-gate extern int dvmasize;			/* usable dvma size in pages */
527c478bd9Sstevel@tonic-gate 
537c478bd9Sstevel@tonic-gate /*
547c478bd9Sstevel@tonic-gate  * Cache defines
557c478bd9Sstevel@tonic-gate  *
567c478bd9Sstevel@tonic-gate  * Each bit represents an attribute of the system's caches that
577c478bd9Sstevel@tonic-gate  * the OS must handle.  For example, VAC caches must have virtual
587c478bd9Sstevel@tonic-gate  * alias detection, VTAG caches must be flushed on every demap, etc.
597c478bd9Sstevel@tonic-gate  */
607c478bd9Sstevel@tonic-gate #define	CACHE_NONE		0	/* No caches of any type */
617c478bd9Sstevel@tonic-gate #define	CACHE_VAC		0x01	/* Virtual addressed cache */
627c478bd9Sstevel@tonic-gate #define	CACHE_VTAG		0x02	/* Virtual tagged cache */
637c478bd9Sstevel@tonic-gate #define	CACHE_PAC		0x04	/* Physical addressed cache */
647c478bd9Sstevel@tonic-gate #define	CACHE_PTAG		0x08	/* Physical tagged cache */
657c478bd9Sstevel@tonic-gate #define	CACHE_WRITEBACK		0x10	/* Writeback cache */
667c478bd9Sstevel@tonic-gate #define	CACHE_IOCOHERENT	0x20	/* I/O coherent cache */
677c478bd9Sstevel@tonic-gate 
687c478bd9Sstevel@tonic-gate extern int cache;
697c478bd9Sstevel@tonic-gate 
707c478bd9Sstevel@tonic-gate /* set this to zero if no vac */
717c478bd9Sstevel@tonic-gate extern int vac;
727c478bd9Sstevel@tonic-gate 
737c478bd9Sstevel@tonic-gate /*
747c478bd9Sstevel@tonic-gate  * Use to insert cpu-dependent instructions into spin loops
757c478bd9Sstevel@tonic-gate  */
7625cf1a30Sjl139090 #pragma	weak	cpu_smt_pause
7725cf1a30Sjl139090 extern  void	cpu_smt_pause();
7825cf1a30Sjl139090 #define	SMT_PAUSE()	{ if (&cpu_smt_pause) cpu_smt_pause(); }
797c478bd9Sstevel@tonic-gate 
807c478bd9Sstevel@tonic-gate #endif /* defined(_KERNEL) && !defined(_ASM) */
817c478bd9Sstevel@tonic-gate 
827c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
837c478bd9Sstevel@tonic-gate }
847c478bd9Sstevel@tonic-gate #endif
857c478bd9Sstevel@tonic-gate 
867c478bd9Sstevel@tonic-gate #endif	/* _SYS_CPU_H */
87