1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2017 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 /* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94 /* 0x00000004 - reserved */ 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107 /* 0x00008000 - reserved */ 108 /* 0x00010000 - reserved */ 109 /* 0x00020000 - reserved */ 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 117 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 118 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 119 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 120 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 121 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 122 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 123 124 /* 125 * cpuid instruction feature flags in %edx (extended function 0x80000001) 126 */ 127 128 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 129 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 130 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 131 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 132 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 133 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 134 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 135 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 136 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 137 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 138 /* 0x00000400 - sysc on K6m6 */ 139 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 140 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 141 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 142 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 143 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 144 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 145 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 146 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 147 /* 0x00040000 - reserved */ 148 /* 0x00080000 - reserved */ 149 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 150 /* 0x00200000 - reserved */ 151 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 152 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 153 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 154 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 155 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 156 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 157 /* 0x10000000 - reserved */ 158 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 159 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 160 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 161 162 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 163 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 164 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 165 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 166 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 167 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 168 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 169 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 170 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 171 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 172 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 173 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 174 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 175 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 176 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 177 178 /* 179 * AMD uses %ebx for some of their features (extended function 0x80000008). 180 */ 181 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */ 182 183 /* 184 * Intel now seems to have claimed part of the "extended" function 185 * space that we previously for non-Intel implementors to use. 186 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 187 * is available in long mode i.e. what AMD indicate using bit 0. 188 * On the other hand, everything else is labelled as reserved. 189 */ 190 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 191 192 /* 193 * Intel also uses cpuid leaf 7 to have additional instructions and features. 194 * Like some other leaves, but unlike the current ones we care about, it 195 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 196 * with the potential use of additional sub-leaves in the future, we now 197 * specifically label the EBX features with their leaf and sub-leaf. 198 */ 199 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 200 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 201 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 202 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 203 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 204 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 205 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 206 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 207 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 208 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 209 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 210 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 211 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 212 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 213 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 214 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 215 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 216 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 217 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 218 219 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 220 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 221 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 222 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 223 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 224 225 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 226 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 227 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 228 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 229 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 230 231 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 232 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 233 234 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 235 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 236 237 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 238 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 239 240 /* 241 * Intel also uses cpuid leaf 0xd to report additional instructions and features 242 * when the sub-leaf in %ecx == 1. We label these using the same convention as 243 * with leaf 7. 244 */ 245 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 246 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 247 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 248 249 #define REG_PAT 0x277 250 #define REG_TSC 0x10 /* timestamp counter */ 251 #define REG_APIC_BASE_MSR 0x1b 252 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 253 254 #if !defined(__xpv) 255 /* 256 * AMD C1E 257 */ 258 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 259 #define AMD_ACTONCMPHALT_SHIFT 27 260 #define AMD_ACTONCMPHALT_MASK 3 261 #endif 262 263 #define MSR_DEBUGCTL 0x1d9 264 265 #define DEBUGCTL_LBR 0x01 266 #define DEBUGCTL_BTF 0x02 267 268 /* Intel P6, AMD */ 269 #define MSR_LBR_FROM 0x1db 270 #define MSR_LBR_TO 0x1dc 271 #define MSR_LEX_FROM 0x1dd 272 #define MSR_LEX_TO 0x1de 273 274 /* Intel P4 (pre-Prescott, non P4 M) */ 275 #define MSR_P4_LBSTK_TOS 0x1da 276 #define MSR_P4_LBSTK_0 0x1db 277 #define MSR_P4_LBSTK_1 0x1dc 278 #define MSR_P4_LBSTK_2 0x1dd 279 #define MSR_P4_LBSTK_3 0x1de 280 281 /* Intel Pentium M */ 282 #define MSR_P6M_LBSTK_TOS 0x1c9 283 #define MSR_P6M_LBSTK_0 0x040 284 #define MSR_P6M_LBSTK_1 0x041 285 #define MSR_P6M_LBSTK_2 0x042 286 #define MSR_P6M_LBSTK_3 0x043 287 #define MSR_P6M_LBSTK_4 0x044 288 #define MSR_P6M_LBSTK_5 0x045 289 #define MSR_P6M_LBSTK_6 0x046 290 #define MSR_P6M_LBSTK_7 0x047 291 292 /* Intel P4 (Prescott) */ 293 #define MSR_PRP4_LBSTK_TOS 0x1da 294 #define MSR_PRP4_LBSTK_FROM_0 0x680 295 #define MSR_PRP4_LBSTK_FROM_1 0x681 296 #define MSR_PRP4_LBSTK_FROM_2 0x682 297 #define MSR_PRP4_LBSTK_FROM_3 0x683 298 #define MSR_PRP4_LBSTK_FROM_4 0x684 299 #define MSR_PRP4_LBSTK_FROM_5 0x685 300 #define MSR_PRP4_LBSTK_FROM_6 0x686 301 #define MSR_PRP4_LBSTK_FROM_7 0x687 302 #define MSR_PRP4_LBSTK_FROM_8 0x688 303 #define MSR_PRP4_LBSTK_FROM_9 0x689 304 #define MSR_PRP4_LBSTK_FROM_10 0x68a 305 #define MSR_PRP4_LBSTK_FROM_11 0x68b 306 #define MSR_PRP4_LBSTK_FROM_12 0x68c 307 #define MSR_PRP4_LBSTK_FROM_13 0x68d 308 #define MSR_PRP4_LBSTK_FROM_14 0x68e 309 #define MSR_PRP4_LBSTK_FROM_15 0x68f 310 #define MSR_PRP4_LBSTK_TO_0 0x6c0 311 #define MSR_PRP4_LBSTK_TO_1 0x6c1 312 #define MSR_PRP4_LBSTK_TO_2 0x6c2 313 #define MSR_PRP4_LBSTK_TO_3 0x6c3 314 #define MSR_PRP4_LBSTK_TO_4 0x6c4 315 #define MSR_PRP4_LBSTK_TO_5 0x6c5 316 #define MSR_PRP4_LBSTK_TO_6 0x6c6 317 #define MSR_PRP4_LBSTK_TO_7 0x6c7 318 #define MSR_PRP4_LBSTK_TO_8 0x6c8 319 #define MSR_PRP4_LBSTK_TO_9 0x6c9 320 #define MSR_PRP4_LBSTK_TO_10 0x6ca 321 #define MSR_PRP4_LBSTK_TO_11 0x6cb 322 #define MSR_PRP4_LBSTK_TO_12 0x6cc 323 #define MSR_PRP4_LBSTK_TO_13 0x6cd 324 #define MSR_PRP4_LBSTK_TO_14 0x6ce 325 #define MSR_PRP4_LBSTK_TO_15 0x6cf 326 327 #define MCI_CTL_VALUE 0xffffffff 328 329 #define MTRR_TYPE_UC 0 330 #define MTRR_TYPE_WC 1 331 #define MTRR_TYPE_WT 4 332 #define MTRR_TYPE_WP 5 333 #define MTRR_TYPE_WB 6 334 #define MTRR_TYPE_UC_ 7 335 336 /* 337 * For Solaris we set up the page attritubute table in the following way: 338 * PAT0 Write-Back 339 * PAT1 Write-Through 340 * PAT2 Unchacheable- 341 * PAT3 Uncacheable 342 * PAT4 Write-Back 343 * PAT5 Write-Through 344 * PAT6 Write-Combine 345 * PAT7 Uncacheable 346 * The only difference from h/w default is entry 6. 347 */ 348 #define PAT_DEFAULT_ATTRIBUTE \ 349 ((uint64_t)MTRR_TYPE_WB | \ 350 ((uint64_t)MTRR_TYPE_WT << 8) | \ 351 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 352 ((uint64_t)MTRR_TYPE_UC << 24) | \ 353 ((uint64_t)MTRR_TYPE_WB << 32) | \ 354 ((uint64_t)MTRR_TYPE_WT << 40) | \ 355 ((uint64_t)MTRR_TYPE_WC << 48) | \ 356 ((uint64_t)MTRR_TYPE_UC << 56)) 357 358 #define X86FSET_LARGEPAGE 0 359 #define X86FSET_TSC 1 360 #define X86FSET_MSR 2 361 #define X86FSET_MTRR 3 362 #define X86FSET_PGE 4 363 #define X86FSET_DE 5 364 #define X86FSET_CMOV 6 365 #define X86FSET_MMX 7 366 #define X86FSET_MCA 8 367 #define X86FSET_PAE 9 368 #define X86FSET_CX8 10 369 #define X86FSET_PAT 11 370 #define X86FSET_SEP 12 371 #define X86FSET_SSE 13 372 #define X86FSET_SSE2 14 373 #define X86FSET_HTT 15 374 #define X86FSET_ASYSC 16 375 #define X86FSET_NX 17 376 #define X86FSET_SSE3 18 377 #define X86FSET_CX16 19 378 #define X86FSET_CMP 20 379 #define X86FSET_TSCP 21 380 #define X86FSET_MWAIT 22 381 #define X86FSET_SSE4A 23 382 #define X86FSET_CPUID 24 383 #define X86FSET_SSSE3 25 384 #define X86FSET_SSE4_1 26 385 #define X86FSET_SSE4_2 27 386 #define X86FSET_1GPG 28 387 #define X86FSET_CLFSH 29 388 #define X86FSET_64 30 389 #define X86FSET_AES 31 390 #define X86FSET_PCLMULQDQ 32 391 #define X86FSET_XSAVE 33 392 #define X86FSET_AVX 34 393 #define X86FSET_VMX 35 394 #define X86FSET_SVM 36 395 #define X86FSET_TOPOEXT 37 396 #define X86FSET_F16C 38 397 #define X86FSET_RDRAND 39 398 #define X86FSET_X2APIC 40 399 #define X86FSET_AVX2 41 400 #define X86FSET_BMI1 42 401 #define X86FSET_BMI2 43 402 #define X86FSET_FMA 44 403 #define X86FSET_SMEP 45 404 #define X86FSET_SMAP 46 405 #define X86FSET_ADX 47 406 #define X86FSET_RDSEED 48 407 #define X86FSET_MPX 49 408 #define X86FSET_AVX512F 50 409 #define X86FSET_AVX512DQ 51 410 #define X86FSET_AVX512PF 52 411 #define X86FSET_AVX512ER 53 412 #define X86FSET_AVX512CD 54 413 #define X86FSET_AVX512BW 55 414 #define X86FSET_AVX512VL 56 415 #define X86FSET_AVX512FMA 57 416 #define X86FSET_AVX512VBMI 58 417 #define X86FSET_AVX512VPOPCDQ 59 418 #define X86FSET_AVX512NNIW 60 419 #define X86FSET_AVX512FMAPS 61 420 #define X86FSET_XSAVEOPT 62 421 #define X86FSET_XSAVEC 63 422 #define X86FSET_XSAVES 64 423 #define X86FSET_SHA 65 424 #define X86FSET_UMIP 66 425 #define X86FSET_PKU 67 426 #define X86FSET_OSPKE 68 427 428 /* 429 * Intel Deep C-State invariant TSC in leaf 0x80000007. 430 */ 431 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 432 433 /* 434 * Intel Deep C-state always-running local APIC timer 435 */ 436 #define CPUID_CSTATE_ARAT (0x4) 437 438 /* 439 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 440 */ 441 #define CPUID_EPB_SUPPORT (1 << 3) 442 443 /* 444 * Intel TSC deadline timer 445 */ 446 #define CPUID_DEADLINE_TSC (1 << 24) 447 448 /* 449 * x86_type is a legacy concept; this is supplanted 450 * for most purposes by x86_featureset; modern CPUs 451 * should be X86_TYPE_OTHER 452 */ 453 #define X86_TYPE_OTHER 0 454 #define X86_TYPE_486 1 455 #define X86_TYPE_P5 2 456 #define X86_TYPE_P6 3 457 #define X86_TYPE_CYRIX_486 4 458 #define X86_TYPE_CYRIX_6x86L 5 459 #define X86_TYPE_CYRIX_6x86 6 460 #define X86_TYPE_CYRIX_GXm 7 461 #define X86_TYPE_CYRIX_6x86MX 8 462 #define X86_TYPE_CYRIX_MediaGX 9 463 #define X86_TYPE_CYRIX_MII 10 464 #define X86_TYPE_VIA_CYRIX_III 11 465 #define X86_TYPE_P4 12 466 467 /* 468 * x86_vendor allows us to select between 469 * implementation features and helps guide 470 * the interpretation of the cpuid instruction. 471 */ 472 #define X86_VENDOR_Intel 0 473 #define X86_VENDORSTR_Intel "GenuineIntel" 474 475 #define X86_VENDOR_IntelClone 1 476 477 #define X86_VENDOR_AMD 2 478 #define X86_VENDORSTR_AMD "AuthenticAMD" 479 480 #define X86_VENDOR_Cyrix 3 481 #define X86_VENDORSTR_CYRIX "CyrixInstead" 482 483 #define X86_VENDOR_UMC 4 484 #define X86_VENDORSTR_UMC "UMC UMC UMC " 485 486 #define X86_VENDOR_NexGen 5 487 #define X86_VENDORSTR_NexGen "NexGenDriven" 488 489 #define X86_VENDOR_Centaur 6 490 #define X86_VENDORSTR_Centaur "CentaurHauls" 491 492 #define X86_VENDOR_Rise 7 493 #define X86_VENDORSTR_Rise "RiseRiseRise" 494 495 #define X86_VENDOR_SiS 8 496 #define X86_VENDORSTR_SiS "SiS SiS SiS " 497 498 #define X86_VENDOR_TM 9 499 #define X86_VENDORSTR_TM "GenuineTMx86" 500 501 #define X86_VENDOR_NSC 10 502 #define X86_VENDORSTR_NSC "Geode by NSC" 503 504 /* 505 * Vendor string max len + \0 506 */ 507 #define X86_VENDOR_STRLEN 13 508 509 /* 510 * Some vendor/family/model/stepping ranges are commonly grouped under 511 * a single identifying banner by the vendor. The following encode 512 * that "revision" in a uint32_t with the 8 most significant bits 513 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 514 * family, and the remaining 16 typically forming a bitmask of revisions 515 * within that family with more significant bits indicating "later" revisions. 516 */ 517 518 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 519 #define _X86_CHIPREV_VENDOR_SHIFT 24 520 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 521 #define _X86_CHIPREV_FAMILY_SHIFT 16 522 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 523 524 #define _X86_CHIPREV_VENDOR(x) \ 525 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 526 #define _X86_CHIPREV_FAMILY(x) \ 527 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 528 #define _X86_CHIPREV_REV(x) \ 529 ((x) & _X86_CHIPREV_REV_MASK) 530 531 /* True if x matches in vendor and family and if x matches the given rev mask */ 532 #define X86_CHIPREV_MATCH(x, mask) \ 533 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 534 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 535 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 536 537 /* True if x matches in vendor and family, and rev is at least minx */ 538 #define X86_CHIPREV_ATLEAST(x, minx) \ 539 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 540 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 541 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 542 543 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 544 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 545 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 546 547 /* True if x matches in vendor, and family is at least minx */ 548 #define X86_CHIPFAM_ATLEAST(x, minx) \ 549 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 550 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 551 552 /* Revision default */ 553 #define X86_CHIPREV_UNKNOWN 0x0 554 555 /* 556 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 557 * sufficiently different that we will distinguish them; in all other 558 * case we will identify the major revision. 559 */ 560 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 561 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 562 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 563 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 564 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 565 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 566 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 567 568 /* 569 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 570 */ 571 #define X86_CHIPREV_AMD_10_REV_A \ 572 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 573 #define X86_CHIPREV_AMD_10_REV_B \ 574 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 575 #define X86_CHIPREV_AMD_10_REV_C2 \ 576 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 577 #define X86_CHIPREV_AMD_10_REV_C3 \ 578 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 579 #define X86_CHIPREV_AMD_10_REV_D0 \ 580 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 581 #define X86_CHIPREV_AMD_10_REV_D1 \ 582 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 583 #define X86_CHIPREV_AMD_10_REV_E \ 584 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 585 586 /* 587 * Definitions for AMD Family 0x11. 588 */ 589 #define X86_CHIPREV_AMD_11_REV_B \ 590 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 591 592 /* 593 * Definitions for AMD Family 0x12. 594 */ 595 #define X86_CHIPREV_AMD_12_REV_B \ 596 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 597 598 /* 599 * Definitions for AMD Family 0x14. 600 */ 601 #define X86_CHIPREV_AMD_14_REV_B \ 602 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 603 #define X86_CHIPREV_AMD_14_REV_C \ 604 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 605 606 /* 607 * Definitions for AMD Family 0x15 608 */ 609 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 610 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 611 612 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 613 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 614 615 /* 616 * Various socket/package types, extended as the need to distinguish 617 * a new type arises. The top 8 byte identfies the vendor and the 618 * remaining 24 bits describe 24 socket types. 619 */ 620 621 #define _X86_SOCKET_VENDOR_SHIFT 24 622 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 623 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 624 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 625 626 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 627 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 628 629 #define X86_SOCKET_MATCH(s, mask) \ 630 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 631 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 632 633 #define X86_SOCKET_UNKNOWN 0x0 634 /* 635 * AMD socket types 636 */ 637 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 638 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 639 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 640 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 641 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 642 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 643 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 644 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 645 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 646 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 647 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 648 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 649 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 650 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 651 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 652 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 653 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 654 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 655 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 656 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 657 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 658 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 659 660 /* 661 * xgetbv/xsetbv support 662 * See section 13.3 in vol. 1 of the Intel devlopers manual. 663 */ 664 665 #define XFEATURE_ENABLED_MASK 0x0 666 /* 667 * XFEATURE_ENABLED_MASK values (eax) 668 * See setup_xfem(). 669 */ 670 #define XFEATURE_LEGACY_FP 0x1 671 #define XFEATURE_SSE 0x2 672 #define XFEATURE_AVX 0x4 673 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 674 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 675 /* bit 8 unused */ 676 #define XFEATURE_PKRU 0x200 677 #define XFEATURE_FP_ALL \ 678 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 679 XFEATURE_AVX512 | XFEATURE_PKRU) 680 681 #if !defined(_ASM) 682 683 #if defined(_KERNEL) || defined(_KMEMUSER) 684 685 #define NUM_X86_FEATURES 69 686 extern uchar_t x86_featureset[]; 687 688 extern void free_x86_featureset(void *featureset); 689 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 690 extern void add_x86_feature(void *featureset, uint_t feature); 691 extern void remove_x86_feature(void *featureset, uint_t feature); 692 extern boolean_t compare_x86_featureset(void *setA, void *setB); 693 extern void print_x86_featureset(void *featureset); 694 695 696 extern uint_t x86_type; 697 extern uint_t x86_vendor; 698 extern uint_t x86_clflush_size; 699 700 extern uint_t pentiumpro_bug4046376; 701 702 extern const char CyrixInstead[]; 703 704 #endif 705 706 #if defined(_KERNEL) 707 708 /* 709 * This structure is used to pass arguments and get return values back 710 * from the CPUID instruction in __cpuid_insn() routine. 711 */ 712 struct cpuid_regs { 713 uint32_t cp_eax; 714 uint32_t cp_ebx; 715 uint32_t cp_ecx; 716 uint32_t cp_edx; 717 }; 718 719 /* 720 * Utility functions to get/set extended control registers (XCR) 721 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 722 */ 723 extern uint64_t get_xcr(uint_t); 724 extern void set_xcr(uint_t, uint64_t); 725 726 extern uint64_t rdmsr(uint_t); 727 extern void wrmsr(uint_t, const uint64_t); 728 extern uint64_t xrdmsr(uint_t); 729 extern void xwrmsr(uint_t, const uint64_t); 730 extern int checked_rdmsr(uint_t, uint64_t *); 731 extern int checked_wrmsr(uint_t, uint64_t); 732 733 extern void invalidate_cache(void); 734 extern ulong_t getcr4(void); 735 extern void setcr4(ulong_t); 736 737 extern void mtrr_sync(void); 738 739 extern void cpu_fast_syscall_enable(void *); 740 extern void cpu_fast_syscall_disable(void *); 741 742 struct cpu; 743 744 extern int cpuid_checkpass(struct cpu *, int); 745 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 746 extern uint32_t __cpuid_insn(struct cpuid_regs *); 747 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 748 extern int cpuid_getidstr(struct cpu *, char *, size_t); 749 extern const char *cpuid_getvendorstr(struct cpu *); 750 extern uint_t cpuid_getvendor(struct cpu *); 751 extern uint_t cpuid_getfamily(struct cpu *); 752 extern uint_t cpuid_getmodel(struct cpu *); 753 extern uint_t cpuid_getstep(struct cpu *); 754 extern uint_t cpuid_getsig(struct cpu *); 755 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 756 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 757 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 758 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 759 extern int cpuid_get_chipid(struct cpu *); 760 extern id_t cpuid_get_coreid(struct cpu *); 761 extern int cpuid_get_pkgcoreid(struct cpu *); 762 extern int cpuid_get_clogid(struct cpu *); 763 extern int cpuid_get_cacheid(struct cpu *); 764 extern uint32_t cpuid_get_apicid(struct cpu *); 765 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 766 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 767 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 768 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 769 extern size_t cpuid_get_xsave_size(); 770 extern boolean_t cpuid_need_fp_excp_handling(); 771 extern int cpuid_is_cmt(struct cpu *); 772 extern int cpuid_syscall32_insn(struct cpu *); 773 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 774 775 extern uint32_t cpuid_getchiprev(struct cpu *); 776 extern const char *cpuid_getchiprevstr(struct cpu *); 777 extern uint32_t cpuid_getsockettype(struct cpu *); 778 extern const char *cpuid_getsocketstr(struct cpu *); 779 780 extern int cpuid_have_cr8access(struct cpu *); 781 782 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 783 784 struct cpuid_info; 785 786 extern void setx86isalist(void); 787 extern void cpuid_alloc_space(struct cpu *); 788 extern void cpuid_free_space(struct cpu *); 789 extern void cpuid_pass1(struct cpu *, uchar_t *); 790 extern void cpuid_pass2(struct cpu *); 791 extern void cpuid_pass3(struct cpu *); 792 extern void cpuid_pass4(struct cpu *, uint_t *); 793 extern void cpuid_set_cpu_properties(void *, processorid_t, 794 struct cpuid_info *); 795 796 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 797 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 798 799 #if !defined(__xpv) 800 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 801 extern void cpuid_mwait_free(struct cpu *); 802 extern int cpuid_deep_cstates_supported(void); 803 extern int cpuid_arat_supported(void); 804 extern int cpuid_iepb_supported(struct cpu *); 805 extern int cpuid_deadline_tsc_supported(void); 806 extern void vmware_port(int, uint32_t *); 807 #endif 808 809 struct cpu_ucode_info; 810 811 extern void ucode_alloc_space(struct cpu *); 812 extern void ucode_free_space(struct cpu *); 813 extern void ucode_check(struct cpu *); 814 extern void ucode_cleanup(); 815 816 #if !defined(__xpv) 817 extern char _tsc_mfence_start; 818 extern char _tsc_mfence_end; 819 extern char _tscp_start; 820 extern char _tscp_end; 821 extern char _no_rdtsc_start; 822 extern char _no_rdtsc_end; 823 extern char _tsc_lfence_start; 824 extern char _tsc_lfence_end; 825 #endif 826 827 #if !defined(__xpv) 828 extern char bcopy_patch_start; 829 extern char bcopy_patch_end; 830 extern char bcopy_ck_size; 831 #endif 832 833 extern void post_startup_cpu_fixups(void); 834 835 extern uint_t workaround_errata(struct cpu *); 836 837 #if defined(OPTERON_ERRATUM_93) 838 extern int opteron_erratum_93; 839 #endif 840 841 #if defined(OPTERON_ERRATUM_91) 842 extern int opteron_erratum_91; 843 #endif 844 845 #if defined(OPTERON_ERRATUM_100) 846 extern int opteron_erratum_100; 847 #endif 848 849 #if defined(OPTERON_ERRATUM_121) 850 extern int opteron_erratum_121; 851 #endif 852 853 #if defined(OPTERON_WORKAROUND_6323525) 854 extern int opteron_workaround_6323525; 855 extern void patch_workaround_6323525(void); 856 #endif 857 858 #if !defined(__xpv) 859 extern void determine_platform(void); 860 #endif 861 extern int get_hwenv(void); 862 extern int is_controldom(void); 863 864 extern void xsave_setup_msr(struct cpu *); 865 866 /* 867 * Hypervisor signatures 868 */ 869 #define HVSIG_XEN_HVM "XenVMMXenVMM" 870 #define HVSIG_VMWARE "VMwareVMware" 871 #define HVSIG_KVM "KVMKVMKVM" 872 #define HVSIG_MICROSOFT "Microsoft Hv" 873 874 /* 875 * Defined hardware environments 876 */ 877 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 878 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 879 880 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 881 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 882 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 883 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 884 885 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT) 886 887 #endif /* _KERNEL */ 888 889 #endif /* !_ASM */ 890 891 /* 892 * VMware hypervisor related defines 893 */ 894 #define VMWARE_HVMAGIC 0x564d5868 895 #define VMWARE_HVPORT 0x5658 896 #define VMWARE_HVCMD_GETVERSION 0x0a 897 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 898 899 #ifdef __cplusplus 900 } 901 #endif 902 903 #endif /* _SYS_X86_ARCHEXT_H */ 904