1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright (c) 2012, Joyent, Inc. All rights reserved. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 */ 34 35 #ifndef _SYS_X86_ARCHEXT_H 36 #define _SYS_X86_ARCHEXT_H 37 38 #if !defined(_ASM) 39 #include <sys/regset.h> 40 #include <sys/processor.h> 41 #include <vm/seg_enum.h> 42 #include <vm/page.h> 43 #endif /* _ASM */ 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /* 50 * cpuid instruction feature flags in %edx (standard function 1) 51 */ 52 53 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 54 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 55 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 56 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 57 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 58 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 59 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 60 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 61 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 62 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 63 /* 0x400 - reserved */ 64 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 65 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 66 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 67 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 68 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 69 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 70 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 71 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 72 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 73 /* 0x100000 - reserved */ 74 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 75 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 76 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 77 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 78 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 79 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 80 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 81 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 82 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 83 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 84 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 85 86 #define FMT_CPUID_INTC_EDX \ 87 "\20" \ 88 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 89 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 90 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 91 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 92 93 /* 94 * cpuid instruction feature flags in %ecx (standard function 1) 95 */ 96 97 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 98 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 99 /* 0x00000004 - reserved */ 100 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 101 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 102 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 103 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 104 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 105 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 106 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 107 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 108 /* 0x00000800 - reserved */ 109 /* 0x00001000 - reserved */ 110 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 111 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 112 /* 0x00008000 - reserved */ 113 /* 0x00010000 - reserved */ 114 /* 0x00020000 - reserved */ 115 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 116 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 117 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 118 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 119 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 120 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 121 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 122 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 123 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 124 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 125 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 126 127 #define FMT_CPUID_INTC_ECX \ 128 "\20" \ 129 "\37rdrand\36f16c\35avx\34osxsav\33xsave" \ 130 "\32aes" \ 131 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \ 132 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 133 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 134 135 /* 136 * cpuid instruction feature flags in %edx (extended function 0x80000001) 137 */ 138 139 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 140 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 141 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 142 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 143 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 144 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 145 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 146 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 147 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 148 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 149 /* 0x00000400 - sysc on K6m6 */ 150 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 151 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 152 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 153 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 154 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 155 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 156 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 157 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 158 /* 0x00040000 - reserved */ 159 /* 0x00080000 - reserved */ 160 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 161 /* 0x00200000 - reserved */ 162 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 163 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 164 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 165 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 166 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 167 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 168 /* 0x10000000 - reserved */ 169 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 170 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 171 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 172 173 #define FMT_CPUID_AMD_EDX \ 174 "\20" \ 175 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 176 "\30mmx\27mmxext\25nx\22pse\21pat" \ 177 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 178 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 179 180 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 181 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 182 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 183 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 184 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 185 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 186 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 187 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 188 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 189 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 190 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 191 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 192 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 193 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 194 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 195 196 #define FMT_CPUID_AMD_ECX \ 197 "\20" \ 198 "\22topoext" \ 199 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 200 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 201 202 /* 203 * Intel now seems to have claimed part of the "extended" function 204 * space that we previously for non-Intel implementors to use. 205 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 206 * is available in long mode i.e. what AMD indicate using bit 0. 207 * On the other hand, everything else is labelled as reserved. 208 */ 209 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 210 211 212 #define P5_MCHADDR 0x0 213 #define P5_CESR 0x11 214 #define P5_CTR0 0x12 215 #define P5_CTR1 0x13 216 217 #define K5_MCHADDR 0x0 218 #define K5_MCHTYPE 0x01 219 #define K5_TSC 0x10 220 #define K5_TR12 0x12 221 222 #define REG_PAT 0x277 223 224 #define REG_MC0_CTL 0x400 225 #define REG_MC5_MISC 0x417 226 #define REG_PERFCTR0 0xc1 227 #define REG_PERFCTR1 0xc2 228 229 #define REG_PERFEVNT0 0x186 230 #define REG_PERFEVNT1 0x187 231 232 #define REG_TSC 0x10 /* timestamp counter */ 233 #define REG_APIC_BASE_MSR 0x1b 234 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 235 236 #if !defined(__xpv) 237 /* 238 * AMD C1E 239 */ 240 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 241 #define AMD_ACTONCMPHALT_SHIFT 27 242 #define AMD_ACTONCMPHALT_MASK 3 243 #endif 244 245 #define MSR_DEBUGCTL 0x1d9 246 247 #define DEBUGCTL_LBR 0x01 248 #define DEBUGCTL_BTF 0x02 249 250 /* Intel P6, AMD */ 251 #define MSR_LBR_FROM 0x1db 252 #define MSR_LBR_TO 0x1dc 253 #define MSR_LEX_FROM 0x1dd 254 #define MSR_LEX_TO 0x1de 255 256 /* Intel P4 (pre-Prescott, non P4 M) */ 257 #define MSR_P4_LBSTK_TOS 0x1da 258 #define MSR_P4_LBSTK_0 0x1db 259 #define MSR_P4_LBSTK_1 0x1dc 260 #define MSR_P4_LBSTK_2 0x1dd 261 #define MSR_P4_LBSTK_3 0x1de 262 263 /* Intel Pentium M */ 264 #define MSR_P6M_LBSTK_TOS 0x1c9 265 #define MSR_P6M_LBSTK_0 0x040 266 #define MSR_P6M_LBSTK_1 0x041 267 #define MSR_P6M_LBSTK_2 0x042 268 #define MSR_P6M_LBSTK_3 0x043 269 #define MSR_P6M_LBSTK_4 0x044 270 #define MSR_P6M_LBSTK_5 0x045 271 #define MSR_P6M_LBSTK_6 0x046 272 #define MSR_P6M_LBSTK_7 0x047 273 274 /* Intel P4 (Prescott) */ 275 #define MSR_PRP4_LBSTK_TOS 0x1da 276 #define MSR_PRP4_LBSTK_FROM_0 0x680 277 #define MSR_PRP4_LBSTK_FROM_1 0x681 278 #define MSR_PRP4_LBSTK_FROM_2 0x682 279 #define MSR_PRP4_LBSTK_FROM_3 0x683 280 #define MSR_PRP4_LBSTK_FROM_4 0x684 281 #define MSR_PRP4_LBSTK_FROM_5 0x685 282 #define MSR_PRP4_LBSTK_FROM_6 0x686 283 #define MSR_PRP4_LBSTK_FROM_7 0x687 284 #define MSR_PRP4_LBSTK_FROM_8 0x688 285 #define MSR_PRP4_LBSTK_FROM_9 0x689 286 #define MSR_PRP4_LBSTK_FROM_10 0x68a 287 #define MSR_PRP4_LBSTK_FROM_11 0x68b 288 #define MSR_PRP4_LBSTK_FROM_12 0x68c 289 #define MSR_PRP4_LBSTK_FROM_13 0x68d 290 #define MSR_PRP4_LBSTK_FROM_14 0x68e 291 #define MSR_PRP4_LBSTK_FROM_15 0x68f 292 #define MSR_PRP4_LBSTK_TO_0 0x6c0 293 #define MSR_PRP4_LBSTK_TO_1 0x6c1 294 #define MSR_PRP4_LBSTK_TO_2 0x6c2 295 #define MSR_PRP4_LBSTK_TO_3 0x6c3 296 #define MSR_PRP4_LBSTK_TO_4 0x6c4 297 #define MSR_PRP4_LBSTK_TO_5 0x6c5 298 #define MSR_PRP4_LBSTK_TO_6 0x6c6 299 #define MSR_PRP4_LBSTK_TO_7 0x6c7 300 #define MSR_PRP4_LBSTK_TO_8 0x6c8 301 #define MSR_PRP4_LBSTK_TO_9 0x6c9 302 #define MSR_PRP4_LBSTK_TO_10 0x6ca 303 #define MSR_PRP4_LBSTK_TO_11 0x6cb 304 #define MSR_PRP4_LBSTK_TO_12 0x6cc 305 #define MSR_PRP4_LBSTK_TO_13 0x6cd 306 #define MSR_PRP4_LBSTK_TO_14 0x6ce 307 #define MSR_PRP4_LBSTK_TO_15 0x6cf 308 309 #define MCI_CTL_VALUE 0xffffffff 310 311 #define MTRR_TYPE_UC 0 312 #define MTRR_TYPE_WC 1 313 #define MTRR_TYPE_WT 4 314 #define MTRR_TYPE_WP 5 315 #define MTRR_TYPE_WB 6 316 #define MTRR_TYPE_UC_ 7 317 318 /* 319 * For Solaris we set up the page attritubute table in the following way: 320 * PAT0 Write-Back 321 * PAT1 Write-Through 322 * PAT2 Unchacheable- 323 * PAT3 Uncacheable 324 * PAT4 Write-Back 325 * PAT5 Write-Through 326 * PAT6 Write-Combine 327 * PAT7 Uncacheable 328 * The only difference from h/w default is entry 6. 329 */ 330 #define PAT_DEFAULT_ATTRIBUTE \ 331 ((uint64_t)MTRR_TYPE_WB | \ 332 ((uint64_t)MTRR_TYPE_WT << 8) | \ 333 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 334 ((uint64_t)MTRR_TYPE_UC << 24) | \ 335 ((uint64_t)MTRR_TYPE_WB << 32) | \ 336 ((uint64_t)MTRR_TYPE_WT << 40) | \ 337 ((uint64_t)MTRR_TYPE_WC << 48) | \ 338 ((uint64_t)MTRR_TYPE_UC << 56)) 339 340 #define X86FSET_LARGEPAGE 0 341 #define X86FSET_TSC 1 342 #define X86FSET_MSR 2 343 #define X86FSET_MTRR 3 344 #define X86FSET_PGE 4 345 #define X86FSET_DE 5 346 #define X86FSET_CMOV 6 347 #define X86FSET_MMX 7 348 #define X86FSET_MCA 8 349 #define X86FSET_PAE 9 350 #define X86FSET_CX8 10 351 #define X86FSET_PAT 11 352 #define X86FSET_SEP 12 353 #define X86FSET_SSE 13 354 #define X86FSET_SSE2 14 355 #define X86FSET_HTT 15 356 #define X86FSET_ASYSC 16 357 #define X86FSET_NX 17 358 #define X86FSET_SSE3 18 359 #define X86FSET_CX16 19 360 #define X86FSET_CMP 20 361 #define X86FSET_TSCP 21 362 #define X86FSET_MWAIT 22 363 #define X86FSET_SSE4A 23 364 #define X86FSET_CPUID 24 365 #define X86FSET_SSSE3 25 366 #define X86FSET_SSE4_1 26 367 #define X86FSET_SSE4_2 27 368 #define X86FSET_1GPG 28 369 #define X86FSET_CLFSH 29 370 #define X86FSET_64 30 371 #define X86FSET_AES 31 372 #define X86FSET_PCLMULQDQ 32 373 #define X86FSET_XSAVE 33 374 #define X86FSET_AVX 34 375 #define X86FSET_VMX 35 376 #define X86FSET_SVM 36 377 #define X86FSET_TOPOEXT 37 378 #define X86FSET_F16C 38 379 #define X86FSET_RDRAND 39 380 381 /* 382 * flags to patch tsc_read routine. 383 */ 384 #define X86_NO_TSC 0x0 385 #define X86_HAVE_TSCP 0x1 386 #define X86_TSC_MFENCE 0x2 387 #define X86_TSC_LFENCE 0x4 388 389 /* 390 * Intel Deep C-State invariant TSC in leaf 0x80000007. 391 */ 392 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 393 394 /* 395 * Intel Deep C-state always-running local APIC timer 396 */ 397 #define CPUID_CSTATE_ARAT (0x4) 398 399 /* 400 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 401 */ 402 #define CPUID_EPB_SUPPORT (1 << 3) 403 404 /* 405 * Intel TSC deadline timer 406 */ 407 #define CPUID_DEADLINE_TSC (1 << 24) 408 409 /* 410 * x86_type is a legacy concept; this is supplanted 411 * for most purposes by x86_featureset; modern CPUs 412 * should be X86_TYPE_OTHER 413 */ 414 #define X86_TYPE_OTHER 0 415 #define X86_TYPE_486 1 416 #define X86_TYPE_P5 2 417 #define X86_TYPE_P6 3 418 #define X86_TYPE_CYRIX_486 4 419 #define X86_TYPE_CYRIX_6x86L 5 420 #define X86_TYPE_CYRIX_6x86 6 421 #define X86_TYPE_CYRIX_GXm 7 422 #define X86_TYPE_CYRIX_6x86MX 8 423 #define X86_TYPE_CYRIX_MediaGX 9 424 #define X86_TYPE_CYRIX_MII 10 425 #define X86_TYPE_VIA_CYRIX_III 11 426 #define X86_TYPE_P4 12 427 428 /* 429 * x86_vendor allows us to select between 430 * implementation features and helps guide 431 * the interpretation of the cpuid instruction. 432 */ 433 #define X86_VENDOR_Intel 0 434 #define X86_VENDORSTR_Intel "GenuineIntel" 435 436 #define X86_VENDOR_IntelClone 1 437 438 #define X86_VENDOR_AMD 2 439 #define X86_VENDORSTR_AMD "AuthenticAMD" 440 441 #define X86_VENDOR_Cyrix 3 442 #define X86_VENDORSTR_CYRIX "CyrixInstead" 443 444 #define X86_VENDOR_UMC 4 445 #define X86_VENDORSTR_UMC "UMC UMC UMC " 446 447 #define X86_VENDOR_NexGen 5 448 #define X86_VENDORSTR_NexGen "NexGenDriven" 449 450 #define X86_VENDOR_Centaur 6 451 #define X86_VENDORSTR_Centaur "CentaurHauls" 452 453 #define X86_VENDOR_Rise 7 454 #define X86_VENDORSTR_Rise "RiseRiseRise" 455 456 #define X86_VENDOR_SiS 8 457 #define X86_VENDORSTR_SiS "SiS SiS SiS " 458 459 #define X86_VENDOR_TM 9 460 #define X86_VENDORSTR_TM "GenuineTMx86" 461 462 #define X86_VENDOR_NSC 10 463 #define X86_VENDORSTR_NSC "Geode by NSC" 464 465 /* 466 * Vendor string max len + \0 467 */ 468 #define X86_VENDOR_STRLEN 13 469 470 /* 471 * Some vendor/family/model/stepping ranges are commonly grouped under 472 * a single identifying banner by the vendor. The following encode 473 * that "revision" in a uint32_t with the 8 most significant bits 474 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 475 * family, and the remaining 16 typically forming a bitmask of revisions 476 * within that family with more significant bits indicating "later" revisions. 477 */ 478 479 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 480 #define _X86_CHIPREV_VENDOR_SHIFT 24 481 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 482 #define _X86_CHIPREV_FAMILY_SHIFT 16 483 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 484 485 #define _X86_CHIPREV_VENDOR(x) \ 486 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 487 #define _X86_CHIPREV_FAMILY(x) \ 488 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 489 #define _X86_CHIPREV_REV(x) \ 490 ((x) & _X86_CHIPREV_REV_MASK) 491 492 /* True if x matches in vendor and family and if x matches the given rev mask */ 493 #define X86_CHIPREV_MATCH(x, mask) \ 494 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 495 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 496 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 497 498 /* True if x matches in vendor and family, and rev is at least minx */ 499 #define X86_CHIPREV_ATLEAST(x, minx) \ 500 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 501 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 502 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 503 504 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 505 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 506 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 507 508 /* True if x matches in vendor, and family is at least minx */ 509 #define X86_CHIPFAM_ATLEAST(x, minx) \ 510 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 511 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 512 513 /* Revision default */ 514 #define X86_CHIPREV_UNKNOWN 0x0 515 516 /* 517 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 518 * sufficiently different that we will distinguish them; in all other 519 * case we will identify the major revision. 520 */ 521 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 522 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 523 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 524 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 525 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 526 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 527 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 528 529 /* 530 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 531 */ 532 #define X86_CHIPREV_AMD_10_REV_A \ 533 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 534 #define X86_CHIPREV_AMD_10_REV_B \ 535 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 536 #define X86_CHIPREV_AMD_10_REV_C2 \ 537 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 538 #define X86_CHIPREV_AMD_10_REV_C3 \ 539 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 540 #define X86_CHIPREV_AMD_10_REV_D0 \ 541 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 542 #define X86_CHIPREV_AMD_10_REV_D1 \ 543 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 544 #define X86_CHIPREV_AMD_10_REV_E \ 545 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 546 547 /* 548 * Definitions for AMD Family 0x11. 549 */ 550 #define X86_CHIPREV_AMD_11_REV_B \ 551 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 552 553 /* 554 * Definitions for AMD Family 0x12. 555 */ 556 #define X86_CHIPREV_AMD_12_REV_B \ 557 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 558 559 /* 560 * Definitions for AMD Family 0x14. 561 */ 562 #define X86_CHIPREV_AMD_14_REV_B \ 563 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 564 #define X86_CHIPREV_AMD_14_REV_C \ 565 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 566 567 /* 568 * Definitions for AMD Family 0x15 569 */ 570 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 571 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 572 573 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 574 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 575 576 /* 577 * Various socket/package types, extended as the need to distinguish 578 * a new type arises. The top 8 byte identfies the vendor and the 579 * remaining 24 bits describe 24 socket types. 580 */ 581 582 #define _X86_SOCKET_VENDOR_SHIFT 24 583 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 584 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 585 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 586 587 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 588 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 589 590 #define X86_SOCKET_MATCH(s, mask) \ 591 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 592 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 593 594 #define X86_SOCKET_UNKNOWN 0x0 595 /* 596 * AMD socket types 597 */ 598 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 599 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 600 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 601 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 602 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 603 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 604 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 605 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 606 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 607 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 608 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 609 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 610 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 611 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 612 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 613 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 614 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 615 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 616 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 617 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 618 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 619 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 620 621 /* 622 * xgetbv/xsetbv support 623 */ 624 625 #define XFEATURE_ENABLED_MASK 0x0 626 /* 627 * XFEATURE_ENABLED_MASK values (eax) 628 */ 629 #define XFEATURE_LEGACY_FP 0x1 630 #define XFEATURE_SSE 0x2 631 #define XFEATURE_AVX 0x4 632 #define XFEATURE_MAX XFEATURE_AVX 633 #define XFEATURE_FP_ALL \ 634 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) 635 636 #if !defined(_ASM) 637 638 #if defined(_KERNEL) || defined(_KMEMUSER) 639 640 #define NUM_X86_FEATURES 40 641 extern uchar_t x86_featureset[]; 642 643 extern void free_x86_featureset(void *featureset); 644 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 645 extern void add_x86_feature(void *featureset, uint_t feature); 646 extern void remove_x86_feature(void *featureset, uint_t feature); 647 extern boolean_t compare_x86_featureset(void *setA, void *setB); 648 extern void print_x86_featureset(void *featureset); 649 650 651 extern uint_t x86_type; 652 extern uint_t x86_vendor; 653 extern uint_t x86_clflush_size; 654 655 extern uint_t pentiumpro_bug4046376; 656 extern uint_t pentiumpro_bug4064495; 657 658 extern uint_t enable486; 659 660 extern const char CyrixInstead[]; 661 662 #endif 663 664 #if defined(_KERNEL) 665 666 /* 667 * This structure is used to pass arguments and get return values back 668 * from the CPUID instruction in __cpuid_insn() routine. 669 */ 670 struct cpuid_regs { 671 uint32_t cp_eax; 672 uint32_t cp_ebx; 673 uint32_t cp_ecx; 674 uint32_t cp_edx; 675 }; 676 677 /* 678 * Utility functions to get/set extended control registers (XCR) 679 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 680 */ 681 extern uint64_t get_xcr(uint_t); 682 extern void set_xcr(uint_t, uint64_t); 683 684 extern uint64_t rdmsr(uint_t); 685 extern void wrmsr(uint_t, const uint64_t); 686 extern uint64_t xrdmsr(uint_t); 687 extern void xwrmsr(uint_t, const uint64_t); 688 extern int checked_rdmsr(uint_t, uint64_t *); 689 extern int checked_wrmsr(uint_t, uint64_t); 690 691 extern void invalidate_cache(void); 692 extern ulong_t getcr4(void); 693 extern void setcr4(ulong_t); 694 695 extern void mtrr_sync(void); 696 697 extern void cpu_fast_syscall_enable(void *); 698 extern void cpu_fast_syscall_disable(void *); 699 700 struct cpu; 701 702 extern int cpuid_checkpass(struct cpu *, int); 703 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 704 extern uint32_t __cpuid_insn(struct cpuid_regs *); 705 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 706 extern int cpuid_getidstr(struct cpu *, char *, size_t); 707 extern const char *cpuid_getvendorstr(struct cpu *); 708 extern uint_t cpuid_getvendor(struct cpu *); 709 extern uint_t cpuid_getfamily(struct cpu *); 710 extern uint_t cpuid_getmodel(struct cpu *); 711 extern uint_t cpuid_getstep(struct cpu *); 712 extern uint_t cpuid_getsig(struct cpu *); 713 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 714 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 715 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 716 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 717 extern int cpuid_get_chipid(struct cpu *); 718 extern id_t cpuid_get_coreid(struct cpu *); 719 extern int cpuid_get_pkgcoreid(struct cpu *); 720 extern int cpuid_get_clogid(struct cpu *); 721 extern int cpuid_get_cacheid(struct cpu *); 722 extern uint32_t cpuid_get_apicid(struct cpu *); 723 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 724 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 725 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 726 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 727 extern int cpuid_is_cmt(struct cpu *); 728 extern int cpuid_syscall32_insn(struct cpu *); 729 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 730 731 extern uint32_t cpuid_getchiprev(struct cpu *); 732 extern const char *cpuid_getchiprevstr(struct cpu *); 733 extern uint32_t cpuid_getsockettype(struct cpu *); 734 extern const char *cpuid_getsocketstr(struct cpu *); 735 736 extern int cpuid_have_cr8access(struct cpu *); 737 738 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 739 740 struct cpuid_info; 741 742 extern void setx86isalist(void); 743 extern void cpuid_alloc_space(struct cpu *); 744 extern void cpuid_free_space(struct cpu *); 745 extern void cpuid_pass1(struct cpu *, uchar_t *); 746 extern void cpuid_pass2(struct cpu *); 747 extern void cpuid_pass3(struct cpu *); 748 extern void cpuid_pass4(struct cpu *, uint_t *); 749 extern void cpuid_set_cpu_properties(void *, processorid_t, 750 struct cpuid_info *); 751 752 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 753 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 754 755 #if !defined(__xpv) 756 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 757 extern void cpuid_mwait_free(struct cpu *); 758 extern int cpuid_deep_cstates_supported(void); 759 extern int cpuid_arat_supported(void); 760 extern int cpuid_iepb_supported(struct cpu *); 761 extern int cpuid_deadline_tsc_supported(void); 762 extern int vmware_platform(void); 763 #endif 764 765 struct cpu_ucode_info; 766 767 extern void ucode_alloc_space(struct cpu *); 768 extern void ucode_free_space(struct cpu *); 769 extern void ucode_check(struct cpu *); 770 extern void ucode_cleanup(); 771 772 #if !defined(__xpv) 773 extern char _tsc_mfence_start; 774 extern char _tsc_mfence_end; 775 extern char _tscp_start; 776 extern char _tscp_end; 777 extern char _no_rdtsc_start; 778 extern char _no_rdtsc_end; 779 extern char _tsc_lfence_start; 780 extern char _tsc_lfence_end; 781 #endif 782 783 #if !defined(__xpv) 784 extern char bcopy_patch_start; 785 extern char bcopy_patch_end; 786 extern char bcopy_ck_size; 787 #endif 788 789 extern void post_startup_cpu_fixups(void); 790 791 extern uint_t workaround_errata(struct cpu *); 792 793 #if defined(OPTERON_ERRATUM_93) 794 extern int opteron_erratum_93; 795 #endif 796 797 #if defined(OPTERON_ERRATUM_91) 798 extern int opteron_erratum_91; 799 #endif 800 801 #if defined(OPTERON_ERRATUM_100) 802 extern int opteron_erratum_100; 803 #endif 804 805 #if defined(OPTERON_ERRATUM_121) 806 extern int opteron_erratum_121; 807 #endif 808 809 #if defined(OPTERON_WORKAROUND_6323525) 810 extern int opteron_workaround_6323525; 811 extern void patch_workaround_6323525(void); 812 #endif 813 814 #if !defined(__xpv) 815 extern void determine_platform(void); 816 #endif 817 extern int get_hwenv(void); 818 extern int is_controldom(void); 819 820 extern void xsave_setup_msr(struct cpu *); 821 822 /* 823 * Defined hardware environments 824 */ 825 #define HW_NATIVE 0x00 /* Running on bare metal */ 826 #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */ 827 #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */ 828 #define HW_VMWARE 0x03 /* Running on VMware hypervisor */ 829 830 #endif /* _KERNEL */ 831 832 #endif 833 834 #ifdef __cplusplus 835 } 836 #endif 837 838 #endif /* _SYS_X86_ARCHEXT_H */ 839