1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2018 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 /* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108 /* 0x00010000 - reserved */ 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124 125 /* 126 * cpuid instruction feature flags in %edx (extended function 0x80000001) 127 */ 128 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 139 /* 0x00000400 - sysc on K6m6 */ 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 148 /* 0x00040000 - reserved */ 149 /* 0x00080000 - reserved */ 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 151 /* 0x00200000 - reserved */ 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 158 /* 0x10000000 - reserved */ 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 162 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 177 /* 0x00004000 - reserved */ 178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 180 /* 0x00020000 - reserved */ 181 /* 0x00040000 - reserved */ 182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 183 /* 0x00100000 - reserved */ 184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 186 187 /* 188 * AMD uses %ebx for some of their features (extended function 0x80000008). 189 */ 190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 191 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 192 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 193 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 194 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 195 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 196 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 197 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 198 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 199 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 200 201 /* 202 * Intel now seems to have claimed part of the "extended" function 203 * space that we previously for non-Intel implementors to use. 204 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 205 * is available in long mode i.e. what AMD indicate using bit 0. 206 * On the other hand, everything else is labelled as reserved. 207 */ 208 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 209 210 /* 211 * Intel also uses cpuid leaf 7 to have additional instructions and features. 212 * Like some other leaves, but unlike the current ones we care about, it 213 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 214 * with the potential use of additional sub-leaves in the future, we now 215 * specifically label the EBX features with their leaf and sub-leaf. 216 */ 217 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 218 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 219 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 220 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 221 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 222 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 223 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 224 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 225 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 226 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 227 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 228 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 229 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 230 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 231 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 232 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 233 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 234 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 235 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 236 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 237 238 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 239 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 240 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 241 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 242 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 243 244 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 245 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 246 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 247 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 248 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 249 250 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 251 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 252 253 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 254 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 255 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 256 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 257 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 258 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 259 260 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 261 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 262 263 /* 264 * Intel also uses cpuid leaf 0xd to report additional instructions and features 265 * when the sub-leaf in %ecx == 1. We label these using the same convention as 266 * with leaf 7. 267 */ 268 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 269 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 270 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 271 272 #define REG_PAT 0x277 273 #define REG_TSC 0x10 /* timestamp counter */ 274 #define REG_APIC_BASE_MSR 0x1b 275 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 276 277 #if !defined(__xpv) 278 /* 279 * AMD C1E 280 */ 281 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 282 #define AMD_ACTONCMPHALT_SHIFT 27 283 #define AMD_ACTONCMPHALT_MASK 3 284 #endif 285 286 #define MSR_DEBUGCTL 0x1d9 287 288 #define DEBUGCTL_LBR 0x01 289 #define DEBUGCTL_BTF 0x02 290 291 /* Intel P6, AMD */ 292 #define MSR_LBR_FROM 0x1db 293 #define MSR_LBR_TO 0x1dc 294 #define MSR_LEX_FROM 0x1dd 295 #define MSR_LEX_TO 0x1de 296 297 /* Intel P4 (pre-Prescott, non P4 M) */ 298 #define MSR_P4_LBSTK_TOS 0x1da 299 #define MSR_P4_LBSTK_0 0x1db 300 #define MSR_P4_LBSTK_1 0x1dc 301 #define MSR_P4_LBSTK_2 0x1dd 302 #define MSR_P4_LBSTK_3 0x1de 303 304 /* Intel Pentium M */ 305 #define MSR_P6M_LBSTK_TOS 0x1c9 306 #define MSR_P6M_LBSTK_0 0x040 307 #define MSR_P6M_LBSTK_1 0x041 308 #define MSR_P6M_LBSTK_2 0x042 309 #define MSR_P6M_LBSTK_3 0x043 310 #define MSR_P6M_LBSTK_4 0x044 311 #define MSR_P6M_LBSTK_5 0x045 312 #define MSR_P6M_LBSTK_6 0x046 313 #define MSR_P6M_LBSTK_7 0x047 314 315 /* Intel P4 (Prescott) */ 316 #define MSR_PRP4_LBSTK_TOS 0x1da 317 #define MSR_PRP4_LBSTK_FROM_0 0x680 318 #define MSR_PRP4_LBSTK_FROM_1 0x681 319 #define MSR_PRP4_LBSTK_FROM_2 0x682 320 #define MSR_PRP4_LBSTK_FROM_3 0x683 321 #define MSR_PRP4_LBSTK_FROM_4 0x684 322 #define MSR_PRP4_LBSTK_FROM_5 0x685 323 #define MSR_PRP4_LBSTK_FROM_6 0x686 324 #define MSR_PRP4_LBSTK_FROM_7 0x687 325 #define MSR_PRP4_LBSTK_FROM_8 0x688 326 #define MSR_PRP4_LBSTK_FROM_9 0x689 327 #define MSR_PRP4_LBSTK_FROM_10 0x68a 328 #define MSR_PRP4_LBSTK_FROM_11 0x68b 329 #define MSR_PRP4_LBSTK_FROM_12 0x68c 330 #define MSR_PRP4_LBSTK_FROM_13 0x68d 331 #define MSR_PRP4_LBSTK_FROM_14 0x68e 332 #define MSR_PRP4_LBSTK_FROM_15 0x68f 333 #define MSR_PRP4_LBSTK_TO_0 0x6c0 334 #define MSR_PRP4_LBSTK_TO_1 0x6c1 335 #define MSR_PRP4_LBSTK_TO_2 0x6c2 336 #define MSR_PRP4_LBSTK_TO_3 0x6c3 337 #define MSR_PRP4_LBSTK_TO_4 0x6c4 338 #define MSR_PRP4_LBSTK_TO_5 0x6c5 339 #define MSR_PRP4_LBSTK_TO_6 0x6c6 340 #define MSR_PRP4_LBSTK_TO_7 0x6c7 341 #define MSR_PRP4_LBSTK_TO_8 0x6c8 342 #define MSR_PRP4_LBSTK_TO_9 0x6c9 343 #define MSR_PRP4_LBSTK_TO_10 0x6ca 344 #define MSR_PRP4_LBSTK_TO_11 0x6cb 345 #define MSR_PRP4_LBSTK_TO_12 0x6cc 346 #define MSR_PRP4_LBSTK_TO_13 0x6cd 347 #define MSR_PRP4_LBSTK_TO_14 0x6ce 348 #define MSR_PRP4_LBSTK_TO_15 0x6cf 349 350 /* 351 * Intel IA32_ARCH_CAPABILITIES MSR. 352 */ 353 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 354 #define IA32_ARCH_CAP_RDCL_NO 0x0001 355 #define IA32_ARCH_CAP_IBRS_ALL 0x0002 356 #define IA32_ARCH_CAP_RSBA 0x0004 357 #define IA32_ARCH_CAP_SSB_NO 0x0010 358 359 /* 360 * Intel Speculation related MSRs 361 */ 362 #define MSR_IA32_SPEC_CTRL 0x48 363 #define IA32_SPEC_CTRL_IBRS 0x01 364 #define IA32_SPEC_CTRL_STIBP 0x02 365 #define IA32_SPEC_CTRL_SSBD 0x04 366 367 #define MSR_IA32_PRED_CMD 0x49 368 #define IA32_PRED_CMD_IBPB 0x01 369 370 #define MCI_CTL_VALUE 0xffffffff 371 372 #define MTRR_TYPE_UC 0 373 #define MTRR_TYPE_WC 1 374 #define MTRR_TYPE_WT 4 375 #define MTRR_TYPE_WP 5 376 #define MTRR_TYPE_WB 6 377 #define MTRR_TYPE_UC_ 7 378 379 /* 380 * For Solaris we set up the page attritubute table in the following way: 381 * PAT0 Write-Back 382 * PAT1 Write-Through 383 * PAT2 Unchacheable- 384 * PAT3 Uncacheable 385 * PAT4 Write-Back 386 * PAT5 Write-Through 387 * PAT6 Write-Combine 388 * PAT7 Uncacheable 389 * The only difference from h/w default is entry 6. 390 */ 391 #define PAT_DEFAULT_ATTRIBUTE \ 392 ((uint64_t)MTRR_TYPE_WB | \ 393 ((uint64_t)MTRR_TYPE_WT << 8) | \ 394 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 395 ((uint64_t)MTRR_TYPE_UC << 24) | \ 396 ((uint64_t)MTRR_TYPE_WB << 32) | \ 397 ((uint64_t)MTRR_TYPE_WT << 40) | \ 398 ((uint64_t)MTRR_TYPE_WC << 48) | \ 399 ((uint64_t)MTRR_TYPE_UC << 56)) 400 401 #define X86FSET_LARGEPAGE 0 402 #define X86FSET_TSC 1 403 #define X86FSET_MSR 2 404 #define X86FSET_MTRR 3 405 #define X86FSET_PGE 4 406 #define X86FSET_DE 5 407 #define X86FSET_CMOV 6 408 #define X86FSET_MMX 7 409 #define X86FSET_MCA 8 410 #define X86FSET_PAE 9 411 #define X86FSET_CX8 10 412 #define X86FSET_PAT 11 413 #define X86FSET_SEP 12 414 #define X86FSET_SSE 13 415 #define X86FSET_SSE2 14 416 #define X86FSET_HTT 15 417 #define X86FSET_ASYSC 16 418 #define X86FSET_NX 17 419 #define X86FSET_SSE3 18 420 #define X86FSET_CX16 19 421 #define X86FSET_CMP 20 422 #define X86FSET_TSCP 21 423 #define X86FSET_MWAIT 22 424 #define X86FSET_SSE4A 23 425 #define X86FSET_CPUID 24 426 #define X86FSET_SSSE3 25 427 #define X86FSET_SSE4_1 26 428 #define X86FSET_SSE4_2 27 429 #define X86FSET_1GPG 28 430 #define X86FSET_CLFSH 29 431 #define X86FSET_64 30 432 #define X86FSET_AES 31 433 #define X86FSET_PCLMULQDQ 32 434 #define X86FSET_XSAVE 33 435 #define X86FSET_AVX 34 436 #define X86FSET_VMX 35 437 #define X86FSET_SVM 36 438 #define X86FSET_TOPOEXT 37 439 #define X86FSET_F16C 38 440 #define X86FSET_RDRAND 39 441 #define X86FSET_X2APIC 40 442 #define X86FSET_AVX2 41 443 #define X86FSET_BMI1 42 444 #define X86FSET_BMI2 43 445 #define X86FSET_FMA 44 446 #define X86FSET_SMEP 45 447 #define X86FSET_SMAP 46 448 #define X86FSET_ADX 47 449 #define X86FSET_RDSEED 48 450 #define X86FSET_MPX 49 451 #define X86FSET_AVX512F 50 452 #define X86FSET_AVX512DQ 51 453 #define X86FSET_AVX512PF 52 454 #define X86FSET_AVX512ER 53 455 #define X86FSET_AVX512CD 54 456 #define X86FSET_AVX512BW 55 457 #define X86FSET_AVX512VL 56 458 #define X86FSET_AVX512FMA 57 459 #define X86FSET_AVX512VBMI 58 460 #define X86FSET_AVX512VPOPCDQ 59 461 #define X86FSET_AVX512NNIW 60 462 #define X86FSET_AVX512FMAPS 61 463 #define X86FSET_XSAVEOPT 62 464 #define X86FSET_XSAVEC 63 465 #define X86FSET_XSAVES 64 466 #define X86FSET_SHA 65 467 #define X86FSET_UMIP 66 468 #define X86FSET_PKU 67 469 #define X86FSET_OSPKE 68 470 #define X86FSET_PCID 69 471 #define X86FSET_INVPCID 70 472 #define X86FSET_IBRS 71 473 #define X86FSET_IBPB 72 474 #define X86FSET_STIBP 73 475 #define X86FSET_SSBD 74 476 #define X86FSET_SSBD_VIRT 75 477 #define X86FSET_RDCL_NO 76 478 #define X86FSET_IBRS_ALL 77 479 #define X86FSET_RSBA 78 480 #define X86FSET_SSB_NO 79 481 #define X86FSET_STIBP_ALL 80 482 483 /* 484 * Intel Deep C-State invariant TSC in leaf 0x80000007. 485 */ 486 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 487 488 /* 489 * Intel Deep C-state always-running local APIC timer 490 */ 491 #define CPUID_CSTATE_ARAT (0x4) 492 493 /* 494 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 495 */ 496 #define CPUID_EPB_SUPPORT (1 << 3) 497 498 /* 499 * Intel TSC deadline timer 500 */ 501 #define CPUID_DEADLINE_TSC (1 << 24) 502 503 /* 504 * x86_type is a legacy concept; this is supplanted 505 * for most purposes by x86_featureset; modern CPUs 506 * should be X86_TYPE_OTHER 507 */ 508 #define X86_TYPE_OTHER 0 509 #define X86_TYPE_486 1 510 #define X86_TYPE_P5 2 511 #define X86_TYPE_P6 3 512 #define X86_TYPE_CYRIX_486 4 513 #define X86_TYPE_CYRIX_6x86L 5 514 #define X86_TYPE_CYRIX_6x86 6 515 #define X86_TYPE_CYRIX_GXm 7 516 #define X86_TYPE_CYRIX_6x86MX 8 517 #define X86_TYPE_CYRIX_MediaGX 9 518 #define X86_TYPE_CYRIX_MII 10 519 #define X86_TYPE_VIA_CYRIX_III 11 520 #define X86_TYPE_P4 12 521 522 /* 523 * x86_vendor allows us to select between 524 * implementation features and helps guide 525 * the interpretation of the cpuid instruction. 526 */ 527 #define X86_VENDOR_Intel 0 528 #define X86_VENDORSTR_Intel "GenuineIntel" 529 530 #define X86_VENDOR_IntelClone 1 531 532 #define X86_VENDOR_AMD 2 533 #define X86_VENDORSTR_AMD "AuthenticAMD" 534 535 #define X86_VENDOR_Cyrix 3 536 #define X86_VENDORSTR_CYRIX "CyrixInstead" 537 538 #define X86_VENDOR_UMC 4 539 #define X86_VENDORSTR_UMC "UMC UMC UMC " 540 541 #define X86_VENDOR_NexGen 5 542 #define X86_VENDORSTR_NexGen "NexGenDriven" 543 544 #define X86_VENDOR_Centaur 6 545 #define X86_VENDORSTR_Centaur "CentaurHauls" 546 547 #define X86_VENDOR_Rise 7 548 #define X86_VENDORSTR_Rise "RiseRiseRise" 549 550 #define X86_VENDOR_SiS 8 551 #define X86_VENDORSTR_SiS "SiS SiS SiS " 552 553 #define X86_VENDOR_TM 9 554 #define X86_VENDORSTR_TM "GenuineTMx86" 555 556 #define X86_VENDOR_NSC 10 557 #define X86_VENDORSTR_NSC "Geode by NSC" 558 559 /* 560 * Vendor string max len + \0 561 */ 562 #define X86_VENDOR_STRLEN 13 563 564 /* 565 * Some vendor/family/model/stepping ranges are commonly grouped under 566 * a single identifying banner by the vendor. The following encode 567 * that "revision" in a uint32_t with the 8 most significant bits 568 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 569 * family, and the remaining 16 typically forming a bitmask of revisions 570 * within that family with more significant bits indicating "later" revisions. 571 */ 572 573 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 574 #define _X86_CHIPREV_VENDOR_SHIFT 24 575 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 576 #define _X86_CHIPREV_FAMILY_SHIFT 16 577 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 578 579 #define _X86_CHIPREV_VENDOR(x) \ 580 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 581 #define _X86_CHIPREV_FAMILY(x) \ 582 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 583 #define _X86_CHIPREV_REV(x) \ 584 ((x) & _X86_CHIPREV_REV_MASK) 585 586 /* True if x matches in vendor and family and if x matches the given rev mask */ 587 #define X86_CHIPREV_MATCH(x, mask) \ 588 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 589 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 590 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 591 592 /* True if x matches in vendor and family, and rev is at least minx */ 593 #define X86_CHIPREV_ATLEAST(x, minx) \ 594 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 595 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 596 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 597 598 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 599 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 600 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 601 602 /* True if x matches in vendor, and family is at least minx */ 603 #define X86_CHIPFAM_ATLEAST(x, minx) \ 604 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 605 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 606 607 /* Revision default */ 608 #define X86_CHIPREV_UNKNOWN 0x0 609 610 /* 611 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 612 * sufficiently different that we will distinguish them; in all other 613 * case we will identify the major revision. 614 */ 615 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 616 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 617 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 618 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 619 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 620 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 621 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 622 623 /* 624 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 625 */ 626 #define X86_CHIPREV_AMD_10_REV_A \ 627 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 628 #define X86_CHIPREV_AMD_10_REV_B \ 629 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 630 #define X86_CHIPREV_AMD_10_REV_C2 \ 631 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 632 #define X86_CHIPREV_AMD_10_REV_C3 \ 633 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 634 #define X86_CHIPREV_AMD_10_REV_D0 \ 635 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 636 #define X86_CHIPREV_AMD_10_REV_D1 \ 637 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 638 #define X86_CHIPREV_AMD_10_REV_E \ 639 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 640 641 /* 642 * Definitions for AMD Family 0x11. 643 */ 644 #define X86_CHIPREV_AMD_11_REV_B \ 645 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 646 647 /* 648 * Definitions for AMD Family 0x12. 649 */ 650 #define X86_CHIPREV_AMD_12_REV_B \ 651 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 652 653 /* 654 * Definitions for AMD Family 0x14. 655 */ 656 #define X86_CHIPREV_AMD_14_REV_B \ 657 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 658 #define X86_CHIPREV_AMD_14_REV_C \ 659 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 660 661 /* 662 * Definitions for AMD Family 0x15 663 */ 664 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 665 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 666 667 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 668 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 669 670 /* 671 * Various socket/package types, extended as the need to distinguish 672 * a new type arises. The top 8 byte identfies the vendor and the 673 * remaining 24 bits describe 24 socket types. 674 */ 675 676 #define _X86_SOCKET_VENDOR_SHIFT 24 677 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 678 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 679 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 680 681 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 682 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 683 684 #define X86_SOCKET_MATCH(s, mask) \ 685 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 686 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 687 688 #define X86_SOCKET_UNKNOWN 0x0 689 /* 690 * AMD socket types 691 */ 692 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 693 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 694 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 695 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 696 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 697 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 698 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 699 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 700 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 701 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 702 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 703 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 704 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 705 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 706 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 707 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 708 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 709 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 710 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 711 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 712 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 713 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 714 715 /* 716 * xgetbv/xsetbv support 717 * See section 13.3 in vol. 1 of the Intel devlopers manual. 718 */ 719 720 #define XFEATURE_ENABLED_MASK 0x0 721 /* 722 * XFEATURE_ENABLED_MASK values (eax) 723 * See setup_xfem(). 724 */ 725 #define XFEATURE_LEGACY_FP 0x1 726 #define XFEATURE_SSE 0x2 727 #define XFEATURE_AVX 0x4 728 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 729 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 730 /* bit 8 unused */ 731 #define XFEATURE_PKRU 0x200 732 #define XFEATURE_FP_ALL \ 733 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 734 XFEATURE_AVX512 | XFEATURE_PKRU) 735 736 /* 737 * Define the set of xfeature flags that should be considered valid in the xsave 738 * state vector when we initialize an lwp. This is distinct from the full set so 739 * that all of the processor's normal logic and tracking of the xsave state is 740 * usable. This should correspond to the state that's been initialized by the 741 * ABI to hold meaningful values. Adding additional bits here can have serious 742 * performance implications and cause performance degradations when using the 743 * FPU vector (xmm) registers. 744 */ 745 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 746 747 #if !defined(_ASM) 748 749 #if defined(_KERNEL) || defined(_KMEMUSER) 750 751 #define NUM_X86_FEATURES 81 752 extern uchar_t x86_featureset[]; 753 754 extern void free_x86_featureset(void *featureset); 755 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 756 extern void add_x86_feature(void *featureset, uint_t feature); 757 extern void remove_x86_feature(void *featureset, uint_t feature); 758 extern boolean_t compare_x86_featureset(void *setA, void *setB); 759 extern void print_x86_featureset(void *featureset); 760 761 762 extern uint_t x86_type; 763 extern uint_t x86_vendor; 764 extern uint_t x86_clflush_size; 765 766 extern uint_t pentiumpro_bug4046376; 767 768 extern const char CyrixInstead[]; 769 770 #endif 771 772 #if defined(_KERNEL) 773 774 /* 775 * This structure is used to pass arguments and get return values back 776 * from the CPUID instruction in __cpuid_insn() routine. 777 */ 778 struct cpuid_regs { 779 uint32_t cp_eax; 780 uint32_t cp_ebx; 781 uint32_t cp_ecx; 782 uint32_t cp_edx; 783 }; 784 785 extern int x86_use_pcid; 786 extern int x86_use_invpcid; 787 788 /* 789 * Utility functions to get/set extended control registers (XCR) 790 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 791 */ 792 extern uint64_t get_xcr(uint_t); 793 extern void set_xcr(uint_t, uint64_t); 794 795 extern uint64_t rdmsr(uint_t); 796 extern void wrmsr(uint_t, const uint64_t); 797 extern uint64_t xrdmsr(uint_t); 798 extern void xwrmsr(uint_t, const uint64_t); 799 extern int checked_rdmsr(uint_t, uint64_t *); 800 extern int checked_wrmsr(uint_t, uint64_t); 801 802 extern void invalidate_cache(void); 803 extern ulong_t getcr4(void); 804 extern void setcr4(ulong_t); 805 806 extern void mtrr_sync(void); 807 808 extern void cpu_fast_syscall_enable(void); 809 extern void cpu_fast_syscall_disable(void); 810 811 struct cpu; 812 813 extern int cpuid_checkpass(struct cpu *, int); 814 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 815 extern uint32_t __cpuid_insn(struct cpuid_regs *); 816 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 817 extern int cpuid_getidstr(struct cpu *, char *, size_t); 818 extern const char *cpuid_getvendorstr(struct cpu *); 819 extern uint_t cpuid_getvendor(struct cpu *); 820 extern uint_t cpuid_getfamily(struct cpu *); 821 extern uint_t cpuid_getmodel(struct cpu *); 822 extern uint_t cpuid_getstep(struct cpu *); 823 extern uint_t cpuid_getsig(struct cpu *); 824 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 825 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 826 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 827 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 828 extern int cpuid_get_chipid(struct cpu *); 829 extern id_t cpuid_get_coreid(struct cpu *); 830 extern int cpuid_get_pkgcoreid(struct cpu *); 831 extern int cpuid_get_clogid(struct cpu *); 832 extern int cpuid_get_cacheid(struct cpu *); 833 extern uint32_t cpuid_get_apicid(struct cpu *); 834 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 835 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 836 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 837 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 838 extern size_t cpuid_get_xsave_size(); 839 extern boolean_t cpuid_need_fp_excp_handling(); 840 extern int cpuid_is_cmt(struct cpu *); 841 extern int cpuid_syscall32_insn(struct cpu *); 842 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 843 844 extern uint32_t cpuid_getchiprev(struct cpu *); 845 extern const char *cpuid_getchiprevstr(struct cpu *); 846 extern uint32_t cpuid_getsockettype(struct cpu *); 847 extern const char *cpuid_getsocketstr(struct cpu *); 848 849 extern int cpuid_have_cr8access(struct cpu *); 850 851 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 852 853 struct cpuid_info; 854 855 extern void setx86isalist(void); 856 extern void cpuid_alloc_space(struct cpu *); 857 extern void cpuid_free_space(struct cpu *); 858 extern void cpuid_pass1(struct cpu *, uchar_t *); 859 extern void cpuid_pass2(struct cpu *); 860 extern void cpuid_pass3(struct cpu *); 861 extern void cpuid_pass4(struct cpu *, uint_t *); 862 extern void cpuid_set_cpu_properties(void *, processorid_t, 863 struct cpuid_info *); 864 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 865 extern void cpuid_post_ucodeadm(void); 866 867 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 868 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 869 870 #if !defined(__xpv) 871 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 872 extern void cpuid_mwait_free(struct cpu *); 873 extern int cpuid_deep_cstates_supported(void); 874 extern int cpuid_arat_supported(void); 875 extern int cpuid_iepb_supported(struct cpu *); 876 extern int cpuid_deadline_tsc_supported(void); 877 extern void vmware_port(int, uint32_t *); 878 #endif 879 880 struct cpu_ucode_info; 881 882 extern void ucode_alloc_space(struct cpu *); 883 extern void ucode_free_space(struct cpu *); 884 extern void ucode_check(struct cpu *); 885 extern void ucode_cleanup(); 886 887 #if !defined(__xpv) 888 extern char _tsc_mfence_start; 889 extern char _tsc_mfence_end; 890 extern char _tscp_start; 891 extern char _tscp_end; 892 extern char _no_rdtsc_start; 893 extern char _no_rdtsc_end; 894 extern char _tsc_lfence_start; 895 extern char _tsc_lfence_end; 896 #endif 897 898 #if !defined(__xpv) 899 extern char bcopy_patch_start; 900 extern char bcopy_patch_end; 901 extern char bcopy_ck_size; 902 #endif 903 904 extern void post_startup_cpu_fixups(void); 905 906 extern uint_t workaround_errata(struct cpu *); 907 908 #if defined(OPTERON_ERRATUM_93) 909 extern int opteron_erratum_93; 910 #endif 911 912 #if defined(OPTERON_ERRATUM_91) 913 extern int opteron_erratum_91; 914 #endif 915 916 #if defined(OPTERON_ERRATUM_100) 917 extern int opteron_erratum_100; 918 #endif 919 920 #if defined(OPTERON_ERRATUM_121) 921 extern int opteron_erratum_121; 922 #endif 923 924 #if defined(OPTERON_WORKAROUND_6323525) 925 extern int opteron_workaround_6323525; 926 extern void patch_workaround_6323525(void); 927 #endif 928 929 #if !defined(__xpv) 930 extern void determine_platform(void); 931 #endif 932 extern int get_hwenv(void); 933 extern int is_controldom(void); 934 935 extern void enable_pcid(void); 936 937 extern void xsave_setup_msr(struct cpu *); 938 939 #if !defined(__xpv) 940 extern void reset_gdtr_limit(void); 941 #endif 942 943 /* 944 * Hypervisor signatures 945 */ 946 #define HVSIG_XEN_HVM "XenVMMXenVMM" 947 #define HVSIG_VMWARE "VMwareVMware" 948 #define HVSIG_KVM "KVMKVMKVM" 949 #define HVSIG_MICROSOFT "Microsoft Hv" 950 #define HVSIG_BHYVE "bhyve bhyve " 951 952 /* 953 * Defined hardware environments 954 */ 955 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 956 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 957 958 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 959 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 960 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 961 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 962 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 963 964 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 965 HW_BHYVE) 966 967 #endif /* _KERNEL */ 968 969 #endif /* !_ASM */ 970 971 /* 972 * VMware hypervisor related defines 973 */ 974 #define VMWARE_HVMAGIC 0x564d5868 975 #define VMWARE_HVPORT 0x5658 976 #define VMWARE_HVCMD_GETVERSION 0x0a 977 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 978 979 #ifdef __cplusplus 980 } 981 #endif 982 983 #endif /* _SYS_X86_ARCHEXT_H */ 984