1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2018 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 */ 36 37 #ifndef _SYS_X86_ARCHEXT_H 38 #define _SYS_X86_ARCHEXT_H 39 40 #if !defined(_ASM) 41 #include <sys/regset.h> 42 #include <sys/processor.h> 43 #include <vm/seg_enum.h> 44 #include <vm/page.h> 45 #endif /* _ASM */ 46 47 #ifdef __cplusplus 48 extern "C" { 49 #endif 50 51 /* 52 * cpuid instruction feature flags in %edx (standard function 1) 53 */ 54 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 65 /* 0x400 - reserved */ 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 75 /* 0x100000 - reserved */ 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 87 88 /* 89 * cpuid instruction feature flags in %ecx (standard function 1) 90 */ 91 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 103 /* 0x00000800 - reserved */ 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 108 /* 0x00010000 - reserved */ 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 124 125 /* 126 * cpuid instruction feature flags in %edx (extended function 0x80000001) 127 */ 128 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 139 /* 0x00000400 - sysc on K6m6 */ 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 148 /* 0x00040000 - reserved */ 149 /* 0x00080000 - reserved */ 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 151 /* 0x00200000 - reserved */ 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 158 /* 0x10000000 - reserved */ 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 162 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 177 /* 0x00004000 - reserved */ 178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 180 /* 0x00020000 - reserved */ 181 /* 0x00040000 - reserved */ 182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 183 /* 0x00100000 - reserved */ 184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 186 187 /* 188 * AMD uses %ebx for some of their features (extended function 0x80000008). 189 */ 190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 191 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 192 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 193 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 194 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 195 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 196 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 197 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 198 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 199 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 200 201 /* 202 * Intel now seems to have claimed part of the "extended" function 203 * space that we previously for non-Intel implementors to use. 204 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 205 * is available in long mode i.e. what AMD indicate using bit 0. 206 * On the other hand, everything else is labelled as reserved. 207 */ 208 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 209 210 /* 211 * Intel also uses cpuid leaf 7 to have additional instructions and features. 212 * Like some other leaves, but unlike the current ones we care about, it 213 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 214 * with the potential use of additional sub-leaves in the future, we now 215 * specifically label the EBX features with their leaf and sub-leaf. 216 */ 217 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 218 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 219 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 220 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 221 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 222 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 223 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 224 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 225 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 226 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 227 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 228 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 229 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 230 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 231 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 232 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 233 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 234 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 235 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 236 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 237 238 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 239 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 240 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 241 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 242 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 243 244 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 245 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 246 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 247 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 248 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 249 250 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 251 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 252 253 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 254 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 255 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 256 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 257 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 258 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 259 260 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 261 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 262 263 /* 264 * Intel also uses cpuid leaf 0xd to report additional instructions and features 265 * when the sub-leaf in %ecx == 1. We label these using the same convention as 266 * with leaf 7. 267 */ 268 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 269 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 270 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 271 272 #define REG_PAT 0x277 273 #define REG_TSC 0x10 /* timestamp counter */ 274 #define REG_APIC_BASE_MSR 0x1b 275 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 276 277 #if !defined(__xpv) 278 /* 279 * AMD C1E 280 */ 281 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 282 #define AMD_ACTONCMPHALT_SHIFT 27 283 #define AMD_ACTONCMPHALT_MASK 3 284 #endif 285 286 #define MSR_DEBUGCTL 0x1d9 287 288 #define DEBUGCTL_LBR 0x01 289 #define DEBUGCTL_BTF 0x02 290 291 /* Intel P6, AMD */ 292 #define MSR_LBR_FROM 0x1db 293 #define MSR_LBR_TO 0x1dc 294 #define MSR_LEX_FROM 0x1dd 295 #define MSR_LEX_TO 0x1de 296 297 /* Intel P4 (pre-Prescott, non P4 M) */ 298 #define MSR_P4_LBSTK_TOS 0x1da 299 #define MSR_P4_LBSTK_0 0x1db 300 #define MSR_P4_LBSTK_1 0x1dc 301 #define MSR_P4_LBSTK_2 0x1dd 302 #define MSR_P4_LBSTK_3 0x1de 303 304 /* Intel Pentium M */ 305 #define MSR_P6M_LBSTK_TOS 0x1c9 306 #define MSR_P6M_LBSTK_0 0x040 307 #define MSR_P6M_LBSTK_1 0x041 308 #define MSR_P6M_LBSTK_2 0x042 309 #define MSR_P6M_LBSTK_3 0x043 310 #define MSR_P6M_LBSTK_4 0x044 311 #define MSR_P6M_LBSTK_5 0x045 312 #define MSR_P6M_LBSTK_6 0x046 313 #define MSR_P6M_LBSTK_7 0x047 314 315 /* Intel P4 (Prescott) */ 316 #define MSR_PRP4_LBSTK_TOS 0x1da 317 #define MSR_PRP4_LBSTK_FROM_0 0x680 318 #define MSR_PRP4_LBSTK_FROM_1 0x681 319 #define MSR_PRP4_LBSTK_FROM_2 0x682 320 #define MSR_PRP4_LBSTK_FROM_3 0x683 321 #define MSR_PRP4_LBSTK_FROM_4 0x684 322 #define MSR_PRP4_LBSTK_FROM_5 0x685 323 #define MSR_PRP4_LBSTK_FROM_6 0x686 324 #define MSR_PRP4_LBSTK_FROM_7 0x687 325 #define MSR_PRP4_LBSTK_FROM_8 0x688 326 #define MSR_PRP4_LBSTK_FROM_9 0x689 327 #define MSR_PRP4_LBSTK_FROM_10 0x68a 328 #define MSR_PRP4_LBSTK_FROM_11 0x68b 329 #define MSR_PRP4_LBSTK_FROM_12 0x68c 330 #define MSR_PRP4_LBSTK_FROM_13 0x68d 331 #define MSR_PRP4_LBSTK_FROM_14 0x68e 332 #define MSR_PRP4_LBSTK_FROM_15 0x68f 333 #define MSR_PRP4_LBSTK_TO_0 0x6c0 334 #define MSR_PRP4_LBSTK_TO_1 0x6c1 335 #define MSR_PRP4_LBSTK_TO_2 0x6c2 336 #define MSR_PRP4_LBSTK_TO_3 0x6c3 337 #define MSR_PRP4_LBSTK_TO_4 0x6c4 338 #define MSR_PRP4_LBSTK_TO_5 0x6c5 339 #define MSR_PRP4_LBSTK_TO_6 0x6c6 340 #define MSR_PRP4_LBSTK_TO_7 0x6c7 341 #define MSR_PRP4_LBSTK_TO_8 0x6c8 342 #define MSR_PRP4_LBSTK_TO_9 0x6c9 343 #define MSR_PRP4_LBSTK_TO_10 0x6ca 344 #define MSR_PRP4_LBSTK_TO_11 0x6cb 345 #define MSR_PRP4_LBSTK_TO_12 0x6cc 346 #define MSR_PRP4_LBSTK_TO_13 0x6cd 347 #define MSR_PRP4_LBSTK_TO_14 0x6ce 348 #define MSR_PRP4_LBSTK_TO_15 0x6cf 349 350 /* 351 * General Xeon based MSRs 352 */ 353 #define MSR_PPIN_CTL 0x04e 354 #define MSR_PPIN 0x04f 355 #define MSR_PLATFORM_INFO 0x0ce 356 357 #define MSR_PLATFORM_INFO_PPIN (1 << 23) 358 #define MSR_PPIN_CTL_MASK 0x03 359 #define MSR_PPIN_CTL_LOCKED 0x01 360 #define MSR_PPIN_CTL_ENABLED 0x02 361 362 /* 363 * Intel IA32_ARCH_CAPABILITIES MSR. 364 */ 365 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 366 #define IA32_ARCH_CAP_RDCL_NO 0x0001 367 #define IA32_ARCH_CAP_IBRS_ALL 0x0002 368 #define IA32_ARCH_CAP_RSBA 0x0004 369 #define IA32_ARCH_CAP_SSB_NO 0x0010 370 371 /* 372 * Intel Speculation related MSRs 373 */ 374 #define MSR_IA32_SPEC_CTRL 0x48 375 #define IA32_SPEC_CTRL_IBRS 0x01 376 #define IA32_SPEC_CTRL_STIBP 0x02 377 #define IA32_SPEC_CTRL_SSBD 0x04 378 379 #define MSR_IA32_PRED_CMD 0x49 380 #define IA32_PRED_CMD_IBPB 0x01 381 382 #define MCI_CTL_VALUE 0xffffffff 383 384 #define MTRR_TYPE_UC 0 385 #define MTRR_TYPE_WC 1 386 #define MTRR_TYPE_WT 4 387 #define MTRR_TYPE_WP 5 388 #define MTRR_TYPE_WB 6 389 #define MTRR_TYPE_UC_ 7 390 391 /* 392 * For Solaris we set up the page attritubute table in the following way: 393 * PAT0 Write-Back 394 * PAT1 Write-Through 395 * PAT2 Unchacheable- 396 * PAT3 Uncacheable 397 * PAT4 Write-Back 398 * PAT5 Write-Through 399 * PAT6 Write-Combine 400 * PAT7 Uncacheable 401 * The only difference from h/w default is entry 6. 402 */ 403 #define PAT_DEFAULT_ATTRIBUTE \ 404 ((uint64_t)MTRR_TYPE_WB | \ 405 ((uint64_t)MTRR_TYPE_WT << 8) | \ 406 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 407 ((uint64_t)MTRR_TYPE_UC << 24) | \ 408 ((uint64_t)MTRR_TYPE_WB << 32) | \ 409 ((uint64_t)MTRR_TYPE_WT << 40) | \ 410 ((uint64_t)MTRR_TYPE_WC << 48) | \ 411 ((uint64_t)MTRR_TYPE_UC << 56)) 412 413 #define X86FSET_LARGEPAGE 0 414 #define X86FSET_TSC 1 415 #define X86FSET_MSR 2 416 #define X86FSET_MTRR 3 417 #define X86FSET_PGE 4 418 #define X86FSET_DE 5 419 #define X86FSET_CMOV 6 420 #define X86FSET_MMX 7 421 #define X86FSET_MCA 8 422 #define X86FSET_PAE 9 423 #define X86FSET_CX8 10 424 #define X86FSET_PAT 11 425 #define X86FSET_SEP 12 426 #define X86FSET_SSE 13 427 #define X86FSET_SSE2 14 428 #define X86FSET_HTT 15 429 #define X86FSET_ASYSC 16 430 #define X86FSET_NX 17 431 #define X86FSET_SSE3 18 432 #define X86FSET_CX16 19 433 #define X86FSET_CMP 20 434 #define X86FSET_TSCP 21 435 #define X86FSET_MWAIT 22 436 #define X86FSET_SSE4A 23 437 #define X86FSET_CPUID 24 438 #define X86FSET_SSSE3 25 439 #define X86FSET_SSE4_1 26 440 #define X86FSET_SSE4_2 27 441 #define X86FSET_1GPG 28 442 #define X86FSET_CLFSH 29 443 #define X86FSET_64 30 444 #define X86FSET_AES 31 445 #define X86FSET_PCLMULQDQ 32 446 #define X86FSET_XSAVE 33 447 #define X86FSET_AVX 34 448 #define X86FSET_VMX 35 449 #define X86FSET_SVM 36 450 #define X86FSET_TOPOEXT 37 451 #define X86FSET_F16C 38 452 #define X86FSET_RDRAND 39 453 #define X86FSET_X2APIC 40 454 #define X86FSET_AVX2 41 455 #define X86FSET_BMI1 42 456 #define X86FSET_BMI2 43 457 #define X86FSET_FMA 44 458 #define X86FSET_SMEP 45 459 #define X86FSET_SMAP 46 460 #define X86FSET_ADX 47 461 #define X86FSET_RDSEED 48 462 #define X86FSET_MPX 49 463 #define X86FSET_AVX512F 50 464 #define X86FSET_AVX512DQ 51 465 #define X86FSET_AVX512PF 52 466 #define X86FSET_AVX512ER 53 467 #define X86FSET_AVX512CD 54 468 #define X86FSET_AVX512BW 55 469 #define X86FSET_AVX512VL 56 470 #define X86FSET_AVX512FMA 57 471 #define X86FSET_AVX512VBMI 58 472 #define X86FSET_AVX512VPOPCDQ 59 473 #define X86FSET_AVX512NNIW 60 474 #define X86FSET_AVX512FMAPS 61 475 #define X86FSET_XSAVEOPT 62 476 #define X86FSET_XSAVEC 63 477 #define X86FSET_XSAVES 64 478 #define X86FSET_SHA 65 479 #define X86FSET_UMIP 66 480 #define X86FSET_PKU 67 481 #define X86FSET_OSPKE 68 482 #define X86FSET_PCID 69 483 #define X86FSET_INVPCID 70 484 #define X86FSET_IBRS 71 485 #define X86FSET_IBPB 72 486 #define X86FSET_STIBP 73 487 #define X86FSET_SSBD 74 488 #define X86FSET_SSBD_VIRT 75 489 #define X86FSET_RDCL_NO 76 490 #define X86FSET_IBRS_ALL 77 491 #define X86FSET_RSBA 78 492 #define X86FSET_SSB_NO 79 493 #define X86FSET_STIBP_ALL 80 494 495 /* 496 * Intel Deep C-State invariant TSC in leaf 0x80000007. 497 */ 498 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 499 500 /* 501 * Intel Deep C-state always-running local APIC timer 502 */ 503 #define CPUID_CSTATE_ARAT (0x4) 504 505 /* 506 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 507 */ 508 #define CPUID_EPB_SUPPORT (1 << 3) 509 510 /* 511 * Intel TSC deadline timer 512 */ 513 #define CPUID_DEADLINE_TSC (1 << 24) 514 515 /* 516 * x86_type is a legacy concept; this is supplanted 517 * for most purposes by x86_featureset; modern CPUs 518 * should be X86_TYPE_OTHER 519 */ 520 #define X86_TYPE_OTHER 0 521 #define X86_TYPE_486 1 522 #define X86_TYPE_P5 2 523 #define X86_TYPE_P6 3 524 #define X86_TYPE_CYRIX_486 4 525 #define X86_TYPE_CYRIX_6x86L 5 526 #define X86_TYPE_CYRIX_6x86 6 527 #define X86_TYPE_CYRIX_GXm 7 528 #define X86_TYPE_CYRIX_6x86MX 8 529 #define X86_TYPE_CYRIX_MediaGX 9 530 #define X86_TYPE_CYRIX_MII 10 531 #define X86_TYPE_VIA_CYRIX_III 11 532 #define X86_TYPE_P4 12 533 534 /* 535 * x86_vendor allows us to select between 536 * implementation features and helps guide 537 * the interpretation of the cpuid instruction. 538 */ 539 #define X86_VENDOR_Intel 0 540 #define X86_VENDORSTR_Intel "GenuineIntel" 541 542 #define X86_VENDOR_IntelClone 1 543 544 #define X86_VENDOR_AMD 2 545 #define X86_VENDORSTR_AMD "AuthenticAMD" 546 547 #define X86_VENDOR_Cyrix 3 548 #define X86_VENDORSTR_CYRIX "CyrixInstead" 549 550 #define X86_VENDOR_UMC 4 551 #define X86_VENDORSTR_UMC "UMC UMC UMC " 552 553 #define X86_VENDOR_NexGen 5 554 #define X86_VENDORSTR_NexGen "NexGenDriven" 555 556 #define X86_VENDOR_Centaur 6 557 #define X86_VENDORSTR_Centaur "CentaurHauls" 558 559 #define X86_VENDOR_Rise 7 560 #define X86_VENDORSTR_Rise "RiseRiseRise" 561 562 #define X86_VENDOR_SiS 8 563 #define X86_VENDORSTR_SiS "SiS SiS SiS " 564 565 #define X86_VENDOR_TM 9 566 #define X86_VENDORSTR_TM "GenuineTMx86" 567 568 #define X86_VENDOR_NSC 10 569 #define X86_VENDORSTR_NSC "Geode by NSC" 570 571 /* 572 * Vendor string max len + \0 573 */ 574 #define X86_VENDOR_STRLEN 13 575 576 /* 577 * Some vendor/family/model/stepping ranges are commonly grouped under 578 * a single identifying banner by the vendor. The following encode 579 * that "revision" in a uint32_t with the 8 most significant bits 580 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 581 * family, and the remaining 16 typically forming a bitmask of revisions 582 * within that family with more significant bits indicating "later" revisions. 583 */ 584 585 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 586 #define _X86_CHIPREV_VENDOR_SHIFT 24 587 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 588 #define _X86_CHIPREV_FAMILY_SHIFT 16 589 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 590 591 #define _X86_CHIPREV_VENDOR(x) \ 592 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 593 #define _X86_CHIPREV_FAMILY(x) \ 594 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 595 #define _X86_CHIPREV_REV(x) \ 596 ((x) & _X86_CHIPREV_REV_MASK) 597 598 /* True if x matches in vendor and family and if x matches the given rev mask */ 599 #define X86_CHIPREV_MATCH(x, mask) \ 600 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 601 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 602 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 603 604 /* True if x matches in vendor and family, and rev is at least minx */ 605 #define X86_CHIPREV_ATLEAST(x, minx) \ 606 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 607 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 608 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 609 610 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 611 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 612 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 613 614 /* True if x matches in vendor, and family is at least minx */ 615 #define X86_CHIPFAM_ATLEAST(x, minx) \ 616 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 617 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 618 619 /* Revision default */ 620 #define X86_CHIPREV_UNKNOWN 0x0 621 622 /* 623 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 624 * sufficiently different that we will distinguish them; in all other 625 * case we will identify the major revision. 626 */ 627 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 628 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 629 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 630 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 631 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 632 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 633 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 634 635 /* 636 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 637 */ 638 #define X86_CHIPREV_AMD_10_REV_A \ 639 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 640 #define X86_CHIPREV_AMD_10_REV_B \ 641 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 642 #define X86_CHIPREV_AMD_10_REV_C2 \ 643 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 644 #define X86_CHIPREV_AMD_10_REV_C3 \ 645 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 646 #define X86_CHIPREV_AMD_10_REV_D0 \ 647 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 648 #define X86_CHIPREV_AMD_10_REV_D1 \ 649 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 650 #define X86_CHIPREV_AMD_10_REV_E \ 651 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 652 653 /* 654 * Definitions for AMD Family 0x11. 655 */ 656 #define X86_CHIPREV_AMD_11_REV_B \ 657 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 658 659 /* 660 * Definitions for AMD Family 0x12. 661 */ 662 #define X86_CHIPREV_AMD_12_REV_B \ 663 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 664 665 /* 666 * Definitions for AMD Family 0x14. 667 */ 668 #define X86_CHIPREV_AMD_14_REV_B \ 669 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 670 #define X86_CHIPREV_AMD_14_REV_C \ 671 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 672 673 /* 674 * Definitions for AMD Family 0x15 675 */ 676 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 677 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 678 679 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 680 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 681 682 /* 683 * Various socket/package types, extended as the need to distinguish 684 * a new type arises. The top 8 byte identfies the vendor and the 685 * remaining 24 bits describe 24 socket types. 686 */ 687 688 #define _X86_SOCKET_VENDOR_SHIFT 24 689 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 690 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 691 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 692 693 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 694 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 695 696 #define X86_SOCKET_MATCH(s, mask) \ 697 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 698 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 699 700 #define X86_SOCKET_UNKNOWN 0x0 701 /* 702 * AMD socket types 703 */ 704 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 705 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 706 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 707 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 708 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 709 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 710 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 711 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 712 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 713 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 714 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 715 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 716 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 717 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 718 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000) 719 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000) 720 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000) 721 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000) 722 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000) 723 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000) 724 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000) 725 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000) 726 727 728 /* 729 * Definitions for Intel processor models. Note, these model values can overlap 730 * in a given family. Processor models are added here on an as needed basis. The 731 * Xeon extension here is to refer to what has been called the EP/EX lines or 732 * E5/E7, generally multi-socket capable processors. 733 */ 734 #define INTC_MODEL_IVYBRIDGE_XEON 0x3E 735 #define INTC_MODEL_HASWELL_XEON 0x3F 736 #define INTC_MODEL_BROADWELL_XEON 0x4F 737 #define INTC_MODEL_BROADWELL_XEON_D 0x56 738 #define INTC_MODEL_SKYLAKE_XEON 0x55 739 740 /* 741 * xgetbv/xsetbv support 742 * See section 13.3 in vol. 1 of the Intel devlopers manual. 743 */ 744 745 #define XFEATURE_ENABLED_MASK 0x0 746 /* 747 * XFEATURE_ENABLED_MASK values (eax) 748 * See setup_xfem(). 749 */ 750 #define XFEATURE_LEGACY_FP 0x1 751 #define XFEATURE_SSE 0x2 752 #define XFEATURE_AVX 0x4 753 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 754 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 755 /* bit 8 unused */ 756 #define XFEATURE_PKRU 0x200 757 #define XFEATURE_FP_ALL \ 758 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 759 XFEATURE_AVX512 | XFEATURE_PKRU) 760 761 /* 762 * Define the set of xfeature flags that should be considered valid in the xsave 763 * state vector when we initialize an lwp. This is distinct from the full set so 764 * that all of the processor's normal logic and tracking of the xsave state is 765 * usable. This should correspond to the state that's been initialized by the 766 * ABI to hold meaningful values. Adding additional bits here can have serious 767 * performance implications and cause performance degradations when using the 768 * FPU vector (xmm) registers. 769 */ 770 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 771 772 #if !defined(_ASM) 773 774 #if defined(_KERNEL) || defined(_KMEMUSER) 775 776 #define NUM_X86_FEATURES 81 777 extern uchar_t x86_featureset[]; 778 779 extern void free_x86_featureset(void *featureset); 780 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 781 extern void add_x86_feature(void *featureset, uint_t feature); 782 extern void remove_x86_feature(void *featureset, uint_t feature); 783 extern boolean_t compare_x86_featureset(void *setA, void *setB); 784 extern void print_x86_featureset(void *featureset); 785 786 787 extern uint_t x86_type; 788 extern uint_t x86_vendor; 789 extern uint_t x86_clflush_size; 790 791 extern uint_t pentiumpro_bug4046376; 792 793 extern const char CyrixInstead[]; 794 795 #endif 796 797 #if defined(_KERNEL) 798 799 /* 800 * This structure is used to pass arguments and get return values back 801 * from the CPUID instruction in __cpuid_insn() routine. 802 */ 803 struct cpuid_regs { 804 uint32_t cp_eax; 805 uint32_t cp_ebx; 806 uint32_t cp_ecx; 807 uint32_t cp_edx; 808 }; 809 810 extern int x86_use_pcid; 811 extern int x86_use_invpcid; 812 813 /* 814 * Utility functions to get/set extended control registers (XCR) 815 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 816 */ 817 extern uint64_t get_xcr(uint_t); 818 extern void set_xcr(uint_t, uint64_t); 819 820 extern uint64_t rdmsr(uint_t); 821 extern void wrmsr(uint_t, const uint64_t); 822 extern uint64_t xrdmsr(uint_t); 823 extern void xwrmsr(uint_t, const uint64_t); 824 extern int checked_rdmsr(uint_t, uint64_t *); 825 extern int checked_wrmsr(uint_t, uint64_t); 826 827 extern void invalidate_cache(void); 828 extern ulong_t getcr4(void); 829 extern void setcr4(ulong_t); 830 831 extern void mtrr_sync(void); 832 833 extern void cpu_fast_syscall_enable(void); 834 extern void cpu_fast_syscall_disable(void); 835 836 struct cpu; 837 838 extern int cpuid_checkpass(struct cpu *, int); 839 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 840 extern uint32_t __cpuid_insn(struct cpuid_regs *); 841 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 842 extern int cpuid_getidstr(struct cpu *, char *, size_t); 843 extern const char *cpuid_getvendorstr(struct cpu *); 844 extern uint_t cpuid_getvendor(struct cpu *); 845 extern uint_t cpuid_getfamily(struct cpu *); 846 extern uint_t cpuid_getmodel(struct cpu *); 847 extern uint_t cpuid_getstep(struct cpu *); 848 extern uint_t cpuid_getsig(struct cpu *); 849 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 850 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 851 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 852 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 853 extern int cpuid_get_chipid(struct cpu *); 854 extern id_t cpuid_get_coreid(struct cpu *); 855 extern int cpuid_get_pkgcoreid(struct cpu *); 856 extern int cpuid_get_clogid(struct cpu *); 857 extern int cpuid_get_cacheid(struct cpu *); 858 extern uint32_t cpuid_get_apicid(struct cpu *); 859 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 860 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 861 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 862 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 863 extern size_t cpuid_get_xsave_size(); 864 extern boolean_t cpuid_need_fp_excp_handling(); 865 extern int cpuid_is_cmt(struct cpu *); 866 extern int cpuid_syscall32_insn(struct cpu *); 867 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 868 869 extern uint32_t cpuid_getchiprev(struct cpu *); 870 extern const char *cpuid_getchiprevstr(struct cpu *); 871 extern uint32_t cpuid_getsockettype(struct cpu *); 872 extern const char *cpuid_getsocketstr(struct cpu *); 873 874 extern int cpuid_have_cr8access(struct cpu *); 875 876 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 877 878 struct cpuid_info; 879 880 extern void setx86isalist(void); 881 extern void cpuid_alloc_space(struct cpu *); 882 extern void cpuid_free_space(struct cpu *); 883 extern void cpuid_pass1(struct cpu *, uchar_t *); 884 extern void cpuid_pass2(struct cpu *); 885 extern void cpuid_pass3(struct cpu *); 886 extern void cpuid_pass4(struct cpu *, uint_t *); 887 extern void cpuid_set_cpu_properties(void *, processorid_t, 888 struct cpuid_info *); 889 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 890 extern void cpuid_post_ucodeadm(void); 891 892 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 893 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 894 895 #if !defined(__xpv) 896 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 897 extern void cpuid_mwait_free(struct cpu *); 898 extern int cpuid_deep_cstates_supported(void); 899 extern int cpuid_arat_supported(void); 900 extern int cpuid_iepb_supported(struct cpu *); 901 extern int cpuid_deadline_tsc_supported(void); 902 extern void vmware_port(int, uint32_t *); 903 #endif 904 905 struct cpu_ucode_info; 906 907 extern void ucode_alloc_space(struct cpu *); 908 extern void ucode_free_space(struct cpu *); 909 extern void ucode_check(struct cpu *); 910 extern void ucode_cleanup(); 911 912 #if !defined(__xpv) 913 extern char _tsc_mfence_start; 914 extern char _tsc_mfence_end; 915 extern char _tscp_start; 916 extern char _tscp_end; 917 extern char _no_rdtsc_start; 918 extern char _no_rdtsc_end; 919 extern char _tsc_lfence_start; 920 extern char _tsc_lfence_end; 921 #endif 922 923 #if !defined(__xpv) 924 extern char bcopy_patch_start; 925 extern char bcopy_patch_end; 926 extern char bcopy_ck_size; 927 #endif 928 929 extern void post_startup_cpu_fixups(void); 930 931 extern uint_t workaround_errata(struct cpu *); 932 933 #if defined(OPTERON_ERRATUM_93) 934 extern int opteron_erratum_93; 935 #endif 936 937 #if defined(OPTERON_ERRATUM_91) 938 extern int opteron_erratum_91; 939 #endif 940 941 #if defined(OPTERON_ERRATUM_100) 942 extern int opteron_erratum_100; 943 #endif 944 945 #if defined(OPTERON_ERRATUM_121) 946 extern int opteron_erratum_121; 947 #endif 948 949 #if defined(OPTERON_WORKAROUND_6323525) 950 extern int opteron_workaround_6323525; 951 extern void patch_workaround_6323525(void); 952 #endif 953 954 #if !defined(__xpv) 955 extern void determine_platform(void); 956 #endif 957 extern int get_hwenv(void); 958 extern int is_controldom(void); 959 960 extern void enable_pcid(void); 961 962 extern void xsave_setup_msr(struct cpu *); 963 964 #if !defined(__xpv) 965 extern void reset_gdtr_limit(void); 966 #endif 967 968 /* 969 * Hypervisor signatures 970 */ 971 #define HVSIG_XEN_HVM "XenVMMXenVMM" 972 #define HVSIG_VMWARE "VMwareVMware" 973 #define HVSIG_KVM "KVMKVMKVM" 974 #define HVSIG_MICROSOFT "Microsoft Hv" 975 #define HVSIG_BHYVE "bhyve bhyve " 976 977 /* 978 * Defined hardware environments 979 */ 980 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 981 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 982 983 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 984 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 985 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 986 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 987 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 988 989 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 990 HW_BHYVE) 991 992 #endif /* _KERNEL */ 993 994 #endif /* !_ASM */ 995 996 /* 997 * VMware hypervisor related defines 998 */ 999 #define VMWARE_HVMAGIC 0x564d5868 1000 #define VMWARE_HVPORT 0x5658 1001 #define VMWARE_HVCMD_GETVERSION 0x0a 1002 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 1003 1004 #ifdef __cplusplus 1005 } 1006 #endif 1007 1008 #endif /* _SYS_X86_ARCHEXT_H */ 1009