1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2020 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 * Copyright 2022 Oxide Computer Company 36 */ 37 38 #ifndef _SYS_X86_ARCHEXT_H 39 #define _SYS_X86_ARCHEXT_H 40 41 #if !defined(_ASM) 42 #include <sys/bitext.h> 43 #include <sys/regset.h> 44 #include <sys/processor.h> 45 #include <vm/seg_enum.h> 46 #include <vm/page.h> 47 #endif /* _ASM */ 48 49 #ifdef __cplusplus 50 extern "C" { 51 #endif 52 53 /* 54 * cpuid instruction feature flags in %edx (standard function 1) 55 */ 56 57 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 58 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 59 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 60 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 61 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 62 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 63 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 64 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 65 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 66 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 67 /* 0x400 - reserved */ 68 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 69 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 70 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 71 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 72 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 73 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 74 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 75 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 76 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 77 /* 0x100000 - reserved */ 78 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 79 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 80 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 81 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 82 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 83 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 84 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 85 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 86 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 87 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 88 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 89 90 /* 91 * cpuid instruction feature flags in %ecx (standard function 1) 92 */ 93 94 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 95 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 96 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 97 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 98 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 99 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 100 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 101 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 102 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 103 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 104 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 105 /* 0x00000800 - reserved */ 106 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 107 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 108 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 109 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 110 /* 0x00010000 - reserved */ 111 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 112 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 113 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 114 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 115 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 116 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 117 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 118 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 119 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 120 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 121 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 122 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 123 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 124 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 125 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 126 127 /* 128 * cpuid instruction feature flags in %edx (extended function 0x80000001) 129 */ 130 131 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 132 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 133 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 134 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 135 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 136 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 137 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 138 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 139 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 140 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 141 /* 0x00000400 - sysc on K6m6 */ 142 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 143 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 144 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 145 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 146 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 147 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 148 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 149 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 150 /* 0x00040000 - reserved */ 151 /* 0x00080000 - reserved */ 152 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 153 /* 0x00200000 - reserved */ 154 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 155 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 156 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 157 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 158 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 159 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 160 /* 0x10000000 - reserved */ 161 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 162 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 163 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 164 165 /* 166 * AMD extended function 0x80000001 %ecx 167 */ 168 169 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 170 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 171 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 172 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 173 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 174 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 175 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 176 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 177 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 178 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 179 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 180 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 181 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 182 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 183 /* 0x00004000 - reserved */ 184 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 185 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 186 /* 0x00020000 - reserved */ 187 /* 0x00040000 - reserved */ 188 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 189 /* 0x00100000 - reserved */ 190 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 191 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 192 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 193 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 194 /* 0x02000000 - reserved */ 195 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 196 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 197 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 198 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 199 /* 0x40000000 - reserved */ 200 /* 0x80000000 - reserved */ 201 202 /* 203 * AMD uses %ebx for some of their features (extended function 0x80000008). 204 */ 205 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 206 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 207 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 208 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 209 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 210 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 211 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 212 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 213 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 214 #define CPUID_AMD_EBX_PPIN 0x000800000 /* AMD: PPIN Support */ 215 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 216 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 217 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 218 219 /* 220 * AMD SVM features (extended function 0x8000000A). 221 */ 222 #define CPUID_AMD_EDX_NESTED_PAGING 0x000000001 /* AMD: SVM NP */ 223 #define CPUID_AMD_EDX_LBR_VIRT 0x000000002 /* AMD: LBR virt. */ 224 #define CPUID_AMD_EDX_SVML 0x000000004 /* AMD: SVM lock */ 225 #define CPUID_AMD_EDX_NRIPS 0x000000008 /* AMD: NRIP save */ 226 #define CPUID_AMD_EDX_TSC_RATE_MSR 0x000000010 /* AMD: MSR TSC ctrl */ 227 #define CPUID_AMD_EDX_VMCB_CLEAN 0x000000020 /* AMD: VMCB clean bits */ 228 #define CPUID_AMD_EDX_FLUSH_ASID 0x000000040 /* AMD: flush by ASID */ 229 #define CPUID_AMD_EDX_DECODE_ASSISTS 0x000000080 /* AMD: decode assists */ 230 231 /* 232 * Intel now seems to have claimed part of the "extended" function 233 * space that we previously for non-Intel implementors to use. 234 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 235 * is available in long mode i.e. what AMD indicate using bit 0. 236 * On the other hand, everything else is labelled as reserved. 237 */ 238 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 239 240 /* 241 * Intel uses cpuid leaf 6 to cover various thermal and power control 242 * operations. 243 */ 244 #define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */ 245 #define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */ 246 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */ 247 /* bit 3 is reserved */ 248 #define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */ 249 #define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */ 250 #define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */ 251 #define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */ 252 #define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */ 253 #define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */ 254 #define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */ 255 #define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */ 256 /* bit 12 is reserved */ 257 #define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */ 258 #define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */ 259 #define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */ 260 #define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */ 261 #define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */ 262 #define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */ 263 /* bit 19 is reserved */ 264 #define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */ 265 266 #define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf) 267 268 #define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */ 269 /* bits 1-2 are reserved */ 270 #define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */ 271 272 /* 273 * Intel also uses cpuid leaf 7 to have additional instructions and features. 274 * Like some other leaves, but unlike the current ones we care about, it 275 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 276 * with the potential use of additional sub-leaves in the future, we now 277 * specifically label the EBX features with their leaf and sub-leaf. 278 */ 279 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 280 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 281 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 282 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 283 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 284 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 285 #define CPUID_INTC_EBX_7_0_FDP_EXCPN 0x00000040 /* FDP on exception */ 286 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 287 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 288 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 289 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 290 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 291 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 292 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 293 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 294 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 295 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 296 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 297 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 298 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 299 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 300 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 301 /* Bit 22 is reserved */ 302 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 303 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 304 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 305 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 306 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 307 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 308 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 309 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 310 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 311 312 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 313 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 314 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 315 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 316 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 317 318 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 319 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 320 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 321 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 322 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 323 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 324 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 325 #define CPUID_INTC_ECX_7_0_CET_SS 0x00000080 /* CET Shadow Stack */ 326 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 327 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 328 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 329 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 330 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 331 #define CPUID_INTC_ECX_7_0_TME_EN 0x00002000 /* Total Memory Encr. */ 332 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 333 /* bit 15 is reserved */ 334 #define CPUID_INTC_ECX_7_0_LA57 0x00010000 /* 57-bit paging */ 335 /* bits 17-21 are the value of MAWAU */ 336 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 337 #define CPUID_INTC_ECX_7_0_KLSUP 0x00800000 /* Key Locker */ 338 /* bit 24 is reserved */ 339 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 340 /* bit 26 is resrved */ 341 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 342 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 343 #define CPUID_INTC_ECX_7_0_ENQCMD 0x20000000 /* Enqueue Stores */ 344 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 345 #define CPUID_INTC_ECX_7_0_PKS 0x80000000 /* protection keys */ 346 347 /* 348 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 349 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 350 * valid when AVX512 is not. However, the following flags all are only valid 351 * when AVX512 is present. 352 */ 353 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 354 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 355 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 356 357 /* bits 0-1 are reserved */ 358 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 359 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 360 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 361 #define CPUID_INTC_EDX_7_0_UINTR 0x00000020 /* user interrupts */ 362 /* bits 6-7 are reserved */ 363 #define CPUID_INTC_EDX_7_0_AVX512VP2INT 0x00000100 /* VP2INTERSECT */ 364 /* bit 9 is reserved */ 365 #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */ 366 /* bits 11-13 are reserved */ 367 #define CPUID_INTC_EDX_7_0_SERIALIZE 0x00004000 /* Serialize instr */ 368 #define CPUID_INTC_EDX_7_0_HYBRID 0x00008000 /* Hybrid CPU */ 369 #define CPUID_INTC_EDX_7_0_TSXLDTRK 0x00010000 /* TSX load track */ 370 /* bit 17 is reserved */ 371 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 372 /* bit 19 is reserved */ 373 #define CPUID_INTC_EDX_7_0_CET_IBT 0x00100000 /* CET ind. branch */ 374 /* bit 21 is reserved */ 375 #define CPUID_INTC_EDX_7_0_AMX_BF16 0x00400000 /* Tile F16 */ 376 #define CPUID_INTC_EDX_7_0_AVX512FP16 0x00800000 /* AVX512 FP16 */ 377 #define CPUID_INTC_EDX_7_0_AMX_TILE 0x01000000 /* Tile arch */ 378 #define CPUID_INTC_EDX_7_0_AMX_INT8 0x02000000 /* Tile INT8 */ 379 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 380 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 381 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 382 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 383 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 384 385 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 386 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS | \ 387 CPUID_INTC_EDX_7_0_AVX512VP2INT | CPUID_INTC_EDX_7_0_AVX512FP16) 388 389 /* bits 0-3 are reserved */ 390 #define CPUID_INTC_EAX_7_1_AVXVNNI 0x00000010 /* VEX VNNI */ 391 #define CPUID_INTC_EAX_7_1_AVX512_BF16 0x00000020 /* AVX512 BF16 */ 392 /* bits 6-9 are reserved */ 393 #define CPUID_INTC_EAX_7_1_ZL_MOVSB 0x00000400 /* zero-length MOVSB */ 394 #define CPUID_INTC_EAX_7_1_FS_STOSB 0x00000800 /* fast short STOSB */ 395 #define CPUID_INTC_EAX_7_1_FS_CMPSB 0x00001000 /* fast CMPSB, SCASB */ 396 /* bits 13-21 are reserved */ 397 #define CPUID_INTC_EAX_7_1_HRESET 0x00400000 /* History Reset leaf */ 398 /* bits 23-25 are reserved */ 399 #define CPUID_INTC_EAX_7_1_LAM 0x02000000 /* Linear addr mask */ 400 /* bits 27-31 are reserved */ 401 402 /* 403 * Intel also uses cpuid leaf 0xd to report additional instructions and features 404 * when the sub-leaf in %ecx == 1. We label these using the same convention as 405 * with leaf 7. 406 */ 407 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 408 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 409 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 410 411 #define REG_PAT 0x277 412 #define REG_TSC 0x10 /* timestamp counter */ 413 #define REG_APIC_BASE_MSR 0x1b 414 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 415 416 #if !defined(__xpv) 417 /* 418 * AMD C1E 419 */ 420 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 421 #define AMD_ACTONCMPHALT_SHIFT 27 422 #define AMD_ACTONCMPHALT_MASK 3 423 #endif 424 425 #define MSR_DEBUGCTL 0x1d9 426 427 #define DEBUGCTL_LBR 0x01 428 #define DEBUGCTL_BTF 0x02 429 430 /* Intel P6, AMD */ 431 #define MSR_LBR_FROM 0x1db 432 #define MSR_LBR_TO 0x1dc 433 #define MSR_LEX_FROM 0x1dd 434 #define MSR_LEX_TO 0x1de 435 436 /* Intel P4 (pre-Prescott, non P4 M) */ 437 #define MSR_P4_LBSTK_TOS 0x1da 438 #define MSR_P4_LBSTK_0 0x1db 439 #define MSR_P4_LBSTK_1 0x1dc 440 #define MSR_P4_LBSTK_2 0x1dd 441 #define MSR_P4_LBSTK_3 0x1de 442 443 /* Intel Pentium M */ 444 #define MSR_P6M_LBSTK_TOS 0x1c9 445 #define MSR_P6M_LBSTK_0 0x040 446 #define MSR_P6M_LBSTK_1 0x041 447 #define MSR_P6M_LBSTK_2 0x042 448 #define MSR_P6M_LBSTK_3 0x043 449 #define MSR_P6M_LBSTK_4 0x044 450 #define MSR_P6M_LBSTK_5 0x045 451 #define MSR_P6M_LBSTK_6 0x046 452 #define MSR_P6M_LBSTK_7 0x047 453 454 /* Intel P4 (Prescott) */ 455 #define MSR_PRP4_LBSTK_TOS 0x1da 456 #define MSR_PRP4_LBSTK_FROM_0 0x680 457 #define MSR_PRP4_LBSTK_FROM_1 0x681 458 #define MSR_PRP4_LBSTK_FROM_2 0x682 459 #define MSR_PRP4_LBSTK_FROM_3 0x683 460 #define MSR_PRP4_LBSTK_FROM_4 0x684 461 #define MSR_PRP4_LBSTK_FROM_5 0x685 462 #define MSR_PRP4_LBSTK_FROM_6 0x686 463 #define MSR_PRP4_LBSTK_FROM_7 0x687 464 #define MSR_PRP4_LBSTK_FROM_8 0x688 465 #define MSR_PRP4_LBSTK_FROM_9 0x689 466 #define MSR_PRP4_LBSTK_FROM_10 0x68a 467 #define MSR_PRP4_LBSTK_FROM_11 0x68b 468 #define MSR_PRP4_LBSTK_FROM_12 0x68c 469 #define MSR_PRP4_LBSTK_FROM_13 0x68d 470 #define MSR_PRP4_LBSTK_FROM_14 0x68e 471 #define MSR_PRP4_LBSTK_FROM_15 0x68f 472 #define MSR_PRP4_LBSTK_TO_0 0x6c0 473 #define MSR_PRP4_LBSTK_TO_1 0x6c1 474 #define MSR_PRP4_LBSTK_TO_2 0x6c2 475 #define MSR_PRP4_LBSTK_TO_3 0x6c3 476 #define MSR_PRP4_LBSTK_TO_4 0x6c4 477 #define MSR_PRP4_LBSTK_TO_5 0x6c5 478 #define MSR_PRP4_LBSTK_TO_6 0x6c6 479 #define MSR_PRP4_LBSTK_TO_7 0x6c7 480 #define MSR_PRP4_LBSTK_TO_8 0x6c8 481 #define MSR_PRP4_LBSTK_TO_9 0x6c9 482 #define MSR_PRP4_LBSTK_TO_10 0x6ca 483 #define MSR_PRP4_LBSTK_TO_11 0x6cb 484 #define MSR_PRP4_LBSTK_TO_12 0x6cc 485 #define MSR_PRP4_LBSTK_TO_13 0x6cd 486 #define MSR_PRP4_LBSTK_TO_14 0x6ce 487 #define MSR_PRP4_LBSTK_TO_15 0x6cf 488 489 /* 490 * PPIN definitions for Intel and AMD. Unfortunately, Intel and AMD use 491 * different MSRS for this and different MSRS to control whether or not it 492 * should be readable. 493 */ 494 #define MSR_PPIN_CTL_INTC 0x04e 495 #define MSR_PPIN_INTC 0x04f 496 #define MSR_PLATFORM_INFO 0x0ce 497 #define MSR_PLATFORM_INFO_PPIN (1 << 23) 498 499 #define MSR_PPIN_CTL_AMD 0xC00102F0 500 #define MSR_PPIN_AMD 0xC00102F1 501 502 /* 503 * These values are currently the same between Intel and AMD. 504 */ 505 #define MSR_PPIN_CTL_MASK 0x03 506 #define MSR_PPIN_CTL_DISABLED 0x00 507 #define MSR_PPIN_CTL_LOCKED 0x01 508 #define MSR_PPIN_CTL_ENABLED 0x02 509 510 /* 511 * Intel IA32_ARCH_CAPABILITIES MSR. 512 */ 513 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 514 #define IA32_ARCH_CAP_RDCL_NO 0x0001 515 #define IA32_ARCH_CAP_IBRS_ALL 0x0002 516 #define IA32_ARCH_CAP_RSBA 0x0004 517 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 518 #define IA32_ARCH_CAP_SSB_NO 0x0010 519 #define IA32_ARCH_CAP_MDS_NO 0x0020 520 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x0040 521 #define IA32_ARCH_CAP_TSX_CTRL 0x0080 522 #define IA32_ARCH_CAP_TAA_NO 0x0100 523 524 /* 525 * Intel Speculation related MSRs 526 */ 527 #define MSR_IA32_SPEC_CTRL 0x48 528 #define IA32_SPEC_CTRL_IBRS 0x01 529 #define IA32_SPEC_CTRL_STIBP 0x02 530 #define IA32_SPEC_CTRL_SSBD 0x04 531 532 #define MSR_IA32_PRED_CMD 0x49 533 #define IA32_PRED_CMD_IBPB 0x01 534 535 #define MSR_IA32_FLUSH_CMD 0x10b 536 #define IA32_FLUSH_CMD_L1D 0x01 537 538 /* 539 * Intel VMX related MSRs 540 */ 541 #define MSR_IA32_FEAT_CTRL 0x03a 542 #define IA32_FEAT_CTRL_LOCK 0x1 543 #define IA32_FEAT_CTRL_SMX_EN 0x2 544 #define IA32_FEAT_CTRL_VMX_EN 0x4 545 546 #define MSR_IA32_VMX_BASIC 0x480 547 #define IA32_VMX_BASIC_INS_OUTS (1UL << 54) 548 #define IA32_VMX_BASIC_TRUE_CTRLS (1UL << 55) 549 550 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 551 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 552 #define IA32_VMX_PROCBASED_2ND_CTLS (1UL << 31) 553 554 #define MSR_IA32_VMX_PROCBASED2_CTLS 0x48b 555 #define IA32_VMX_PROCBASED2_EPT (1UL << 1) 556 #define IA32_VMX_PROCBASED2_VPID (1UL << 5) 557 558 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 559 #define IA32_VMX_EPT_VPID_EXEC_ONLY (1UL << 0) 560 #define IA32_VMX_EPT_VPID_PWL4 (1UL << 6) 561 #define IA32_VMX_EPT_VPID_TYPE_UC (1UL << 8) 562 #define IA32_VMX_EPT_VPID_TYPE_WB (1UL << 14) 563 #define IA32_VMX_EPT_VPID_MAP_2M (1UL << 16) 564 #define IA32_VMX_EPT_VPID_MAP_1G (1UL << 17) 565 #define IA32_VMX_EPT_VPID_HW_AD (1UL << 21) 566 #define IA32_VMX_EPT_VPID_INVEPT (1UL << 20) 567 #define IA32_VMX_EPT_VPID_INVEPT_SINGLE (1UL << 25) 568 #define IA32_VMX_EPT_VPID_INVEPT_ALL (1UL << 26) 569 #define IA32_VMX_EPT_VPID_INVVPID (1UL << 32) 570 #define IA32_VMX_EPT_VPID_INVVPID_ADDR (1UL << 40) 571 #define IA32_VMX_EPT_VPID_INVVPID_SINGLE (1UL << 41) 572 #define IA32_VMX_EPT_VPID_INVVPID_ALL (1UL << 42) 573 #define IA32_VMX_EPT_VPID_INVVPID_RETAIN (1UL << 43) 574 575 /* 576 * Intel TSX Control MSRs 577 */ 578 #define MSR_IA32_TSX_CTRL 0x122 579 #define IA32_TSX_CTRL_RTM_DISABLE 0x01 580 #define IA32_TSX_CTRL_CPUID_CLEAR 0x02 581 582 /* 583 * Intel Thermal MSRs 584 */ 585 #define MSR_IA32_THERM_INTERRUPT 0x19b 586 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001 587 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002 588 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004 589 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008 590 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010 591 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 592 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000 593 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 594 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000 595 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000 596 597 #define MSR_IA32_THERM_STATUS 0x19c 598 #define IA32_THERM_STATUS_STATUS 0x00000001 599 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002 600 #define IA32_THERM_STATUS_PROCHOT 0x00000004 601 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008 602 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010 603 #define IA32_THERM_STATUS_CRIT_LOG 0x00000020 604 #define IA32_THERM_STATUS_TR1_STATUS 0x00000040 605 #define IA32_THERM_STATUS_TR1_LOG 0x00000080 606 #define IA32_THERM_STATUS_TR2_STATUS 0x00000100 607 #define IA32_THERM_STATUS_TR2_LOG 0x00000200 608 #define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400 609 #define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800 610 #define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000 611 #define IA32_THERM_STATUS_CURRENT_LOG 0x00002000 612 #define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000 613 #define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000 614 #define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 615 #define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f) 616 #define IA32_THERM_STATUS_READ_VALID 0x80000000 617 618 #define MSR_TEMPERATURE_TARGET 0x1a2 619 #define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff) 620 /* 621 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list 622 * of which models have support for which bits. 623 */ 624 #define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f) 625 626 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 627 #define IA32_PKG_THERM_STATUS_STATUS 0x00000001 628 #define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002 629 #define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004 630 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008 631 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010 632 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020 633 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040 634 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080 635 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100 636 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200 637 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 638 639 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 640 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001 641 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002 642 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004 643 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010 644 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 645 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000 646 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 647 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 648 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 649 650 /* 651 * AMD TOM and TOM2 MSRs. These control the split between DRAM and MMIO below 652 * and above 4 GiB respectively. These have existed since family 0xf. 653 */ 654 #define MSR_AMD_TOM 0xc001001a 655 #define MSR_AMD_TOM_MASK(x) ((x) & 0xffffff800000) 656 #define MSR_AMD_TOM2 0xc001001d 657 #define MSR_AMD_TOM2_MASK(x) ((x) & 0xffffff800000) 658 659 660 #define MCI_CTL_VALUE 0xffffffff 661 662 #define MTRR_TYPE_UC 0 663 #define MTRR_TYPE_WC 1 664 #define MTRR_TYPE_WT 4 665 #define MTRR_TYPE_WP 5 666 #define MTRR_TYPE_WB 6 667 #define MTRR_TYPE_UC_ 7 668 669 /* 670 * For Solaris we set up the page attritubute table in the following way: 671 * PAT0 Write-Back 672 * PAT1 Write-Through 673 * PAT2 Unchacheable- 674 * PAT3 Uncacheable 675 * PAT4 Write-Back 676 * PAT5 Write-Through 677 * PAT6 Write-Combine 678 * PAT7 Uncacheable 679 * The only difference from h/w default is entry 6. 680 */ 681 #define PAT_DEFAULT_ATTRIBUTE \ 682 ((uint64_t)MTRR_TYPE_WB | \ 683 ((uint64_t)MTRR_TYPE_WT << 8) | \ 684 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 685 ((uint64_t)MTRR_TYPE_UC << 24) | \ 686 ((uint64_t)MTRR_TYPE_WB << 32) | \ 687 ((uint64_t)MTRR_TYPE_WT << 40) | \ 688 ((uint64_t)MTRR_TYPE_WC << 48) | \ 689 ((uint64_t)MTRR_TYPE_UC << 56)) 690 691 #define X86FSET_LARGEPAGE 0 692 #define X86FSET_TSC 1 693 #define X86FSET_MSR 2 694 #define X86FSET_MTRR 3 695 #define X86FSET_PGE 4 696 #define X86FSET_DE 5 697 #define X86FSET_CMOV 6 698 #define X86FSET_MMX 7 699 #define X86FSET_MCA 8 700 #define X86FSET_PAE 9 701 #define X86FSET_CX8 10 702 #define X86FSET_PAT 11 703 #define X86FSET_SEP 12 704 #define X86FSET_SSE 13 705 #define X86FSET_SSE2 14 706 #define X86FSET_HTT 15 707 #define X86FSET_ASYSC 16 708 #define X86FSET_NX 17 709 #define X86FSET_SSE3 18 710 #define X86FSET_CX16 19 711 #define X86FSET_CMP 20 712 #define X86FSET_TSCP 21 713 #define X86FSET_MWAIT 22 714 #define X86FSET_SSE4A 23 715 #define X86FSET_CPUID 24 716 #define X86FSET_SSSE3 25 717 #define X86FSET_SSE4_1 26 718 #define X86FSET_SSE4_2 27 719 #define X86FSET_1GPG 28 720 #define X86FSET_CLFSH 29 721 #define X86FSET_64 30 722 #define X86FSET_AES 31 723 #define X86FSET_PCLMULQDQ 32 724 #define X86FSET_XSAVE 33 725 #define X86FSET_AVX 34 726 #define X86FSET_VMX 35 727 #define X86FSET_SVM 36 728 #define X86FSET_TOPOEXT 37 729 #define X86FSET_F16C 38 730 #define X86FSET_RDRAND 39 731 #define X86FSET_X2APIC 40 732 #define X86FSET_AVX2 41 733 #define X86FSET_BMI1 42 734 #define X86FSET_BMI2 43 735 #define X86FSET_FMA 44 736 #define X86FSET_SMEP 45 737 #define X86FSET_SMAP 46 738 #define X86FSET_ADX 47 739 #define X86FSET_RDSEED 48 740 #define X86FSET_MPX 49 741 #define X86FSET_AVX512F 50 742 #define X86FSET_AVX512DQ 51 743 #define X86FSET_AVX512PF 52 744 #define X86FSET_AVX512ER 53 745 #define X86FSET_AVX512CD 54 746 #define X86FSET_AVX512BW 55 747 #define X86FSET_AVX512VL 56 748 #define X86FSET_AVX512FMA 57 749 #define X86FSET_AVX512VBMI 58 750 #define X86FSET_AVX512VPOPCDQ 59 751 #define X86FSET_AVX512NNIW 60 752 #define X86FSET_AVX512FMAPS 61 753 #define X86FSET_XSAVEOPT 62 754 #define X86FSET_XSAVEC 63 755 #define X86FSET_XSAVES 64 756 #define X86FSET_SHA 65 757 #define X86FSET_UMIP 66 758 #define X86FSET_PKU 67 759 #define X86FSET_OSPKE 68 760 #define X86FSET_PCID 69 761 #define X86FSET_INVPCID 70 762 #define X86FSET_IBRS 71 763 #define X86FSET_IBPB 72 764 #define X86FSET_STIBP 73 765 #define X86FSET_SSBD 74 766 #define X86FSET_SSBD_VIRT 75 767 #define X86FSET_RDCL_NO 76 768 #define X86FSET_IBRS_ALL 77 769 #define X86FSET_RSBA 78 770 #define X86FSET_SSB_NO 79 771 #define X86FSET_STIBP_ALL 80 772 #define X86FSET_FLUSH_CMD 81 773 #define X86FSET_L1D_VM_NO 82 774 #define X86FSET_FSGSBASE 83 775 #define X86FSET_CLFLUSHOPT 84 776 #define X86FSET_CLWB 85 777 #define X86FSET_MONITORX 86 778 #define X86FSET_CLZERO 87 779 #define X86FSET_XOP 88 780 #define X86FSET_FMA4 89 781 #define X86FSET_TBM 90 782 #define X86FSET_AVX512VNNI 91 783 #define X86FSET_AMD_PCEC 92 784 #define X86FSET_MD_CLEAR 93 785 #define X86FSET_MDS_NO 94 786 #define X86FSET_CORE_THERMAL 95 787 #define X86FSET_PKG_THERMAL 96 788 #define X86FSET_TSX_CTRL 97 789 #define X86FSET_TAA_NO 98 790 #define X86FSET_PPIN 99 791 #define X86FSET_VAES 100 792 #define X86FSET_VPCLMULQDQ 101 793 #define X86FSET_LFENCE_SER 102 794 #define X86FSET_GFNI 103 795 #define X86FSET_AVX512_VP2INT 104 796 #define X86FSET_AVX512_BITALG 105 797 #define X86FSET_AVX512_VBMI2 106 798 #define X86FSET_AVX512_BF16 107 799 800 /* 801 * Intel Deep C-State invariant TSC in leaf 0x80000007. 802 */ 803 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 804 805 /* 806 * Intel TSC deadline timer 807 */ 808 #define CPUID_DEADLINE_TSC (1 << 24) 809 810 /* 811 * x86_type is a legacy concept; this is supplanted 812 * for most purposes by x86_featureset; modern CPUs 813 * should be X86_TYPE_OTHER 814 */ 815 #define X86_TYPE_OTHER 0 816 #define X86_TYPE_486 1 817 #define X86_TYPE_P5 2 818 #define X86_TYPE_P6 3 819 #define X86_TYPE_CYRIX_486 4 820 #define X86_TYPE_CYRIX_6x86L 5 821 #define X86_TYPE_CYRIX_6x86 6 822 #define X86_TYPE_CYRIX_GXm 7 823 #define X86_TYPE_CYRIX_6x86MX 8 824 #define X86_TYPE_CYRIX_MediaGX 9 825 #define X86_TYPE_CYRIX_MII 10 826 #define X86_TYPE_VIA_CYRIX_III 11 827 #define X86_TYPE_P4 12 828 829 /* 830 * x86_vendor allows us to select between 831 * implementation features and helps guide 832 * the interpretation of the cpuid instruction. 833 */ 834 #define X86_VENDOR_Intel 0 835 #define X86_VENDORSTR_Intel "GenuineIntel" 836 837 #define X86_VENDOR_IntelClone 1 838 839 #define X86_VENDOR_AMD 2 840 #define X86_VENDORSTR_AMD "AuthenticAMD" 841 842 #define X86_VENDOR_Cyrix 3 843 #define X86_VENDORSTR_CYRIX "CyrixInstead" 844 845 #define X86_VENDOR_UMC 4 846 #define X86_VENDORSTR_UMC "UMC UMC UMC " 847 848 #define X86_VENDOR_NexGen 5 849 #define X86_VENDORSTR_NexGen "NexGenDriven" 850 851 #define X86_VENDOR_Centaur 6 852 #define X86_VENDORSTR_Centaur "CentaurHauls" 853 854 #define X86_VENDOR_Rise 7 855 #define X86_VENDORSTR_Rise "RiseRiseRise" 856 857 #define X86_VENDOR_SiS 8 858 #define X86_VENDORSTR_SiS "SiS SiS SiS " 859 860 #define X86_VENDOR_TM 9 861 #define X86_VENDORSTR_TM "GenuineTMx86" 862 863 #define X86_VENDOR_NSC 10 864 #define X86_VENDORSTR_NSC "Geode by NSC" 865 866 #define X86_VENDOR_HYGON 11 867 #define X86_VENDORSTR_HYGON "HygonGenuine" 868 869 /* 870 * Vendor string max len + \0 871 */ 872 #define X86_VENDOR_STRLEN 13 873 874 /* 875 * For lookups and matching functions only; not an actual vendor. 876 */ 877 #define _X86_VENDOR_MATCH_ALL 0xff 878 879 /* 880 * See the big theory statement at the top of cpuid.c for information about how 881 * processor families and microarchitecture families relate to cpuid families, 882 * models, and steppings. 883 */ 884 885 #define _X86_CHIPREV_VENDOR_SHIFT 24 886 #define _X86_CHIPREV_FAMILY_SHIFT 16 887 888 #define _X86_CHIPREV_VENDOR(x) \ 889 bitx32((uint32_t)(x), 31, _X86_CHIPREV_VENDOR_SHIFT) 890 891 #define _X86_CHIPREV_FAMILY(x) \ 892 bitx32((uint32_t)(x), 23, _X86_CHIPREV_FAMILY_SHIFT) 893 894 #define _X86_CHIPREV_REV(x) \ 895 bitx32((uint32_t)(x), 15, 0) 896 897 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 898 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 899 (uint32_t)(family) << _X86_CHIPREV_FAMILY_SHIFT | (uint32_t)(rev)) 900 901 /* 902 * The legacy families here are a little bit unfortunate. Part of this is that 903 * the way AMD used the cpuid family/model/stepping changed somewhat over time, 904 * but the more immediate reason it's this way is more that the way we use 905 * chiprev/processor family changed with it. The ancient amd_opteron and mc-amd 906 * drivers used the chiprevs that were based on cpuid family, mainly 0xf and 907 * 0x10. amdzen_umc wants the processor family, in part because AMD's 908 * overloading of the cpuid family has made it effectively useless for 909 * discerning anything about the processor. That also tied into the way 910 * amd_revmap was previously organised in cpuid_subr.c: up to family 0x14 911 * everything was just "rev A", "rev B", etc.; afterward we started using the 912 * new shorthand, again tied to how AMD was presenting this information. 913 * Because there are other consumers of the processor family, it no longer made 914 * sense for amdzen to derive the processor family from the cpuid family/model 915 * given that we have this collection of definitions already and code in 916 * cpuid_subr.c to make use of them. The result is this unified approach that 917 * tries to keep old consumers happy while allowing new ones to get the degree 918 * of detail they need and expect. That required bending things a bit to make 919 * them fit, though critically as long as AMD keep on their current path and all 920 * new consumers look like the ones we are adding these days, we will be able to 921 * continue making new additions that will match all the recent ones and the way 922 * AMD are currently using families and models. There is absolutely no reason 923 * we couldn't go back and dig through all the legacy parts and break them down 924 * the same way, then change the old MC and CPU drivers to match, but I didn't 925 * feel like doing a lot of work for processors that it's unlikely anyone is 926 * still using and even more unlikely anyone will introduce new code to support. 927 * My compromise was to flesh things out starting where we already had more 928 * detail even if nothing was consuming it programmatically: at 0x15. Before 929 * that, processor family and cpuid family were effectively the same, because 930 * that's what those old consumers expect. 931 */ 932 933 #ifndef _ASM 934 typedef enum x86_processor_family { 935 X86_PF_UNKNOWN, 936 X86_PF_AMD_LEGACY_F = 0xf, 937 X86_PF_AMD_LEGACY_10 = 0x10, 938 X86_PF_AMD_LEGACY_11 = 0x11, 939 X86_PF_AMD_LEGACY_12 = 0x12, 940 X86_PF_AMD_LEGACY_14 = 0x14, 941 X86_PF_AMD_OROCHI, 942 X86_PF_AMD_TRINITY, 943 X86_PF_AMD_KAVERI, 944 X86_PF_AMD_CARRIZO, 945 X86_PF_AMD_STONEY_RIDGE, 946 X86_PF_AMD_KABINI, 947 X86_PF_AMD_MULLINS, 948 X86_PF_AMD_NAPLES, 949 X86_PF_AMD_PINNACLE_RIDGE, 950 X86_PF_AMD_RAVEN_RIDGE, 951 X86_PF_AMD_PICASSO, 952 X86_PF_AMD_DALI, 953 X86_PF_AMD_ROME, 954 X86_PF_AMD_RENOIR, 955 X86_PF_AMD_MATISSE, 956 X86_PF_AMD_VAN_GOGH, 957 X86_PF_AMD_MENDOCINO, 958 X86_PF_HYGON_DHYANA, 959 X86_PF_AMD_MILAN, 960 X86_PF_AMD_GENOA, 961 X86_PF_AMD_VERMEER, 962 X86_PF_AMD_REMBRANDT, 963 X86_PF_AMD_CEZANNE, 964 X86_PF_AMD_RAPHAEL, 965 966 X86_PF_ANY = 0xff 967 } x86_processor_family_t; 968 969 #define _DECL_CHIPREV(_v, _f, _revn, _revb) \ 970 X86_CHIPREV_ ## _v ## _ ## _f ## _ ## _revn = \ 971 _X86_CHIPREV_MKREV(X86_VENDOR_ ## _v, X86_PF_ ## _v ## _ ## _f, _revb) 972 973 #define _X86_CHIPREV_REV_MATCH_ALL 0xffff 974 975 typedef enum x86_chiprev { 976 X86_CHIPREV_UNKNOWN, 977 _DECL_CHIPREV(AMD, LEGACY_F, REV_B, 0x0001), 978 /* 979 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 980 * sufficiently different that we will distinguish them; in all other 981 * case we will identify the major revision. 982 */ 983 _DECL_CHIPREV(AMD, LEGACY_F, REV_C0, 0x0002), 984 _DECL_CHIPREV(AMD, LEGACY_F, REV_CG, 0x0004), 985 _DECL_CHIPREV(AMD, LEGACY_F, REV_D, 0x0008), 986 _DECL_CHIPREV(AMD, LEGACY_F, REV_E, 0x0010), 987 _DECL_CHIPREV(AMD, LEGACY_F, REV_F, 0x0020), 988 _DECL_CHIPREV(AMD, LEGACY_F, REV_G, 0x0040), 989 _DECL_CHIPREV(AMD, LEGACY_F, ANY, _X86_CHIPREV_REV_MATCH_ALL), 990 991 _DECL_CHIPREV(AMD, LEGACY_10, UNKNOWN, 0x0001), 992 _DECL_CHIPREV(AMD, LEGACY_10, REV_A, 0x0002), 993 _DECL_CHIPREV(AMD, LEGACY_10, REV_B, 0x0004), 994 _DECL_CHIPREV(AMD, LEGACY_10, REV_C2, 0x0008), 995 _DECL_CHIPREV(AMD, LEGACY_10, REV_C3, 0x0010), 996 _DECL_CHIPREV(AMD, LEGACY_10, REV_D0, 0x0020), 997 _DECL_CHIPREV(AMD, LEGACY_10, REV_D1, 0x0040), 998 _DECL_CHIPREV(AMD, LEGACY_10, REV_E, 0x0080), 999 _DECL_CHIPREV(AMD, LEGACY_10, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1000 1001 _DECL_CHIPREV(AMD, LEGACY_11, UNKNOWN, 0x0001), 1002 _DECL_CHIPREV(AMD, LEGACY_11, REV_B, 0x0002), 1003 _DECL_CHIPREV(AMD, LEGACY_11, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1004 1005 _DECL_CHIPREV(AMD, LEGACY_12, UNKNOWN, 0x0001), 1006 _DECL_CHIPREV(AMD, LEGACY_12, REV_B, 0x0002), 1007 _DECL_CHIPREV(AMD, LEGACY_12, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1008 1009 _DECL_CHIPREV(AMD, LEGACY_14, UNKNOWN, 0x0001), 1010 _DECL_CHIPREV(AMD, LEGACY_14, REV_B, 0x0002), 1011 _DECL_CHIPREV(AMD, LEGACY_14, REV_C, 0x0004), 1012 _DECL_CHIPREV(AMD, LEGACY_14, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1013 1014 _DECL_CHIPREV(AMD, OROCHI, UNKNOWN, 0x0001), 1015 _DECL_CHIPREV(AMD, OROCHI, REV_B2, 0x0002), 1016 _DECL_CHIPREV(AMD, OROCHI, REV_C0, 0x0004), 1017 _DECL_CHIPREV(AMD, OROCHI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1018 1019 _DECL_CHIPREV(AMD, TRINITY, UNKNOWN, 0x0001), 1020 _DECL_CHIPREV(AMD, TRINITY, REV_A1, 0x0002), 1021 _DECL_CHIPREV(AMD, TRINITY, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1022 1023 _DECL_CHIPREV(AMD, KAVERI, UNKNOWN, 0x0001), 1024 _DECL_CHIPREV(AMD, KAVERI, REV_A1, 0x0002), 1025 _DECL_CHIPREV(AMD, KAVERI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1026 1027 _DECL_CHIPREV(AMD, CARRIZO, UNKNOWN, 0x0001), 1028 _DECL_CHIPREV(AMD, CARRIZO, REV_A0, 0x0002), 1029 _DECL_CHIPREV(AMD, CARRIZO, REV_A1, 0x0004), 1030 _DECL_CHIPREV(AMD, CARRIZO, REV_DDR4, 0x0008), 1031 _DECL_CHIPREV(AMD, CARRIZO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1032 1033 _DECL_CHIPREV(AMD, STONEY_RIDGE, UNKNOWN, 0x0001), 1034 _DECL_CHIPREV(AMD, STONEY_RIDGE, REV_A0, 0x0002), 1035 _DECL_CHIPREV(AMD, STONEY_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1036 1037 _DECL_CHIPREV(AMD, KABINI, UNKNOWN, 0x0001), 1038 _DECL_CHIPREV(AMD, KABINI, A1, 0x0002), 1039 _DECL_CHIPREV(AMD, KABINI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1040 1041 _DECL_CHIPREV(AMD, MULLINS, UNKNOWN, 0x0001), 1042 _DECL_CHIPREV(AMD, MULLINS, A1, 0x0002), 1043 _DECL_CHIPREV(AMD, MULLINS, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1044 1045 _DECL_CHIPREV(AMD, NAPLES, UNKNOWN, 0x0001), 1046 _DECL_CHIPREV(AMD, NAPLES, A0, 0x0002), 1047 _DECL_CHIPREV(AMD, NAPLES, B1, 0x0004), 1048 _DECL_CHIPREV(AMD, NAPLES, B2, 0x0008), 1049 _DECL_CHIPREV(AMD, NAPLES, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1050 1051 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, UNKNOWN, 0x0001), 1052 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, B2, 0x0002), 1053 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1054 1055 _DECL_CHIPREV(AMD, RAVEN_RIDGE, UNKNOWN, 0x0001), 1056 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B0, 0x0002), 1057 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B1, 0x0004), 1058 _DECL_CHIPREV(AMD, RAVEN_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1059 1060 _DECL_CHIPREV(AMD, PICASSO, UNKNOWN, 0x0001), 1061 _DECL_CHIPREV(AMD, PICASSO, B1, 0x0002), 1062 _DECL_CHIPREV(AMD, PICASSO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1063 1064 _DECL_CHIPREV(AMD, DALI, UNKNOWN, 0x0001), 1065 _DECL_CHIPREV(AMD, DALI, A1, 0x0002), 1066 _DECL_CHIPREV(AMD, DALI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1067 1068 _DECL_CHIPREV(AMD, ROME, UNKNOWN, 0x0001), 1069 _DECL_CHIPREV(AMD, ROME, A0, 0x0002), 1070 _DECL_CHIPREV(AMD, ROME, B0, 0x0004), 1071 _DECL_CHIPREV(AMD, ROME, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1072 1073 _DECL_CHIPREV(AMD, RENOIR, UNKNOWN, 0x0001), 1074 _DECL_CHIPREV(AMD, RENOIR, A1, 0x0002), 1075 _DECL_CHIPREV(AMD, RENOIR, LCN_A1, 0x0004), 1076 _DECL_CHIPREV(AMD, RENOIR, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1077 1078 _DECL_CHIPREV(AMD, MATISSE, UNKNOWN, 0x0001), 1079 _DECL_CHIPREV(AMD, MATISSE, B0, 0x0002), 1080 _DECL_CHIPREV(AMD, MATISSE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1081 1082 _DECL_CHIPREV(AMD, VAN_GOGH, UNKNOWN, 0x0001), 1083 _DECL_CHIPREV(AMD, VAN_GOGH, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1084 1085 _DECL_CHIPREV(AMD, MENDOCINO, UNKNOWN, 0x0001), 1086 _DECL_CHIPREV(AMD, MENDOCINO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1087 1088 _DECL_CHIPREV(HYGON, DHYANA, UNKNOWN, 0x0001), 1089 _DECL_CHIPREV(HYGON, DHYANA, A1, 0x0002), 1090 _DECL_CHIPREV(HYGON, DHYANA, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1091 1092 _DECL_CHIPREV(AMD, MILAN, UNKNOWN, 0x0001), 1093 _DECL_CHIPREV(AMD, MILAN, A0, 0x0002), 1094 _DECL_CHIPREV(AMD, MILAN, B0, 0x0004), 1095 _DECL_CHIPREV(AMD, MILAN, B1, 0x0008), 1096 _DECL_CHIPREV(AMD, MILAN, B2, 0x0010), 1097 _DECL_CHIPREV(AMD, MILAN, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1098 1099 _DECL_CHIPREV(AMD, GENOA, UNKNOWN, 0x0001), 1100 _DECL_CHIPREV(AMD, GENOA, A0, 0x0002), 1101 _DECL_CHIPREV(AMD, GENOA, A1, 0x0004), 1102 _DECL_CHIPREV(AMD, GENOA, B0, 0x0008), 1103 _DECL_CHIPREV(AMD, GENOA, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1104 1105 _DECL_CHIPREV(AMD, VERMEER, UNKNOWN, 0x0001), 1106 _DECL_CHIPREV(AMD, VERMEER, A0, 0x0002), 1107 _DECL_CHIPREV(AMD, VERMEER, B0, 0x0004), 1108 _DECL_CHIPREV(AMD, VERMEER, B2, 0x0008), /* No B1 */ 1109 _DECL_CHIPREV(AMD, VERMEER, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1110 1111 _DECL_CHIPREV(AMD, REMBRANDT, UNKNOWN, 0x0001), 1112 _DECL_CHIPREV(AMD, REMBRANDT, A0, 0x0002), 1113 _DECL_CHIPREV(AMD, REMBRANDT, B0, 0x0004), 1114 _DECL_CHIPREV(AMD, REMBRANDT, B1, 0x0008), 1115 _DECL_CHIPREV(AMD, REMBRANDT, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1116 1117 _DECL_CHIPREV(AMD, CEZANNE, UNKNOWN, 0x0001), 1118 _DECL_CHIPREV(AMD, CEZANNE, A0, 0x0002), 1119 _DECL_CHIPREV(AMD, CEZANNE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1120 1121 _DECL_CHIPREV(AMD, RAPHAEL, UNKNOWN, 0x0001), 1122 _DECL_CHIPREV(AMD, RAPHAEL, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1123 1124 /* Keep at the end */ 1125 X86_CHIPREV_ANY = _X86_CHIPREV_MKREV(_X86_VENDOR_MATCH_ALL, X86_PF_ANY, 1126 _X86_CHIPREV_REV_MATCH_ALL) 1127 } x86_chiprev_t; 1128 1129 #undef _DECL_CHIPREV 1130 1131 /* 1132 * Same thing, but for microarchitecture (core implementations). We are not 1133 * attempting to capture every possible fine-grained detail here; to the extent 1134 * that it matters, we do so in cpuid.c via ISA/feature bits. We use the same 1135 * number of bits for each field as in chiprev. 1136 */ 1137 1138 #define _X86_UARCHREV_VENDOR(x) _X86_CHIPREV_VENDOR(x) 1139 #define _X86_UARCHREV_UARCH(x) _X86_CHIPREV_FAMILY(x) 1140 #define _X86_UARCHREV_REV(x) _X86_CHIPREV_REV(x) 1141 1142 #define _X86_UARCHREV_MKREV(vendor, family, rev) \ 1143 _X86_CHIPREV_MKREV(vendor, family, rev) 1144 1145 typedef enum x86_uarch { 1146 X86_UARCH_UNKNOWN, 1147 1148 X86_UARCH_AMD_LEGACY, 1149 X86_UARCH_AMD_ZEN1, 1150 X86_UARCH_AMD_ZENPLUS, 1151 X86_UARCH_AMD_ZEN2, 1152 X86_UARCH_AMD_ZEN3, 1153 X86_UARCH_AMD_ZEN4, 1154 1155 X86_UARCH_ANY = 0xff 1156 } x86_uarch_t; 1157 1158 #define _DECL_UARCHREV(_v, _f, _revn, _revb) \ 1159 X86_UARCHREV_ ## _v ## _ ## _f ## _ ## _revn = \ 1160 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \ 1161 _revb) 1162 1163 #define _DECL_UARCHREV_NOREV(_v, _f, _revb) \ 1164 X86_UARCHREV_ ## _v ## _ ## _f = \ 1165 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \ 1166 _revb) 1167 1168 #define _X86_UARCHREV_REV_MATCH_ALL 0xffff 1169 1170 typedef enum x86_uarchrev { 1171 X86_UARCHREV_UNKNOWN, 1172 _DECL_UARCHREV_NOREV(AMD, LEGACY, 0x0001), 1173 _DECL_UARCHREV(AMD, LEGACY, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1174 1175 _DECL_UARCHREV_NOREV(AMD, ZEN1, 0x0001), 1176 _DECL_UARCHREV(AMD, ZEN1, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1177 1178 _DECL_UARCHREV_NOREV(AMD, ZENPLUS, 0x0001), 1179 _DECL_UARCHREV(AMD, ZENPLUS, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1180 1181 _DECL_UARCHREV(AMD, ZEN2, UNKNOWN, 0x0001), 1182 _DECL_UARCHREV(AMD, ZEN2, A0, 0x0002), 1183 _DECL_UARCHREV(AMD, ZEN2, B0, 0x0004), 1184 _DECL_UARCHREV(AMD, ZEN2, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1185 1186 _DECL_UARCHREV(AMD, ZEN3, UNKNOWN, 0x0001), 1187 _DECL_UARCHREV(AMD, ZEN3, A0, 0x0002), 1188 _DECL_UARCHREV(AMD, ZEN3, B0, 0x0004), 1189 _DECL_UARCHREV(AMD, ZEN3, B1, 0x0008), 1190 _DECL_UARCHREV(AMD, ZEN3, B2, 0x0010), 1191 _DECL_UARCHREV(AMD, ZEN3, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1192 1193 _DECL_UARCHREV_NOREV(AMD, ZEN4, 0x0001), 1194 _DECL_UARCHREV(AMD, ZEN4, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1195 1196 /* Keep at the end */ 1197 _X86_UARCHREV_ANY = _X86_UARCHREV_MKREV(_X86_VENDOR_MATCH_ALL, 1198 X86_UARCH_ANY, _X86_UARCHREV_REV_MATCH_ALL) 1199 } x86_uarchrev_t; 1200 1201 #undef _DECL_UARCHREV 1202 1203 #endif /* !_ASM */ 1204 1205 /* 1206 * Various socket/package types, extended as the need to distinguish 1207 * a new type arises. The top 8 byte identfies the vendor and the 1208 * remaining 24 bits describe 24 socket types. 1209 */ 1210 1211 #define _X86_SOCKET_VENDOR_SHIFT 24 1212 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 1213 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 1214 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 1215 1216 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 1217 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 1218 1219 #define X86_SOCKET_MATCH(s, mask) \ 1220 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 1221 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 1222 1223 #define X86_SOCKET_UNKNOWN 0x0 1224 /* 1225 * AMD socket types 1226 */ 1227 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01) 1228 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02) 1229 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03) 1230 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04) 1231 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05) 1232 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06) 1233 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07) 1234 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08) 1235 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09) 1236 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a) 1237 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b) 1238 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c) 1239 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d) 1240 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e) 1241 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f) 1242 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10) 1243 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11) 1244 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12) 1245 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13) 1246 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14) 1247 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15) 1248 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16) 1249 #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17) 1250 #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18) 1251 #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19) 1252 #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a) 1253 #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b) 1254 #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c) 1255 #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d) 1256 #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e) 1257 #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f) 1258 #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20) 1259 #define X86_SOCKET_FP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x21) 1260 #define X86_SOCKET_FP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x22) 1261 #define X86_SOCKET_STRX4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x23) 1262 #define X86_SOCKET_SP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x24) 1263 #define X86_SOCKET_AM5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x25) 1264 #define X86_SOCKET_FP7 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x26) 1265 #define X86_SOCKET_FP7R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x27) 1266 #define X86_SOCKET_FF3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x28) 1267 #define X86_NUM_SOCKETS_AMD 0x28 1268 1269 /* 1270 * Hygon socket types 1271 */ 1272 #define X86_SOCKET_SL1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x01) 1273 #define X86_SOCKET_SL1R2 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x02) 1274 #define X86_SOCKET_DM1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x03) 1275 #define X86_NUM_SOCKETS_HYGON 0x03 1276 1277 #define X86_NUM_SOCKETS (X86_NUM_SOCKETS_AMD + X86_NUM_SOCKETS_HYGON) 1278 1279 /* 1280 * Definitions for Intel processor models. These are all for Family 6 1281 * processors. This list and the Atom set below it are not exhuastive. 1282 */ 1283 #define INTC_MODEL_YONAH 0x0e 1284 #define INTC_MODEL_MEROM 0x0f 1285 #define INTC_MODEL_MEROM_L 0x16 1286 #define INTC_MODEL_PENRYN 0x17 1287 #define INTC_MODEL_DUNNINGTON 0x1d 1288 1289 #define INTC_MODEL_NEHALEM 0x1e 1290 #define INTC_MODEL_NEHALEM2 0x1f 1291 #define INTC_MODEL_NEHALEM_EP 0x1a 1292 #define INTC_MODEL_NEHALEM_EX 0x2e 1293 1294 #define INTC_MODEL_WESTMERE 0x25 1295 #define INTC_MODEL_WESTMERE_EP 0x2c 1296 #define INTC_MODEL_WESTMERE_EX 0x2f 1297 1298 #define INTC_MODEL_SANDYBRIDGE 0x2a 1299 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 1300 #define INTC_MODEL_IVYBRIDGE 0x3a 1301 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 1302 1303 #define INTC_MODEL_HASWELL 0x3c 1304 #define INTC_MODEL_HASWELL_ULT 0x45 1305 #define INTC_MODEL_HASWELL_GT3E 0x46 1306 #define INTC_MODEL_HASWELL_XEON 0x3f 1307 1308 #define INTC_MODEL_BROADWELL 0x3d 1309 #define INTC_MODEL_BROADELL_2 0x47 1310 #define INTC_MODEL_BROADWELL_XEON 0x4f 1311 #define INTC_MODEL_BROADWELL_XEON_D 0x56 1312 1313 #define INTC_MODEL_SKYLAKE_MOBILE 0x4e 1314 /* 1315 * Note, this model is shared with Cascade Lake and Cooper Lake. 1316 */ 1317 #define INTC_MODEL_SKYLAKE_XEON 0x55 1318 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 1319 1320 /* 1321 * Note, both Kaby Lake models are shared with Coffee Lake, Whiskey Lake, Amber 1322 * Lake, and some Comet Lake parts. 1323 */ 1324 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 1325 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 1326 1327 #define INTC_MODEL_ICELAKE_XEON 0x6a 1328 #define INTC_MODEL_ICELAKE_MOBILE 0x7e 1329 #define INTC_MODEL_TIGERLAKE_MOBILE 0x8c 1330 1331 #define INTC_MODEL_COMETLAKE 0xa5 1332 #define INTC_MODEL_COMETLAKE_MOBILE 0xa6 1333 #define INTC_MODEL_ROCKETLAKE 0xa7 1334 1335 /* 1336 * Atom Processors 1337 */ 1338 #define INTC_MODEL_SILVERTHORNE 0x1c 1339 #define INTC_MODEL_LINCROFT 0x26 1340 #define INTC_MODEL_PENWELL 0x27 1341 #define INTC_MODEL_CLOVERVIEW 0x35 1342 #define INTC_MODEL_CEDARVIEW 0x36 1343 #define INTC_MODEL_BAY_TRAIL 0x37 1344 #define INTC_MODEL_AVATON 0x4d 1345 #define INTC_MODEL_AIRMONT 0x4c 1346 #define INTC_MODEL_GOLDMONT 0x5c 1347 #define INTC_MODEL_DENVERTON 0x5f 1348 #define INTC_MODEL_GEMINI_LAKE 0x7a 1349 1350 /* 1351 * xgetbv/xsetbv support 1352 * See section 13.3 in vol. 1 of the Intel devlopers manual. 1353 */ 1354 1355 #define XFEATURE_ENABLED_MASK 0x0 1356 /* 1357 * XFEATURE_ENABLED_MASK values (eax) 1358 * See setup_xfem(). 1359 */ 1360 #define XFEATURE_LEGACY_FP 0x1 1361 #define XFEATURE_SSE 0x2 1362 #define XFEATURE_AVX 0x4 1363 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 1364 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 1365 /* bit 8 unused */ 1366 #define XFEATURE_PKRU 0x200 1367 #define XFEATURE_FP_ALL \ 1368 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 1369 XFEATURE_AVX512 | XFEATURE_PKRU) 1370 1371 /* 1372 * Define the set of xfeature flags that should be considered valid in the xsave 1373 * state vector when we initialize an lwp. This is distinct from the full set so 1374 * that all of the processor's normal logic and tracking of the xsave state is 1375 * usable. This should correspond to the state that's been initialized by the 1376 * ABI to hold meaningful values. Adding additional bits here can have serious 1377 * performance implications and cause performance degradations when using the 1378 * FPU vector (xmm) registers. 1379 */ 1380 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 1381 1382 #if !defined(_ASM) 1383 1384 #if defined(_KERNEL) || defined(_KMEMUSER) 1385 1386 #define NUM_X86_FEATURES 108 1387 extern uchar_t x86_featureset[]; 1388 1389 extern void free_x86_featureset(void *featureset); 1390 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 1391 extern void add_x86_feature(void *featureset, uint_t feature); 1392 extern void remove_x86_feature(void *featureset, uint_t feature); 1393 extern boolean_t compare_x86_featureset(void *setA, void *setB); 1394 extern void print_x86_featureset(void *featureset); 1395 1396 1397 extern uint_t x86_type; 1398 extern uint_t x86_vendor; 1399 extern uint_t x86_clflush_size; 1400 1401 extern uint_t pentiumpro_bug4046376; 1402 1403 /* 1404 * These functions are all used to perform various side-channel mitigations. 1405 * Please see uts/i86pc/os/cpuid.c for more information. 1406 */ 1407 extern void (*spec_uarch_flush)(void); 1408 extern void x86_rsb_stuff(void); 1409 extern void x86_md_clear(void); 1410 1411 #endif 1412 1413 #if defined(_KERNEL) 1414 1415 /* 1416 * This structure is used to pass arguments and get return values back 1417 * from the CPUID instruction in __cpuid_insn() routine. 1418 */ 1419 struct cpuid_regs { 1420 uint32_t cp_eax; 1421 uint32_t cp_ebx; 1422 uint32_t cp_ecx; 1423 uint32_t cp_edx; 1424 }; 1425 1426 extern int x86_use_pcid; 1427 extern int x86_use_invpcid; 1428 1429 /* 1430 * Utility functions to get/set extended control registers (XCR) 1431 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 1432 */ 1433 extern uint64_t get_xcr(uint_t); 1434 extern void set_xcr(uint_t, uint64_t); 1435 1436 extern uint64_t rdmsr(uint_t); 1437 extern void wrmsr(uint_t, const uint64_t); 1438 extern uint64_t xrdmsr(uint_t); 1439 extern void xwrmsr(uint_t, const uint64_t); 1440 extern int checked_rdmsr(uint_t, uint64_t *); 1441 extern int checked_wrmsr(uint_t, uint64_t); 1442 1443 extern void invalidate_cache(void); 1444 extern ulong_t getcr4(void); 1445 extern void setcr4(ulong_t); 1446 1447 extern void mtrr_sync(void); 1448 1449 extern void cpu_fast_syscall_enable(void); 1450 extern void cpu_fast_syscall_disable(void); 1451 1452 typedef enum cpuid_pass { 1453 CPUID_PASS_NONE = 0, 1454 CPUID_PASS_PRELUDE, 1455 CPUID_PASS_IDENT, 1456 CPUID_PASS_BASIC, 1457 CPUID_PASS_EXTENDED, 1458 CPUID_PASS_DYNAMIC, 1459 CPUID_PASS_RESOLVE 1460 } cpuid_pass_t; 1461 1462 struct cpu; 1463 1464 extern boolean_t cpuid_checkpass(const struct cpu *const, const cpuid_pass_t); 1465 extern void cpuid_execpass(struct cpu *, const cpuid_pass_t, void *); 1466 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 1467 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 1468 extern uint32_t __cpuid_insn(struct cpuid_regs *); 1469 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 1470 extern int cpuid_getidstr(struct cpu *, char *, size_t); 1471 extern const char *cpuid_getvendorstr(struct cpu *); 1472 extern uint_t cpuid_getvendor(struct cpu *); 1473 extern uint_t cpuid_getfamily(struct cpu *); 1474 extern uint_t cpuid_getmodel(struct cpu *); 1475 extern uint_t cpuid_getstep(struct cpu *); 1476 extern uint_t cpuid_getsig(struct cpu *); 1477 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 1478 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 1479 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 1480 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 1481 extern int cpuid_get_chipid(struct cpu *); 1482 extern id_t cpuid_get_coreid(struct cpu *); 1483 extern int cpuid_get_pkgcoreid(struct cpu *); 1484 extern int cpuid_get_clogid(struct cpu *); 1485 extern int cpuid_get_cacheid(struct cpu *); 1486 extern uint32_t cpuid_get_apicid(struct cpu *); 1487 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 1488 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 1489 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 1490 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 1491 extern size_t cpuid_get_xsave_size(); 1492 extern boolean_t cpuid_need_fp_excp_handling(); 1493 extern int cpuid_is_cmt(struct cpu *); 1494 extern int cpuid_syscall32_insn(struct cpu *); 1495 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 1496 1497 extern x86_chiprev_t cpuid_getchiprev(struct cpu *); 1498 extern const char *cpuid_getchiprevstr(struct cpu *); 1499 extern uint32_t cpuid_getsockettype(struct cpu *); 1500 extern const char *cpuid_getsocketstr(struct cpu *); 1501 extern x86_uarchrev_t cpuid_getuarchrev(struct cpu *); 1502 1503 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 1504 1505 struct cpuid_info; 1506 1507 extern void setx86isalist(void); 1508 extern void cpuid_alloc_space(struct cpu *); 1509 extern void cpuid_free_space(struct cpu *); 1510 extern void cpuid_set_cpu_properties(void *, processorid_t, 1511 struct cpuid_info *); 1512 extern void cpuid_post_ucodeadm(void); 1513 1514 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 1515 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 1516 1517 #if !defined(__xpv) 1518 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 1519 extern void cpuid_mwait_free(struct cpu *); 1520 extern int cpuid_deep_cstates_supported(void); 1521 extern int cpuid_arat_supported(void); 1522 extern int cpuid_iepb_supported(struct cpu *); 1523 extern int cpuid_deadline_tsc_supported(void); 1524 extern void vmware_port(int, uint32_t *); 1525 #endif 1526 1527 extern x86_processor_family_t chiprev_family(const x86_chiprev_t); 1528 extern boolean_t chiprev_matches(const x86_chiprev_t, const x86_chiprev_t); 1529 extern boolean_t chiprev_at_least(const x86_chiprev_t, const x86_chiprev_t); 1530 1531 extern x86_uarch_t uarchrev_uarch(const x86_uarchrev_t); 1532 extern boolean_t uarchrev_matches(const x86_uarchrev_t, const x86_uarchrev_t); 1533 extern boolean_t uarchrev_at_least(const x86_uarchrev_t, const x86_uarchrev_t); 1534 1535 struct cpu_ucode_info; 1536 1537 extern void ucode_alloc_space(struct cpu *); 1538 extern void ucode_free_space(struct cpu *); 1539 extern void ucode_check(struct cpu *); 1540 extern void ucode_cleanup(); 1541 1542 #if !defined(__xpv) 1543 extern char _tsc_mfence_start; 1544 extern char _tsc_mfence_end; 1545 extern char _tscp_start; 1546 extern char _tscp_end; 1547 extern char _no_rdtsc_start; 1548 extern char _no_rdtsc_end; 1549 extern char _tsc_lfence_start; 1550 extern char _tsc_lfence_end; 1551 #endif 1552 1553 #if !defined(__xpv) 1554 extern char bcopy_patch_start; 1555 extern char bcopy_patch_end; 1556 extern char bcopy_ck_size; 1557 #endif 1558 1559 extern void post_startup_cpu_fixups(void); 1560 1561 extern uint_t workaround_errata(struct cpu *); 1562 1563 #if defined(OPTERON_ERRATUM_93) 1564 extern int opteron_erratum_93; 1565 #endif 1566 1567 #if defined(OPTERON_ERRATUM_91) 1568 extern int opteron_erratum_91; 1569 #endif 1570 1571 #if defined(OPTERON_ERRATUM_100) 1572 extern int opteron_erratum_100; 1573 #endif 1574 1575 #if defined(OPTERON_ERRATUM_121) 1576 extern int opteron_erratum_121; 1577 #endif 1578 1579 #if defined(OPTERON_ERRATUM_147) 1580 extern int opteron_erratum_147; 1581 extern void patch_erratum_147(void); 1582 #endif 1583 1584 #if !defined(__xpv) 1585 extern void determine_platform(void); 1586 #endif 1587 extern int get_hwenv(void); 1588 extern int is_controldom(void); 1589 1590 extern void enable_pcid(void); 1591 1592 extern void xsave_setup_msr(struct cpu *); 1593 1594 #if !defined(__xpv) 1595 extern void reset_gdtr_limit(void); 1596 #endif 1597 1598 extern int enable_platform_detection; 1599 1600 /* 1601 * Hypervisor signatures 1602 */ 1603 #define HVSIG_XEN_HVM "XenVMMXenVMM" 1604 #define HVSIG_VMWARE "VMwareVMware" 1605 #define HVSIG_KVM "KVMKVMKVM" 1606 #define HVSIG_MICROSOFT "Microsoft Hv" 1607 #define HVSIG_BHYVE "bhyve bhyve " 1608 1609 /* 1610 * Defined hardware environments 1611 */ 1612 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 1613 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 1614 1615 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 1616 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 1617 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 1618 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1619 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 1620 1621 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1622 HW_BHYVE) 1623 1624 #endif /* _KERNEL */ 1625 1626 #endif /* !_ASM */ 1627 1628 /* 1629 * VMware hypervisor related defines 1630 */ 1631 #define VMWARE_HVMAGIC 0x564d5868 1632 #define VMWARE_HVPORT 0x5658 1633 #define VMWARE_HVCMD_GETVERSION 0x0a 1634 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 1635 1636 #ifdef __cplusplus 1637 } 1638 #endif 1639 1640 #endif /* _SYS_X86_ARCHEXT_H */ 1641