1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2020 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 * Copyright 2022 Oxide Computer Company 36 */ 37 38 #ifndef _SYS_X86_ARCHEXT_H 39 #define _SYS_X86_ARCHEXT_H 40 41 #if !defined(_ASM) 42 #include <sys/regset.h> 43 #include <sys/processor.h> 44 #include <vm/seg_enum.h> 45 #include <vm/page.h> 46 #endif /* _ASM */ 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 /* 53 * cpuid instruction feature flags in %edx (standard function 1) 54 */ 55 56 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 57 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 58 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 59 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 60 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 61 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 62 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 63 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 64 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 65 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 66 /* 0x400 - reserved */ 67 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 68 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 69 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 70 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 71 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 72 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 73 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 74 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 75 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 76 /* 0x100000 - reserved */ 77 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 78 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 79 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 80 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 81 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 82 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 83 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 84 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 85 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 86 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 87 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 88 89 /* 90 * cpuid instruction feature flags in %ecx (standard function 1) 91 */ 92 93 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 94 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 95 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 96 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 97 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 98 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 99 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 100 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 101 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 102 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 103 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 104 /* 0x00000800 - reserved */ 105 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 106 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 107 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 108 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 109 /* 0x00010000 - reserved */ 110 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 111 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 112 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 113 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 114 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 115 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 116 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 117 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 118 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 119 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 120 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 121 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 122 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 123 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 124 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 125 126 /* 127 * cpuid instruction feature flags in %edx (extended function 0x80000001) 128 */ 129 130 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 131 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 132 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 133 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 134 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 135 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 136 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 137 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 138 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 139 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 140 /* 0x00000400 - sysc on K6m6 */ 141 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 142 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 143 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 144 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 145 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 146 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 147 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 148 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 149 /* 0x00040000 - reserved */ 150 /* 0x00080000 - reserved */ 151 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 152 /* 0x00200000 - reserved */ 153 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 154 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 155 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 156 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 157 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 158 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 159 /* 0x10000000 - reserved */ 160 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 161 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 162 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 163 164 /* 165 * AMD extended function 0x80000001 %ecx 166 */ 167 168 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 169 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 170 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 171 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 172 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 173 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 174 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 175 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 176 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 177 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 178 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 179 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 180 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 181 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 182 /* 0x00004000 - reserved */ 183 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 184 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 185 /* 0x00020000 - reserved */ 186 /* 0x00040000 - reserved */ 187 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 188 /* 0x00100000 - reserved */ 189 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 190 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 191 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 192 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 193 /* 0x02000000 - reserved */ 194 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 195 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 196 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 197 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 198 /* 0x40000000 - reserved */ 199 /* 0x80000000 - reserved */ 200 201 /* 202 * AMD uses %ebx for some of their features (extended function 0x80000008). 203 */ 204 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 205 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 206 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 207 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 208 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 209 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 210 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 211 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 212 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 213 #define CPUID_AMD_EBX_PPIN 0x000800000 /* AMD: PPIN Support */ 214 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 215 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 216 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 217 218 /* 219 * AMD SVM features (extended function 0x8000000A). 220 */ 221 #define CPUID_AMD_EDX_NESTED_PAGING 0x000000001 /* AMD: SVM NP */ 222 #define CPUID_AMD_EDX_LBR_VIRT 0x000000002 /* AMD: LBR virt. */ 223 #define CPUID_AMD_EDX_SVML 0x000000004 /* AMD: SVM lock */ 224 #define CPUID_AMD_EDX_NRIPS 0x000000008 /* AMD: NRIP save */ 225 #define CPUID_AMD_EDX_TSC_RATE_MSR 0x000000010 /* AMD: MSR TSC ctrl */ 226 #define CPUID_AMD_EDX_VMCB_CLEAN 0x000000020 /* AMD: VMCB clean bits */ 227 #define CPUID_AMD_EDX_FLUSH_ASID 0x000000040 /* AMD: flush by ASID */ 228 #define CPUID_AMD_EDX_DECODE_ASSISTS 0x000000080 /* AMD: decode assists */ 229 230 /* 231 * Intel now seems to have claimed part of the "extended" function 232 * space that we previously for non-Intel implementors to use. 233 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 234 * is available in long mode i.e. what AMD indicate using bit 0. 235 * On the other hand, everything else is labelled as reserved. 236 */ 237 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 238 239 /* 240 * Intel uses cpuid leaf 6 to cover various thermal and power control 241 * operations. 242 */ 243 #define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */ 244 #define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */ 245 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */ 246 /* bit 3 is reserved */ 247 #define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */ 248 #define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */ 249 #define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */ 250 #define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */ 251 #define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */ 252 #define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */ 253 #define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */ 254 #define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */ 255 /* bit 12 is reserved */ 256 #define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */ 257 #define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */ 258 #define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */ 259 #define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */ 260 #define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */ 261 #define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */ 262 /* bit 19 is reserved */ 263 #define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */ 264 265 #define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf) 266 267 #define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */ 268 /* bits 1-2 are reserved */ 269 #define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */ 270 271 /* 272 * Intel also uses cpuid leaf 7 to have additional instructions and features. 273 * Like some other leaves, but unlike the current ones we care about, it 274 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 275 * with the potential use of additional sub-leaves in the future, we now 276 * specifically label the EBX features with their leaf and sub-leaf. 277 */ 278 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 279 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 280 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 281 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 282 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 283 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 284 /* Bit 6 is reserved */ 285 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 286 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 287 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 288 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 289 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 290 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 291 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 292 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 293 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 294 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 295 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 296 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 297 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 298 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 299 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 300 /* Bit 22 is reserved */ 301 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 302 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 303 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 304 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 305 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 306 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 307 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 308 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 309 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 310 311 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 312 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 313 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 314 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 315 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 316 317 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 318 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 319 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 320 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 321 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 322 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 323 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 324 /* bit 7 is reserved */ 325 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 326 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 327 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 328 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 329 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 330 /* bit 13 is reserved */ 331 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 332 /* bits 15-16 are reserved */ 333 /* bits 17-21 are the value of MAWAU */ 334 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 335 /* bits 23-24 are reserved */ 336 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 337 /* bit 26 is resrved */ 338 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 339 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 340 /* bit 29 is reserved */ 341 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 342 /* bit 31 is reserved */ 343 344 /* 345 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 346 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 347 * valid when AVX512 is not. However, the following flags all are only valid 348 * when AVX512 is present. 349 */ 350 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 351 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 352 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 353 354 /* bits 0-1 are reserved */ 355 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 356 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 357 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 358 /* bits 5-9 are reserved */ 359 #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */ 360 /* bits 11-17 are reserved */ 361 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 362 /* bits 19-26 are reserved */ 363 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 364 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 365 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 366 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 367 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 368 369 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 370 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 371 372 /* 373 * Intel also uses cpuid leaf 0xd to report additional instructions and features 374 * when the sub-leaf in %ecx == 1. We label these using the same convention as 375 * with leaf 7. 376 */ 377 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 378 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 379 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 380 381 #define REG_PAT 0x277 382 #define REG_TSC 0x10 /* timestamp counter */ 383 #define REG_APIC_BASE_MSR 0x1b 384 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 385 386 #if !defined(__xpv) 387 /* 388 * AMD C1E 389 */ 390 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 391 #define AMD_ACTONCMPHALT_SHIFT 27 392 #define AMD_ACTONCMPHALT_MASK 3 393 #endif 394 395 #define MSR_DEBUGCTL 0x1d9 396 397 #define DEBUGCTL_LBR 0x01 398 #define DEBUGCTL_BTF 0x02 399 400 /* Intel P6, AMD */ 401 #define MSR_LBR_FROM 0x1db 402 #define MSR_LBR_TO 0x1dc 403 #define MSR_LEX_FROM 0x1dd 404 #define MSR_LEX_TO 0x1de 405 406 /* Intel P4 (pre-Prescott, non P4 M) */ 407 #define MSR_P4_LBSTK_TOS 0x1da 408 #define MSR_P4_LBSTK_0 0x1db 409 #define MSR_P4_LBSTK_1 0x1dc 410 #define MSR_P4_LBSTK_2 0x1dd 411 #define MSR_P4_LBSTK_3 0x1de 412 413 /* Intel Pentium M */ 414 #define MSR_P6M_LBSTK_TOS 0x1c9 415 #define MSR_P6M_LBSTK_0 0x040 416 #define MSR_P6M_LBSTK_1 0x041 417 #define MSR_P6M_LBSTK_2 0x042 418 #define MSR_P6M_LBSTK_3 0x043 419 #define MSR_P6M_LBSTK_4 0x044 420 #define MSR_P6M_LBSTK_5 0x045 421 #define MSR_P6M_LBSTK_6 0x046 422 #define MSR_P6M_LBSTK_7 0x047 423 424 /* Intel P4 (Prescott) */ 425 #define MSR_PRP4_LBSTK_TOS 0x1da 426 #define MSR_PRP4_LBSTK_FROM_0 0x680 427 #define MSR_PRP4_LBSTK_FROM_1 0x681 428 #define MSR_PRP4_LBSTK_FROM_2 0x682 429 #define MSR_PRP4_LBSTK_FROM_3 0x683 430 #define MSR_PRP4_LBSTK_FROM_4 0x684 431 #define MSR_PRP4_LBSTK_FROM_5 0x685 432 #define MSR_PRP4_LBSTK_FROM_6 0x686 433 #define MSR_PRP4_LBSTK_FROM_7 0x687 434 #define MSR_PRP4_LBSTK_FROM_8 0x688 435 #define MSR_PRP4_LBSTK_FROM_9 0x689 436 #define MSR_PRP4_LBSTK_FROM_10 0x68a 437 #define MSR_PRP4_LBSTK_FROM_11 0x68b 438 #define MSR_PRP4_LBSTK_FROM_12 0x68c 439 #define MSR_PRP4_LBSTK_FROM_13 0x68d 440 #define MSR_PRP4_LBSTK_FROM_14 0x68e 441 #define MSR_PRP4_LBSTK_FROM_15 0x68f 442 #define MSR_PRP4_LBSTK_TO_0 0x6c0 443 #define MSR_PRP4_LBSTK_TO_1 0x6c1 444 #define MSR_PRP4_LBSTK_TO_2 0x6c2 445 #define MSR_PRP4_LBSTK_TO_3 0x6c3 446 #define MSR_PRP4_LBSTK_TO_4 0x6c4 447 #define MSR_PRP4_LBSTK_TO_5 0x6c5 448 #define MSR_PRP4_LBSTK_TO_6 0x6c6 449 #define MSR_PRP4_LBSTK_TO_7 0x6c7 450 #define MSR_PRP4_LBSTK_TO_8 0x6c8 451 #define MSR_PRP4_LBSTK_TO_9 0x6c9 452 #define MSR_PRP4_LBSTK_TO_10 0x6ca 453 #define MSR_PRP4_LBSTK_TO_11 0x6cb 454 #define MSR_PRP4_LBSTK_TO_12 0x6cc 455 #define MSR_PRP4_LBSTK_TO_13 0x6cd 456 #define MSR_PRP4_LBSTK_TO_14 0x6ce 457 #define MSR_PRP4_LBSTK_TO_15 0x6cf 458 459 /* 460 * PPIN definitions for Intel and AMD. Unfortunately, Intel and AMD use 461 * different MSRS for this and different MSRS to control whether or not it 462 * should be readable. 463 */ 464 #define MSR_PPIN_CTL_INTC 0x04e 465 #define MSR_PPIN_INTC 0x04f 466 #define MSR_PLATFORM_INFO 0x0ce 467 #define MSR_PLATFORM_INFO_PPIN (1 << 23) 468 469 #define MSR_PPIN_CTL_AMD 0xC00102F0 470 #define MSR_PPIN_AMD 0xC00102F1 471 472 /* 473 * These values are currently the same between Intel and AMD. 474 */ 475 #define MSR_PPIN_CTL_MASK 0x03 476 #define MSR_PPIN_CTL_DISABLED 0x00 477 #define MSR_PPIN_CTL_LOCKED 0x01 478 #define MSR_PPIN_CTL_ENABLED 0x02 479 480 /* 481 * Intel IA32_ARCH_CAPABILITIES MSR. 482 */ 483 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 484 #define IA32_ARCH_CAP_RDCL_NO 0x0001 485 #define IA32_ARCH_CAP_IBRS_ALL 0x0002 486 #define IA32_ARCH_CAP_RSBA 0x0004 487 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 488 #define IA32_ARCH_CAP_SSB_NO 0x0010 489 #define IA32_ARCH_CAP_MDS_NO 0x0020 490 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x0040 491 #define IA32_ARCH_CAP_TSX_CTRL 0x0080 492 #define IA32_ARCH_CAP_TAA_NO 0x0100 493 494 /* 495 * Intel Speculation related MSRs 496 */ 497 #define MSR_IA32_SPEC_CTRL 0x48 498 #define IA32_SPEC_CTRL_IBRS 0x01 499 #define IA32_SPEC_CTRL_STIBP 0x02 500 #define IA32_SPEC_CTRL_SSBD 0x04 501 502 #define MSR_IA32_PRED_CMD 0x49 503 #define IA32_PRED_CMD_IBPB 0x01 504 505 #define MSR_IA32_FLUSH_CMD 0x10b 506 #define IA32_FLUSH_CMD_L1D 0x01 507 508 /* 509 * Intel VMX related MSRs 510 */ 511 #define MSR_IA32_FEAT_CTRL 0x03a 512 #define IA32_FEAT_CTRL_LOCK 0x1 513 #define IA32_FEAT_CTRL_SMX_EN 0x2 514 #define IA32_FEAT_CTRL_VMX_EN 0x4 515 516 #define MSR_IA32_VMX_BASIC 0x480 517 #define IA32_VMX_BASIC_INS_OUTS (1UL << 54) 518 #define IA32_VMX_BASIC_TRUE_CTRLS (1UL << 55) 519 520 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 521 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 522 #define IA32_VMX_PROCBASED_2ND_CTLS (1UL << 31) 523 524 #define MSR_IA32_VMX_PROCBASED2_CTLS 0x48b 525 #define IA32_VMX_PROCBASED2_EPT (1UL << 1) 526 #define IA32_VMX_PROCBASED2_VPID (1UL << 5) 527 528 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 529 #define IA32_VMX_EPT_VPID_EXEC_ONLY (1UL << 0) 530 #define IA32_VMX_EPT_VPID_PWL4 (1UL << 6) 531 #define IA32_VMX_EPT_VPID_TYPE_UC (1UL << 8) 532 #define IA32_VMX_EPT_VPID_TYPE_WB (1UL << 14) 533 #define IA32_VMX_EPT_VPID_MAP_2M (1UL << 16) 534 #define IA32_VMX_EPT_VPID_MAP_1G (1UL << 17) 535 #define IA32_VMX_EPT_VPID_HW_AD (1UL << 21) 536 #define IA32_VMX_EPT_VPID_INVEPT (1UL << 20) 537 #define IA32_VMX_EPT_VPID_INVEPT_SINGLE (1UL << 25) 538 #define IA32_VMX_EPT_VPID_INVEPT_ALL (1UL << 26) 539 #define IA32_VMX_EPT_VPID_INVVPID (1UL << 32) 540 #define IA32_VMX_EPT_VPID_INVVPID_ADDR (1UL << 40) 541 #define IA32_VMX_EPT_VPID_INVVPID_SINGLE (1UL << 41) 542 #define IA32_VMX_EPT_VPID_INVVPID_ALL (1UL << 42) 543 #define IA32_VMX_EPT_VPID_INVVPID_RETAIN (1UL << 43) 544 545 /* 546 * Intel TSX Control MSRs 547 */ 548 #define MSR_IA32_TSX_CTRL 0x122 549 #define IA32_TSX_CTRL_RTM_DISABLE 0x01 550 #define IA32_TSX_CTRL_CPUID_CLEAR 0x02 551 552 /* 553 * Intel Thermal MSRs 554 */ 555 #define MSR_IA32_THERM_INTERRUPT 0x19b 556 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001 557 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002 558 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004 559 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008 560 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010 561 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 562 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000 563 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 564 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000 565 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000 566 567 #define MSR_IA32_THERM_STATUS 0x19c 568 #define IA32_THERM_STATUS_STATUS 0x00000001 569 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002 570 #define IA32_THERM_STATUS_PROCHOT 0x00000004 571 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008 572 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010 573 #define IA32_THERM_STATUS_CRIT_LOG 0x00000020 574 #define IA32_THERM_STATUS_TR1_STATUS 0x00000040 575 #define IA32_THERM_STATUS_TR1_LOG 0x00000080 576 #define IA32_THERM_STATUS_TR2_STATUS 0x00000100 577 #define IA32_THERM_STATUS_TR2_LOG 0x00000200 578 #define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400 579 #define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800 580 #define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000 581 #define IA32_THERM_STATUS_CURRENT_LOG 0x00002000 582 #define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000 583 #define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000 584 #define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 585 #define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f) 586 #define IA32_THERM_STATUS_READ_VALID 0x80000000 587 588 #define MSR_TEMPERATURE_TARGET 0x1a2 589 #define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff) 590 /* 591 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list 592 * of which models have support for which bits. 593 */ 594 #define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f) 595 596 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 597 #define IA32_PKG_THERM_STATUS_STATUS 0x00000001 598 #define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002 599 #define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004 600 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008 601 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010 602 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020 603 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040 604 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080 605 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100 606 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200 607 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 608 609 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 610 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001 611 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002 612 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004 613 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010 614 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 615 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000 616 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 617 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 618 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 619 620 /* 621 * AMD TOM and TOM2 MSRs. These control the split between DRAM and MMIO below 622 * and above 4 GiB respectively. These have existed since family 0xf. 623 */ 624 #define MSR_AMD_TOM 0xc001001a 625 #define MSR_AMD_TOM_MASK(x) ((x) & 0xffffff800000) 626 #define MSR_AMD_TOM2 0xc001001d 627 #define MSR_AMD_TOM2_MASK(x) ((x) & 0xffffff800000) 628 629 630 #define MCI_CTL_VALUE 0xffffffff 631 632 #define MTRR_TYPE_UC 0 633 #define MTRR_TYPE_WC 1 634 #define MTRR_TYPE_WT 4 635 #define MTRR_TYPE_WP 5 636 #define MTRR_TYPE_WB 6 637 #define MTRR_TYPE_UC_ 7 638 639 /* 640 * For Solaris we set up the page attritubute table in the following way: 641 * PAT0 Write-Back 642 * PAT1 Write-Through 643 * PAT2 Unchacheable- 644 * PAT3 Uncacheable 645 * PAT4 Write-Back 646 * PAT5 Write-Through 647 * PAT6 Write-Combine 648 * PAT7 Uncacheable 649 * The only difference from h/w default is entry 6. 650 */ 651 #define PAT_DEFAULT_ATTRIBUTE \ 652 ((uint64_t)MTRR_TYPE_WB | \ 653 ((uint64_t)MTRR_TYPE_WT << 8) | \ 654 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 655 ((uint64_t)MTRR_TYPE_UC << 24) | \ 656 ((uint64_t)MTRR_TYPE_WB << 32) | \ 657 ((uint64_t)MTRR_TYPE_WT << 40) | \ 658 ((uint64_t)MTRR_TYPE_WC << 48) | \ 659 ((uint64_t)MTRR_TYPE_UC << 56)) 660 661 #define X86FSET_LARGEPAGE 0 662 #define X86FSET_TSC 1 663 #define X86FSET_MSR 2 664 #define X86FSET_MTRR 3 665 #define X86FSET_PGE 4 666 #define X86FSET_DE 5 667 #define X86FSET_CMOV 6 668 #define X86FSET_MMX 7 669 #define X86FSET_MCA 8 670 #define X86FSET_PAE 9 671 #define X86FSET_CX8 10 672 #define X86FSET_PAT 11 673 #define X86FSET_SEP 12 674 #define X86FSET_SSE 13 675 #define X86FSET_SSE2 14 676 #define X86FSET_HTT 15 677 #define X86FSET_ASYSC 16 678 #define X86FSET_NX 17 679 #define X86FSET_SSE3 18 680 #define X86FSET_CX16 19 681 #define X86FSET_CMP 20 682 #define X86FSET_TSCP 21 683 #define X86FSET_MWAIT 22 684 #define X86FSET_SSE4A 23 685 #define X86FSET_CPUID 24 686 #define X86FSET_SSSE3 25 687 #define X86FSET_SSE4_1 26 688 #define X86FSET_SSE4_2 27 689 #define X86FSET_1GPG 28 690 #define X86FSET_CLFSH 29 691 #define X86FSET_64 30 692 #define X86FSET_AES 31 693 #define X86FSET_PCLMULQDQ 32 694 #define X86FSET_XSAVE 33 695 #define X86FSET_AVX 34 696 #define X86FSET_VMX 35 697 #define X86FSET_SVM 36 698 #define X86FSET_TOPOEXT 37 699 #define X86FSET_F16C 38 700 #define X86FSET_RDRAND 39 701 #define X86FSET_X2APIC 40 702 #define X86FSET_AVX2 41 703 #define X86FSET_BMI1 42 704 #define X86FSET_BMI2 43 705 #define X86FSET_FMA 44 706 #define X86FSET_SMEP 45 707 #define X86FSET_SMAP 46 708 #define X86FSET_ADX 47 709 #define X86FSET_RDSEED 48 710 #define X86FSET_MPX 49 711 #define X86FSET_AVX512F 50 712 #define X86FSET_AVX512DQ 51 713 #define X86FSET_AVX512PF 52 714 #define X86FSET_AVX512ER 53 715 #define X86FSET_AVX512CD 54 716 #define X86FSET_AVX512BW 55 717 #define X86FSET_AVX512VL 56 718 #define X86FSET_AVX512FMA 57 719 #define X86FSET_AVX512VBMI 58 720 #define X86FSET_AVX512VPOPCDQ 59 721 #define X86FSET_AVX512NNIW 60 722 #define X86FSET_AVX512FMAPS 61 723 #define X86FSET_XSAVEOPT 62 724 #define X86FSET_XSAVEC 63 725 #define X86FSET_XSAVES 64 726 #define X86FSET_SHA 65 727 #define X86FSET_UMIP 66 728 #define X86FSET_PKU 67 729 #define X86FSET_OSPKE 68 730 #define X86FSET_PCID 69 731 #define X86FSET_INVPCID 70 732 #define X86FSET_IBRS 71 733 #define X86FSET_IBPB 72 734 #define X86FSET_STIBP 73 735 #define X86FSET_SSBD 74 736 #define X86FSET_SSBD_VIRT 75 737 #define X86FSET_RDCL_NO 76 738 #define X86FSET_IBRS_ALL 77 739 #define X86FSET_RSBA 78 740 #define X86FSET_SSB_NO 79 741 #define X86FSET_STIBP_ALL 80 742 #define X86FSET_FLUSH_CMD 81 743 #define X86FSET_L1D_VM_NO 82 744 #define X86FSET_FSGSBASE 83 745 #define X86FSET_CLFLUSHOPT 84 746 #define X86FSET_CLWB 85 747 #define X86FSET_MONITORX 86 748 #define X86FSET_CLZERO 87 749 #define X86FSET_XOP 88 750 #define X86FSET_FMA4 89 751 #define X86FSET_TBM 90 752 #define X86FSET_AVX512VNNI 91 753 #define X86FSET_AMD_PCEC 92 754 #define X86FSET_MD_CLEAR 93 755 #define X86FSET_MDS_NO 94 756 #define X86FSET_CORE_THERMAL 95 757 #define X86FSET_PKG_THERMAL 96 758 #define X86FSET_TSX_CTRL 97 759 #define X86FSET_TAA_NO 98 760 #define X86FSET_PPIN 99 761 #define X86FSET_VAES 100 762 #define X86FSET_VPCLMULQDQ 101 763 #define X86FSET_LFENCE_SER 102 764 765 /* 766 * Intel Deep C-State invariant TSC in leaf 0x80000007. 767 */ 768 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 769 770 /* 771 * Intel TSC deadline timer 772 */ 773 #define CPUID_DEADLINE_TSC (1 << 24) 774 775 /* 776 * x86_type is a legacy concept; this is supplanted 777 * for most purposes by x86_featureset; modern CPUs 778 * should be X86_TYPE_OTHER 779 */ 780 #define X86_TYPE_OTHER 0 781 #define X86_TYPE_486 1 782 #define X86_TYPE_P5 2 783 #define X86_TYPE_P6 3 784 #define X86_TYPE_CYRIX_486 4 785 #define X86_TYPE_CYRIX_6x86L 5 786 #define X86_TYPE_CYRIX_6x86 6 787 #define X86_TYPE_CYRIX_GXm 7 788 #define X86_TYPE_CYRIX_6x86MX 8 789 #define X86_TYPE_CYRIX_MediaGX 9 790 #define X86_TYPE_CYRIX_MII 10 791 #define X86_TYPE_VIA_CYRIX_III 11 792 #define X86_TYPE_P4 12 793 794 /* 795 * x86_vendor allows us to select between 796 * implementation features and helps guide 797 * the interpretation of the cpuid instruction. 798 */ 799 #define X86_VENDOR_Intel 0 800 #define X86_VENDORSTR_Intel "GenuineIntel" 801 802 #define X86_VENDOR_IntelClone 1 803 804 #define X86_VENDOR_AMD 2 805 #define X86_VENDORSTR_AMD "AuthenticAMD" 806 807 #define X86_VENDOR_Cyrix 3 808 #define X86_VENDORSTR_CYRIX "CyrixInstead" 809 810 #define X86_VENDOR_UMC 4 811 #define X86_VENDORSTR_UMC "UMC UMC UMC " 812 813 #define X86_VENDOR_NexGen 5 814 #define X86_VENDORSTR_NexGen "NexGenDriven" 815 816 #define X86_VENDOR_Centaur 6 817 #define X86_VENDORSTR_Centaur "CentaurHauls" 818 819 #define X86_VENDOR_Rise 7 820 #define X86_VENDORSTR_Rise "RiseRiseRise" 821 822 #define X86_VENDOR_SiS 8 823 #define X86_VENDORSTR_SiS "SiS SiS SiS " 824 825 #define X86_VENDOR_TM 9 826 #define X86_VENDORSTR_TM "GenuineTMx86" 827 828 #define X86_VENDOR_NSC 10 829 #define X86_VENDORSTR_NSC "Geode by NSC" 830 831 #define X86_VENDOR_HYGON 11 832 #define X86_VENDORSTR_HYGON "HygonGenuine" 833 834 /* 835 * Vendor string max len + \0 836 */ 837 #define X86_VENDOR_STRLEN 13 838 839 /* 840 * Some vendor/family/model/stepping ranges are commonly grouped under 841 * a single identifying banner by the vendor. The following encode 842 * that "revision" in a uint32_t with the 8 most significant bits 843 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 844 * family, and the remaining 16 typically forming a bitmask of revisions 845 * within that family with more significant bits indicating "later" revisions. 846 */ 847 848 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 849 #define _X86_CHIPREV_VENDOR_SHIFT 24 850 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 851 #define _X86_CHIPREV_FAMILY_SHIFT 16 852 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 853 854 #define _X86_CHIPREV_VENDOR(x) \ 855 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 856 #define _X86_CHIPREV_FAMILY(x) \ 857 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 858 #define _X86_CHIPREV_REV(x) \ 859 ((x) & _X86_CHIPREV_REV_MASK) 860 861 /* True if x matches in vendor and family and if x matches the given rev mask */ 862 #define X86_CHIPREV_MATCH(x, mask) \ 863 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 864 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 865 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 866 867 /* True if x matches in vendor and family, and rev is at least minx */ 868 #define X86_CHIPREV_ATLEAST(x, minx) \ 869 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 870 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 871 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 872 873 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 874 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 875 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 876 877 /* True if x matches in vendor, and family is at least minx */ 878 #define X86_CHIPFAM_ATLEAST(x, minx) \ 879 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 880 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 881 882 /* Revision default */ 883 #define X86_CHIPREV_UNKNOWN 0x0 884 885 /* 886 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 887 * sufficiently different that we will distinguish them; in all other 888 * case we will identify the major revision. 889 */ 890 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 891 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 892 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 893 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 894 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 895 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 896 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 897 898 /* 899 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 900 */ 901 #define X86_CHIPREV_AMD_10_REV_A \ 902 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 903 #define X86_CHIPREV_AMD_10_REV_B \ 904 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 905 #define X86_CHIPREV_AMD_10_REV_C2 \ 906 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 907 #define X86_CHIPREV_AMD_10_REV_C3 \ 908 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 909 #define X86_CHIPREV_AMD_10_REV_D0 \ 910 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010) 911 #define X86_CHIPREV_AMD_10_REV_D1 \ 912 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020) 913 #define X86_CHIPREV_AMD_10_REV_E \ 914 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040) 915 916 /* 917 * Definitions for AMD Family 0x11. 918 */ 919 #define X86_CHIPREV_AMD_11_REV_B \ 920 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002) 921 922 /* 923 * Definitions for AMD Family 0x12. 924 */ 925 #define X86_CHIPREV_AMD_12_REV_B \ 926 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002) 927 928 /* 929 * Definitions for AMD Family 0x14. 930 */ 931 #define X86_CHIPREV_AMD_14_REV_B \ 932 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002) 933 #define X86_CHIPREV_AMD_14_REV_C \ 934 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004) 935 936 /* 937 * Definitions for AMD Family 0x15 938 */ 939 #define X86_CHIPREV_AMD_15OR_REV_B2 \ 940 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001) 941 942 #define X86_CHIPREV_AMD_15TN_REV_A1 \ 943 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002) 944 945 #define X86_CHIPREV_AMD_150R_REV_C0 \ 946 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0003) 947 948 #define X86_CHIPREV_AMD_15KV_REV_A1 \ 949 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0004) 950 951 #define X86_CHIPREV_AMD_15F60 \ 952 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0005) 953 954 #define X86_CHIPREV_AMD_15ST_REV_A0 \ 955 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0006) 956 957 /* 958 * Definitions for AMD Family 0x16 959 */ 960 #define X86_CHIPREV_AMD_16_KB_A1 \ 961 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0001) 962 963 #define X86_CHIPREV_AMD_16_ML_A1 \ 964 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0002) 965 966 /* 967 * Definitions for AMD Family 0x17 968 */ 969 970 #define X86_CHIPREV_AMD_17_ZP_B1 \ 971 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0001) 972 973 #define X86_CHIPREV_AMD_17_ZP_B2 \ 974 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0002) 975 976 #define X86_CHIPREV_AMD_17_PiR_B2 \ 977 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0003) 978 979 #define X86_CHIPREV_AMD_17_RV_B0 \ 980 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0004) 981 982 #define X86_CHIPREV_AMD_17_RV_B1 \ 983 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0005) 984 985 #define X86_CHIPREV_AMD_17_PCO_B1 \ 986 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0006) 987 988 #define X86_CHIPREV_AMD_17_SSP_A0 \ 989 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0007) 990 991 #define X86_CHIPREV_AMD_17_SSP_B0 \ 992 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0008) 993 994 #define X86_CHIPREV_AMD_17_MTS_B0 \ 995 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0009) 996 997 /* 998 * Definitions for Hygon Family 0x18 999 */ 1000 #define X86_CHIPREV_HYGON_18_DN_A1 \ 1001 _X86_CHIPREV_MKREV(X86_VENDOR_HYGON, 0x18, 0x0001) 1002 1003 #define X86_CHIPREV_AMD_19_GN_A0 \ 1004 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0000) 1005 #define X86_CHIPREV_AMD_19_GN_B0 \ 1006 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0001) 1007 #define X86_CHIPREV_AMD_19_GN_B1 \ 1008 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0002) 1009 #define X86_CHIPREV_AMD_19_VMR_B0 \ 1010 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0003) 1011 #define X86_CHIPREV_AMD_19_VMR_B1 \ 1012 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x19, 0x0004) 1013 1014 /* 1015 * Various socket/package types, extended as the need to distinguish 1016 * a new type arises. The top 8 byte identfies the vendor and the 1017 * remaining 24 bits describe 24 socket types. 1018 */ 1019 1020 #define _X86_SOCKET_VENDOR_SHIFT 24 1021 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 1022 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 1023 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 1024 1025 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 1026 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 1027 1028 #define X86_SOCKET_MATCH(s, mask) \ 1029 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 1030 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 1031 1032 #define X86_SOCKET_UNKNOWN 0x0 1033 /* 1034 * AMD socket types 1035 */ 1036 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01) 1037 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02) 1038 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03) 1039 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04) 1040 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05) 1041 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06) 1042 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07) 1043 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08) 1044 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09) 1045 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a) 1046 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b) 1047 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c) 1048 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d) 1049 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e) 1050 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f) 1051 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10) 1052 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11) 1053 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12) 1054 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13) 1055 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14) 1056 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15) 1057 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16) 1058 #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17) 1059 #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18) 1060 #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19) 1061 #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a) 1062 #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b) 1063 #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c) 1064 #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d) 1065 #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e) 1066 #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f) 1067 #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20) 1068 #define X86_SOCKET_FP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x21) 1069 #define X86_SOCKET_FP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x22) 1070 #define X86_SOCKET_STRX4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x23) 1071 #define X86_NUM_SOCKETS_AMD 0x24 1072 1073 /* 1074 * Hygon socket types 1075 */ 1076 #define X86_SOCKET_SL1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x01) 1077 #define X86_SOCKET_SL1R2 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x02) 1078 #define X86_SOCKET_DM1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x03) 1079 #define X86_NUM_SOCKETS_HYGON 0x04 1080 1081 #define X86_NUM_SOCKETS (X86_NUM_SOCKETS_AMD + X86_NUM_SOCKETS_HYGON) 1082 1083 /* 1084 * Definitions for Intel processor models. These are all for Family 6 1085 * processors. This list and the Atom set below it are not exhuastive. 1086 */ 1087 #define INTC_MODEL_YONAH 0x0e 1088 #define INTC_MODEL_MEROM 0x0f 1089 #define INTC_MODEL_MEROM_L 0x16 1090 #define INTC_MODEL_PENRYN 0x17 1091 #define INTC_MODEL_DUNNINGTON 0x1d 1092 1093 #define INTC_MODEL_NEHALEM 0x1e 1094 #define INTC_MODEL_NEHALEM2 0x1f 1095 #define INTC_MODEL_NEHALEM_EP 0x1a 1096 #define INTC_MODEL_NEHALEM_EX 0x2e 1097 1098 #define INTC_MODEL_WESTMERE 0x25 1099 #define INTC_MODEL_WESTMERE_EP 0x2c 1100 #define INTC_MODEL_WESTMERE_EX 0x2f 1101 1102 #define INTC_MODEL_SANDYBRIDGE 0x2a 1103 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 1104 #define INTC_MODEL_IVYBRIDGE 0x3a 1105 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 1106 1107 #define INTC_MODEL_HASWELL 0x3c 1108 #define INTC_MODEL_HASWELL_ULT 0x45 1109 #define INTC_MODEL_HASWELL_GT3E 0x46 1110 #define INTC_MODEL_HASWELL_XEON 0x3f 1111 1112 #define INTC_MODEL_BROADWELL 0x3d 1113 #define INTC_MODEL_BROADELL_2 0x47 1114 #define INTC_MODEL_BROADWELL_XEON 0x4f 1115 #define INTC_MODEL_BROADWELL_XEON_D 0x56 1116 1117 #define INTC_MODEL_SKYLAKE_MOBILE 0x4e 1118 /* 1119 * Note, this model is shared with Cascade Lake and Cooper Lake. 1120 */ 1121 #define INTC_MODEL_SKYLAKE_XEON 0x55 1122 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 1123 1124 /* 1125 * Note, both Kaby Lake models are shared with Coffee Lake, Whiskey Lake, Amber 1126 * Lake, and some Comet Lake parts. 1127 */ 1128 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 1129 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 1130 1131 #define INTC_MODEL_ICELAKE_XEON 0x6a 1132 #define INTC_MODEL_ICELAKE_MOBILE 0x7e 1133 #define INTC_MODEL_TIGERLAKE_MOBILE 0x8c 1134 1135 #define INTC_MODEL_COMETLAKE 0xa5 1136 #define INTC_MODEL_COMETLAKE_MOBILE 0xa6 1137 #define INTC_MODEL_ROCKETLAKE 0xa7 1138 1139 /* 1140 * Atom Processors 1141 */ 1142 #define INTC_MODEL_SILVERTHORNE 0x1c 1143 #define INTC_MODEL_LINCROFT 0x26 1144 #define INTC_MODEL_PENWELL 0x27 1145 #define INTC_MODEL_CLOVERVIEW 0x35 1146 #define INTC_MODEL_CEDARVIEW 0x36 1147 #define INTC_MODEL_BAY_TRAIL 0x37 1148 #define INTC_MODEL_AVATON 0x4d 1149 #define INTC_MODEL_AIRMONT 0x4c 1150 #define INTC_MODEL_GOLDMONT 0x5c 1151 #define INTC_MODEL_DENVERTON 0x5f 1152 #define INTC_MODEL_GEMINI_LAKE 0x7a 1153 1154 /* 1155 * xgetbv/xsetbv support 1156 * See section 13.3 in vol. 1 of the Intel devlopers manual. 1157 */ 1158 1159 #define XFEATURE_ENABLED_MASK 0x0 1160 /* 1161 * XFEATURE_ENABLED_MASK values (eax) 1162 * See setup_xfem(). 1163 */ 1164 #define XFEATURE_LEGACY_FP 0x1 1165 #define XFEATURE_SSE 0x2 1166 #define XFEATURE_AVX 0x4 1167 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 1168 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 1169 /* bit 8 unused */ 1170 #define XFEATURE_PKRU 0x200 1171 #define XFEATURE_FP_ALL \ 1172 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 1173 XFEATURE_AVX512 | XFEATURE_PKRU) 1174 1175 /* 1176 * Define the set of xfeature flags that should be considered valid in the xsave 1177 * state vector when we initialize an lwp. This is distinct from the full set so 1178 * that all of the processor's normal logic and tracking of the xsave state is 1179 * usable. This should correspond to the state that's been initialized by the 1180 * ABI to hold meaningful values. Adding additional bits here can have serious 1181 * performance implications and cause performance degradations when using the 1182 * FPU vector (xmm) registers. 1183 */ 1184 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 1185 1186 #if !defined(_ASM) 1187 1188 #if defined(_KERNEL) || defined(_KMEMUSER) 1189 1190 #define NUM_X86_FEATURES 103 1191 extern uchar_t x86_featureset[]; 1192 1193 extern void free_x86_featureset(void *featureset); 1194 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 1195 extern void add_x86_feature(void *featureset, uint_t feature); 1196 extern void remove_x86_feature(void *featureset, uint_t feature); 1197 extern boolean_t compare_x86_featureset(void *setA, void *setB); 1198 extern void print_x86_featureset(void *featureset); 1199 1200 1201 extern uint_t x86_type; 1202 extern uint_t x86_vendor; 1203 extern uint_t x86_clflush_size; 1204 1205 extern uint_t pentiumpro_bug4046376; 1206 1207 extern const char CyrixInstead[]; 1208 1209 /* 1210 * These functions are all used to perform various side-channel mitigations. 1211 * Please see uts/i86pc/os/cpuid.c for more information. 1212 */ 1213 extern void (*spec_uarch_flush)(void); 1214 extern void x86_rsb_stuff(void); 1215 extern void x86_md_clear(void); 1216 1217 #endif 1218 1219 #if defined(_KERNEL) 1220 1221 /* 1222 * This structure is used to pass arguments and get return values back 1223 * from the CPUID instruction in __cpuid_insn() routine. 1224 */ 1225 struct cpuid_regs { 1226 uint32_t cp_eax; 1227 uint32_t cp_ebx; 1228 uint32_t cp_ecx; 1229 uint32_t cp_edx; 1230 }; 1231 1232 extern int x86_use_pcid; 1233 extern int x86_use_invpcid; 1234 1235 /* 1236 * Utility functions to get/set extended control registers (XCR) 1237 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 1238 */ 1239 extern uint64_t get_xcr(uint_t); 1240 extern void set_xcr(uint_t, uint64_t); 1241 1242 extern uint64_t rdmsr(uint_t); 1243 extern void wrmsr(uint_t, const uint64_t); 1244 extern uint64_t xrdmsr(uint_t); 1245 extern void xwrmsr(uint_t, const uint64_t); 1246 extern int checked_rdmsr(uint_t, uint64_t *); 1247 extern int checked_wrmsr(uint_t, uint64_t); 1248 1249 extern void invalidate_cache(void); 1250 extern ulong_t getcr4(void); 1251 extern void setcr4(ulong_t); 1252 1253 extern void mtrr_sync(void); 1254 1255 extern void cpu_fast_syscall_enable(void); 1256 extern void cpu_fast_syscall_disable(void); 1257 1258 struct cpu; 1259 1260 extern int cpuid_checkpass(struct cpu *, int); 1261 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 1262 extern uint32_t __cpuid_insn(struct cpuid_regs *); 1263 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 1264 extern int cpuid_getidstr(struct cpu *, char *, size_t); 1265 extern const char *cpuid_getvendorstr(struct cpu *); 1266 extern uint_t cpuid_getvendor(struct cpu *); 1267 extern uint_t cpuid_getfamily(struct cpu *); 1268 extern uint_t cpuid_getmodel(struct cpu *); 1269 extern uint_t cpuid_getstep(struct cpu *); 1270 extern uint_t cpuid_getsig(struct cpu *); 1271 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 1272 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 1273 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 1274 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 1275 extern int cpuid_get_chipid(struct cpu *); 1276 extern id_t cpuid_get_coreid(struct cpu *); 1277 extern int cpuid_get_pkgcoreid(struct cpu *); 1278 extern int cpuid_get_clogid(struct cpu *); 1279 extern int cpuid_get_cacheid(struct cpu *); 1280 extern uint32_t cpuid_get_apicid(struct cpu *); 1281 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 1282 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 1283 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 1284 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 1285 extern size_t cpuid_get_xsave_size(); 1286 extern boolean_t cpuid_need_fp_excp_handling(); 1287 extern int cpuid_is_cmt(struct cpu *); 1288 extern int cpuid_syscall32_insn(struct cpu *); 1289 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 1290 1291 extern uint32_t cpuid_getchiprev(struct cpu *); 1292 extern const char *cpuid_getchiprevstr(struct cpu *); 1293 extern uint32_t cpuid_getsockettype(struct cpu *); 1294 extern const char *cpuid_getsocketstr(struct cpu *); 1295 1296 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 1297 1298 struct cpuid_info; 1299 1300 extern void setx86isalist(void); 1301 extern void cpuid_alloc_space(struct cpu *); 1302 extern void cpuid_free_space(struct cpu *); 1303 extern void cpuid_pass1(struct cpu *, uchar_t *); 1304 extern void cpuid_pass2(struct cpu *); 1305 extern void cpuid_pass3(struct cpu *); 1306 extern void cpuid_pass4(struct cpu *, uint_t *); 1307 extern void cpuid_set_cpu_properties(void *, processorid_t, 1308 struct cpuid_info *); 1309 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 1310 extern void cpuid_post_ucodeadm(void); 1311 1312 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 1313 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 1314 1315 #if !defined(__xpv) 1316 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 1317 extern void cpuid_mwait_free(struct cpu *); 1318 extern int cpuid_deep_cstates_supported(void); 1319 extern int cpuid_arat_supported(void); 1320 extern int cpuid_iepb_supported(struct cpu *); 1321 extern int cpuid_deadline_tsc_supported(void); 1322 extern void vmware_port(int, uint32_t *); 1323 #endif 1324 1325 struct cpu_ucode_info; 1326 1327 extern void ucode_alloc_space(struct cpu *); 1328 extern void ucode_free_space(struct cpu *); 1329 extern void ucode_check(struct cpu *); 1330 extern void ucode_cleanup(); 1331 1332 #if !defined(__xpv) 1333 extern char _tsc_mfence_start; 1334 extern char _tsc_mfence_end; 1335 extern char _tscp_start; 1336 extern char _tscp_end; 1337 extern char _no_rdtsc_start; 1338 extern char _no_rdtsc_end; 1339 extern char _tsc_lfence_start; 1340 extern char _tsc_lfence_end; 1341 #endif 1342 1343 #if !defined(__xpv) 1344 extern char bcopy_patch_start; 1345 extern char bcopy_patch_end; 1346 extern char bcopy_ck_size; 1347 #endif 1348 1349 extern void post_startup_cpu_fixups(void); 1350 1351 extern uint_t workaround_errata(struct cpu *); 1352 1353 #if defined(OPTERON_ERRATUM_93) 1354 extern int opteron_erratum_93; 1355 #endif 1356 1357 #if defined(OPTERON_ERRATUM_91) 1358 extern int opteron_erratum_91; 1359 #endif 1360 1361 #if defined(OPTERON_ERRATUM_100) 1362 extern int opteron_erratum_100; 1363 #endif 1364 1365 #if defined(OPTERON_ERRATUM_121) 1366 extern int opteron_erratum_121; 1367 #endif 1368 1369 #if defined(OPTERON_WORKAROUND_6323525) 1370 extern int opteron_workaround_6323525; 1371 extern void patch_workaround_6323525(void); 1372 #endif 1373 1374 #if !defined(__xpv) 1375 extern void determine_platform(void); 1376 #endif 1377 extern int get_hwenv(void); 1378 extern int is_controldom(void); 1379 1380 extern void enable_pcid(void); 1381 1382 extern void xsave_setup_msr(struct cpu *); 1383 1384 #if !defined(__xpv) 1385 extern void reset_gdtr_limit(void); 1386 #endif 1387 1388 /* 1389 * Hypervisor signatures 1390 */ 1391 #define HVSIG_XEN_HVM "XenVMMXenVMM" 1392 #define HVSIG_VMWARE "VMwareVMware" 1393 #define HVSIG_KVM "KVMKVMKVM" 1394 #define HVSIG_MICROSOFT "Microsoft Hv" 1395 #define HVSIG_BHYVE "bhyve bhyve " 1396 1397 /* 1398 * Defined hardware environments 1399 */ 1400 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 1401 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 1402 1403 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 1404 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 1405 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 1406 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1407 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 1408 1409 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1410 HW_BHYVE) 1411 1412 #endif /* _KERNEL */ 1413 1414 #endif /* !_ASM */ 1415 1416 /* 1417 * VMware hypervisor related defines 1418 */ 1419 #define VMWARE_HVMAGIC 0x564d5868 1420 #define VMWARE_HVPORT 0x5658 1421 #define VMWARE_HVCMD_GETVERSION 0x0a 1422 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 1423 1424 #ifdef __cplusplus 1425 } 1426 #endif 1427 1428 #endif /* _SYS_X86_ARCHEXT_H */ 1429