1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2020 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 * Copyright 2024 Oxide Computer Company 36 */ 37 38 #ifndef _SYS_X86_ARCHEXT_H 39 #define _SYS_X86_ARCHEXT_H 40 41 #if !defined(_ASM) 42 #include <sys/bitext.h> 43 #include <sys/regset.h> 44 #include <sys/processor.h> 45 #include <vm/seg_enum.h> 46 #include <vm/page.h> 47 #endif /* _ASM */ 48 49 #ifdef __cplusplus 50 extern "C" { 51 #endif 52 53 /* 54 * cpuid instruction feature flags in %edx (standard function 1) 55 */ 56 57 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 58 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 59 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 60 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 61 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 62 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 63 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 64 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 65 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 66 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 67 /* 0x400 - reserved */ 68 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 69 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 70 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 71 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 72 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 73 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 74 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 75 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 76 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 77 /* 0x100000 - reserved */ 78 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 79 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 80 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 81 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 82 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 83 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 84 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 85 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 86 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 87 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 88 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 89 90 /* 91 * cpuid instruction feature flags in %ecx (standard function 1) 92 */ 93 94 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 95 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 96 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 97 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 98 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 99 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 100 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 101 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 102 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 103 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 104 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 105 /* 0x00000800 - reserved */ 106 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 107 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 108 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 109 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 110 /* 0x00010000 - reserved */ 111 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 112 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 113 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 114 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 115 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 116 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 117 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 118 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 119 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 120 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 121 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 122 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 123 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 124 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 125 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 126 127 /* 128 * cpuid instruction feature flags in %edx (extended function 0x80000001) 129 */ 130 131 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 132 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 133 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 134 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 135 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 136 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 137 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 138 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 139 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 140 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 141 /* 0x00000400 - sysc on K6m6 */ 142 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 143 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 144 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 145 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 146 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 147 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 148 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 149 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 150 /* 0x00040000 - reserved */ 151 /* 0x00080000 - reserved */ 152 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 153 /* 0x00200000 - reserved */ 154 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 155 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 156 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 157 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 158 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 159 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 160 /* 0x10000000 - reserved */ 161 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 162 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 163 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 164 165 /* 166 * AMD extended function 0x80000001 %ecx 167 */ 168 169 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 170 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 171 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 172 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 173 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 174 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 175 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 176 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 177 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 178 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 179 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 180 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 181 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 182 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 183 /* 0x00004000 - reserved */ 184 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 185 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 186 /* 0x00020000 - reserved */ 187 /* 0x00040000 - reserved */ 188 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 189 /* 0x00100000 - reserved */ 190 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 191 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 192 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 193 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 194 /* 0x02000000 - reserved */ 195 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 196 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 197 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 198 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 199 /* 0x40000000 - reserved */ 200 /* 0x80000000 - reserved */ 201 202 /* 203 * AMD uses %ebx for some of their features (extended function 0x80000008). 204 */ 205 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 206 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 207 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 208 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 209 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 210 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 211 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 212 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 213 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 214 #define CPUID_AMD_EBX_PPIN 0x000800000 /* AMD: PPIN Support */ 215 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 216 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 217 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 218 219 /* 220 * AMD SVM features (extended function 0x8000000A). 221 */ 222 #define CPUID_AMD_EDX_NESTED_PAGING (1 << 0) /* AMD: Nested paging */ 223 #define CPUID_AMD_EDX_LBR_VIRT (1 << 1) /* AMD: LBR virt. */ 224 #define CPUID_AMD_EDX_SVML (1 << 2) /* AMD: SVM lock */ 225 #define CPUID_AMD_EDX_NRIPS (1 << 3) /* AMD: NRIP save */ 226 #define CPUID_AMD_EDX_TSC_RATE_MSR (1 << 4) /* AMD: TSC ratio ctrl */ 227 #define CPUID_AMD_EDX_VMCB_CLEAN (1 << 5) /* AMD: VMCB clean bits */ 228 #define CPUID_AMD_EDX_FLUSH_ASID (1 << 6) /* AMD: flush by ASID */ 229 #define CPUID_AMD_EDX_DECODE_ASSISTS (1 << 7) /* AMD: decode assists */ 230 #define CPUID_AMD_EDX_PAUSE_INCPT (1 << 8) /* AMD: pause intercept */ 231 #define CPUID_AMD_EDX_PAUSE_TRSH (1 << 9) /* AMD: pause threshold */ 232 #define CPUID_AMD_EDX_AVIC (1 << 10) /* AMD: AVIC */ 233 234 /* 235 * AMD Encrypted Memory Capabilities -- 0x8000_001F 236 * 237 * %ecx is the number of encrypted guests. 238 * %edx is the minimum ASID value for SEV enabled, SEV-ES disabled guests 239 */ 240 #define CPUID_AMD_8X1F_EAX_NVS (1 << 29) /* VIRT_RMPUPDATE MSR */ 241 #define CPUID_AMD_8X1F_EAX_SCP (1 << 28) /* SVSM Comm Page MSR */ 242 #define CPUID_AMD_8X1F_EAX_SMT_PROT (1 << 25) /* SMT Protection */ 243 #define CPUID_AMD_8X1F_EAX_VMSAR_PROT (1 << 24) /* VMSA Reg Protection */ 244 #define CPUID_AMD_8X1F_EAX_IBSVGC (1 << 19) /* IBS Virt. for SEV-ES */ 245 #define CPUID_AMD_8X1F_EAX_VIRT_TOM (1 << 18) /* Virt TOM MSR */ 246 #define CPUID_AMD_8X1F_EAX_VMGEXIT (1 << 17) /* VMGEXIT Parameter */ 247 #define CPUID_AMD_8X1F_EAX_VTE (1 << 16) /* Virt Transparent Enc. */ 248 #define CPUID_AMD_8X1F_EAX_NO_IBS (1 << 15) /* No IBS by host */ 249 #define CPUID_AMD_8X1F_EAX_DBGSWP (1 << 14) /* Debug state for SEV-ES */ 250 #define CPUID_AMD_8X1F_EAX_ALT_INJ (1 << 13) /* Alternate Injection */ 251 #define CPUID_AMD_8X1F_EAX_RES_INJ (1 << 12) /* Restricted Injection */ 252 #define CPUID_AMD_8X1F_EAX_64B_HOST (1 << 11) /* SEV requires amd64 */ 253 #define CPUID_AMD_8X1F_EAX_HWECC (1 << 10) /* HW cache coherency req */ 254 #define CPUID_AMD_8X1F_EAX_TSC_AUX (1 << 9) /* TSC AUX Virtualization */ 255 #define CPUID_AMD_8X1F_EAX_SEC_TSC (1 << 8) /* Secure TSC */ 256 #define CPUID_AMD_8X1F_EAX_VSSS (1 << 7) /* VMPL Super. Shadow Stack */ 257 #define CPUID_AMD_8X1F_EAX_RMPQUERY (1 << 6) /* RMPQUERY Instr */ 258 #define CPUID_AMD_8X1F_EAX_VMPL (1 << 5) /* VM Permission Levels */ 259 #define CPUID_AMD_8X1F_EAX_SEV_SNP (1 << 4) /* SEV Secure Nested Paging */ 260 #define CPUID_AMD_8X1F_EAX_SEV_ES (1 << 3) /* SEV Encrypted State */ 261 #define CPUID_AMD_8X1F_EAX_PAGE_FLUSH (1 << 2) /* Page Flush MSR */ 262 #define CPUID_AMD_8X1F_EAX_SEV (1 << 1) /* Secure Encrypted Virt. */ 263 #define CPUID_AMD_8X1F_EAX_SME (1 << 0) /* Secure Memory Encrypt. */ 264 265 #define CPUID_AMD_8X1F_EBX_NVMPL(r) bitx32(r, 15, 12) /* num VM Perm lvl */ 266 #define CPUID_AMD_8X1F_EBX_PAR(r) bitx32(r, 11, 6) /* paddr bit rem */ 267 #define CPUID_AMD_8X1F_EBX_CBIT(r) bitx32(r, 5, 0) /* C-bit loc in PTE */ 268 269 /* 270 * AMD Platform QoS Extended Features -- 0x8000_0020 271 */ 272 #define CPUID_AMD_8X20_EBX_L3RR (1 << 4) /* L3 Range Reservations */ 273 274 /* 275 * AMD Extended Feature 2 -- 0x8000_0021 276 */ 277 #define CPUID_AMD_8X21_EAX_CPUID_DIS (1 << 17) /* CPUID dis for CPL > 0 */ 278 #define CPUID_AMD_8X21_EAX_PREFETCH (1 << 13) /* Prefetch control MSR */ 279 #define CPUID_AMD_8X21_EAX_NO_SMMCTL (1 << 9) /* No SMM_CTL MSR */ 280 #define CPUID_AMD_8X21_EAX_AIBRS (1 << 8) /* Automatic IBRS */ 281 #define CPUID_AMD_8X21_EAX_UAI (1 << 7) /* Upper Address Ignore */ 282 #define CPUID_AMD_8X21_EAX_SMM_PGLK (1 << 3) /* SMM Page config lock */ 283 #define CPUID_AMD_8X21_EAX_LFENCE_SER (1 << 2) /* LFENCE is dispatch serial */ 284 #define CPUID_AMD_8X21_EAX_NO_NDBP (1 << 0) /* No nested data #BP */ 285 286 #define CPUID_AMD_8X21_EBX_MPS(r) bitx32(11, 0) /* MCU Patch size x 16B */ 287 288 /* 289 * AMD Extended Performance Monitoring and Debug -- 0x8000_0022 290 */ 291 #define CPUID_AMD_8X22_LBR_FRZ (1 << 2) /* Freeze PMC / LBR on ovflw */ 292 #define CPUID_AMD_8X22_LBR_STK (1 << 1) /* Last Branch Record Stack */ 293 #define CPUID_AMD_8X22_EAX_PMV2 (1 << 0) /* Perfmon v2 */ 294 295 #define CPUID_AMD_8X22_EBX_NPMC_NB(r) bitx32(r, 15, 10) /* # NB PMC */ 296 #define CPUID_AMD_8X22_EBX_LBR_SZ(r) bitx32(r, 9, 4) /* # LBR Stack ents. */ 297 #define CPUID_AMD_8X22_EBX_NPMC_CORE(r) bitx32(r, 3, 0) /* # core PMC */ 298 299 /* 300 * AMD Secure Multi-key Encryption -- 0x8000_00023 301 */ 302 #define CPUID_AMD_8X23_EAX_MEMHMK (1 << 0) /* Secure Host Multi-Key Mem */ 303 304 #define CPUID_AMD_8X23_EBX_MAX_HMK(r) bitx32(r, 15, 0) /* Max HMK IDs */ 305 306 /* 307 * AMD Extended CPU Topology -- 0x8000_0026 308 * 309 * This is AMD's version of extended CPU topology. The topology level is placed 310 * in %ecx and also contains information about the heterogeneity of the CPUs at 311 * the core level. Note, this is similar to, but not the same as Intel's 0x1f. 312 * 313 * The %eax values other than the APIC shift are only available when the type is 314 * a core. The %ebx values other than the number of logical processors are only 315 * available when the type is a core. The core and native model ID values are 316 * processor specific. 317 * 318 * %edx is the entire extended APIC ID of the logical processor we're on. 319 */ 320 #define CPUID_AMD_8X26_EAX_ASYM_TOPO(r) bitx32(r, 31, 31) 321 #define CPUID_AMD_8x26_EAX_HET_CORES(r) bitx32(r, 30, 30) 322 #define CPUID_AMD_8X26_EAX_EFF_AVAIL(r) bitx32(r, 29, 29) 323 #define CPUID_AMD_8X26_EAX_APIC_SHIFT(r) bitx32(r, 4, 0) 324 325 #define CPUID_AMD_8X26_EBX_CORE_TYPE(r) bitx32(r, 31, 28) 326 #define CPUID_AMD_8X26_EBX_MODEL_ID(r) bitx32(r, 27, 24) 327 #define CPUID_AMD_8X26_EBX_PWR_EFF(r) bitx32(r, 23, 16) 328 #define CPUID_AMD_8X26_EBX_NLOG_PROC(r) bitx32(r, 15, 0) 329 330 #define CPUID_AMD_8X26_ECX_TYPE(r) bitx32(r, 15, 8) 331 #define CPUID_AMD_8X26_TYPE_DONE 0 /* Technically reserved */ 332 #define CUPID_AMD_8X26_TYPE_CORE 1 333 #define CUPID_AMD_8X26_TYPE_COMPLEX 2 334 #define CUPID_AMD_8X26_TYPE_DIE 3 335 #define CUPID_AMD_8X26_TYPE_SOCK 4 336 #define CPUID_AMD_8X26_ECX_INPUT(r) bitx32(r, 7, 0) 337 338 /* 339 * Intel now seems to have claimed part of the "extended" function 340 * space that we previously for non-Intel implementors to use. 341 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 342 * is available in long mode i.e. what AMD indicate using bit 0. 343 * On the other hand, everything else is labelled as reserved. 344 */ 345 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 346 347 /* 348 * Intel uses cpuid leaf 6 to cover various thermal and power control 349 * operations. 350 */ 351 #define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */ 352 #define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */ 353 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */ 354 /* bit 3 is reserved */ 355 #define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */ 356 #define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */ 357 #define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */ 358 #define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */ 359 #define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */ 360 #define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */ 361 #define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */ 362 #define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */ 363 /* bit 12 is reserved */ 364 #define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */ 365 #define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */ 366 #define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */ 367 #define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */ 368 #define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */ 369 #define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */ 370 /* bit 19 is reserved */ 371 #define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */ 372 373 #define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf) 374 375 #define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */ 376 /* bits 1-2 are reserved */ 377 #define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */ 378 379 /* 380 * Intel also uses cpuid leaf 7 to have additional instructions and features. 381 * Like some other leaves, but unlike the current ones we care about, it 382 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 383 * with the potential use of additional sub-leaves in the future, we now 384 * specifically label the EBX features with their leaf and sub-leaf. 385 */ 386 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 387 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 388 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 389 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 390 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 391 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 392 #define CPUID_INTC_EBX_7_0_FDP_EXCPN 0x00000040 /* FDP on exception */ 393 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 394 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 395 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 396 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 397 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 398 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 399 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 400 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 401 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 402 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 403 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 404 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 405 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 406 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 407 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 408 /* Bit 22 is reserved */ 409 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 410 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 411 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 412 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 413 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 414 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 415 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 416 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 417 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 418 419 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 420 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 421 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 422 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 423 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 424 425 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 426 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 427 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 428 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 429 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 430 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 431 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 432 #define CPUID_INTC_ECX_7_0_CET_SS 0x00000080 /* CET Shadow Stack */ 433 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 434 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 435 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 436 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 437 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 438 #define CPUID_INTC_ECX_7_0_TME_EN 0x00002000 /* Total Memory Encr. */ 439 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 440 /* bit 15 is reserved */ 441 #define CPUID_INTC_ECX_7_0_LA57 0x00010000 /* 57-bit paging */ 442 /* bits 17-21 are the value of MAWAU */ 443 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 444 #define CPUID_INTC_ECX_7_0_KLSUP 0x00800000 /* Key Locker */ 445 /* bit 24 is reserved */ 446 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 447 /* bit 26 is resrved */ 448 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 449 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 450 #define CPUID_INTC_ECX_7_0_ENQCMD 0x20000000 /* Enqueue Stores */ 451 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 452 #define CPUID_INTC_ECX_7_0_PKS 0x80000000 /* protection keys */ 453 454 /* 455 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 456 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 457 * valid when AVX512 is not. However, the following flags all are only valid 458 * when AVX512 is present. 459 */ 460 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 461 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 462 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 463 464 /* bits 0-1 are reserved */ 465 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 466 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 467 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 468 #define CPUID_INTC_EDX_7_0_UINTR 0x00000020 /* user interrupts */ 469 /* bits 6-7 are reserved */ 470 #define CPUID_INTC_EDX_7_0_AVX512VP2INT 0x00000100 /* VP2INTERSECT */ 471 /* bit 9 is reserved */ 472 #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */ 473 /* bits 11-13 are reserved */ 474 #define CPUID_INTC_EDX_7_0_SERIALIZE 0x00004000 /* Serialize instr */ 475 #define CPUID_INTC_EDX_7_0_HYBRID 0x00008000 /* Hybrid CPU */ 476 #define CPUID_INTC_EDX_7_0_TSXLDTRK 0x00010000 /* TSX load track */ 477 /* bit 17 is reserved */ 478 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 479 /* bit 19 is reserved */ 480 #define CPUID_INTC_EDX_7_0_CET_IBT 0x00100000 /* CET ind. branch */ 481 /* bit 21 is reserved */ 482 #define CPUID_INTC_EDX_7_0_AMX_BF16 0x00400000 /* Tile F16 */ 483 #define CPUID_INTC_EDX_7_0_AVX512FP16 0x00800000 /* AVX512 FP16 */ 484 #define CPUID_INTC_EDX_7_0_AMX_TILE 0x01000000 /* Tile arch */ 485 #define CPUID_INTC_EDX_7_0_AMX_INT8 0x02000000 /* Tile INT8 */ 486 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 487 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 488 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 489 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 490 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 491 492 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 493 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS | \ 494 CPUID_INTC_EDX_7_0_AVX512VP2INT | CPUID_INTC_EDX_7_0_AVX512FP16) 495 496 /* bits 0-3 are reserved */ 497 #define CPUID_INTC_EAX_7_1_AVXVNNI 0x00000010 /* VEX VNNI */ 498 #define CPUID_INTC_EAX_7_1_AVX512_BF16 0x00000020 /* AVX512 BF16 */ 499 /* bits 6-9 are reserved */ 500 #define CPUID_INTC_EAX_7_1_ZL_MOVSB 0x00000400 /* zero-length MOVSB */ 501 #define CPUID_INTC_EAX_7_1_FS_STOSB 0x00000800 /* fast short STOSB */ 502 #define CPUID_INTC_EAX_7_1_FS_CMPSB 0x00001000 /* fast CMPSB, SCASB */ 503 /* bits 13-21 are reserved */ 504 #define CPUID_INTC_EAX_7_1_HRESET 0x00400000 /* History Reset leaf */ 505 /* bits 23-25 are reserved */ 506 #define CPUID_INTC_EAX_7_1_LAM 0x02000000 /* Linear addr mask */ 507 /* bits 27-31 are reserved */ 508 509 /* 510 * Intel also uses cpuid leaf 0xd to report additional instructions and features 511 * when the sub-leaf in %ecx == 1. We label these using the same convention as 512 * with leaf 7. 513 */ 514 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 515 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 516 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 517 518 #define REG_PAT 0x277 519 #define REG_TSC 0x10 /* timestamp counter */ 520 #define REG_APIC_BASE_MSR 0x1b 521 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 522 523 #if !defined(__xpv) 524 /* 525 * AMD C1E 526 */ 527 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 528 #define AMD_ACTONCMPHALT_SHIFT 27 529 #define AMD_ACTONCMPHALT_MASK 3 530 #endif 531 532 #define MSR_DEBUGCTL 0x1d9 533 534 #define DEBUGCTL_LBR 0x01 535 #define DEBUGCTL_BTF 0x02 536 537 /* Intel P6, AMD */ 538 #define MSR_LBR_FROM 0x1db 539 #define MSR_LBR_TO 0x1dc 540 #define MSR_LEX_FROM 0x1dd 541 #define MSR_LEX_TO 0x1de 542 543 /* Intel P4 (pre-Prescott, non P4 M) */ 544 #define MSR_P4_LBSTK_TOS 0x1da 545 #define MSR_P4_LBSTK_0 0x1db 546 #define MSR_P4_LBSTK_1 0x1dc 547 #define MSR_P4_LBSTK_2 0x1dd 548 #define MSR_P4_LBSTK_3 0x1de 549 550 /* Intel Pentium M */ 551 #define MSR_P6M_LBSTK_TOS 0x1c9 552 #define MSR_P6M_LBSTK_0 0x040 553 #define MSR_P6M_LBSTK_1 0x041 554 #define MSR_P6M_LBSTK_2 0x042 555 #define MSR_P6M_LBSTK_3 0x043 556 #define MSR_P6M_LBSTK_4 0x044 557 #define MSR_P6M_LBSTK_5 0x045 558 #define MSR_P6M_LBSTK_6 0x046 559 #define MSR_P6M_LBSTK_7 0x047 560 561 /* Intel P4 (Prescott) */ 562 #define MSR_PRP4_LBSTK_TOS 0x1da 563 #define MSR_PRP4_LBSTK_FROM_0 0x680 564 #define MSR_PRP4_LBSTK_FROM_1 0x681 565 #define MSR_PRP4_LBSTK_FROM_2 0x682 566 #define MSR_PRP4_LBSTK_FROM_3 0x683 567 #define MSR_PRP4_LBSTK_FROM_4 0x684 568 #define MSR_PRP4_LBSTK_FROM_5 0x685 569 #define MSR_PRP4_LBSTK_FROM_6 0x686 570 #define MSR_PRP4_LBSTK_FROM_7 0x687 571 #define MSR_PRP4_LBSTK_FROM_8 0x688 572 #define MSR_PRP4_LBSTK_FROM_9 0x689 573 #define MSR_PRP4_LBSTK_FROM_10 0x68a 574 #define MSR_PRP4_LBSTK_FROM_11 0x68b 575 #define MSR_PRP4_LBSTK_FROM_12 0x68c 576 #define MSR_PRP4_LBSTK_FROM_13 0x68d 577 #define MSR_PRP4_LBSTK_FROM_14 0x68e 578 #define MSR_PRP4_LBSTK_FROM_15 0x68f 579 #define MSR_PRP4_LBSTK_TO_0 0x6c0 580 #define MSR_PRP4_LBSTK_TO_1 0x6c1 581 #define MSR_PRP4_LBSTK_TO_2 0x6c2 582 #define MSR_PRP4_LBSTK_TO_3 0x6c3 583 #define MSR_PRP4_LBSTK_TO_4 0x6c4 584 #define MSR_PRP4_LBSTK_TO_5 0x6c5 585 #define MSR_PRP4_LBSTK_TO_6 0x6c6 586 #define MSR_PRP4_LBSTK_TO_7 0x6c7 587 #define MSR_PRP4_LBSTK_TO_8 0x6c8 588 #define MSR_PRP4_LBSTK_TO_9 0x6c9 589 #define MSR_PRP4_LBSTK_TO_10 0x6ca 590 #define MSR_PRP4_LBSTK_TO_11 0x6cb 591 #define MSR_PRP4_LBSTK_TO_12 0x6cc 592 #define MSR_PRP4_LBSTK_TO_13 0x6cd 593 #define MSR_PRP4_LBSTK_TO_14 0x6ce 594 #define MSR_PRP4_LBSTK_TO_15 0x6cf 595 596 /* 597 * PPIN definitions for Intel and AMD. Unfortunately, Intel and AMD use 598 * different MSRS for this and different MSRS to control whether or not it 599 * should be readable. 600 */ 601 #define MSR_PPIN_CTL_INTC 0x04e 602 #define MSR_PPIN_INTC 0x04f 603 #define MSR_PLATFORM_INFO 0x0ce 604 #define MSR_PLATFORM_INFO_PPIN (1 << 23) 605 606 #define MSR_PPIN_CTL_AMD 0xC00102F0 607 #define MSR_PPIN_AMD 0xC00102F1 608 609 /* 610 * These values are currently the same between Intel and AMD. 611 */ 612 #define MSR_PPIN_CTL_MASK 0x03 613 #define MSR_PPIN_CTL_DISABLED 0x00 614 #define MSR_PPIN_CTL_LOCKED 0x01 615 #define MSR_PPIN_CTL_ENABLED 0x02 616 617 /* 618 * Intel IA32_ARCH_CAPABILITIES MSR. 619 */ 620 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 621 #define IA32_ARCH_CAP_RDCL_NO 0x0001 622 #define IA32_ARCH_CAP_IBRS_ALL 0x0002 623 #define IA32_ARCH_CAP_RSBA 0x0004 624 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 625 #define IA32_ARCH_CAP_SSB_NO 0x0010 626 #define IA32_ARCH_CAP_MDS_NO 0x0020 627 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x0040 628 #define IA32_ARCH_CAP_TSX_CTRL 0x0080 629 #define IA32_ARCH_CAP_TAA_NO 0x0100 630 631 /* 632 * Intel Speculation related MSRs 633 */ 634 #define MSR_IA32_SPEC_CTRL 0x48 635 #define IA32_SPEC_CTRL_IBRS 0x01 636 #define IA32_SPEC_CTRL_STIBP 0x02 637 #define IA32_SPEC_CTRL_SSBD 0x04 638 639 #define MSR_IA32_PRED_CMD 0x49 640 #define IA32_PRED_CMD_IBPB 0x01 641 642 #define MSR_IA32_FLUSH_CMD 0x10b 643 #define IA32_FLUSH_CMD_L1D 0x01 644 645 /* 646 * Intel VMX related MSRs 647 */ 648 #define MSR_IA32_FEAT_CTRL 0x03a 649 #define IA32_FEAT_CTRL_LOCK 0x1 650 #define IA32_FEAT_CTRL_SMX_EN 0x2 651 #define IA32_FEAT_CTRL_VMX_EN 0x4 652 653 #define MSR_IA32_VMX_BASIC 0x480 654 #define IA32_VMX_BASIC_INS_OUTS (1UL << 54) 655 #define IA32_VMX_BASIC_TRUE_CTRLS (1UL << 55) 656 657 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 658 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 659 #define IA32_VMX_PROCBASED_2ND_CTLS (1UL << 31) 660 661 #define MSR_IA32_VMX_PROCBASED2_CTLS 0x48b 662 #define IA32_VMX_PROCBASED2_EPT (1UL << 1) 663 #define IA32_VMX_PROCBASED2_VPID (1UL << 5) 664 665 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 666 #define IA32_VMX_EPT_VPID_EXEC_ONLY (1UL << 0) 667 #define IA32_VMX_EPT_VPID_PWL4 (1UL << 6) 668 #define IA32_VMX_EPT_VPID_TYPE_UC (1UL << 8) 669 #define IA32_VMX_EPT_VPID_TYPE_WB (1UL << 14) 670 #define IA32_VMX_EPT_VPID_MAP_2M (1UL << 16) 671 #define IA32_VMX_EPT_VPID_MAP_1G (1UL << 17) 672 #define IA32_VMX_EPT_VPID_HW_AD (1UL << 21) 673 #define IA32_VMX_EPT_VPID_INVEPT (1UL << 20) 674 #define IA32_VMX_EPT_VPID_INVEPT_SINGLE (1UL << 25) 675 #define IA32_VMX_EPT_VPID_INVEPT_ALL (1UL << 26) 676 #define IA32_VMX_EPT_VPID_INVVPID (1UL << 32) 677 #define IA32_VMX_EPT_VPID_INVVPID_ADDR (1UL << 40) 678 #define IA32_VMX_EPT_VPID_INVVPID_SINGLE (1UL << 41) 679 #define IA32_VMX_EPT_VPID_INVVPID_ALL (1UL << 42) 680 #define IA32_VMX_EPT_VPID_INVVPID_RETAIN (1UL << 43) 681 682 /* 683 * Intel TSX Control MSRs 684 */ 685 #define MSR_IA32_TSX_CTRL 0x122 686 #define IA32_TSX_CTRL_RTM_DISABLE 0x01 687 #define IA32_TSX_CTRL_CPUID_CLEAR 0x02 688 689 /* 690 * Intel Thermal MSRs 691 */ 692 #define MSR_IA32_THERM_INTERRUPT 0x19b 693 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001 694 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002 695 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004 696 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008 697 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010 698 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 699 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000 700 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 701 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000 702 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000 703 704 #define MSR_IA32_THERM_STATUS 0x19c 705 #define IA32_THERM_STATUS_STATUS 0x00000001 706 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002 707 #define IA32_THERM_STATUS_PROCHOT 0x00000004 708 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008 709 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010 710 #define IA32_THERM_STATUS_CRIT_LOG 0x00000020 711 #define IA32_THERM_STATUS_TR1_STATUS 0x00000040 712 #define IA32_THERM_STATUS_TR1_LOG 0x00000080 713 #define IA32_THERM_STATUS_TR2_STATUS 0x00000100 714 #define IA32_THERM_STATUS_TR2_LOG 0x00000200 715 #define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400 716 #define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800 717 #define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000 718 #define IA32_THERM_STATUS_CURRENT_LOG 0x00002000 719 #define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000 720 #define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000 721 #define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 722 #define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f) 723 #define IA32_THERM_STATUS_READ_VALID 0x80000000 724 725 #define MSR_TEMPERATURE_TARGET 0x1a2 726 #define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff) 727 /* 728 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list 729 * of which models have support for which bits. 730 */ 731 #define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f) 732 733 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 734 #define IA32_PKG_THERM_STATUS_STATUS 0x00000001 735 #define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002 736 #define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004 737 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008 738 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010 739 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020 740 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040 741 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080 742 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100 743 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200 744 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 745 746 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 747 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001 748 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002 749 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004 750 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010 751 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 752 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000 753 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 754 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 755 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 756 757 /* 758 * AMD TOM and TOM2 MSRs. These control the split between DRAM and MMIO below 759 * and above 4 GiB respectively. These have existed since family 0xf. 760 */ 761 #define MSR_AMD_TOM 0xc001001a 762 #define MSR_AMD_TOM_MASK(x) ((x) & 0xffffff800000) 763 #define MSR_AMD_TOM2 0xc001001d 764 #define MSR_AMD_TOM2_MASK(x) ((x) & 0xffffff800000) 765 766 767 #define MCI_CTL_VALUE 0xffffffff 768 769 #define MTRR_TYPE_UC 0 770 #define MTRR_TYPE_WC 1 771 #define MTRR_TYPE_WT 4 772 #define MTRR_TYPE_WP 5 773 #define MTRR_TYPE_WB 6 774 #define MTRR_TYPE_UC_ 7 775 776 /* 777 * For Solaris we set up the page attritubute table in the following way: 778 * PAT0 Write-Back 779 * PAT1 Write-Through 780 * PAT2 Unchacheable- 781 * PAT3 Uncacheable 782 * PAT4 Write-Back 783 * PAT5 Write-Through 784 * PAT6 Write-Combine 785 * PAT7 Uncacheable 786 * The only difference from h/w default is entry 6. 787 */ 788 #define PAT_DEFAULT_ATTRIBUTE \ 789 ((uint64_t)MTRR_TYPE_WB | \ 790 ((uint64_t)MTRR_TYPE_WT << 8) | \ 791 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 792 ((uint64_t)MTRR_TYPE_UC << 24) | \ 793 ((uint64_t)MTRR_TYPE_WB << 32) | \ 794 ((uint64_t)MTRR_TYPE_WT << 40) | \ 795 ((uint64_t)MTRR_TYPE_WC << 48) | \ 796 ((uint64_t)MTRR_TYPE_UC << 56)) 797 798 #define X86FSET_LARGEPAGE 0 799 #define X86FSET_TSC 1 800 #define X86FSET_MSR 2 801 #define X86FSET_MTRR 3 802 #define X86FSET_PGE 4 803 #define X86FSET_DE 5 804 #define X86FSET_CMOV 6 805 #define X86FSET_MMX 7 806 #define X86FSET_MCA 8 807 #define X86FSET_PAE 9 808 #define X86FSET_CX8 10 809 #define X86FSET_PAT 11 810 #define X86FSET_SEP 12 811 #define X86FSET_SSE 13 812 #define X86FSET_SSE2 14 813 #define X86FSET_HTT 15 814 #define X86FSET_ASYSC 16 815 #define X86FSET_NX 17 816 #define X86FSET_SSE3 18 817 #define X86FSET_CX16 19 818 #define X86FSET_CMP 20 819 #define X86FSET_TSCP 21 820 #define X86FSET_MWAIT 22 821 #define X86FSET_SSE4A 23 822 #define X86FSET_CPUID 24 823 #define X86FSET_SSSE3 25 824 #define X86FSET_SSE4_1 26 825 #define X86FSET_SSE4_2 27 826 #define X86FSET_1GPG 28 827 #define X86FSET_CLFSH 29 828 #define X86FSET_64 30 829 #define X86FSET_AES 31 830 #define X86FSET_PCLMULQDQ 32 831 #define X86FSET_XSAVE 33 832 #define X86FSET_AVX 34 833 #define X86FSET_VMX 35 834 #define X86FSET_SVM 36 835 #define X86FSET_TOPOEXT 37 836 #define X86FSET_F16C 38 837 #define X86FSET_RDRAND 39 838 #define X86FSET_X2APIC 40 839 #define X86FSET_AVX2 41 840 #define X86FSET_BMI1 42 841 #define X86FSET_BMI2 43 842 #define X86FSET_FMA 44 843 #define X86FSET_SMEP 45 844 #define X86FSET_SMAP 46 845 #define X86FSET_ADX 47 846 #define X86FSET_RDSEED 48 847 #define X86FSET_MPX 49 848 #define X86FSET_AVX512F 50 849 #define X86FSET_AVX512DQ 51 850 #define X86FSET_AVX512PF 52 851 #define X86FSET_AVX512ER 53 852 #define X86FSET_AVX512CD 54 853 #define X86FSET_AVX512BW 55 854 #define X86FSET_AVX512VL 56 855 #define X86FSET_AVX512FMA 57 856 #define X86FSET_AVX512VBMI 58 857 #define X86FSET_AVX512VPOPCDQ 59 858 #define X86FSET_AVX512NNIW 60 859 #define X86FSET_AVX512FMAPS 61 860 #define X86FSET_XSAVEOPT 62 861 #define X86FSET_XSAVEC 63 862 #define X86FSET_XSAVES 64 863 #define X86FSET_SHA 65 864 #define X86FSET_UMIP 66 865 #define X86FSET_PKU 67 866 #define X86FSET_OSPKE 68 867 #define X86FSET_PCID 69 868 #define X86FSET_INVPCID 70 869 #define X86FSET_IBRS 71 870 #define X86FSET_IBPB 72 871 #define X86FSET_STIBP 73 872 #define X86FSET_SSBD 74 873 #define X86FSET_SSBD_VIRT 75 874 #define X86FSET_RDCL_NO 76 875 #define X86FSET_IBRS_ALL 77 876 #define X86FSET_RSBA 78 877 #define X86FSET_SSB_NO 79 878 #define X86FSET_STIBP_ALL 80 879 #define X86FSET_FLUSH_CMD 81 880 #define X86FSET_L1D_VM_NO 82 881 #define X86FSET_FSGSBASE 83 882 #define X86FSET_CLFLUSHOPT 84 883 #define X86FSET_CLWB 85 884 #define X86FSET_MONITORX 86 885 #define X86FSET_CLZERO 87 886 #define X86FSET_XOP 88 887 #define X86FSET_FMA4 89 888 #define X86FSET_TBM 90 889 #define X86FSET_AVX512VNNI 91 890 #define X86FSET_AMD_PCEC 92 891 #define X86FSET_MD_CLEAR 93 892 #define X86FSET_MDS_NO 94 893 #define X86FSET_CORE_THERMAL 95 894 #define X86FSET_PKG_THERMAL 96 895 #define X86FSET_TSX_CTRL 97 896 #define X86FSET_TAA_NO 98 897 #define X86FSET_PPIN 99 898 #define X86FSET_VAES 100 899 #define X86FSET_VPCLMULQDQ 101 900 #define X86FSET_LFENCE_SER 102 901 #define X86FSET_GFNI 103 902 #define X86FSET_AVX512_VP2INT 104 903 #define X86FSET_AVX512_BITALG 105 904 #define X86FSET_AVX512_VBMI2 106 905 #define X86FSET_AVX512_BF16 107 906 #define X86FSET_AUTO_IBRS 108 907 908 /* 909 * Intel Deep C-State invariant TSC in leaf 0x80000007. 910 */ 911 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 912 913 /* 914 * Intel TSC deadline timer 915 */ 916 #define CPUID_DEADLINE_TSC (1 << 24) 917 918 /* 919 * x86_type is a legacy concept; this is supplanted 920 * for most purposes by x86_featureset; modern CPUs 921 * should be X86_TYPE_OTHER 922 */ 923 #define X86_TYPE_OTHER 0 924 #define X86_TYPE_486 1 925 #define X86_TYPE_P5 2 926 #define X86_TYPE_P6 3 927 #define X86_TYPE_CYRIX_486 4 928 #define X86_TYPE_CYRIX_6x86L 5 929 #define X86_TYPE_CYRIX_6x86 6 930 #define X86_TYPE_CYRIX_GXm 7 931 #define X86_TYPE_CYRIX_6x86MX 8 932 #define X86_TYPE_CYRIX_MediaGX 9 933 #define X86_TYPE_CYRIX_MII 10 934 #define X86_TYPE_VIA_CYRIX_III 11 935 #define X86_TYPE_P4 12 936 937 /* 938 * x86_vendor allows us to select between 939 * implementation features and helps guide 940 * the interpretation of the cpuid instruction. 941 */ 942 #define X86_VENDOR_Intel 0 943 #define X86_VENDORSTR_Intel "GenuineIntel" 944 945 #define X86_VENDOR_IntelClone 1 946 947 #define X86_VENDOR_AMD 2 948 #define X86_VENDORSTR_AMD "AuthenticAMD" 949 950 #define X86_VENDOR_Cyrix 3 951 #define X86_VENDORSTR_CYRIX "CyrixInstead" 952 953 #define X86_VENDOR_UMC 4 954 #define X86_VENDORSTR_UMC "UMC UMC UMC " 955 956 #define X86_VENDOR_NexGen 5 957 #define X86_VENDORSTR_NexGen "NexGenDriven" 958 959 #define X86_VENDOR_Centaur 6 960 #define X86_VENDORSTR_Centaur "CentaurHauls" 961 962 #define X86_VENDOR_Rise 7 963 #define X86_VENDORSTR_Rise "RiseRiseRise" 964 965 #define X86_VENDOR_SiS 8 966 #define X86_VENDORSTR_SiS "SiS SiS SiS " 967 968 #define X86_VENDOR_TM 9 969 #define X86_VENDORSTR_TM "GenuineTMx86" 970 971 #define X86_VENDOR_NSC 10 972 #define X86_VENDORSTR_NSC "Geode by NSC" 973 974 #define X86_VENDOR_HYGON 11 975 #define X86_VENDORSTR_HYGON "HygonGenuine" 976 977 /* 978 * Vendor string max len + \0 979 */ 980 #define X86_VENDOR_STRLEN 13 981 982 /* 983 * For lookups and matching functions only; not an actual vendor. 984 */ 985 #define _X86_VENDOR_MATCH_ALL 0xff 986 987 /* 988 * See the big theory statement at the top of cpuid.c for information about how 989 * processor families and microarchitecture families relate to cpuid families, 990 * models, and steppings. 991 */ 992 993 #define _X86_CHIPREV_VENDOR_SHIFT 24 994 #define _X86_CHIPREV_FAMILY_SHIFT 16 995 996 #define _X86_CHIPREV_VENDOR(x) \ 997 bitx32((uint32_t)(x), 31, _X86_CHIPREV_VENDOR_SHIFT) 998 999 #define _X86_CHIPREV_FAMILY(x) \ 1000 bitx32((uint32_t)(x), 23, _X86_CHIPREV_FAMILY_SHIFT) 1001 1002 #define _X86_CHIPREV_REV(x) \ 1003 bitx32((uint32_t)(x), 15, 0) 1004 1005 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 1006 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 1007 (uint32_t)(family) << _X86_CHIPREV_FAMILY_SHIFT | (uint32_t)(rev)) 1008 1009 /* 1010 * The legacy families here are a little bit unfortunate. Part of this is that 1011 * the way AMD used the cpuid family/model/stepping changed somewhat over time, 1012 * but the more immediate reason it's this way is more that the way we use 1013 * chiprev/processor family changed with it. The ancient amd_opteron and mc-amd 1014 * drivers used the chiprevs that were based on cpuid family, mainly 0xf and 1015 * 0x10. amdzen_umc wants the processor family, in part because AMD's 1016 * overloading of the cpuid family has made it effectively useless for 1017 * discerning anything about the processor. That also tied into the way 1018 * amd_revmap was previously organised in cpuid_subr.c: up to family 0x14 1019 * everything was just "rev A", "rev B", etc.; afterward we started using the 1020 * new shorthand, again tied to how AMD was presenting this information. 1021 * Because there are other consumers of the processor family, it no longer made 1022 * sense for amdzen to derive the processor family from the cpuid family/model 1023 * given that we have this collection of definitions already and code in 1024 * cpuid_subr.c to make use of them. The result is this unified approach that 1025 * tries to keep old consumers happy while allowing new ones to get the degree 1026 * of detail they need and expect. That required bending things a bit to make 1027 * them fit, though critically as long as AMD keep on their current path and all 1028 * new consumers look like the ones we are adding these days, we will be able to 1029 * continue making new additions that will match all the recent ones and the way 1030 * AMD are currently using families and models. There is absolutely no reason 1031 * we couldn't go back and dig through all the legacy parts and break them down 1032 * the same way, then change the old MC and CPU drivers to match, but I didn't 1033 * feel like doing a lot of work for processors that it's unlikely anyone is 1034 * still using and even more unlikely anyone will introduce new code to support. 1035 * My compromise was to flesh things out starting where we already had more 1036 * detail even if nothing was consuming it programmatically: at 0x15. Before 1037 * that, processor family and cpuid family were effectively the same, because 1038 * that's what those old consumers expect. 1039 */ 1040 1041 #ifndef _ASM 1042 typedef enum x86_processor_family { 1043 X86_PF_UNKNOWN, 1044 X86_PF_AMD_LEGACY_F = 0xf, 1045 X86_PF_AMD_LEGACY_10 = 0x10, 1046 X86_PF_AMD_LEGACY_11 = 0x11, 1047 X86_PF_AMD_LEGACY_12 = 0x12, 1048 X86_PF_AMD_LEGACY_14 = 0x14, 1049 X86_PF_AMD_OROCHI, 1050 X86_PF_AMD_TRINITY, 1051 X86_PF_AMD_KAVERI, 1052 X86_PF_AMD_CARRIZO, 1053 X86_PF_AMD_STONEY_RIDGE, 1054 X86_PF_AMD_KABINI, 1055 X86_PF_AMD_MULLINS, 1056 X86_PF_AMD_NAPLES, 1057 X86_PF_AMD_PINNACLE_RIDGE, 1058 X86_PF_AMD_RAVEN_RIDGE, 1059 X86_PF_AMD_PICASSO, 1060 X86_PF_AMD_DALI, 1061 X86_PF_AMD_ROME, 1062 X86_PF_AMD_RENOIR, 1063 X86_PF_AMD_MATISSE, 1064 X86_PF_AMD_VAN_GOGH, 1065 X86_PF_AMD_MENDOCINO, 1066 X86_PF_HYGON_DHYANA, 1067 X86_PF_AMD_MILAN, 1068 X86_PF_AMD_GENOA, 1069 X86_PF_AMD_VERMEER, 1070 X86_PF_AMD_REMBRANDT, 1071 X86_PF_AMD_CEZANNE, 1072 X86_PF_AMD_RAPHAEL, 1073 X86_PF_AMD_PHOENIX, 1074 X86_PF_AMD_BERGAMO, 1075 1076 X86_PF_ANY = 0xff 1077 } x86_processor_family_t; 1078 1079 #define _DECL_CHIPREV(_v, _f, _revn, _revb) \ 1080 X86_CHIPREV_ ## _v ## _ ## _f ## _ ## _revn = \ 1081 _X86_CHIPREV_MKREV(X86_VENDOR_ ## _v, X86_PF_ ## _v ## _ ## _f, _revb) 1082 1083 #define _X86_CHIPREV_REV_MATCH_ALL 0xffff 1084 1085 typedef enum x86_chiprev { 1086 X86_CHIPREV_UNKNOWN, 1087 _DECL_CHIPREV(AMD, LEGACY_F, REV_B, 0x0001), 1088 /* 1089 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 1090 * sufficiently different that we will distinguish them; in all other 1091 * case we will identify the major revision. 1092 */ 1093 _DECL_CHIPREV(AMD, LEGACY_F, REV_C0, 0x0002), 1094 _DECL_CHIPREV(AMD, LEGACY_F, REV_CG, 0x0004), 1095 _DECL_CHIPREV(AMD, LEGACY_F, REV_D, 0x0008), 1096 _DECL_CHIPREV(AMD, LEGACY_F, REV_E, 0x0010), 1097 _DECL_CHIPREV(AMD, LEGACY_F, REV_F, 0x0020), 1098 _DECL_CHIPREV(AMD, LEGACY_F, REV_G, 0x0040), 1099 _DECL_CHIPREV(AMD, LEGACY_F, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1100 1101 _DECL_CHIPREV(AMD, LEGACY_10, UNKNOWN, 0x0001), 1102 _DECL_CHIPREV(AMD, LEGACY_10, REV_A, 0x0002), 1103 _DECL_CHIPREV(AMD, LEGACY_10, REV_B, 0x0004), 1104 _DECL_CHIPREV(AMD, LEGACY_10, REV_C2, 0x0008), 1105 _DECL_CHIPREV(AMD, LEGACY_10, REV_C3, 0x0010), 1106 _DECL_CHIPREV(AMD, LEGACY_10, REV_D0, 0x0020), 1107 _DECL_CHIPREV(AMD, LEGACY_10, REV_D1, 0x0040), 1108 _DECL_CHIPREV(AMD, LEGACY_10, REV_E, 0x0080), 1109 _DECL_CHIPREV(AMD, LEGACY_10, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1110 1111 _DECL_CHIPREV(AMD, LEGACY_11, UNKNOWN, 0x0001), 1112 _DECL_CHIPREV(AMD, LEGACY_11, REV_B, 0x0002), 1113 _DECL_CHIPREV(AMD, LEGACY_11, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1114 1115 _DECL_CHIPREV(AMD, LEGACY_12, UNKNOWN, 0x0001), 1116 _DECL_CHIPREV(AMD, LEGACY_12, REV_B, 0x0002), 1117 _DECL_CHIPREV(AMD, LEGACY_12, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1118 1119 _DECL_CHIPREV(AMD, LEGACY_14, UNKNOWN, 0x0001), 1120 _DECL_CHIPREV(AMD, LEGACY_14, REV_B, 0x0002), 1121 _DECL_CHIPREV(AMD, LEGACY_14, REV_C, 0x0004), 1122 _DECL_CHIPREV(AMD, LEGACY_14, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1123 1124 _DECL_CHIPREV(AMD, OROCHI, UNKNOWN, 0x0001), 1125 _DECL_CHIPREV(AMD, OROCHI, REV_B2, 0x0002), 1126 _DECL_CHIPREV(AMD, OROCHI, REV_C0, 0x0004), 1127 _DECL_CHIPREV(AMD, OROCHI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1128 1129 _DECL_CHIPREV(AMD, TRINITY, UNKNOWN, 0x0001), 1130 _DECL_CHIPREV(AMD, TRINITY, REV_A1, 0x0002), 1131 _DECL_CHIPREV(AMD, TRINITY, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1132 1133 _DECL_CHIPREV(AMD, KAVERI, UNKNOWN, 0x0001), 1134 _DECL_CHIPREV(AMD, KAVERI, REV_A1, 0x0002), 1135 _DECL_CHIPREV(AMD, KAVERI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1136 1137 _DECL_CHIPREV(AMD, CARRIZO, UNKNOWN, 0x0001), 1138 _DECL_CHIPREV(AMD, CARRIZO, REV_A0, 0x0002), 1139 _DECL_CHIPREV(AMD, CARRIZO, REV_A1, 0x0004), 1140 _DECL_CHIPREV(AMD, CARRIZO, REV_DDR4, 0x0008), 1141 _DECL_CHIPREV(AMD, CARRIZO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1142 1143 _DECL_CHIPREV(AMD, STONEY_RIDGE, UNKNOWN, 0x0001), 1144 _DECL_CHIPREV(AMD, STONEY_RIDGE, REV_A0, 0x0002), 1145 _DECL_CHIPREV(AMD, STONEY_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1146 1147 _DECL_CHIPREV(AMD, KABINI, UNKNOWN, 0x0001), 1148 _DECL_CHIPREV(AMD, KABINI, A1, 0x0002), 1149 _DECL_CHIPREV(AMD, KABINI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1150 1151 _DECL_CHIPREV(AMD, MULLINS, UNKNOWN, 0x0001), 1152 _DECL_CHIPREV(AMD, MULLINS, A1, 0x0002), 1153 _DECL_CHIPREV(AMD, MULLINS, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1154 1155 _DECL_CHIPREV(AMD, NAPLES, UNKNOWN, 0x0001), 1156 _DECL_CHIPREV(AMD, NAPLES, A0, 0x0002), 1157 _DECL_CHIPREV(AMD, NAPLES, B1, 0x0004), 1158 _DECL_CHIPREV(AMD, NAPLES, B2, 0x0008), 1159 _DECL_CHIPREV(AMD, NAPLES, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1160 1161 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, UNKNOWN, 0x0001), 1162 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, B2, 0x0002), 1163 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1164 1165 _DECL_CHIPREV(AMD, RAVEN_RIDGE, UNKNOWN, 0x0001), 1166 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B0, 0x0002), 1167 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B1, 0x0004), 1168 _DECL_CHIPREV(AMD, RAVEN_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1169 1170 _DECL_CHIPREV(AMD, PICASSO, UNKNOWN, 0x0001), 1171 _DECL_CHIPREV(AMD, PICASSO, B1, 0x0002), 1172 _DECL_CHIPREV(AMD, PICASSO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1173 1174 _DECL_CHIPREV(AMD, DALI, UNKNOWN, 0x0001), 1175 _DECL_CHIPREV(AMD, DALI, A1, 0x0002), 1176 _DECL_CHIPREV(AMD, DALI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1177 1178 _DECL_CHIPREV(AMD, ROME, UNKNOWN, 0x0001), 1179 _DECL_CHIPREV(AMD, ROME, A0, 0x0002), 1180 _DECL_CHIPREV(AMD, ROME, B0, 0x0004), 1181 _DECL_CHIPREV(AMD, ROME, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1182 1183 _DECL_CHIPREV(AMD, RENOIR, UNKNOWN, 0x0001), 1184 _DECL_CHIPREV(AMD, RENOIR, A1, 0x0002), 1185 _DECL_CHIPREV(AMD, RENOIR, LCN_A1, 0x0004), 1186 _DECL_CHIPREV(AMD, RENOIR, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1187 1188 _DECL_CHIPREV(AMD, MATISSE, UNKNOWN, 0x0001), 1189 _DECL_CHIPREV(AMD, MATISSE, B0, 0x0002), 1190 _DECL_CHIPREV(AMD, MATISSE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1191 1192 _DECL_CHIPREV(AMD, VAN_GOGH, UNKNOWN, 0x0001), 1193 _DECL_CHIPREV(AMD, VAN_GOGH, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1194 1195 _DECL_CHIPREV(AMD, MENDOCINO, UNKNOWN, 0x0001), 1196 _DECL_CHIPREV(AMD, MENDOCINO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1197 1198 _DECL_CHIPREV(HYGON, DHYANA, UNKNOWN, 0x0001), 1199 _DECL_CHIPREV(HYGON, DHYANA, A1, 0x0002), 1200 _DECL_CHIPREV(HYGON, DHYANA, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1201 1202 _DECL_CHIPREV(AMD, MILAN, UNKNOWN, 0x0001), 1203 _DECL_CHIPREV(AMD, MILAN, A0, 0x0002), 1204 _DECL_CHIPREV(AMD, MILAN, B0, 0x0004), 1205 _DECL_CHIPREV(AMD, MILAN, B1, 0x0008), 1206 _DECL_CHIPREV(AMD, MILAN, B2, 0x0010), 1207 _DECL_CHIPREV(AMD, MILAN, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1208 1209 _DECL_CHIPREV(AMD, GENOA, UNKNOWN, 0x0001), 1210 _DECL_CHIPREV(AMD, GENOA, A0, 0x0002), 1211 _DECL_CHIPREV(AMD, GENOA, A1, 0x0004), 1212 _DECL_CHIPREV(AMD, GENOA, B0, 0x0008), 1213 _DECL_CHIPREV(AMD, GENOA, B1, 0x0010), 1214 _DECL_CHIPREV(AMD, GENOA, B2, 0x0020), 1215 _DECL_CHIPREV(AMD, GENOA, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1216 1217 _DECL_CHIPREV(AMD, VERMEER, UNKNOWN, 0x0001), 1218 _DECL_CHIPREV(AMD, VERMEER, A0, 0x0002), 1219 _DECL_CHIPREV(AMD, VERMEER, B0, 0x0004), 1220 _DECL_CHIPREV(AMD, VERMEER, B2, 0x0008), /* No B1 */ 1221 _DECL_CHIPREV(AMD, VERMEER, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1222 1223 _DECL_CHIPREV(AMD, REMBRANDT, UNKNOWN, 0x0001), 1224 _DECL_CHIPREV(AMD, REMBRANDT, A0, 0x0002), 1225 _DECL_CHIPREV(AMD, REMBRANDT, B0, 0x0004), 1226 _DECL_CHIPREV(AMD, REMBRANDT, B1, 0x0008), 1227 _DECL_CHIPREV(AMD, REMBRANDT, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1228 1229 _DECL_CHIPREV(AMD, CEZANNE, UNKNOWN, 0x0001), 1230 _DECL_CHIPREV(AMD, CEZANNE, A0, 0x0002), 1231 _DECL_CHIPREV(AMD, CEZANNE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1232 1233 _DECL_CHIPREV(AMD, RAPHAEL, UNKNOWN, 0x0001), 1234 _DECL_CHIPREV(AMD, RAPHAEL, B2, 0x0002), 1235 _DECL_CHIPREV(AMD, RAPHAEL, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1236 1237 _DECL_CHIPREV(AMD, PHOENIX, UNKNOWN, 0x0001), 1238 _DECL_CHIPREV(AMD, PHOENIX, A0, 0x0002), 1239 _DECL_CHIPREV(AMD, PHOENIX, A1, 0x0004), 1240 _DECL_CHIPREV(AMD, PHOENIX, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1241 1242 _DECL_CHIPREV(AMD, BERGAMO, UNKNOWN, 0x0001), 1243 _DECL_CHIPREV(AMD, BERGAMO, A0, 0x0002), 1244 _DECL_CHIPREV(AMD, BERGAMO, A1, 0x0004), 1245 _DECL_CHIPREV(AMD, BERGAMO, A2, 0x0008), 1246 _DECL_CHIPREV(AMD, BERGAMO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1247 1248 /* Keep at the end */ 1249 X86_CHIPREV_ANY = _X86_CHIPREV_MKREV(_X86_VENDOR_MATCH_ALL, X86_PF_ANY, 1250 _X86_CHIPREV_REV_MATCH_ALL) 1251 } x86_chiprev_t; 1252 1253 #undef _DECL_CHIPREV 1254 1255 /* 1256 * Same thing, but for microarchitecture (core implementations). We are not 1257 * attempting to capture every possible fine-grained detail here; to the extent 1258 * that it matters, we do so in cpuid.c via ISA/feature bits. We use the same 1259 * number of bits for each field as in chiprev. 1260 */ 1261 1262 #define _X86_UARCHREV_VENDOR(x) _X86_CHIPREV_VENDOR(x) 1263 #define _X86_UARCHREV_UARCH(x) _X86_CHIPREV_FAMILY(x) 1264 #define _X86_UARCHREV_REV(x) _X86_CHIPREV_REV(x) 1265 1266 #define _X86_UARCHREV_MKREV(vendor, family, rev) \ 1267 _X86_CHIPREV_MKREV(vendor, family, rev) 1268 1269 typedef enum x86_uarch { 1270 X86_UARCH_UNKNOWN, 1271 1272 X86_UARCH_AMD_LEGACY, 1273 X86_UARCH_AMD_ZEN1, 1274 X86_UARCH_AMD_ZENPLUS, 1275 X86_UARCH_AMD_ZEN2, 1276 X86_UARCH_AMD_ZEN3, 1277 X86_UARCH_AMD_ZEN4, 1278 1279 X86_UARCH_ANY = 0xff 1280 } x86_uarch_t; 1281 1282 #define _DECL_UARCHREV(_v, _f, _revn, _revb) \ 1283 X86_UARCHREV_ ## _v ## _ ## _f ## _ ## _revn = \ 1284 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \ 1285 _revb) 1286 1287 #define _DECL_UARCHREV_NOREV(_v, _f, _revb) \ 1288 X86_UARCHREV_ ## _v ## _ ## _f = \ 1289 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \ 1290 _revb) 1291 1292 #define _X86_UARCHREV_REV_MATCH_ALL 0xffff 1293 1294 typedef enum x86_uarchrev { 1295 X86_UARCHREV_UNKNOWN, 1296 _DECL_UARCHREV_NOREV(AMD, LEGACY, 0x0001), 1297 _DECL_UARCHREV(AMD, LEGACY, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1298 1299 _DECL_UARCHREV_NOREV(AMD, ZEN1, 0x0001), 1300 _DECL_UARCHREV(AMD, ZEN1, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1301 1302 _DECL_UARCHREV_NOREV(AMD, ZENPLUS, 0x0001), 1303 _DECL_UARCHREV(AMD, ZENPLUS, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1304 1305 _DECL_UARCHREV(AMD, ZEN2, UNKNOWN, 0x0001), 1306 _DECL_UARCHREV(AMD, ZEN2, A0, 0x0002), 1307 _DECL_UARCHREV(AMD, ZEN2, B0, 0x0004), 1308 _DECL_UARCHREV(AMD, ZEN2, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1309 1310 _DECL_UARCHREV(AMD, ZEN3, UNKNOWN, 0x0001), 1311 _DECL_UARCHREV(AMD, ZEN3, A0, 0x0002), 1312 _DECL_UARCHREV(AMD, ZEN3, B0, 0x0004), 1313 _DECL_UARCHREV(AMD, ZEN3, B1, 0x0008), 1314 _DECL_UARCHREV(AMD, ZEN3, B2, 0x0010), 1315 _DECL_UARCHREV(AMD, ZEN3, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1316 1317 _DECL_UARCHREV(AMD, ZEN4, UNKNOWN, 0x0001), 1318 _DECL_UARCHREV(AMD, ZEN4, A0, 0x0002), 1319 _DECL_UARCHREV(AMD, ZEN4, A1, 0x0004), 1320 _DECL_UARCHREV(AMD, ZEN4, A2, 0x0008), 1321 _DECL_UARCHREV(AMD, ZEN4, B0, 0x0010), 1322 _DECL_UARCHREV(AMD, ZEN4, B1, 0x0020), 1323 _DECL_UARCHREV(AMD, ZEN4, B2, 0x0040), 1324 _DECL_UARCHREV(AMD, ZEN4, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1325 1326 /* Keep at the end */ 1327 _X86_UARCHREV_ANY = _X86_UARCHREV_MKREV(_X86_VENDOR_MATCH_ALL, 1328 X86_UARCH_ANY, _X86_UARCHREV_REV_MATCH_ALL) 1329 } x86_uarchrev_t; 1330 1331 #undef _DECL_UARCHREV 1332 1333 #endif /* !_ASM */ 1334 1335 /* 1336 * Various socket/package types, extended as the need to distinguish 1337 * a new type arises. The top 8 byte identfies the vendor and the 1338 * remaining 24 bits describe 24 socket types. 1339 */ 1340 1341 #define _X86_SOCKET_VENDOR_SHIFT 24 1342 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 1343 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 1344 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 1345 1346 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 1347 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 1348 1349 #define X86_SOCKET_MATCH(s, mask) \ 1350 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 1351 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 1352 1353 #define X86_SOCKET_UNKNOWN 0x0 1354 /* 1355 * AMD socket types 1356 */ 1357 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01) 1358 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02) 1359 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03) 1360 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04) 1361 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05) 1362 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06) 1363 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07) 1364 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08) 1365 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09) 1366 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a) 1367 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b) 1368 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c) 1369 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d) 1370 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e) 1371 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f) 1372 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10) 1373 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11) 1374 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12) 1375 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13) 1376 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14) 1377 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15) 1378 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16) 1379 #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17) 1380 #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18) 1381 #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19) 1382 #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a) 1383 #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b) 1384 #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c) 1385 #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d) 1386 #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e) 1387 #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f) 1388 #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20) 1389 #define X86_SOCKET_FP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x21) 1390 #define X86_SOCKET_FP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x22) 1391 #define X86_SOCKET_STRX4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x23) 1392 #define X86_SOCKET_SP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x24) 1393 #define X86_SOCKET_AM5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x25) 1394 #define X86_SOCKET_FP7 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x26) 1395 #define X86_SOCKET_FP7R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x27) 1396 #define X86_SOCKET_FF3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x28) 1397 #define X86_SOCKET_FT6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x29) 1398 #define X86_SOCKET_FP8 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2a) 1399 #define X86_SOCKET_FL1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2b) 1400 #define X86_SOCKET_SP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2c) 1401 #define X86_SOCKET_TR5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2d) 1402 #define X86_NUM_SOCKETS_AMD 0x2d 1403 1404 /* 1405 * Hygon socket types 1406 */ 1407 #define X86_SOCKET_SL1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x01) 1408 #define X86_SOCKET_SL1R2 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x02) 1409 #define X86_SOCKET_DM1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x03) 1410 #define X86_NUM_SOCKETS_HYGON 0x03 1411 1412 #define X86_NUM_SOCKETS (X86_NUM_SOCKETS_AMD + X86_NUM_SOCKETS_HYGON) 1413 1414 /* 1415 * Definitions for Intel processor models. These are all for Family 6 1416 * processors. This list and the Atom set below it are not exhuastive. 1417 */ 1418 #define INTC_MODEL_YONAH 0x0e 1419 #define INTC_MODEL_MEROM 0x0f 1420 #define INTC_MODEL_MEROM_L 0x16 1421 #define INTC_MODEL_PENRYN 0x17 1422 #define INTC_MODEL_DUNNINGTON 0x1d 1423 1424 #define INTC_MODEL_NEHALEM 0x1e 1425 #define INTC_MODEL_NEHALEM2 0x1f 1426 #define INTC_MODEL_NEHALEM_EP 0x1a 1427 #define INTC_MODEL_NEHALEM_EX 0x2e 1428 1429 #define INTC_MODEL_WESTMERE 0x25 1430 #define INTC_MODEL_WESTMERE_EP 0x2c 1431 #define INTC_MODEL_WESTMERE_EX 0x2f 1432 1433 #define INTC_MODEL_SANDYBRIDGE 0x2a 1434 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 1435 #define INTC_MODEL_IVYBRIDGE 0x3a 1436 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 1437 1438 #define INTC_MODEL_HASWELL 0x3c 1439 #define INTC_MODEL_HASWELL_ULT 0x45 1440 #define INTC_MODEL_HASWELL_GT3E 0x46 1441 #define INTC_MODEL_HASWELL_XEON 0x3f 1442 1443 #define INTC_MODEL_BROADWELL 0x3d 1444 #define INTC_MODEL_BROADELL_2 0x47 1445 #define INTC_MODEL_BROADWELL_XEON 0x4f 1446 #define INTC_MODEL_BROADWELL_XEON_D 0x56 1447 1448 #define INTC_MODEL_SKYLAKE_MOBILE 0x4e 1449 /* 1450 * Note, this model is shared with Cascade Lake and Cooper Lake. 1451 */ 1452 #define INTC_MODEL_SKYLAKE_XEON 0x55 1453 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 1454 1455 /* 1456 * Note, both Kaby Lake models are shared with Coffee Lake, Whiskey Lake, Amber 1457 * Lake, and some Comet Lake parts. 1458 */ 1459 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 1460 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 1461 1462 #define INTC_MODEL_ICELAKE_XEON 0x6a 1463 #define INTC_MODEL_ICELAKE_MOBILE 0x7e 1464 #define INTC_MODEL_TIGERLAKE_MOBILE 0x8c 1465 1466 #define INTC_MODEL_COMETLAKE 0xa5 1467 #define INTC_MODEL_COMETLAKE_MOBILE 0xa6 1468 #define INTC_MODEL_ROCKETLAKE 0xa7 1469 1470 /* 1471 * Atom Processors 1472 */ 1473 #define INTC_MODEL_SILVERTHORNE 0x1c 1474 #define INTC_MODEL_LINCROFT 0x26 1475 #define INTC_MODEL_PENWELL 0x27 1476 #define INTC_MODEL_CLOVERVIEW 0x35 1477 #define INTC_MODEL_CEDARVIEW 0x36 1478 #define INTC_MODEL_BAY_TRAIL 0x37 1479 #define INTC_MODEL_AVATON 0x4d 1480 #define INTC_MODEL_AIRMONT 0x4c 1481 #define INTC_MODEL_GOLDMONT 0x5c 1482 #define INTC_MODEL_DENVERTON 0x5f 1483 #define INTC_MODEL_GEMINI_LAKE 0x7a 1484 1485 /* 1486 * xgetbv/xsetbv support 1487 * See section 13.3 in vol. 1 of the Intel Developer's manual. 1488 */ 1489 1490 #define XFEATURE_ENABLED_MASK 0x0 1491 /* 1492 * XFEATURE_ENABLED_MASK values (eax) 1493 * See setup_xfem(). 1494 */ 1495 #define XFEATURE_LEGACY_FP (1 << 0) 1496 #define XFEATURE_SSE (1 << 1) 1497 #define XFEATURE_AVX (1 << 2) 1498 /* 1499 * MPX is meant to be all or nothing, therefore for most of the kernel prefer 1500 * the XFEATURE_MPX definition over the individual state bits. 1501 */ 1502 #define XFEATURE_MPX_BNDREGS (1 << 3) 1503 #define XFEATURE_MPX_BNDCSR (1 << 4) 1504 #define XFEATURE_MPX (XFEATURE_MPX_BNDREGS | XFEATURE_MPX_BNDCSR) 1505 /* 1506 * AX512 is meant to be all or nothing, therefore for most of the kernel prefer 1507 * the XFEATURE_AVX512 definition over the individual state bits. 1508 */ 1509 #define XFEATURE_AVX512_OPMASK (1 << 5) 1510 #define XFEATURE_AVX512_ZMM (1 << 6) 1511 #define XFEATURE_AVX512_HI_ZMM (1 << 7) 1512 #define XFEATURE_AVX512 (XFEATURE_AVX512_OPMASK | \ 1513 XFEATURE_AVX512_ZMM | XFEATURE_AVX512_HI_ZMM) 1514 /* bit 8 unused */ 1515 #define XFEATURE_PKRU (1 << 9) 1516 #define XFEATURE_FP_ALL \ 1517 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 1518 XFEATURE_AVX512 | XFEATURE_PKRU) 1519 1520 /* 1521 * Define the set of xfeature flags that should be considered valid in the xsave 1522 * state vector when we initialize an lwp. This is distinct from the full set so 1523 * that all of the processor's normal logic and tracking of the xsave state is 1524 * usable. This should correspond to the state that's been initialized by the 1525 * ABI to hold meaningful values. Adding additional bits here can have serious 1526 * performance implications and cause performance degradations when using the 1527 * FPU vector (xmm) registers. 1528 */ 1529 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 1530 1531 #if !defined(_ASM) 1532 1533 #if defined(_KERNEL) || defined(_KMEMUSER) 1534 1535 #define NUM_X86_FEATURES 109 1536 extern uchar_t x86_featureset[]; 1537 1538 extern void free_x86_featureset(void *featureset); 1539 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 1540 extern void add_x86_feature(void *featureset, uint_t feature); 1541 extern void remove_x86_feature(void *featureset, uint_t feature); 1542 extern boolean_t compare_x86_featureset(void *setA, void *setB); 1543 extern void print_x86_featureset(void *featureset); 1544 1545 1546 extern uint_t x86_type; 1547 extern uint_t x86_vendor; 1548 extern uint_t x86_clflush_size; 1549 1550 extern uint_t pentiumpro_bug4046376; 1551 1552 /* 1553 * These functions are all used to perform various side-channel mitigations. 1554 * Please see uts/i86pc/os/cpuid.c for more information. 1555 */ 1556 extern void (*spec_uarch_flush)(void); 1557 extern void x86_rsb_stuff(void); 1558 extern void x86_md_clear(void); 1559 1560 #endif 1561 1562 #if defined(_KERNEL) 1563 1564 /* 1565 * This structure is used to pass arguments and get return values back 1566 * from the CPUID instruction in __cpuid_insn() routine. 1567 */ 1568 struct cpuid_regs { 1569 uint32_t cp_eax; 1570 uint32_t cp_ebx; 1571 uint32_t cp_ecx; 1572 uint32_t cp_edx; 1573 }; 1574 1575 extern int x86_use_pcid; 1576 extern int x86_use_invpcid; 1577 1578 /* 1579 * Utility functions to get/set extended control registers (XCR) 1580 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 1581 */ 1582 extern uint64_t get_xcr(uint_t); 1583 extern void set_xcr(uint_t, uint64_t); 1584 1585 extern uint64_t rdmsr(uint_t); 1586 extern void wrmsr(uint_t, const uint64_t); 1587 extern uint64_t xrdmsr(uint_t); 1588 extern void xwrmsr(uint_t, const uint64_t); 1589 extern int checked_rdmsr(uint_t, uint64_t *); 1590 extern int checked_wrmsr(uint_t, uint64_t); 1591 1592 extern void invalidate_cache(void); 1593 extern ulong_t getcr4(void); 1594 extern void setcr4(ulong_t); 1595 1596 extern void mtrr_sync(void); 1597 1598 extern void cpu_fast_syscall_enable(void); 1599 extern void cpu_fast_syscall_disable(void); 1600 1601 typedef enum cpuid_pass { 1602 CPUID_PASS_NONE = 0, 1603 CPUID_PASS_PRELUDE, 1604 CPUID_PASS_IDENT, 1605 CPUID_PASS_BASIC, 1606 CPUID_PASS_EXTENDED, 1607 CPUID_PASS_DYNAMIC, 1608 CPUID_PASS_RESOLVE 1609 } cpuid_pass_t; 1610 1611 struct cpu; 1612 1613 extern boolean_t cpuid_checkpass(const struct cpu *const, const cpuid_pass_t); 1614 extern void cpuid_execpass(struct cpu *, const cpuid_pass_t, void *); 1615 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 1616 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 1617 extern uint32_t __cpuid_insn(struct cpuid_regs *); 1618 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 1619 extern int cpuid_getidstr(struct cpu *, char *, size_t); 1620 extern const char *cpuid_getvendorstr(struct cpu *); 1621 extern uint_t cpuid_getvendor(struct cpu *); 1622 extern uint_t cpuid_getfamily(struct cpu *); 1623 extern uint_t cpuid_getmodel(struct cpu *); 1624 extern uint_t cpuid_getstep(struct cpu *); 1625 extern uint_t cpuid_getsig(struct cpu *); 1626 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 1627 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 1628 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 1629 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 1630 extern int cpuid_get_chipid(struct cpu *); 1631 extern id_t cpuid_get_coreid(struct cpu *); 1632 extern int cpuid_get_pkgcoreid(struct cpu *); 1633 extern int cpuid_get_clogid(struct cpu *); 1634 extern int cpuid_get_cacheid(struct cpu *); 1635 extern uint32_t cpuid_get_apicid(struct cpu *); 1636 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 1637 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 1638 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 1639 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 1640 extern size_t cpuid_get_xsave_size(void); 1641 extern void cpuid_get_xsave_info(uint64_t, size_t *, size_t *); 1642 extern boolean_t cpuid_need_fp_excp_handling(void); 1643 extern int cpuid_is_cmt(struct cpu *); 1644 extern int cpuid_syscall32_insn(struct cpu *); 1645 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 1646 1647 extern x86_chiprev_t cpuid_getchiprev(struct cpu *); 1648 extern const char *cpuid_getchiprevstr(struct cpu *); 1649 extern uint32_t cpuid_getsockettype(struct cpu *); 1650 extern const char *cpuid_getsocketstr(struct cpu *); 1651 extern x86_uarchrev_t cpuid_getuarchrev(struct cpu *); 1652 1653 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 1654 1655 struct cpuid_info; 1656 1657 extern void setx86isalist(void); 1658 extern void cpuid_alloc_space(struct cpu *); 1659 extern void cpuid_free_space(struct cpu *); 1660 extern void cpuid_set_cpu_properties(void *, processorid_t, 1661 struct cpuid_info *); 1662 extern void cpuid_post_ucodeadm(void); 1663 1664 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 1665 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 1666 1667 #if !defined(__xpv) 1668 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 1669 extern void cpuid_mwait_free(struct cpu *); 1670 extern int cpuid_deep_cstates_supported(void); 1671 extern int cpuid_arat_supported(void); 1672 extern int cpuid_iepb_supported(struct cpu *); 1673 extern int cpuid_deadline_tsc_supported(void); 1674 extern void vmware_port(int, uint32_t *); 1675 #endif 1676 1677 extern x86_processor_family_t chiprev_family(const x86_chiprev_t); 1678 extern boolean_t chiprev_matches(const x86_chiprev_t, const x86_chiprev_t); 1679 extern boolean_t chiprev_at_least(const x86_chiprev_t, const x86_chiprev_t); 1680 1681 extern x86_uarch_t uarchrev_uarch(const x86_uarchrev_t); 1682 extern boolean_t uarchrev_matches(const x86_uarchrev_t, const x86_uarchrev_t); 1683 extern boolean_t uarchrev_at_least(const x86_uarchrev_t, const x86_uarchrev_t); 1684 1685 /* 1686 * Cache information intended for topology and wider use. 1687 */ 1688 typedef enum { 1689 X86_CACHE_TYPE_DATA, 1690 X86_CACHE_TYPE_INST, 1691 X86_CACHE_TYPE_UNIFIED 1692 } x86_cache_type_t; 1693 1694 typedef enum { 1695 X86_CACHE_F_FULL_ASSOC = 1 << 0 1696 } x86_cache_flags_t; 1697 1698 typedef struct x86_cache { 1699 uint32_t xc_level; 1700 x86_cache_type_t xc_type; 1701 x86_cache_flags_t xc_flags; 1702 uint32_t xc_nparts; 1703 uint32_t xc_nways; 1704 uint32_t xc_line_size; 1705 uint64_t xc_nsets; 1706 uint64_t xc_size; 1707 uint64_t xc_id; 1708 uint32_t xc_apic_shift; 1709 } x86_cache_t; 1710 1711 extern int cpuid_getncaches(struct cpu *, uint32_t *); 1712 extern int cpuid_getcache(struct cpu *, uint32_t, x86_cache_t *); 1713 1714 struct cpu_ucode_info; 1715 1716 extern void ucode_alloc_space(struct cpu *); 1717 extern void ucode_free_space(struct cpu *); 1718 extern void ucode_init(void); 1719 extern void ucode_check(struct cpu *); 1720 extern void ucode_cleanup(); 1721 1722 #if !defined(__xpv) 1723 extern char _tsc_mfence_start; 1724 extern char _tsc_mfence_end; 1725 extern char _tscp_start; 1726 extern char _tscp_end; 1727 extern char _no_rdtsc_start; 1728 extern char _no_rdtsc_end; 1729 extern char _tsc_lfence_start; 1730 extern char _tsc_lfence_end; 1731 #endif 1732 1733 #if !defined(__xpv) 1734 extern char bcopy_patch_start; 1735 extern char bcopy_patch_end; 1736 extern char bcopy_ck_size; 1737 #endif 1738 1739 extern void post_startup_cpu_fixups(void); 1740 1741 extern uint_t workaround_errata(struct cpu *); 1742 1743 #if defined(OPTERON_ERRATUM_93) 1744 extern int opteron_erratum_93; 1745 #endif 1746 1747 #if defined(OPTERON_ERRATUM_91) 1748 extern int opteron_erratum_91; 1749 #endif 1750 1751 #if defined(OPTERON_ERRATUM_100) 1752 extern int opteron_erratum_100; 1753 #endif 1754 1755 #if defined(OPTERON_ERRATUM_121) 1756 extern int opteron_erratum_121; 1757 #endif 1758 1759 #if defined(OPTERON_ERRATUM_147) 1760 extern int opteron_erratum_147; 1761 extern void patch_erratum_147(void); 1762 #endif 1763 1764 #if !defined(__xpv) 1765 extern void determine_platform(void); 1766 #endif 1767 extern int get_hwenv(void); 1768 extern int is_controldom(void); 1769 1770 extern void enable_pcid(void); 1771 1772 extern void xsave_setup_msr(struct cpu *); 1773 1774 #if !defined(__xpv) 1775 extern void reset_gdtr_limit(void); 1776 #endif 1777 1778 extern int enable_platform_detection; 1779 1780 /* 1781 * Hypervisor signatures 1782 */ 1783 #define HVSIG_XEN_HVM "XenVMMXenVMM" 1784 #define HVSIG_VMWARE "VMwareVMware" 1785 #define HVSIG_KVM "KVMKVMKVM" 1786 #define HVSIG_MICROSOFT "Microsoft Hv" 1787 #define HVSIG_BHYVE "bhyve bhyve " 1788 #define HVSIG_QEMU_TCG "TCGTCGTCGTCG" 1789 1790 /* 1791 * Defined hardware environments 1792 */ 1793 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 1794 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 1795 1796 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 1797 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 1798 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 1799 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1800 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 1801 #define HW_QEMU_TCG (1 << 7) /* Running on QEMU TCG hypervisor */ 1802 1803 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1804 HW_BHYVE | HW_QEMU_TCG) 1805 1806 #endif /* _KERNEL */ 1807 1808 #endif /* !_ASM */ 1809 1810 /* 1811 * VMware hypervisor related defines 1812 */ 1813 #define VMWARE_HVMAGIC 0x564d5868 1814 #define VMWARE_HVPORT 0x5658 1815 #define VMWARE_HVCMD_GETVERSION 0x0a 1816 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 1817 1818 #ifdef __cplusplus 1819 } 1820 #endif 1821 1822 #endif /* _SYS_X86_ARCHEXT_H */ 1823