1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_X86_ARCHEXT_H 27 #define _SYS_X86_ARCHEXT_H 28 29 #if !defined(_ASM) 30 #include <sys/regset.h> 31 #include <sys/processor.h> 32 #include <vm/seg_enum.h> 33 #include <vm/page.h> 34 #endif /* _ASM */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * cpuid instruction feature flags in %edx (standard function 1) 42 */ 43 44 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 45 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 46 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 47 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 48 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 49 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 50 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 51 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 52 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 53 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 54 /* 0x400 - reserved */ 55 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 56 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 57 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 58 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 59 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 60 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 61 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 62 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 63 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 64 /* 0x100000 - reserved */ 65 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 66 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 67 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 68 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 69 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 70 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 71 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 72 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 73 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 74 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 75 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 76 77 #define FMT_CPUID_INTC_EDX \ 78 "\20" \ 79 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 80 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 81 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 82 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 83 84 /* 85 * cpuid instruction feature flags in %ecx (standard function 1) 86 */ 87 88 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 89 /* 0x00000002 - reserved */ 90 /* 0x00000004 - reserved */ 91 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 92 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 93 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 94 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 95 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 96 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 97 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 98 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 99 /* 0x00000800 - reserved */ 100 /* 0x00001000 - reserved */ 101 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 102 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 103 /* 0x00008000 - reserved */ 104 /* 0x00010000 - reserved */ 105 /* 0x00020000 - reserved */ 106 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 107 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 108 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 109 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 110 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 111 112 #define FMT_CPUID_INTC_ECX \ 113 "\20" \ 114 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \ 115 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 116 "\10est\7smx\6vmx\5dscpl\4mon\1sse3" 117 118 /* 119 * cpuid instruction feature flags in %edx (extended function 0x80000001) 120 */ 121 122 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 123 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 124 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 125 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 126 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 127 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 128 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 129 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 130 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 131 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 132 /* 0x00000400 - sysc on K6m6 */ 133 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 134 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 135 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 136 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 137 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 138 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 139 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 140 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 141 /* 0x00040000 - reserved */ 142 /* 0x00080000 - reserved */ 143 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 144 /* 0x00200000 - reserved */ 145 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 146 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 147 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 148 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 149 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 150 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 151 /* 0x10000000 - reserved */ 152 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 153 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 154 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 155 156 #define FMT_CPUID_AMD_EDX \ 157 "\20" \ 158 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 159 "\30mmx\27mmxext\25nx\22pse\21pat" \ 160 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 161 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 162 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 177 178 #define FMT_CPUID_AMD_ECX \ 179 "\20" \ 180 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 181 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 182 183 /* 184 * Intel now seems to have claimed part of the "extended" function 185 * space that we previously for non-Intel implementors to use. 186 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 187 * is available in long mode i.e. what AMD indicate using bit 0. 188 * On the other hand, everything else is labelled as reserved. 189 */ 190 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 191 192 193 #define P5_MCHADDR 0x0 194 #define P5_CESR 0x11 195 #define P5_CTR0 0x12 196 #define P5_CTR1 0x13 197 198 #define K5_MCHADDR 0x0 199 #define K5_MCHTYPE 0x01 200 #define K5_TSC 0x10 201 #define K5_TR12 0x12 202 203 #define REG_PAT 0x277 204 205 #define REG_MC0_CTL 0x400 206 #define REG_MC5_MISC 0x417 207 #define REG_PERFCTR0 0xc1 208 #define REG_PERFCTR1 0xc2 209 210 #define REG_PERFEVNT0 0x186 211 #define REG_PERFEVNT1 0x187 212 213 #define REG_TSC 0x10 /* timestamp counter */ 214 #define REG_APIC_BASE_MSR 0x1b 215 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 216 217 #define MSR_DEBUGCTL 0x1d9 218 219 #define DEBUGCTL_LBR 0x01 220 #define DEBUGCTL_BTF 0x02 221 222 /* Intel P6, AMD */ 223 #define MSR_LBR_FROM 0x1db 224 #define MSR_LBR_TO 0x1dc 225 #define MSR_LEX_FROM 0x1dd 226 #define MSR_LEX_TO 0x1de 227 228 /* Intel P4 (pre-Prescott, non P4 M) */ 229 #define MSR_P4_LBSTK_TOS 0x1da 230 #define MSR_P4_LBSTK_0 0x1db 231 #define MSR_P4_LBSTK_1 0x1dc 232 #define MSR_P4_LBSTK_2 0x1dd 233 #define MSR_P4_LBSTK_3 0x1de 234 235 /* Intel Pentium M */ 236 #define MSR_P6M_LBSTK_TOS 0x1c9 237 #define MSR_P6M_LBSTK_0 0x040 238 #define MSR_P6M_LBSTK_1 0x041 239 #define MSR_P6M_LBSTK_2 0x042 240 #define MSR_P6M_LBSTK_3 0x043 241 #define MSR_P6M_LBSTK_4 0x044 242 #define MSR_P6M_LBSTK_5 0x045 243 #define MSR_P6M_LBSTK_6 0x046 244 #define MSR_P6M_LBSTK_7 0x047 245 246 /* Intel P4 (Prescott) */ 247 #define MSR_PRP4_LBSTK_TOS 0x1da 248 #define MSR_PRP4_LBSTK_FROM_0 0x680 249 #define MSR_PRP4_LBSTK_FROM_1 0x681 250 #define MSR_PRP4_LBSTK_FROM_2 0x682 251 #define MSR_PRP4_LBSTK_FROM_3 0x683 252 #define MSR_PRP4_LBSTK_FROM_4 0x684 253 #define MSR_PRP4_LBSTK_FROM_5 0x685 254 #define MSR_PRP4_LBSTK_FROM_6 0x686 255 #define MSR_PRP4_LBSTK_FROM_7 0x687 256 #define MSR_PRP4_LBSTK_FROM_8 0x688 257 #define MSR_PRP4_LBSTK_FROM_9 0x689 258 #define MSR_PRP4_LBSTK_FROM_10 0x68a 259 #define MSR_PRP4_LBSTK_FROM_11 0x68b 260 #define MSR_PRP4_LBSTK_FROM_12 0x68c 261 #define MSR_PRP4_LBSTK_FROM_13 0x68d 262 #define MSR_PRP4_LBSTK_FROM_14 0x68e 263 #define MSR_PRP4_LBSTK_FROM_15 0x68f 264 #define MSR_PRP4_LBSTK_TO_0 0x6c0 265 #define MSR_PRP4_LBSTK_TO_1 0x6c1 266 #define MSR_PRP4_LBSTK_TO_2 0x6c2 267 #define MSR_PRP4_LBSTK_TO_3 0x6c3 268 #define MSR_PRP4_LBSTK_TO_4 0x6c4 269 #define MSR_PRP4_LBSTK_TO_5 0x6c5 270 #define MSR_PRP4_LBSTK_TO_6 0x6c6 271 #define MSR_PRP4_LBSTK_TO_7 0x6c7 272 #define MSR_PRP4_LBSTK_TO_8 0x6c8 273 #define MSR_PRP4_LBSTK_TO_9 0x6c9 274 #define MSR_PRP4_LBSTK_TO_10 0x6ca 275 #define MSR_PRP4_LBSTK_TO_11 0x6cb 276 #define MSR_PRP4_LBSTK_TO_12 0x6cc 277 #define MSR_PRP4_LBSTK_TO_13 0x6cd 278 #define MSR_PRP4_LBSTK_TO_14 0x6ce 279 #define MSR_PRP4_LBSTK_TO_15 0x6cf 280 281 #define MCI_CTL_VALUE 0xffffffff 282 283 #define MTRR_TYPE_UC 0 284 #define MTRR_TYPE_WC 1 285 #define MTRR_TYPE_WT 4 286 #define MTRR_TYPE_WP 5 287 #define MTRR_TYPE_WB 6 288 #define MTRR_TYPE_UC_ 7 289 290 /* 291 * For Solaris we set up the page attritubute table in the following way: 292 * PAT0 Write-Back 293 * PAT1 Write-Through 294 * PAT2 Unchacheable- 295 * PAT3 Uncacheable 296 * PAT4 Write-Back 297 * PAT5 Write-Through 298 * PAT6 Write-Combine 299 * PAT7 Uncacheable 300 * The only difference from h/w default is entry 6. 301 */ 302 #define PAT_DEFAULT_ATTRIBUTE \ 303 ((uint64_t)MTRR_TYPE_WB | \ 304 ((uint64_t)MTRR_TYPE_WT << 8) | \ 305 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 306 ((uint64_t)MTRR_TYPE_UC << 24) | \ 307 ((uint64_t)MTRR_TYPE_WB << 32) | \ 308 ((uint64_t)MTRR_TYPE_WT << 40) | \ 309 ((uint64_t)MTRR_TYPE_WC << 48) | \ 310 ((uint64_t)MTRR_TYPE_UC << 56)) 311 312 #define X86_LARGEPAGE 0x00000001 313 #define X86_TSC 0x00000002 314 #define X86_MSR 0x00000004 315 #define X86_MTRR 0x00000008 316 #define X86_PGE 0x00000010 317 #define X86_DE 0x00000020 318 #define X86_CMOV 0x00000040 319 #define X86_MMX 0x00000080 320 #define X86_MCA 0x00000100 321 #define X86_PAE 0x00000200 322 #define X86_CX8 0x00000400 323 #define X86_PAT 0x00000800 324 #define X86_SEP 0x00001000 325 #define X86_SSE 0x00002000 326 #define X86_SSE2 0x00004000 327 #define X86_HTT 0x00008000 328 #define X86_ASYSC 0x00010000 329 #define X86_NX 0x00020000 330 #define X86_SSE3 0x00040000 331 #define X86_CX16 0x00080000 332 #define X86_CMP 0x00100000 333 #define X86_TSCP 0x00200000 334 #define X86_MWAIT 0x00400000 335 #define X86_SSE4A 0x00800000 336 #define X86_CPUID 0x01000000 337 #define X86_SSSE3 0x02000000 338 #define X86_SSE4_1 0x04000000 339 #define X86_SSE4_2 0x08000000 340 #define X86_1GPG 0x10000000 341 #define X86_CLFSH 0x20000000 342 #define X86_64 0x40000000 343 344 /* 345 * flags to patch tsc_read routine. 346 */ 347 #define X86_NO_TSC 0x0 348 #define X86_HAVE_TSCP 0x1 349 #define X86_TSC_MFENCE 0x2 350 #define X86_TSC_LFENCE 0x4 351 352 #define FMT_X86_FEATURE \ 353 "\20" \ 354 "\34sse4_2\33sse4_1\32ssse3\31cpuid" \ 355 "\30sse4a\27mwait\26tscp\25cmp\24cx16\23sse3\22nx\21asysc"\ 356 "\20htt\17sse2\16sse\15sep\14pat\13cx8\12pae\11mca" \ 357 "\10mmx\7cmov\6de\5pge\4mtrr\3msr\2tsc\1lgpg" 358 359 /* 360 * x86_type is a legacy concept; this is supplanted 361 * for most purposes by x86_feature; modern CPUs 362 * should be X86_TYPE_OTHER 363 */ 364 #define X86_TYPE_OTHER 0 365 #define X86_TYPE_486 1 366 #define X86_TYPE_P5 2 367 #define X86_TYPE_P6 3 368 #define X86_TYPE_CYRIX_486 4 369 #define X86_TYPE_CYRIX_6x86L 5 370 #define X86_TYPE_CYRIX_6x86 6 371 #define X86_TYPE_CYRIX_GXm 7 372 #define X86_TYPE_CYRIX_6x86MX 8 373 #define X86_TYPE_CYRIX_MediaGX 9 374 #define X86_TYPE_CYRIX_MII 10 375 #define X86_TYPE_VIA_CYRIX_III 11 376 #define X86_TYPE_P4 12 377 378 /* 379 * x86_vendor allows us to select between 380 * implementation features and helps guide 381 * the interpretation of the cpuid instruction. 382 */ 383 #define X86_VENDOR_Intel 0 384 #define X86_VENDORSTR_Intel "GenuineIntel" 385 386 #define X86_VENDOR_IntelClone 1 387 388 #define X86_VENDOR_AMD 2 389 #define X86_VENDORSTR_AMD "AuthenticAMD" 390 391 #define X86_VENDOR_Cyrix 3 392 #define X86_VENDORSTR_CYRIX "CyrixInstead" 393 394 #define X86_VENDOR_UMC 4 395 #define X86_VENDORSTR_UMC "UMC UMC UMC " 396 397 #define X86_VENDOR_NexGen 5 398 #define X86_VENDORSTR_NexGen "NexGenDriven" 399 400 #define X86_VENDOR_Centaur 6 401 #define X86_VENDORSTR_Centaur "CentaurHauls" 402 403 #define X86_VENDOR_Rise 7 404 #define X86_VENDORSTR_Rise "RiseRiseRise" 405 406 #define X86_VENDOR_SiS 8 407 #define X86_VENDORSTR_SiS "SiS SiS SiS " 408 409 #define X86_VENDOR_TM 9 410 #define X86_VENDORSTR_TM "GenuineTMx86" 411 412 #define X86_VENDOR_NSC 10 413 #define X86_VENDORSTR_NSC "Geode by NSC" 414 415 /* 416 * Vendor string max len + \0 417 */ 418 #define X86_VENDOR_STRLEN 13 419 420 /* 421 * Some vendor/family/model/stepping ranges are commonly grouped under 422 * a single identifying banner by the vendor. The following encode 423 * that "revision" in a uint32_t with the 8 most significant bits 424 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 425 * family, and the remaining 16 typically forming a bitmask of revisions 426 * within that family with more significant bits indicating "later" revisions. 427 */ 428 429 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 430 #define _X86_CHIPREV_VENDOR_SHIFT 24 431 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 432 #define _X86_CHIPREV_FAMILY_SHIFT 16 433 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 434 435 #define _X86_CHIPREV_VENDOR(x) \ 436 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 437 #define _X86_CHIPREV_FAMILY(x) \ 438 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 439 #define _X86_CHIPREV_REV(x) \ 440 ((x) & _X86_CHIPREV_REV_MASK) 441 442 /* True if x matches in vendor and family and if x matches the given rev mask */ 443 #define X86_CHIPREV_MATCH(x, mask) \ 444 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 445 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 446 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 447 448 /* True if x matches in vendor and family and rev is at least minx */ 449 #define X86_CHIPREV_ATLEAST(x, minx) \ 450 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 451 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 452 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 453 454 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 455 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 456 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 457 458 /* Revision default */ 459 #define X86_CHIPREV_UNKNOWN 0x0 460 461 /* 462 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 463 * sufficiently different that we will distinguish them; in all other 464 * case we will identify the major revision. 465 */ 466 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 467 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 468 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 469 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 470 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 471 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 472 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 473 474 /* 475 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 476 */ 477 #define X86_CHIPREV_AMD_10_REV_A \ 478 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 479 #define X86_CHIPREV_AMD_10_REV_B \ 480 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 481 #define X86_CHIPREV_AMD_10_REV_C \ 482 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 483 484 /* 485 * Various socket/package types, extended as the need to distinguish 486 * a new type arises. The top 8 byte identfies the vendor and the 487 * remaining 24 bits describe 24 socket types. 488 */ 489 490 #define _X86_SOCKET_VENDOR_SHIFT 24 491 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 492 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 493 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 494 495 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 496 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 497 498 #define X86_SOCKET_MATCH(s, mask) \ 499 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 500 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 501 502 #define X86_SOCKET_UNKNOWN 0x0 503 /* 504 * AMD socket types 505 */ 506 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 507 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 508 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 509 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 510 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 511 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 512 513 #if !defined(_ASM) 514 515 #if defined(_KERNEL) || defined(_KMEMUSER) 516 517 extern uint_t x86_feature; 518 extern uint_t x86_type; 519 extern uint_t x86_vendor; 520 extern uint_t x86_clflush_size; 521 522 extern uint_t pentiumpro_bug4046376; 523 extern uint_t pentiumpro_bug4064495; 524 525 extern uint_t enable486; 526 527 extern const char CyrixInstead[]; 528 529 #endif 530 531 #if defined(_KERNEL) 532 533 /* 534 * This structure is used to pass arguments and get return values back 535 * from the CPUID instruction in __cpuid_insn() routine. 536 */ 537 struct cpuid_regs { 538 uint32_t cp_eax; 539 uint32_t cp_ebx; 540 uint32_t cp_ecx; 541 uint32_t cp_edx; 542 }; 543 544 extern uint64_t rdmsr(uint_t); 545 extern void wrmsr(uint_t, const uint64_t); 546 extern uint64_t xrdmsr(uint_t); 547 extern void xwrmsr(uint_t, const uint64_t); 548 extern int checked_rdmsr(uint_t, uint64_t *); 549 extern int checked_wrmsr(uint_t, uint64_t); 550 551 extern void invalidate_cache(void); 552 extern ulong_t getcr4(void); 553 extern void setcr4(ulong_t); 554 555 extern void mtrr_sync(void); 556 557 extern void cpu_fast_syscall_enable(void *); 558 extern void cpu_fast_syscall_disable(void *); 559 560 struct cpu; 561 562 extern int cpuid_checkpass(struct cpu *, int); 563 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 564 extern uint32_t __cpuid_insn(struct cpuid_regs *); 565 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 566 extern int cpuid_getidstr(struct cpu *, char *, size_t); 567 extern const char *cpuid_getvendorstr(struct cpu *); 568 extern uint_t cpuid_getvendor(struct cpu *); 569 extern uint_t cpuid_getfamily(struct cpu *); 570 extern uint_t cpuid_getmodel(struct cpu *); 571 extern uint_t cpuid_getstep(struct cpu *); 572 extern uint_t cpuid_getsig(struct cpu *); 573 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 574 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 575 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 576 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 577 extern int cpuid_get_chipid(struct cpu *); 578 extern id_t cpuid_get_coreid(struct cpu *); 579 extern int cpuid_get_pkgcoreid(struct cpu *); 580 extern int cpuid_get_clogid(struct cpu *); 581 extern int cpuid_is_cmt(struct cpu *); 582 extern int cpuid_syscall32_insn(struct cpu *); 583 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 584 585 extern uint32_t cpuid_getchiprev(struct cpu *); 586 extern const char *cpuid_getchiprevstr(struct cpu *); 587 extern uint32_t cpuid_getsockettype(struct cpu *); 588 589 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 590 591 struct cpuid_info; 592 593 extern void setx86isalist(void); 594 extern void cpuid_alloc_space(struct cpu *); 595 extern void cpuid_free_space(struct cpu *); 596 extern uint_t cpuid_pass1(struct cpu *); 597 extern void cpuid_pass2(struct cpu *); 598 extern void cpuid_pass3(struct cpu *); 599 extern uint_t cpuid_pass4(struct cpu *); 600 extern void add_cpunode2devtree(processorid_t, struct cpuid_info *); 601 602 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 603 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 604 605 #if !defined(__xpv) 606 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 607 extern void cpuid_mwait_free(struct cpu *); 608 #endif 609 610 struct cpu_ucode_info; 611 612 extern void ucode_alloc_space(struct cpu *); 613 extern void ucode_free_space(struct cpu *); 614 extern void ucode_check(struct cpu *); 615 extern void ucode_cleanup(); 616 617 #if !defined(__xpv) 618 extern char _tsc_mfence_start; 619 extern char _tsc_mfence_end; 620 extern char _tscp_start; 621 extern char _tscp_end; 622 extern char _no_rdtsc_start; 623 extern char _no_rdtsc_end; 624 extern char _tsc_lfence_start; 625 extern char _tsc_lfence_end; 626 #endif 627 628 #if !defined(__xpv) 629 extern char bcopy_patch_start; 630 extern char bcopy_patch_end; 631 extern char bcopy_ck_size; 632 #endif 633 634 extern uint_t workaround_errata(struct cpu *); 635 636 #if defined(OPTERON_ERRATUM_93) 637 extern int opteron_erratum_93; 638 #endif 639 640 #if defined(OPTERON_ERRATUM_91) 641 extern int opteron_erratum_91; 642 #endif 643 644 #if defined(OPTERON_ERRATUM_100) 645 extern int opteron_erratum_100; 646 #endif 647 648 #if defined(OPTERON_ERRATUM_121) 649 extern int opteron_erratum_121; 650 #endif 651 652 #if defined(OPTERON_WORKAROUND_6323525) 653 extern int opteron_workaround_6323525; 654 extern void patch_workaround_6323525(void); 655 #endif 656 657 #endif /* _KERNEL */ 658 659 #endif 660 661 #ifdef __cplusplus 662 } 663 #endif 664 665 #endif /* _SYS_X86_ARCHEXT_H */ 666