1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright 2020 Joyent, Inc. 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> 34 * Copyright 2018 Nexenta Systems, Inc. 35 * Copyright 2022 Oxide Computer Company 36 */ 37 38 #ifndef _SYS_X86_ARCHEXT_H 39 #define _SYS_X86_ARCHEXT_H 40 41 #if !defined(_ASM) 42 #include <sys/bitext.h> 43 #include <sys/regset.h> 44 #include <sys/processor.h> 45 #include <vm/seg_enum.h> 46 #include <vm/page.h> 47 #endif /* _ASM */ 48 49 #ifdef __cplusplus 50 extern "C" { 51 #endif 52 53 /* 54 * cpuid instruction feature flags in %edx (standard function 1) 55 */ 56 57 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 58 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 59 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 60 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 61 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 62 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 63 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 64 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 65 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 66 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 67 /* 0x400 - reserved */ 68 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 69 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 70 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 71 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 72 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 73 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 74 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 75 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 76 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 77 /* 0x100000 - reserved */ 78 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 79 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 80 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 81 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 82 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 83 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 84 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 85 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 86 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 87 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 88 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 89 90 /* 91 * cpuid instruction feature flags in %ecx (standard function 1) 92 */ 93 94 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 95 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 96 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ 97 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 98 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 99 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 100 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 101 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 102 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 103 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 104 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 105 /* 0x00000800 - reserved */ 106 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ 107 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 108 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 109 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ 110 /* 0x00010000 - reserved */ 111 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ 112 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 113 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 114 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 115 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ 116 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 117 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 118 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ 119 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 120 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ 121 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ 122 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */ 123 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */ 124 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */ 125 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */ 126 127 /* 128 * cpuid instruction feature flags in %edx (extended function 0x80000001) 129 */ 130 131 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 132 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 133 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 134 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 135 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 136 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 137 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 138 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 139 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 140 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 141 /* 0x00000400 - sysc on K6m6 */ 142 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 143 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 144 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 145 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 146 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 147 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 148 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 149 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 150 /* 0x00040000 - reserved */ 151 /* 0x00080000 - reserved */ 152 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 153 /* 0x00200000 - reserved */ 154 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 155 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 156 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 157 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 158 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 159 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 160 /* 0x10000000 - reserved */ 161 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 162 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 163 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 164 165 /* 166 * AMD extended function 0x80000001 %ecx 167 */ 168 169 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 170 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 171 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 172 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 173 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 174 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 175 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 176 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 177 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 178 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 179 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 180 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */ 181 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 182 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 183 /* 0x00004000 - reserved */ 184 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ 185 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ 186 /* 0x00020000 - reserved */ 187 /* 0x00040000 - reserved */ 188 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ 189 /* 0x00100000 - reserved */ 190 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ 191 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ 192 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */ 193 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */ 194 /* 0x02000000 - reserved */ 195 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */ 196 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */ 197 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */ 198 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */ 199 /* 0x40000000 - reserved */ 200 /* 0x80000000 - reserved */ 201 202 /* 203 * AMD uses %ebx for some of their features (extended function 0x80000008). 204 */ 205 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */ 206 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */ 207 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */ 208 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */ 209 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */ 210 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */ 211 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ 212 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ 213 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ 214 #define CPUID_AMD_EBX_PPIN 0x000800000 /* AMD: PPIN Support */ 215 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ 216 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ 217 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ 218 219 /* 220 * AMD SVM features (extended function 0x8000000A). 221 */ 222 #define CPUID_AMD_EDX_NESTED_PAGING 0x000000001 /* AMD: SVM NP */ 223 #define CPUID_AMD_EDX_LBR_VIRT 0x000000002 /* AMD: LBR virt. */ 224 #define CPUID_AMD_EDX_SVML 0x000000004 /* AMD: SVM lock */ 225 #define CPUID_AMD_EDX_NRIPS 0x000000008 /* AMD: NRIP save */ 226 #define CPUID_AMD_EDX_TSC_RATE_MSR 0x000000010 /* AMD: MSR TSC ctrl */ 227 #define CPUID_AMD_EDX_VMCB_CLEAN 0x000000020 /* AMD: VMCB clean bits */ 228 #define CPUID_AMD_EDX_FLUSH_ASID 0x000000040 /* AMD: flush by ASID */ 229 #define CPUID_AMD_EDX_DECODE_ASSISTS 0x000000080 /* AMD: decode assists */ 230 231 /* 232 * Intel now seems to have claimed part of the "extended" function 233 * space that we previously for non-Intel implementors to use. 234 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 235 * is available in long mode i.e. what AMD indicate using bit 0. 236 * On the other hand, everything else is labelled as reserved. 237 */ 238 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 239 240 /* 241 * Intel uses cpuid leaf 6 to cover various thermal and power control 242 * operations. 243 */ 244 #define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */ 245 #define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */ 246 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */ 247 /* bit 3 is reserved */ 248 #define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */ 249 #define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */ 250 #define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */ 251 #define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */ 252 #define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */ 253 #define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */ 254 #define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */ 255 #define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */ 256 /* bit 12 is reserved */ 257 #define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */ 258 #define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */ 259 #define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */ 260 #define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */ 261 #define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */ 262 #define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */ 263 /* bit 19 is reserved */ 264 #define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */ 265 266 #define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf) 267 268 #define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */ 269 /* bits 1-2 are reserved */ 270 #define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */ 271 272 /* 273 * Intel also uses cpuid leaf 7 to have additional instructions and features. 274 * Like some other leaves, but unlike the current ones we care about, it 275 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal 276 * with the potential use of additional sub-leaves in the future, we now 277 * specifically label the EBX features with their leaf and sub-leaf. 278 */ 279 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */ 280 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */ 281 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */ 282 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ 283 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ 284 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ 285 /* Bit 6 is reserved */ 286 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ 287 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ 288 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */ 289 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */ 290 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */ 291 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */ 292 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */ 293 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ 294 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */ 295 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ 296 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ 297 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ 298 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ 299 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ 300 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ 301 /* Bit 22 is reserved */ 302 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */ 303 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ 304 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */ 305 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ 306 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ 307 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ 308 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ 309 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ 310 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ 311 312 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \ 313 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ 314 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ 315 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ 316 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) 317 318 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */ 319 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ 320 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ 321 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ 322 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ 323 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */ 324 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */ 325 /* bit 7 is reserved */ 326 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */ 327 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */ 328 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */ 329 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */ 330 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */ 331 /* bit 13 is reserved */ 332 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ 333 /* bits 15-16 are reserved */ 334 /* bits 17-21 are the value of MAWAU */ 335 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */ 336 /* bits 23-24 are reserved */ 337 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */ 338 /* bit 26 is resrved */ 339 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */ 340 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */ 341 /* bit 29 is reserved */ 342 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */ 343 /* bit 31 is reserved */ 344 345 /* 346 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and 347 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still 348 * valid when AVX512 is not. However, the following flags all are only valid 349 * when AVX512 is present. 350 */ 351 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \ 352 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \ 353 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) 354 355 /* bits 0-1 are reserved */ 356 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ 357 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ 358 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */ 359 /* bits 5-9 are reserved */ 360 #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */ 361 /* bits 11-17 are reserved */ 362 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */ 363 /* bits 19-26 are reserved */ 364 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */ 365 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */ 366 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */ 367 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */ 368 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */ 369 370 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \ 371 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) 372 373 /* 374 * Intel also uses cpuid leaf 0xd to report additional instructions and features 375 * when the sub-leaf in %ecx == 1. We label these using the same convention as 376 * with leaf 7. 377 */ 378 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ 379 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ 380 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ 381 382 #define REG_PAT 0x277 383 #define REG_TSC 0x10 /* timestamp counter */ 384 #define REG_APIC_BASE_MSR 0x1b 385 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 386 387 #if !defined(__xpv) 388 /* 389 * AMD C1E 390 */ 391 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 392 #define AMD_ACTONCMPHALT_SHIFT 27 393 #define AMD_ACTONCMPHALT_MASK 3 394 #endif 395 396 #define MSR_DEBUGCTL 0x1d9 397 398 #define DEBUGCTL_LBR 0x01 399 #define DEBUGCTL_BTF 0x02 400 401 /* Intel P6, AMD */ 402 #define MSR_LBR_FROM 0x1db 403 #define MSR_LBR_TO 0x1dc 404 #define MSR_LEX_FROM 0x1dd 405 #define MSR_LEX_TO 0x1de 406 407 /* Intel P4 (pre-Prescott, non P4 M) */ 408 #define MSR_P4_LBSTK_TOS 0x1da 409 #define MSR_P4_LBSTK_0 0x1db 410 #define MSR_P4_LBSTK_1 0x1dc 411 #define MSR_P4_LBSTK_2 0x1dd 412 #define MSR_P4_LBSTK_3 0x1de 413 414 /* Intel Pentium M */ 415 #define MSR_P6M_LBSTK_TOS 0x1c9 416 #define MSR_P6M_LBSTK_0 0x040 417 #define MSR_P6M_LBSTK_1 0x041 418 #define MSR_P6M_LBSTK_2 0x042 419 #define MSR_P6M_LBSTK_3 0x043 420 #define MSR_P6M_LBSTK_4 0x044 421 #define MSR_P6M_LBSTK_5 0x045 422 #define MSR_P6M_LBSTK_6 0x046 423 #define MSR_P6M_LBSTK_7 0x047 424 425 /* Intel P4 (Prescott) */ 426 #define MSR_PRP4_LBSTK_TOS 0x1da 427 #define MSR_PRP4_LBSTK_FROM_0 0x680 428 #define MSR_PRP4_LBSTK_FROM_1 0x681 429 #define MSR_PRP4_LBSTK_FROM_2 0x682 430 #define MSR_PRP4_LBSTK_FROM_3 0x683 431 #define MSR_PRP4_LBSTK_FROM_4 0x684 432 #define MSR_PRP4_LBSTK_FROM_5 0x685 433 #define MSR_PRP4_LBSTK_FROM_6 0x686 434 #define MSR_PRP4_LBSTK_FROM_7 0x687 435 #define MSR_PRP4_LBSTK_FROM_8 0x688 436 #define MSR_PRP4_LBSTK_FROM_9 0x689 437 #define MSR_PRP4_LBSTK_FROM_10 0x68a 438 #define MSR_PRP4_LBSTK_FROM_11 0x68b 439 #define MSR_PRP4_LBSTK_FROM_12 0x68c 440 #define MSR_PRP4_LBSTK_FROM_13 0x68d 441 #define MSR_PRP4_LBSTK_FROM_14 0x68e 442 #define MSR_PRP4_LBSTK_FROM_15 0x68f 443 #define MSR_PRP4_LBSTK_TO_0 0x6c0 444 #define MSR_PRP4_LBSTK_TO_1 0x6c1 445 #define MSR_PRP4_LBSTK_TO_2 0x6c2 446 #define MSR_PRP4_LBSTK_TO_3 0x6c3 447 #define MSR_PRP4_LBSTK_TO_4 0x6c4 448 #define MSR_PRP4_LBSTK_TO_5 0x6c5 449 #define MSR_PRP4_LBSTK_TO_6 0x6c6 450 #define MSR_PRP4_LBSTK_TO_7 0x6c7 451 #define MSR_PRP4_LBSTK_TO_8 0x6c8 452 #define MSR_PRP4_LBSTK_TO_9 0x6c9 453 #define MSR_PRP4_LBSTK_TO_10 0x6ca 454 #define MSR_PRP4_LBSTK_TO_11 0x6cb 455 #define MSR_PRP4_LBSTK_TO_12 0x6cc 456 #define MSR_PRP4_LBSTK_TO_13 0x6cd 457 #define MSR_PRP4_LBSTK_TO_14 0x6ce 458 #define MSR_PRP4_LBSTK_TO_15 0x6cf 459 460 /* 461 * PPIN definitions for Intel and AMD. Unfortunately, Intel and AMD use 462 * different MSRS for this and different MSRS to control whether or not it 463 * should be readable. 464 */ 465 #define MSR_PPIN_CTL_INTC 0x04e 466 #define MSR_PPIN_INTC 0x04f 467 #define MSR_PLATFORM_INFO 0x0ce 468 #define MSR_PLATFORM_INFO_PPIN (1 << 23) 469 470 #define MSR_PPIN_CTL_AMD 0xC00102F0 471 #define MSR_PPIN_AMD 0xC00102F1 472 473 /* 474 * These values are currently the same between Intel and AMD. 475 */ 476 #define MSR_PPIN_CTL_MASK 0x03 477 #define MSR_PPIN_CTL_DISABLED 0x00 478 #define MSR_PPIN_CTL_LOCKED 0x01 479 #define MSR_PPIN_CTL_ENABLED 0x02 480 481 /* 482 * Intel IA32_ARCH_CAPABILITIES MSR. 483 */ 484 #define MSR_IA32_ARCH_CAPABILITIES 0x10a 485 #define IA32_ARCH_CAP_RDCL_NO 0x0001 486 #define IA32_ARCH_CAP_IBRS_ALL 0x0002 487 #define IA32_ARCH_CAP_RSBA 0x0004 488 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008 489 #define IA32_ARCH_CAP_SSB_NO 0x0010 490 #define IA32_ARCH_CAP_MDS_NO 0x0020 491 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x0040 492 #define IA32_ARCH_CAP_TSX_CTRL 0x0080 493 #define IA32_ARCH_CAP_TAA_NO 0x0100 494 495 /* 496 * Intel Speculation related MSRs 497 */ 498 #define MSR_IA32_SPEC_CTRL 0x48 499 #define IA32_SPEC_CTRL_IBRS 0x01 500 #define IA32_SPEC_CTRL_STIBP 0x02 501 #define IA32_SPEC_CTRL_SSBD 0x04 502 503 #define MSR_IA32_PRED_CMD 0x49 504 #define IA32_PRED_CMD_IBPB 0x01 505 506 #define MSR_IA32_FLUSH_CMD 0x10b 507 #define IA32_FLUSH_CMD_L1D 0x01 508 509 /* 510 * Intel VMX related MSRs 511 */ 512 #define MSR_IA32_FEAT_CTRL 0x03a 513 #define IA32_FEAT_CTRL_LOCK 0x1 514 #define IA32_FEAT_CTRL_SMX_EN 0x2 515 #define IA32_FEAT_CTRL_VMX_EN 0x4 516 517 #define MSR_IA32_VMX_BASIC 0x480 518 #define IA32_VMX_BASIC_INS_OUTS (1UL << 54) 519 #define IA32_VMX_BASIC_TRUE_CTRLS (1UL << 55) 520 521 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 522 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 523 #define IA32_VMX_PROCBASED_2ND_CTLS (1UL << 31) 524 525 #define MSR_IA32_VMX_PROCBASED2_CTLS 0x48b 526 #define IA32_VMX_PROCBASED2_EPT (1UL << 1) 527 #define IA32_VMX_PROCBASED2_VPID (1UL << 5) 528 529 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 530 #define IA32_VMX_EPT_VPID_EXEC_ONLY (1UL << 0) 531 #define IA32_VMX_EPT_VPID_PWL4 (1UL << 6) 532 #define IA32_VMX_EPT_VPID_TYPE_UC (1UL << 8) 533 #define IA32_VMX_EPT_VPID_TYPE_WB (1UL << 14) 534 #define IA32_VMX_EPT_VPID_MAP_2M (1UL << 16) 535 #define IA32_VMX_EPT_VPID_MAP_1G (1UL << 17) 536 #define IA32_VMX_EPT_VPID_HW_AD (1UL << 21) 537 #define IA32_VMX_EPT_VPID_INVEPT (1UL << 20) 538 #define IA32_VMX_EPT_VPID_INVEPT_SINGLE (1UL << 25) 539 #define IA32_VMX_EPT_VPID_INVEPT_ALL (1UL << 26) 540 #define IA32_VMX_EPT_VPID_INVVPID (1UL << 32) 541 #define IA32_VMX_EPT_VPID_INVVPID_ADDR (1UL << 40) 542 #define IA32_VMX_EPT_VPID_INVVPID_SINGLE (1UL << 41) 543 #define IA32_VMX_EPT_VPID_INVVPID_ALL (1UL << 42) 544 #define IA32_VMX_EPT_VPID_INVVPID_RETAIN (1UL << 43) 545 546 /* 547 * Intel TSX Control MSRs 548 */ 549 #define MSR_IA32_TSX_CTRL 0x122 550 #define IA32_TSX_CTRL_RTM_DISABLE 0x01 551 #define IA32_TSX_CTRL_CPUID_CLEAR 0x02 552 553 /* 554 * Intel Thermal MSRs 555 */ 556 #define MSR_IA32_THERM_INTERRUPT 0x19b 557 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001 558 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002 559 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004 560 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008 561 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010 562 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 563 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000 564 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 565 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000 566 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000 567 568 #define MSR_IA32_THERM_STATUS 0x19c 569 #define IA32_THERM_STATUS_STATUS 0x00000001 570 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002 571 #define IA32_THERM_STATUS_PROCHOT 0x00000004 572 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008 573 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010 574 #define IA32_THERM_STATUS_CRIT_LOG 0x00000020 575 #define IA32_THERM_STATUS_TR1_STATUS 0x00000040 576 #define IA32_THERM_STATUS_TR1_LOG 0x00000080 577 #define IA32_THERM_STATUS_TR2_STATUS 0x00000100 578 #define IA32_THERM_STATUS_TR2_LOG 0x00000200 579 #define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400 580 #define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800 581 #define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000 582 #define IA32_THERM_STATUS_CURRENT_LOG 0x00002000 583 #define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000 584 #define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000 585 #define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 586 #define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f) 587 #define IA32_THERM_STATUS_READ_VALID 0x80000000 588 589 #define MSR_TEMPERATURE_TARGET 0x1a2 590 #define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff) 591 /* 592 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list 593 * of which models have support for which bits. 594 */ 595 #define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f) 596 597 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 598 #define IA32_PKG_THERM_STATUS_STATUS 0x00000001 599 #define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002 600 #define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004 601 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008 602 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010 603 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020 604 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040 605 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080 606 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100 607 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200 608 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) 609 610 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 611 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001 612 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002 613 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004 614 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010 615 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) 616 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000 617 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) 618 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 619 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 620 621 /* 622 * AMD TOM and TOM2 MSRs. These control the split between DRAM and MMIO below 623 * and above 4 GiB respectively. These have existed since family 0xf. 624 */ 625 #define MSR_AMD_TOM 0xc001001a 626 #define MSR_AMD_TOM_MASK(x) ((x) & 0xffffff800000) 627 #define MSR_AMD_TOM2 0xc001001d 628 #define MSR_AMD_TOM2_MASK(x) ((x) & 0xffffff800000) 629 630 631 #define MCI_CTL_VALUE 0xffffffff 632 633 #define MTRR_TYPE_UC 0 634 #define MTRR_TYPE_WC 1 635 #define MTRR_TYPE_WT 4 636 #define MTRR_TYPE_WP 5 637 #define MTRR_TYPE_WB 6 638 #define MTRR_TYPE_UC_ 7 639 640 /* 641 * For Solaris we set up the page attritubute table in the following way: 642 * PAT0 Write-Back 643 * PAT1 Write-Through 644 * PAT2 Unchacheable- 645 * PAT3 Uncacheable 646 * PAT4 Write-Back 647 * PAT5 Write-Through 648 * PAT6 Write-Combine 649 * PAT7 Uncacheable 650 * The only difference from h/w default is entry 6. 651 */ 652 #define PAT_DEFAULT_ATTRIBUTE \ 653 ((uint64_t)MTRR_TYPE_WB | \ 654 ((uint64_t)MTRR_TYPE_WT << 8) | \ 655 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 656 ((uint64_t)MTRR_TYPE_UC << 24) | \ 657 ((uint64_t)MTRR_TYPE_WB << 32) | \ 658 ((uint64_t)MTRR_TYPE_WT << 40) | \ 659 ((uint64_t)MTRR_TYPE_WC << 48) | \ 660 ((uint64_t)MTRR_TYPE_UC << 56)) 661 662 #define X86FSET_LARGEPAGE 0 663 #define X86FSET_TSC 1 664 #define X86FSET_MSR 2 665 #define X86FSET_MTRR 3 666 #define X86FSET_PGE 4 667 #define X86FSET_DE 5 668 #define X86FSET_CMOV 6 669 #define X86FSET_MMX 7 670 #define X86FSET_MCA 8 671 #define X86FSET_PAE 9 672 #define X86FSET_CX8 10 673 #define X86FSET_PAT 11 674 #define X86FSET_SEP 12 675 #define X86FSET_SSE 13 676 #define X86FSET_SSE2 14 677 #define X86FSET_HTT 15 678 #define X86FSET_ASYSC 16 679 #define X86FSET_NX 17 680 #define X86FSET_SSE3 18 681 #define X86FSET_CX16 19 682 #define X86FSET_CMP 20 683 #define X86FSET_TSCP 21 684 #define X86FSET_MWAIT 22 685 #define X86FSET_SSE4A 23 686 #define X86FSET_CPUID 24 687 #define X86FSET_SSSE3 25 688 #define X86FSET_SSE4_1 26 689 #define X86FSET_SSE4_2 27 690 #define X86FSET_1GPG 28 691 #define X86FSET_CLFSH 29 692 #define X86FSET_64 30 693 #define X86FSET_AES 31 694 #define X86FSET_PCLMULQDQ 32 695 #define X86FSET_XSAVE 33 696 #define X86FSET_AVX 34 697 #define X86FSET_VMX 35 698 #define X86FSET_SVM 36 699 #define X86FSET_TOPOEXT 37 700 #define X86FSET_F16C 38 701 #define X86FSET_RDRAND 39 702 #define X86FSET_X2APIC 40 703 #define X86FSET_AVX2 41 704 #define X86FSET_BMI1 42 705 #define X86FSET_BMI2 43 706 #define X86FSET_FMA 44 707 #define X86FSET_SMEP 45 708 #define X86FSET_SMAP 46 709 #define X86FSET_ADX 47 710 #define X86FSET_RDSEED 48 711 #define X86FSET_MPX 49 712 #define X86FSET_AVX512F 50 713 #define X86FSET_AVX512DQ 51 714 #define X86FSET_AVX512PF 52 715 #define X86FSET_AVX512ER 53 716 #define X86FSET_AVX512CD 54 717 #define X86FSET_AVX512BW 55 718 #define X86FSET_AVX512VL 56 719 #define X86FSET_AVX512FMA 57 720 #define X86FSET_AVX512VBMI 58 721 #define X86FSET_AVX512VPOPCDQ 59 722 #define X86FSET_AVX512NNIW 60 723 #define X86FSET_AVX512FMAPS 61 724 #define X86FSET_XSAVEOPT 62 725 #define X86FSET_XSAVEC 63 726 #define X86FSET_XSAVES 64 727 #define X86FSET_SHA 65 728 #define X86FSET_UMIP 66 729 #define X86FSET_PKU 67 730 #define X86FSET_OSPKE 68 731 #define X86FSET_PCID 69 732 #define X86FSET_INVPCID 70 733 #define X86FSET_IBRS 71 734 #define X86FSET_IBPB 72 735 #define X86FSET_STIBP 73 736 #define X86FSET_SSBD 74 737 #define X86FSET_SSBD_VIRT 75 738 #define X86FSET_RDCL_NO 76 739 #define X86FSET_IBRS_ALL 77 740 #define X86FSET_RSBA 78 741 #define X86FSET_SSB_NO 79 742 #define X86FSET_STIBP_ALL 80 743 #define X86FSET_FLUSH_CMD 81 744 #define X86FSET_L1D_VM_NO 82 745 #define X86FSET_FSGSBASE 83 746 #define X86FSET_CLFLUSHOPT 84 747 #define X86FSET_CLWB 85 748 #define X86FSET_MONITORX 86 749 #define X86FSET_CLZERO 87 750 #define X86FSET_XOP 88 751 #define X86FSET_FMA4 89 752 #define X86FSET_TBM 90 753 #define X86FSET_AVX512VNNI 91 754 #define X86FSET_AMD_PCEC 92 755 #define X86FSET_MD_CLEAR 93 756 #define X86FSET_MDS_NO 94 757 #define X86FSET_CORE_THERMAL 95 758 #define X86FSET_PKG_THERMAL 96 759 #define X86FSET_TSX_CTRL 97 760 #define X86FSET_TAA_NO 98 761 #define X86FSET_PPIN 99 762 #define X86FSET_VAES 100 763 #define X86FSET_VPCLMULQDQ 101 764 #define X86FSET_LFENCE_SER 102 765 766 /* 767 * Intel Deep C-State invariant TSC in leaf 0x80000007. 768 */ 769 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 770 771 /* 772 * Intel TSC deadline timer 773 */ 774 #define CPUID_DEADLINE_TSC (1 << 24) 775 776 /* 777 * x86_type is a legacy concept; this is supplanted 778 * for most purposes by x86_featureset; modern CPUs 779 * should be X86_TYPE_OTHER 780 */ 781 #define X86_TYPE_OTHER 0 782 #define X86_TYPE_486 1 783 #define X86_TYPE_P5 2 784 #define X86_TYPE_P6 3 785 #define X86_TYPE_CYRIX_486 4 786 #define X86_TYPE_CYRIX_6x86L 5 787 #define X86_TYPE_CYRIX_6x86 6 788 #define X86_TYPE_CYRIX_GXm 7 789 #define X86_TYPE_CYRIX_6x86MX 8 790 #define X86_TYPE_CYRIX_MediaGX 9 791 #define X86_TYPE_CYRIX_MII 10 792 #define X86_TYPE_VIA_CYRIX_III 11 793 #define X86_TYPE_P4 12 794 795 /* 796 * x86_vendor allows us to select between 797 * implementation features and helps guide 798 * the interpretation of the cpuid instruction. 799 */ 800 #define X86_VENDOR_Intel 0 801 #define X86_VENDORSTR_Intel "GenuineIntel" 802 803 #define X86_VENDOR_IntelClone 1 804 805 #define X86_VENDOR_AMD 2 806 #define X86_VENDORSTR_AMD "AuthenticAMD" 807 808 #define X86_VENDOR_Cyrix 3 809 #define X86_VENDORSTR_CYRIX "CyrixInstead" 810 811 #define X86_VENDOR_UMC 4 812 #define X86_VENDORSTR_UMC "UMC UMC UMC " 813 814 #define X86_VENDOR_NexGen 5 815 #define X86_VENDORSTR_NexGen "NexGenDriven" 816 817 #define X86_VENDOR_Centaur 6 818 #define X86_VENDORSTR_Centaur "CentaurHauls" 819 820 #define X86_VENDOR_Rise 7 821 #define X86_VENDORSTR_Rise "RiseRiseRise" 822 823 #define X86_VENDOR_SiS 8 824 #define X86_VENDORSTR_SiS "SiS SiS SiS " 825 826 #define X86_VENDOR_TM 9 827 #define X86_VENDORSTR_TM "GenuineTMx86" 828 829 #define X86_VENDOR_NSC 10 830 #define X86_VENDORSTR_NSC "Geode by NSC" 831 832 #define X86_VENDOR_HYGON 11 833 #define X86_VENDORSTR_HYGON "HygonGenuine" 834 835 /* 836 * Vendor string max len + \0 837 */ 838 #define X86_VENDOR_STRLEN 13 839 840 /* 841 * For lookups and matching functions only; not an actual vendor. 842 */ 843 #define _X86_VENDOR_MATCH_ALL 0xff 844 845 /* 846 * See the big theory statement at the top of cpuid.c for information about how 847 * processor families and microarchitecture families relate to cpuid families, 848 * models, and steppings. 849 */ 850 851 #define _X86_CHIPREV_VENDOR_SHIFT 24 852 #define _X86_CHIPREV_FAMILY_SHIFT 16 853 854 #define _X86_CHIPREV_VENDOR(x) \ 855 bitx32((uint32_t)(x), 31, _X86_CHIPREV_VENDOR_SHIFT) 856 857 #define _X86_CHIPREV_FAMILY(x) \ 858 bitx32((uint32_t)(x), 23, _X86_CHIPREV_FAMILY_SHIFT) 859 860 #define _X86_CHIPREV_REV(x) \ 861 bitx32((uint32_t)(x), 15, 0) 862 863 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 864 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 865 (uint32_t)(family) << _X86_CHIPREV_FAMILY_SHIFT | (uint32_t)(rev)) 866 867 /* 868 * The legacy families here are a little bit unfortunate. Part of this is that 869 * the way AMD used the cpuid family/model/stepping changed somewhat over time, 870 * but the more immediate reason it's this way is more that the way we use 871 * chiprev/processor family changed with it. The ancient amd_opteron and mc-amd 872 * drivers used the chiprevs that were based on cpuid family, mainly 0xf and 873 * 0x10. amdzen_umc wants the processor family, in part because AMD's 874 * overloading of the cpuid family has made it effectively useless for 875 * discerning anything about the processor. That also tied into the way 876 * amd_revmap was previously organised in cpuid_subr.c: up to family 0x14 877 * everything was just "rev A", "rev B", etc.; afterward we started using the 878 * new shorthand, again tied to how AMD was presenting this information. 879 * Because there are other consumers of the processor family, it no longer made 880 * sense for amdzen to derive the processor family from the cpuid family/model 881 * given that we have this collection of definitions already and code in 882 * cpuid_subr.c to make use of them. The result is this unified approach that 883 * tries to keep old consumers happy while allowing new ones to get the degree 884 * of detail they need and expect. That required bending things a bit to make 885 * them fit, though critically as long as AMD keep on their current path and all 886 * new consumers look like the ones we are adding these days, we will be able to 887 * continue making new additions that will match all the recent ones and the way 888 * AMD are currently using families and models. There is absolutely no reason 889 * we couldn't go back and dig through all the legacy parts and break them down 890 * the same way, then change the old MC and CPU drivers to match, but I didn't 891 * feel like doing a lot of work for processors that it's unlikely anyone is 892 * still using and even more unlikely anyone will introduce new code to support. 893 * My compromise was to flesh things out starting where we already had more 894 * detail even if nothing was consuming it programmatically: at 0x15. Before 895 * that, processor family and cpuid family were effectively the same, because 896 * that's what those old consumers expect. 897 */ 898 899 #ifndef _ASM 900 typedef enum x86_processor_family { 901 X86_PF_UNKNOWN, 902 X86_PF_AMD_LEGACY_F = 0xf, 903 X86_PF_AMD_LEGACY_10 = 0x10, 904 X86_PF_AMD_LEGACY_11 = 0x11, 905 X86_PF_AMD_LEGACY_12 = 0x12, 906 X86_PF_AMD_LEGACY_14 = 0x14, 907 X86_PF_AMD_OROCHI, 908 X86_PF_AMD_TRINITY, 909 X86_PF_AMD_KAVERI, 910 X86_PF_AMD_CARRIZO, 911 X86_PF_AMD_STONEY_RIDGE, 912 X86_PF_AMD_KABINI, 913 X86_PF_AMD_MULLINS, 914 X86_PF_AMD_NAPLES, 915 X86_PF_AMD_PINNACLE_RIDGE, 916 X86_PF_AMD_RAVEN_RIDGE, 917 X86_PF_AMD_PICASSO, 918 X86_PF_AMD_DALI, 919 X86_PF_AMD_ROME, 920 X86_PF_AMD_RENOIR, 921 X86_PF_AMD_MATISSE, 922 X86_PF_AMD_VAN_GOGH, 923 X86_PF_AMD_MENDOCINO, 924 X86_PF_HYGON_DHYANA, 925 X86_PF_AMD_MILAN, 926 X86_PF_AMD_GENOA, 927 X86_PF_AMD_VERMEER, 928 X86_PF_AMD_REMBRANDT, 929 X86_PF_AMD_CEZANNE, 930 X86_PF_AMD_RAPHAEL, 931 932 X86_PF_ANY = 0xff 933 } x86_processor_family_t; 934 935 #define _DECL_CHIPREV(_v, _f, _revn, _revb) \ 936 X86_CHIPREV_ ## _v ## _ ## _f ## _ ## _revn = \ 937 _X86_CHIPREV_MKREV(X86_VENDOR_ ## _v, X86_PF_ ## _v ## _ ## _f, _revb) 938 939 #define _X86_CHIPREV_REV_MATCH_ALL 0xffff 940 941 typedef enum x86_chiprev { 942 X86_CHIPREV_UNKNOWN, 943 _DECL_CHIPREV(AMD, LEGACY_F, REV_B, 0x0001), 944 /* 945 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 946 * sufficiently different that we will distinguish them; in all other 947 * case we will identify the major revision. 948 */ 949 _DECL_CHIPREV(AMD, LEGACY_F, REV_C0, 0x0002), 950 _DECL_CHIPREV(AMD, LEGACY_F, REV_CG, 0x0004), 951 _DECL_CHIPREV(AMD, LEGACY_F, REV_D, 0x0008), 952 _DECL_CHIPREV(AMD, LEGACY_F, REV_E, 0x0010), 953 _DECL_CHIPREV(AMD, LEGACY_F, REV_F, 0x0020), 954 _DECL_CHIPREV(AMD, LEGACY_F, REV_G, 0x0040), 955 _DECL_CHIPREV(AMD, LEGACY_F, ANY, _X86_CHIPREV_REV_MATCH_ALL), 956 957 _DECL_CHIPREV(AMD, LEGACY_10, UNKNOWN, 0x0001), 958 _DECL_CHIPREV(AMD, LEGACY_10, REV_A, 0x0002), 959 _DECL_CHIPREV(AMD, LEGACY_10, REV_B, 0x0004), 960 _DECL_CHIPREV(AMD, LEGACY_10, REV_C2, 0x0008), 961 _DECL_CHIPREV(AMD, LEGACY_10, REV_C3, 0x0010), 962 _DECL_CHIPREV(AMD, LEGACY_10, REV_D0, 0x0020), 963 _DECL_CHIPREV(AMD, LEGACY_10, REV_D1, 0x0040), 964 _DECL_CHIPREV(AMD, LEGACY_10, REV_E, 0x0080), 965 _DECL_CHIPREV(AMD, LEGACY_10, ANY, _X86_CHIPREV_REV_MATCH_ALL), 966 967 _DECL_CHIPREV(AMD, LEGACY_11, UNKNOWN, 0x0001), 968 _DECL_CHIPREV(AMD, LEGACY_11, REV_B, 0x0002), 969 _DECL_CHIPREV(AMD, LEGACY_11, ANY, _X86_CHIPREV_REV_MATCH_ALL), 970 971 _DECL_CHIPREV(AMD, LEGACY_12, UNKNOWN, 0x0001), 972 _DECL_CHIPREV(AMD, LEGACY_12, REV_B, 0x0002), 973 _DECL_CHIPREV(AMD, LEGACY_12, ANY, _X86_CHIPREV_REV_MATCH_ALL), 974 975 _DECL_CHIPREV(AMD, LEGACY_14, UNKNOWN, 0x0001), 976 _DECL_CHIPREV(AMD, LEGACY_14, REV_B, 0x0002), 977 _DECL_CHIPREV(AMD, LEGACY_14, REV_C, 0x0004), 978 _DECL_CHIPREV(AMD, LEGACY_14, ANY, _X86_CHIPREV_REV_MATCH_ALL), 979 980 _DECL_CHIPREV(AMD, OROCHI, UNKNOWN, 0x0001), 981 _DECL_CHIPREV(AMD, OROCHI, REV_B2, 0x0002), 982 _DECL_CHIPREV(AMD, OROCHI, REV_C0, 0x0004), 983 _DECL_CHIPREV(AMD, OROCHI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 984 985 _DECL_CHIPREV(AMD, TRINITY, UNKNOWN, 0x0001), 986 _DECL_CHIPREV(AMD, TRINITY, REV_A1, 0x0002), 987 _DECL_CHIPREV(AMD, TRINITY, ANY, _X86_CHIPREV_REV_MATCH_ALL), 988 989 _DECL_CHIPREV(AMD, KAVERI, UNKNOWN, 0x0001), 990 _DECL_CHIPREV(AMD, KAVERI, REV_A1, 0x0002), 991 _DECL_CHIPREV(AMD, KAVERI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 992 993 _DECL_CHIPREV(AMD, CARRIZO, UNKNOWN, 0x0001), 994 _DECL_CHIPREV(AMD, CARRIZO, REV_A0, 0x0002), 995 _DECL_CHIPREV(AMD, CARRIZO, REV_A1, 0x0004), 996 _DECL_CHIPREV(AMD, CARRIZO, REV_DDR4, 0x0008), 997 _DECL_CHIPREV(AMD, CARRIZO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 998 999 _DECL_CHIPREV(AMD, STONEY_RIDGE, UNKNOWN, 0x0001), 1000 _DECL_CHIPREV(AMD, STONEY_RIDGE, REV_A0, 0x0002), 1001 _DECL_CHIPREV(AMD, STONEY_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1002 1003 _DECL_CHIPREV(AMD, KABINI, UNKNOWN, 0x0001), 1004 _DECL_CHIPREV(AMD, KABINI, A1, 0x0002), 1005 _DECL_CHIPREV(AMD, KABINI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1006 1007 _DECL_CHIPREV(AMD, MULLINS, UNKNOWN, 0x0001), 1008 _DECL_CHIPREV(AMD, MULLINS, A1, 0x0002), 1009 _DECL_CHIPREV(AMD, MULLINS, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1010 1011 _DECL_CHIPREV(AMD, NAPLES, UNKNOWN, 0x0001), 1012 _DECL_CHIPREV(AMD, NAPLES, A0, 0x0002), 1013 _DECL_CHIPREV(AMD, NAPLES, B1, 0x0004), 1014 _DECL_CHIPREV(AMD, NAPLES, B2, 0x0008), 1015 _DECL_CHIPREV(AMD, NAPLES, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1016 1017 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, UNKNOWN, 0x0001), 1018 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, B2, 0x0002), 1019 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1020 1021 _DECL_CHIPREV(AMD, RAVEN_RIDGE, UNKNOWN, 0x0001), 1022 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B0, 0x0002), 1023 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B1, 0x0004), 1024 _DECL_CHIPREV(AMD, RAVEN_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1025 1026 _DECL_CHIPREV(AMD, PICASSO, UNKNOWN, 0x0001), 1027 _DECL_CHIPREV(AMD, PICASSO, B1, 0x0002), 1028 _DECL_CHIPREV(AMD, PICASSO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1029 1030 _DECL_CHIPREV(AMD, DALI, UNKNOWN, 0x0001), 1031 _DECL_CHIPREV(AMD, DALI, A1, 0x0002), 1032 _DECL_CHIPREV(AMD, DALI, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1033 1034 _DECL_CHIPREV(AMD, ROME, UNKNOWN, 0x0001), 1035 _DECL_CHIPREV(AMD, ROME, A0, 0x0002), 1036 _DECL_CHIPREV(AMD, ROME, B0, 0x0004), 1037 _DECL_CHIPREV(AMD, ROME, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1038 1039 _DECL_CHIPREV(AMD, RENOIR, UNKNOWN, 0x0001), 1040 _DECL_CHIPREV(AMD, RENOIR, A1, 0x0002), 1041 _DECL_CHIPREV(AMD, RENOIR, LCN_A1, 0x0004), 1042 _DECL_CHIPREV(AMD, RENOIR, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1043 1044 _DECL_CHIPREV(AMD, MATISSE, UNKNOWN, 0x0001), 1045 _DECL_CHIPREV(AMD, MATISSE, B0, 0x0002), 1046 _DECL_CHIPREV(AMD, MATISSE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1047 1048 _DECL_CHIPREV(AMD, VAN_GOGH, UNKNOWN, 0x0001), 1049 _DECL_CHIPREV(AMD, VAN_GOGH, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1050 1051 _DECL_CHIPREV(AMD, MENDOCINO, UNKNOWN, 0x0001), 1052 _DECL_CHIPREV(AMD, MENDOCINO, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1053 1054 _DECL_CHIPREV(HYGON, DHYANA, UNKNOWN, 0x0001), 1055 _DECL_CHIPREV(HYGON, DHYANA, A1, 0x0002), 1056 _DECL_CHIPREV(HYGON, DHYANA, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1057 1058 _DECL_CHIPREV(AMD, MILAN, UNKNOWN, 0x0001), 1059 _DECL_CHIPREV(AMD, MILAN, A0, 0x0002), 1060 _DECL_CHIPREV(AMD, MILAN, B0, 0x0004), 1061 _DECL_CHIPREV(AMD, MILAN, B1, 0x0008), 1062 _DECL_CHIPREV(AMD, MILAN, B2, 0x0010), 1063 _DECL_CHIPREV(AMD, MILAN, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1064 1065 _DECL_CHIPREV(AMD, GENOA, UNKNOWN, 0x0001), 1066 _DECL_CHIPREV(AMD, GENOA, A0, 0x0002), 1067 _DECL_CHIPREV(AMD, GENOA, A1, 0x0004), 1068 _DECL_CHIPREV(AMD, GENOA, B0, 0x0008), 1069 _DECL_CHIPREV(AMD, GENOA, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1070 1071 _DECL_CHIPREV(AMD, VERMEER, UNKNOWN, 0x0001), 1072 _DECL_CHIPREV(AMD, VERMEER, A0, 0x0002), 1073 _DECL_CHIPREV(AMD, VERMEER, B0, 0x0004), 1074 _DECL_CHIPREV(AMD, VERMEER, B2, 0x0008), /* No B1 */ 1075 _DECL_CHIPREV(AMD, VERMEER, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1076 1077 _DECL_CHIPREV(AMD, REMBRANDT, UNKNOWN, 0x0001), 1078 _DECL_CHIPREV(AMD, REMBRANDT, A0, 0x0002), 1079 _DECL_CHIPREV(AMD, REMBRANDT, B0, 0x0004), 1080 _DECL_CHIPREV(AMD, REMBRANDT, B1, 0x0008), 1081 _DECL_CHIPREV(AMD, REMBRANDT, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1082 1083 _DECL_CHIPREV(AMD, CEZANNE, UNKNOWN, 0x0001), 1084 _DECL_CHIPREV(AMD, CEZANNE, A0, 0x0002), 1085 _DECL_CHIPREV(AMD, CEZANNE, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1086 1087 _DECL_CHIPREV(AMD, RAPHAEL, UNKNOWN, 0x0001), 1088 _DECL_CHIPREV(AMD, RAPHAEL, ANY, _X86_CHIPREV_REV_MATCH_ALL), 1089 1090 /* Keep at the end */ 1091 X86_CHIPREV_ANY = _X86_CHIPREV_MKREV(_X86_VENDOR_MATCH_ALL, X86_PF_ANY, 1092 _X86_CHIPREV_REV_MATCH_ALL) 1093 } x86_chiprev_t; 1094 1095 #undef _DECL_CHIPREV 1096 1097 /* 1098 * Same thing, but for microarchitecture (core implementations). We are not 1099 * attempting to capture every possible fine-grained detail here; to the extent 1100 * that it matters, we do so in cpuid.c via ISA/feature bits. We use the same 1101 * number of bits for each field as in chiprev. 1102 */ 1103 1104 #define _X86_UARCHREV_VENDOR(x) _X86_CHIPREV_VENDOR(x) 1105 #define _X86_UARCHREV_UARCH(x) _X86_CHIPREV_FAMILY(x) 1106 #define _X86_UARCHREV_REV(x) _X86_CHIPREV_REV(x) 1107 1108 #define _X86_UARCHREV_MKREV(vendor, family, rev) \ 1109 _X86_CHIPREV_MKREV(vendor, family, rev) 1110 1111 typedef enum x86_uarch { 1112 X86_UARCH_UNKNOWN, 1113 1114 X86_UARCH_AMD_LEGACY, 1115 X86_UARCH_AMD_ZEN1, 1116 X86_UARCH_AMD_ZENPLUS, 1117 X86_UARCH_AMD_ZEN2, 1118 X86_UARCH_AMD_ZEN3, 1119 X86_UARCH_AMD_ZEN4, 1120 1121 X86_UARCH_ANY = 0xff 1122 } x86_uarch_t; 1123 1124 #define _DECL_UARCHREV(_v, _f, _revn, _revb) \ 1125 X86_UARCHREV_ ## _v ## _ ## _f ## _ ## _revn = \ 1126 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \ 1127 _revb) 1128 1129 #define _DECL_UARCHREV_NOREV(_v, _f, _revb) \ 1130 X86_UARCHREV_ ## _v ## _ ## _f = \ 1131 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \ 1132 _revb) 1133 1134 #define _X86_UARCHREV_REV_MATCH_ALL 0xffff 1135 1136 typedef enum x86_uarchrev { 1137 X86_UARCHREV_UNKNOWN, 1138 _DECL_UARCHREV_NOREV(AMD, LEGACY, 0x0001), 1139 _DECL_UARCHREV(AMD, LEGACY, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1140 1141 _DECL_UARCHREV_NOREV(AMD, ZEN1, 0x0001), 1142 _DECL_UARCHREV(AMD, ZEN1, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1143 1144 _DECL_UARCHREV_NOREV(AMD, ZENPLUS, 0x0001), 1145 _DECL_UARCHREV(AMD, ZENPLUS, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1146 1147 _DECL_UARCHREV(AMD, ZEN2, UNKNOWN, 0x0001), 1148 _DECL_UARCHREV(AMD, ZEN2, A0, 0x0002), 1149 _DECL_UARCHREV(AMD, ZEN2, B0, 0x0004), 1150 _DECL_UARCHREV(AMD, ZEN2, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1151 1152 _DECL_UARCHREV(AMD, ZEN3, UNKNOWN, 0x0001), 1153 _DECL_UARCHREV(AMD, ZEN3, A0, 0x0002), 1154 _DECL_UARCHREV(AMD, ZEN3, B0, 0x0004), 1155 _DECL_UARCHREV(AMD, ZEN3, B1, 0x0008), 1156 _DECL_UARCHREV(AMD, ZEN3, B2, 0x0010), 1157 _DECL_UARCHREV(AMD, ZEN3, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1158 1159 _DECL_UARCHREV_NOREV(AMD, ZEN4, 0x0001), 1160 _DECL_UARCHREV(AMD, ZEN4, ANY, _X86_UARCHREV_REV_MATCH_ALL), 1161 1162 /* Keep at the end */ 1163 _X86_UARCHREV_ANY = _X86_UARCHREV_MKREV(_X86_VENDOR_MATCH_ALL, 1164 X86_UARCH_ANY, _X86_UARCHREV_REV_MATCH_ALL) 1165 } x86_uarchrev_t; 1166 1167 #undef _DECL_UARCHREV 1168 1169 #endif /* !_ASM */ 1170 1171 /* 1172 * Various socket/package types, extended as the need to distinguish 1173 * a new type arises. The top 8 byte identfies the vendor and the 1174 * remaining 24 bits describe 24 socket types. 1175 */ 1176 1177 #define _X86_SOCKET_VENDOR_SHIFT 24 1178 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 1179 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 1180 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 1181 1182 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 1183 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 1184 1185 #define X86_SOCKET_MATCH(s, mask) \ 1186 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 1187 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 1188 1189 #define X86_SOCKET_UNKNOWN 0x0 1190 /* 1191 * AMD socket types 1192 */ 1193 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01) 1194 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02) 1195 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03) 1196 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04) 1197 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05) 1198 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06) 1199 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07) 1200 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08) 1201 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09) 1202 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a) 1203 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b) 1204 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c) 1205 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d) 1206 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e) 1207 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f) 1208 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10) 1209 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11) 1210 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12) 1211 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13) 1212 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14) 1213 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15) 1214 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16) 1215 #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17) 1216 #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18) 1217 #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19) 1218 #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a) 1219 #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b) 1220 #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c) 1221 #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d) 1222 #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e) 1223 #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f) 1224 #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20) 1225 #define X86_SOCKET_FP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x21) 1226 #define X86_SOCKET_FP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x22) 1227 #define X86_SOCKET_STRX4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x23) 1228 #define X86_SOCKET_SP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x24) 1229 #define X86_SOCKET_AM5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x25) 1230 #define X86_SOCKET_FP7 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x26) 1231 #define X86_SOCKET_FP7R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x27) 1232 #define X86_SOCKET_FF3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x28) 1233 #define X86_NUM_SOCKETS_AMD 0x28 1234 1235 /* 1236 * Hygon socket types 1237 */ 1238 #define X86_SOCKET_SL1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x01) 1239 #define X86_SOCKET_SL1R2 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x02) 1240 #define X86_SOCKET_DM1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x03) 1241 #define X86_NUM_SOCKETS_HYGON 0x03 1242 1243 #define X86_NUM_SOCKETS (X86_NUM_SOCKETS_AMD + X86_NUM_SOCKETS_HYGON) 1244 1245 /* 1246 * Definitions for Intel processor models. These are all for Family 6 1247 * processors. This list and the Atom set below it are not exhuastive. 1248 */ 1249 #define INTC_MODEL_YONAH 0x0e 1250 #define INTC_MODEL_MEROM 0x0f 1251 #define INTC_MODEL_MEROM_L 0x16 1252 #define INTC_MODEL_PENRYN 0x17 1253 #define INTC_MODEL_DUNNINGTON 0x1d 1254 1255 #define INTC_MODEL_NEHALEM 0x1e 1256 #define INTC_MODEL_NEHALEM2 0x1f 1257 #define INTC_MODEL_NEHALEM_EP 0x1a 1258 #define INTC_MODEL_NEHALEM_EX 0x2e 1259 1260 #define INTC_MODEL_WESTMERE 0x25 1261 #define INTC_MODEL_WESTMERE_EP 0x2c 1262 #define INTC_MODEL_WESTMERE_EX 0x2f 1263 1264 #define INTC_MODEL_SANDYBRIDGE 0x2a 1265 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d 1266 #define INTC_MODEL_IVYBRIDGE 0x3a 1267 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e 1268 1269 #define INTC_MODEL_HASWELL 0x3c 1270 #define INTC_MODEL_HASWELL_ULT 0x45 1271 #define INTC_MODEL_HASWELL_GT3E 0x46 1272 #define INTC_MODEL_HASWELL_XEON 0x3f 1273 1274 #define INTC_MODEL_BROADWELL 0x3d 1275 #define INTC_MODEL_BROADELL_2 0x47 1276 #define INTC_MODEL_BROADWELL_XEON 0x4f 1277 #define INTC_MODEL_BROADWELL_XEON_D 0x56 1278 1279 #define INTC_MODEL_SKYLAKE_MOBILE 0x4e 1280 /* 1281 * Note, this model is shared with Cascade Lake and Cooper Lake. 1282 */ 1283 #define INTC_MODEL_SKYLAKE_XEON 0x55 1284 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e 1285 1286 /* 1287 * Note, both Kaby Lake models are shared with Coffee Lake, Whiskey Lake, Amber 1288 * Lake, and some Comet Lake parts. 1289 */ 1290 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e 1291 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e 1292 1293 #define INTC_MODEL_ICELAKE_XEON 0x6a 1294 #define INTC_MODEL_ICELAKE_MOBILE 0x7e 1295 #define INTC_MODEL_TIGERLAKE_MOBILE 0x8c 1296 1297 #define INTC_MODEL_COMETLAKE 0xa5 1298 #define INTC_MODEL_COMETLAKE_MOBILE 0xa6 1299 #define INTC_MODEL_ROCKETLAKE 0xa7 1300 1301 /* 1302 * Atom Processors 1303 */ 1304 #define INTC_MODEL_SILVERTHORNE 0x1c 1305 #define INTC_MODEL_LINCROFT 0x26 1306 #define INTC_MODEL_PENWELL 0x27 1307 #define INTC_MODEL_CLOVERVIEW 0x35 1308 #define INTC_MODEL_CEDARVIEW 0x36 1309 #define INTC_MODEL_BAY_TRAIL 0x37 1310 #define INTC_MODEL_AVATON 0x4d 1311 #define INTC_MODEL_AIRMONT 0x4c 1312 #define INTC_MODEL_GOLDMONT 0x5c 1313 #define INTC_MODEL_DENVERTON 0x5f 1314 #define INTC_MODEL_GEMINI_LAKE 0x7a 1315 1316 /* 1317 * xgetbv/xsetbv support 1318 * See section 13.3 in vol. 1 of the Intel devlopers manual. 1319 */ 1320 1321 #define XFEATURE_ENABLED_MASK 0x0 1322 /* 1323 * XFEATURE_ENABLED_MASK values (eax) 1324 * See setup_xfem(). 1325 */ 1326 #define XFEATURE_LEGACY_FP 0x1 1327 #define XFEATURE_SSE 0x2 1328 #define XFEATURE_AVX 0x4 1329 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ 1330 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ 1331 /* bit 8 unused */ 1332 #define XFEATURE_PKRU 0x200 1333 #define XFEATURE_FP_ALL \ 1334 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ 1335 XFEATURE_AVX512 | XFEATURE_PKRU) 1336 1337 /* 1338 * Define the set of xfeature flags that should be considered valid in the xsave 1339 * state vector when we initialize an lwp. This is distinct from the full set so 1340 * that all of the processor's normal logic and tracking of the xsave state is 1341 * usable. This should correspond to the state that's been initialized by the 1342 * ABI to hold meaningful values. Adding additional bits here can have serious 1343 * performance implications and cause performance degradations when using the 1344 * FPU vector (xmm) registers. 1345 */ 1346 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE) 1347 1348 #if !defined(_ASM) 1349 1350 #if defined(_KERNEL) || defined(_KMEMUSER) 1351 1352 #define NUM_X86_FEATURES 103 1353 extern uchar_t x86_featureset[]; 1354 1355 extern void free_x86_featureset(void *featureset); 1356 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 1357 extern void add_x86_feature(void *featureset, uint_t feature); 1358 extern void remove_x86_feature(void *featureset, uint_t feature); 1359 extern boolean_t compare_x86_featureset(void *setA, void *setB); 1360 extern void print_x86_featureset(void *featureset); 1361 1362 1363 extern uint_t x86_type; 1364 extern uint_t x86_vendor; 1365 extern uint_t x86_clflush_size; 1366 1367 extern uint_t pentiumpro_bug4046376; 1368 1369 /* 1370 * These functions are all used to perform various side-channel mitigations. 1371 * Please see uts/i86pc/os/cpuid.c for more information. 1372 */ 1373 extern void (*spec_uarch_flush)(void); 1374 extern void x86_rsb_stuff(void); 1375 extern void x86_md_clear(void); 1376 1377 #endif 1378 1379 #if defined(_KERNEL) 1380 1381 /* 1382 * This structure is used to pass arguments and get return values back 1383 * from the CPUID instruction in __cpuid_insn() routine. 1384 */ 1385 struct cpuid_regs { 1386 uint32_t cp_eax; 1387 uint32_t cp_ebx; 1388 uint32_t cp_ecx; 1389 uint32_t cp_edx; 1390 }; 1391 1392 extern int x86_use_pcid; 1393 extern int x86_use_invpcid; 1394 1395 /* 1396 * Utility functions to get/set extended control registers (XCR) 1397 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK. 1398 */ 1399 extern uint64_t get_xcr(uint_t); 1400 extern void set_xcr(uint_t, uint64_t); 1401 1402 extern uint64_t rdmsr(uint_t); 1403 extern void wrmsr(uint_t, const uint64_t); 1404 extern uint64_t xrdmsr(uint_t); 1405 extern void xwrmsr(uint_t, const uint64_t); 1406 extern int checked_rdmsr(uint_t, uint64_t *); 1407 extern int checked_wrmsr(uint_t, uint64_t); 1408 1409 extern void invalidate_cache(void); 1410 extern ulong_t getcr4(void); 1411 extern void setcr4(ulong_t); 1412 1413 extern void mtrr_sync(void); 1414 1415 extern void cpu_fast_syscall_enable(void); 1416 extern void cpu_fast_syscall_disable(void); 1417 1418 typedef enum cpuid_pass { 1419 CPUID_PASS_NONE = 0, 1420 CPUID_PASS_PRELUDE, 1421 CPUID_PASS_IDENT, 1422 CPUID_PASS_BASIC, 1423 CPUID_PASS_EXTENDED, 1424 CPUID_PASS_DYNAMIC, 1425 CPUID_PASS_RESOLVE 1426 } cpuid_pass_t; 1427 1428 struct cpu; 1429 1430 extern boolean_t cpuid_checkpass(const struct cpu *const, const cpuid_pass_t); 1431 extern void cpuid_execpass(struct cpu *, const cpuid_pass_t, void *); 1432 extern void cpuid_pass_ucode(struct cpu *, uchar_t *); 1433 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 1434 extern uint32_t __cpuid_insn(struct cpuid_regs *); 1435 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 1436 extern int cpuid_getidstr(struct cpu *, char *, size_t); 1437 extern const char *cpuid_getvendorstr(struct cpu *); 1438 extern uint_t cpuid_getvendor(struct cpu *); 1439 extern uint_t cpuid_getfamily(struct cpu *); 1440 extern uint_t cpuid_getmodel(struct cpu *); 1441 extern uint_t cpuid_getstep(struct cpu *); 1442 extern uint_t cpuid_getsig(struct cpu *); 1443 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 1444 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 1445 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 1446 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 1447 extern int cpuid_get_chipid(struct cpu *); 1448 extern id_t cpuid_get_coreid(struct cpu *); 1449 extern int cpuid_get_pkgcoreid(struct cpu *); 1450 extern int cpuid_get_clogid(struct cpu *); 1451 extern int cpuid_get_cacheid(struct cpu *); 1452 extern uint32_t cpuid_get_apicid(struct cpu *); 1453 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 1454 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 1455 extern uint_t cpuid_get_compunitid(struct cpu *cpu); 1456 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); 1457 extern size_t cpuid_get_xsave_size(); 1458 extern boolean_t cpuid_need_fp_excp_handling(); 1459 extern int cpuid_is_cmt(struct cpu *); 1460 extern int cpuid_syscall32_insn(struct cpu *); 1461 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 1462 1463 extern x86_chiprev_t cpuid_getchiprev(struct cpu *); 1464 extern const char *cpuid_getchiprevstr(struct cpu *); 1465 extern uint32_t cpuid_getsockettype(struct cpu *); 1466 extern const char *cpuid_getsocketstr(struct cpu *); 1467 extern x86_uarchrev_t cpuid_getuarchrev(struct cpu *); 1468 1469 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 1470 1471 struct cpuid_info; 1472 1473 extern void setx86isalist(void); 1474 extern void cpuid_alloc_space(struct cpu *); 1475 extern void cpuid_free_space(struct cpu *); 1476 extern void cpuid_set_cpu_properties(void *, processorid_t, 1477 struct cpuid_info *); 1478 extern void cpuid_post_ucodeadm(void); 1479 1480 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 1481 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 1482 1483 #if !defined(__xpv) 1484 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 1485 extern void cpuid_mwait_free(struct cpu *); 1486 extern int cpuid_deep_cstates_supported(void); 1487 extern int cpuid_arat_supported(void); 1488 extern int cpuid_iepb_supported(struct cpu *); 1489 extern int cpuid_deadline_tsc_supported(void); 1490 extern void vmware_port(int, uint32_t *); 1491 #endif 1492 1493 extern x86_processor_family_t chiprev_family(const x86_chiprev_t); 1494 extern boolean_t chiprev_matches(const x86_chiprev_t, const x86_chiprev_t); 1495 extern boolean_t chiprev_at_least(const x86_chiprev_t, const x86_chiprev_t); 1496 1497 extern x86_uarch_t uarchrev_uarch(const x86_uarchrev_t); 1498 extern boolean_t uarchrev_matches(const x86_uarchrev_t, const x86_uarchrev_t); 1499 extern boolean_t uarchrev_at_least(const x86_uarchrev_t, const x86_uarchrev_t); 1500 1501 struct cpu_ucode_info; 1502 1503 extern void ucode_alloc_space(struct cpu *); 1504 extern void ucode_free_space(struct cpu *); 1505 extern void ucode_check(struct cpu *); 1506 extern void ucode_cleanup(); 1507 1508 #if !defined(__xpv) 1509 extern char _tsc_mfence_start; 1510 extern char _tsc_mfence_end; 1511 extern char _tscp_start; 1512 extern char _tscp_end; 1513 extern char _no_rdtsc_start; 1514 extern char _no_rdtsc_end; 1515 extern char _tsc_lfence_start; 1516 extern char _tsc_lfence_end; 1517 #endif 1518 1519 #if !defined(__xpv) 1520 extern char bcopy_patch_start; 1521 extern char bcopy_patch_end; 1522 extern char bcopy_ck_size; 1523 #endif 1524 1525 extern void post_startup_cpu_fixups(void); 1526 1527 extern uint_t workaround_errata(struct cpu *); 1528 1529 #if defined(OPTERON_ERRATUM_93) 1530 extern int opteron_erratum_93; 1531 #endif 1532 1533 #if defined(OPTERON_ERRATUM_91) 1534 extern int opteron_erratum_91; 1535 #endif 1536 1537 #if defined(OPTERON_ERRATUM_100) 1538 extern int opteron_erratum_100; 1539 #endif 1540 1541 #if defined(OPTERON_ERRATUM_121) 1542 extern int opteron_erratum_121; 1543 #endif 1544 1545 #if defined(OPTERON_ERRATUM_147) 1546 extern int opteron_erratum_147; 1547 extern void patch_erratum_147(void); 1548 #endif 1549 1550 #if !defined(__xpv) 1551 extern void determine_platform(void); 1552 #endif 1553 extern int get_hwenv(void); 1554 extern int is_controldom(void); 1555 1556 extern void enable_pcid(void); 1557 1558 extern void xsave_setup_msr(struct cpu *); 1559 1560 #if !defined(__xpv) 1561 extern void reset_gdtr_limit(void); 1562 #endif 1563 1564 extern int enable_platform_detection; 1565 1566 /* 1567 * Hypervisor signatures 1568 */ 1569 #define HVSIG_XEN_HVM "XenVMMXenVMM" 1570 #define HVSIG_VMWARE "VMwareVMware" 1571 #define HVSIG_KVM "KVMKVMKVM" 1572 #define HVSIG_MICROSOFT "Microsoft Hv" 1573 #define HVSIG_BHYVE "bhyve bhyve " 1574 1575 /* 1576 * Defined hardware environments 1577 */ 1578 #define HW_NATIVE (1 << 0) /* Running on bare metal */ 1579 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */ 1580 1581 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */ 1582 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */ 1583 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */ 1584 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */ 1585 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */ 1586 1587 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \ 1588 HW_BHYVE) 1589 1590 #endif /* _KERNEL */ 1591 1592 #endif /* !_ASM */ 1593 1594 /* 1595 * VMware hypervisor related defines 1596 */ 1597 #define VMWARE_HVMAGIC 0x564d5868 1598 #define VMWARE_HVPORT 0x5658 1599 #define VMWARE_HVCMD_GETVERSION 0x0a 1600 #define VMWARE_HVCMD_GETTSCFREQ 0x2d 1601 1602 #ifdef __cplusplus 1603 } 1604 #endif 1605 1606 #endif /* _SYS_X86_ARCHEXT_H */ 1607