1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 22 * Use is subject to license terms. 23 */ 24 /* 25 * Copyright 2019 Joyent, Inc. 26 * Copyright 2022 Oxide Computer Company 27 */ 28 29 #ifndef _SYS_MC_H 30 #define _SYS_MC_H 31 32 /* 33 * Public interfaces exposed by the memory controller driver 34 */ 35 36 #include <sys/cpuvar.h> 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #define MC_UNUM_NAMLEN 192 43 #define MC_UNUM_NDIMM 2 44 45 typedef struct mc_unum { 46 int unum_board; /* system board */ 47 int unum_chip; /* chip/socket */ 48 int unum_mc; /* memory-controller or branch */ 49 int unum_chan; /* DRAM channel */ 50 int unum_cs; /* chip-select */ 51 int unum_rank; /* rank */ 52 uint64_t unum_offset; /* row, column, bank-select etc */ 53 int unum_dimms[MC_UNUM_NDIMM]; 54 } mc_unum_t; 55 56 /* 57 * Invalid marker used in some numeric properties 58 */ 59 #define MC_INVALNUM ((uint32_t)-1) 60 61 /* 62 * /dev/mc/mc* ioctl cmds 63 */ 64 #define MC_IOC (0x4d43 << 16) 65 #define MC_IOC_SNAPSHOT_INFO (MC_IOC | 1) 66 #define MC_IOC_SNAPSHOT (MC_IOC | 2) 67 #define MC_IOC_ONLINESPARE_EN (MC_IOC | 4) 68 #define MC_IOC_DECODE_PA (MC_IOC | 5) 69 #define MC_IOC_DECODE_SNAPSHOT_INFO (MC_IOC | 6) 70 #define MC_IOC_DECODE_SNAPSHOT (MC_IOC | 7) 71 72 /* 73 * Prior to requesting a copy of the snapshot, consumers are advised to request 74 * information regarding the snapshot. An mc_snapshot_info_t will be returned, 75 * containing the snapshot size as well as the snapshot generation number. Note 76 * that, due to the potentially dynamic nature of the system, the snapshot may 77 * change at any time. As such, the information in the mc_snapshot_info_t may 78 * be out of date by the time it is used. The generation number is used to 79 * track snapshot changes. That is, the generation number will be updated each 80 * time the source data for the snapshot is updated. The consumer should not 81 * attach any meaning to the magnitude of a generation number change, and pay 82 * attention only to the fact that the number has changed. 83 */ 84 typedef struct mc_snapshot_info { 85 uint32_t mcs_size; /* snapshot size */ 86 uint_t mcs_gen; /* snapshot generation number */ 87 } mc_snapshot_info_t; 88 89 /* 90 * Data used to simulate encoding or decoding of a physical / DIMM address. 91 * These are used in different ways between AMD and Intel, so this is a bit of a 92 * smorgasbord. Details about each field are listed below. 93 */ 94 typedef struct mc_encode_ioc { 95 /* 96 * The first three values here are different addresses. We have a 97 * physical / system address. A DRAM-channel relative address, and 98 * finally a rank-relative address. Where a platform does not support 99 * one of these, UINT64_MAX is used. 100 */ 101 uint64_t mcei_pa; 102 uint64_t mcei_chan_addr; 103 uint64_t mcei_rank_addr; 104 /* 105 * These next two provide a way for the memory controller software 106 * driver to provide additional information. The mcei_err generally 107 * corresponds to an enum that the driver has and the errdata is 108 * error-specific data that can be useful. 109 */ 110 uint64_t mcei_errdata; 111 uint32_t mcei_err; 112 /* 113 * This next set is used to identify information about where to find a 114 * DIMM in question. The board and chip are used to uniquely identify a 115 * socket. Generally on x86, there is only one board, so it would be 116 * zero. The chip should correspond to the socket ID. The die refers to 117 * a particular internal die if on a chiplet or MCP. The memory 118 * controller and channel refer to a unique instance of both within a 119 * given die. On platforms where the memory controller and channel are 120 * 1:1 (that is each memory controller has only a single channel or 121 * doesn't have a specific distinction between the two), set chan to 0 122 * and set the mc to the logical channel value. The DIMM is a relative 123 * DIMM in the channel, meaning it's usually going to be 0, 1, or 2. 124 */ 125 uint32_t mcei_board; 126 uint32_t mcei_chip; 127 uint32_t mcei_die; 128 uint32_t mcei_mc; 129 uint32_t mcei_chan; 130 uint32_t mcei_dimm; 131 /* 132 * These values all refer to information on the DIMM itself and identify 133 * how to find the address. mcei_rank is meant to be a logical rank; 134 * however, some systems phrase things that way while others phrase 135 * things in terms of a chip select and rank multiplication. For unknown 136 * entries use UINT8_MAX. 137 */ 138 uint32_t mcei_row; 139 uint32_t mcei_column; 140 uint8_t mcei_rank; 141 uint8_t mcei_cs; 142 uint8_t mcei_rm; 143 uint8_t mcei_bank; 144 uint8_t mcei_bank_group; 145 uint8_t mcei_subchan; 146 uint8_t mcei_pad[6]; 147 } mc_encode_ioc_t; 148 149 #ifdef __cplusplus 150 } 151 #endif 152 153 #endif /* _SYS_MC_H */ 154