1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 * Copyright 2019 Joyent, Inc. 26 */ 27 28 #ifndef _SYS_CPU_MODULE_H 29 #define _SYS_CPU_MODULE_H 30 31 #include <sys/types.h> 32 #include <sys/cpuvar.h> 33 #include <sys/nvpair.h> 34 #include <sys/mc.h> 35 #include <sys/sunddi.h> 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 #ifdef _KERNEL 42 43 #define CMIERR_BASE 0xc000 44 45 typedef enum cmi_errno { 46 CMI_SUCCESS = 0, 47 /* 48 * CPU Module Interface API error return values/ 49 */ 50 CMIERR_UNKNOWN = CMIERR_BASE, /* no specific error reason reported */ 51 CMIERR_API, /* API usage error caught */ 52 CMIERR_NOTSUP, /* Unsupported operation */ 53 CMIERR_HDL_CLASS, /* Inappropriate handle class */ 54 CMIERR_HDL_NOTFOUND, /* Can't find handle for resource */ 55 CMIERR_MSRGPF, /* #GP during cmi_hdl_{wr,rd}msr */ 56 CMIERR_INTERPOSE, /* MSR/PCICFG interposition error */ 57 CMIERR_DEADLOCK, /* Deadlock avoidance */ 58 /* 59 * Memory-controller related errors 60 */ 61 CMIERR_MC_ABSENT, /* No, or not yet registered, MC ops */ 62 CMIERR_MC_NOTSUP, /* Requested functionality unimpld */ 63 CMIERR_MC_NOMEMSCRUB, /* No dram scrubber, or disabled */ 64 CMIERR_MC_SYNDROME, /* Invalid syndrome or syndrome type */ 65 CMIERR_MC_BADSTATE, /* MC driver state is invalid */ 66 CMIERR_MC_NOADDR, /* Address not found */ 67 CMIERR_MC_RSRCNOTPRESENT, /* Resource not present in system */ 68 CMIERR_MC_ADDRBITS, /* Too few valid addr bits */ 69 CMIERR_MC_INVALUNUM, /* Invalid input unum */ 70 CMIERR_MC_PARTIALUNUMTOPA, /* unum to pa reflected physaddr */ 71 CMIERR_MC_NOTDIMMADDR /* Address not backed by DRAM */ 72 } cmi_errno_t; 73 74 /* 75 * All access to cpu information is made via a handle, in order to get 76 * the desired info even when running non-natively. 77 * 78 * A CMI_HDL_NATIVE handle is used when we believe we are running on 79 * bare-metal. If we *are* on bare metal then this handle type will 80 * get us through to the real hardware, and there will be a 1:1 correspondence 81 * between handles and cpu_t structures; if not, say we are a domU to 82 * some unknown/undetected/unannounced hypervisor then chances are the 83 * hypervisor is not exposing much hardware detail to us so we should 84 * be prepared for some operations that "cannot fail" to fail or return 85 * odd data. 86 * 87 * A CMI_HDL_SOLARIS_xVM_MCA handle is used when we are running 88 * in i86xpv architecture - dom0 to a Solaris xVM hypervisor - and want to 89 * use a handle on each real execution core (as opposed to vcpu) 90 * to perform MCA related activities. The model for this handle type 91 * is that the hypervisor continues to own the real hardware and 92 * includes a polling service and #MC handler which forward error 93 * telemetry to dom0 for logging and diagnosis. As such, the operations 94 * such as RDMSR and WRMSR for this handle type do *not* read and write 95 * real MSRs via hypercalls- instead they should provide the values from 96 * already-read MCA bank telemetry, and writes are discarded. 97 * 98 * If some application requires real MSR read and write access another 99 * handle class should be introduced. 100 */ 101 102 typedef struct cmi_hdl *cmi_hdl_t; /* opaque chip/core/strand handle */ 103 104 enum cmi_hdl_class { 105 CMI_HDL_NATIVE, 106 CMI_HDL_SOLARIS_xVM_MCA, 107 CMI_HDL_NEUTRAL 108 }; 109 110 struct regs; 111 112 typedef struct cmi_mc_ops { 113 cmi_errno_t (*cmi_mc_patounum)(void *, uint64_t, uint8_t, uint8_t, 114 uint32_t, int, mc_unum_t *); 115 cmi_errno_t (*cmi_mc_unumtopa)(void *, mc_unum_t *, nvlist_t *, 116 uint64_t *); 117 void (*cmi_mc_logout)(cmi_hdl_t, boolean_t, boolean_t); 118 } cmi_mc_ops_t; 119 120 extern cmi_hdl_t cmi_init(enum cmi_hdl_class, uint_t, uint_t, uint_t); 121 extern void cmi_post_startup(void); 122 extern void cmi_post_mpstartup(void); 123 extern void cmi_fini(cmi_hdl_t); 124 125 extern void cmi_hdl_hold(cmi_hdl_t); 126 extern void cmi_hdl_rele(cmi_hdl_t); 127 extern void *cmi_hdl_getcmidata(cmi_hdl_t); 128 extern void cmi_hdl_setspecific(cmi_hdl_t, void *); 129 extern void *cmi_hdl_getspecific(cmi_hdl_t); 130 extern const struct cmi_mc_ops *cmi_hdl_getmcops(cmi_hdl_t); 131 extern void *cmi_hdl_getmcdata(cmi_hdl_t); 132 extern enum cmi_hdl_class cmi_hdl_class(cmi_hdl_t); 133 134 extern cmi_hdl_t cmi_hdl_lookup(enum cmi_hdl_class, uint_t, uint_t, uint_t); 135 extern cmi_hdl_t cmi_hdl_any(void); 136 137 #define CMI_HDL_WALK_NEXT 0 138 #define CMI_HDL_WALK_DONE 1 139 extern void cmi_hdl_walk(int (*)(cmi_hdl_t, void *, void *, void *), 140 void *, void *, void *); 141 142 extern void cmi_hdlconf_rdmsr_nohw(cmi_hdl_t); 143 extern void cmi_hdlconf_wrmsr_nohw(cmi_hdl_t); 144 extern cmi_errno_t cmi_hdl_rdmsr(cmi_hdl_t, uint_t, uint64_t *); 145 extern cmi_errno_t cmi_hdl_wrmsr(cmi_hdl_t, uint_t, uint64_t); 146 147 extern void cmi_hdl_enable_mce(cmi_hdl_t); 148 extern uint_t cmi_hdl_vendor(cmi_hdl_t); 149 extern const char *cmi_hdl_vendorstr(cmi_hdl_t); 150 extern uint_t cmi_hdl_family(cmi_hdl_t); 151 extern uint_t cmi_hdl_model(cmi_hdl_t); 152 extern uint_t cmi_hdl_stepping(cmi_hdl_t); 153 extern uint_t cmi_hdl_chipid(cmi_hdl_t); 154 extern uint_t cmi_hdl_procnodeid(cmi_hdl_t); 155 extern uint_t cmi_hdl_coreid(cmi_hdl_t); 156 extern uint_t cmi_hdl_strandid(cmi_hdl_t); 157 extern uint_t cmi_hdl_strand_apicid(cmi_hdl_t); 158 extern uint_t cmi_hdl_procnodes_per_pkg(cmi_hdl_t); 159 extern boolean_t cmi_hdl_is_cmt(cmi_hdl_t); 160 extern uint32_t cmi_hdl_chiprev(cmi_hdl_t); 161 extern const char *cmi_hdl_chiprevstr(cmi_hdl_t); 162 extern uint32_t cmi_hdl_getsockettype(cmi_hdl_t); 163 extern const char *cmi_hdl_getsocketstr(cmi_hdl_t); 164 extern id_t cmi_hdl_logical_id(cmi_hdl_t); 165 extern uint16_t cmi_hdl_smbiosid(cmi_hdl_t); 166 extern uint_t cmi_hdl_smb_chipid(cmi_hdl_t); 167 extern nvlist_t *cmi_hdl_smb_bboard(cmi_hdl_t); 168 extern uint_t cmi_hdl_chipsig(cmi_hdl_t); 169 extern const char *cmi_hdl_chipident(cmi_hdl_t); 170 171 extern int cmi_hdl_online(cmi_hdl_t, int, int *); 172 173 #ifndef __xpv 174 extern uint_t cmi_ntv_hwchipid(cpu_t *); 175 extern uint_t cmi_ntv_hwprocnodeid(cpu_t *); 176 extern uint_t cmi_ntv_hwcoreid(cpu_t *); 177 extern uint_t cmi_ntv_hwstrandid(cpu_t *); 178 extern void cmi_ntv_hwdisable_mce(cmi_hdl_t); 179 #endif /* __xpv */ 180 181 typedef struct cmi_mca_regs { 182 uint_t cmr_msrnum; 183 uint64_t cmr_msrval; 184 } cmi_mca_regs_t; 185 186 extern cmi_errno_t cmi_hdl_msrinject(cmi_hdl_t, cmi_mca_regs_t *, uint_t, 187 int); 188 extern void cmi_hdl_msrinterpose(cmi_hdl_t, cmi_mca_regs_t *, uint_t); 189 extern void cmi_hdl_msrforward(cmi_hdl_t, cmi_mca_regs_t *, uint_t); 190 extern boolean_t cmi_inj_tainted(void); 191 192 extern void cmi_faulted_enter(cmi_hdl_t); 193 extern void cmi_faulted_exit(cmi_hdl_t); 194 195 extern void cmi_pcird_nohw(void); 196 extern void cmi_pciwr_nohw(void); 197 extern uint8_t cmi_pci_getb(int, int, int, int, int *, ddi_acc_handle_t); 198 extern uint16_t cmi_pci_getw(int, int, int, int, int *, ddi_acc_handle_t); 199 extern uint32_t cmi_pci_getl(int, int, int, int, int *, ddi_acc_handle_t); 200 extern void cmi_pci_interposeb(int, int, int, int, uint8_t); 201 extern void cmi_pci_interposew(int, int, int, int, uint16_t); 202 extern void cmi_pci_interposel(int, int, int, int, uint32_t); 203 extern void cmi_pci_putb(int, int, int, int, ddi_acc_handle_t, uint8_t); 204 extern void cmi_pci_putw(int, int, int, int, ddi_acc_handle_t, uint16_t); 205 extern void cmi_pci_putl(int, int, int, int, ddi_acc_handle_t, uint32_t); 206 207 extern void cmi_mca_init(cmi_hdl_t); 208 209 extern void cmi_hdl_poke(cmi_hdl_t); 210 extern void cmi_hdl_int(cmi_hdl_t, int); 211 212 extern void cmi_mca_trap(struct regs *); 213 214 extern boolean_t cmi_panic_on_ue(void); 215 216 extern void cmi_mc_register(cmi_hdl_t, const struct cmi_mc_ops *, void *); 217 extern cmi_errno_t cmi_mc_register_global(const struct cmi_mc_ops *, void *); 218 extern void cmi_mc_sw_memscrub_disable(void); 219 extern cmi_errno_t cmi_mc_patounum(uint64_t, uint8_t, uint8_t, uint32_t, int, 220 mc_unum_t *); 221 extern cmi_errno_t cmi_mc_unumtopa(mc_unum_t *, nvlist_t *, uint64_t *); 222 extern void cmi_mc_logout(cmi_hdl_t, boolean_t, boolean_t); 223 224 extern void cmi_panic_callback(void); 225 226 #endif /* _KERNEL */ 227 228 #ifdef __cplusplus 229 } 230 #endif 231 232 #endif /* _SYS_CPU_MODULE_H */ 233