1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 #ifndef _SYS_UMC_H 17 #define _SYS_UMC_H 18 19 #include <sys/bitext.h> 20 #include <sys/amdzen/smn.h> 21 22 /* 23 * Various register definitions for accessing the AMD Unified Memory Controller 24 * (UMC) over SMN (the system management network). Note, that the SMN exists 25 * independently in each die and must be accessed through the appropriate 26 * IOHC. 27 * 28 * There are effectively four different revisions of the UMC that we know about 29 * and support querying: 30 * 31 * o DDR4 capable APUs 32 * o DDR4 capable CPUs 33 * o DDR5 capable APUs 34 * o DDR5 capable CPUs 35 * 36 * In general for a given revision and generation of a controller (DDR4 vs. 37 * DDR5), all of the address layouts are the same whether it is for an APU or a 38 * CPU. The main difference is generally in the number of features. For example, 39 * most APUs may not support the same rank multiplication bits and related in a 40 * device. However, unlike the DF where everything changes, the main difference 41 * within a generation is just which bits are implemented. This makes it much 42 * easier to define UMC information. 43 * 44 * Between DDR4 and DDR5 based devices, the register locations have shifted; 45 * however, generally speaking, the registers themselves are actually the same. 46 * Registers here, similar to the DF, have a common form: 47 * 48 * UMC_<reg name>_<vers> 49 * 50 * Here, <reg name> would be something like 'BASE', for the UMC 51 * UMC::CH::BaseAddr register. <vers> is one of DDR4 or DDR5. When the same 52 * register is supported at the same address between versions, then <vers> is 53 * elided. 54 * 55 * For fields inside of these registers, everything follows the same pattern in 56 * <sys/amdzen/df.h> which is: 57 * 58 * UMC_<reg name>_<vers>_GET_<field> 59 * 60 * Note, <vers> will be elided if the register is the same between the DDR4 and 61 * DDR5 versions. 62 * 63 * Finally, a cautionary note. While the DF provided a way for us to determine 64 * what version something is, we have not determined a way to programmatically 65 * determine what something supports outside of making notes based on the 66 * family, model, and stepping CPUID information. Unfortunately, you must look 67 * towards the documentation and find what you need in the PPR (processor 68 * programming reference). 69 */ 70 71 #ifdef __cplusplus 72 extern "C" { 73 #endif 74 75 /* 76 * UMC Channel registers. These are in SMN Space. DDR4 and DDR5 based UMCs share 77 * the same base address, somewhat surprisingly. This constructs the appropriate 78 * offset and ensures that a caller doesn't exceed the number of known instances 79 * of the register. See smn.h for additional details on SMN addressing. 80 */ 81 82 static inline smn_reg_t 83 amdzen_umc_smn_reg(const uint8_t umcno, const smn_reg_def_t def, 84 const uint16_t reginst) 85 { 86 const uint32_t APERTURE_BASE = 0x50000; 87 const uint32_t APERTURE_MASK = 0xffffe000; 88 89 const uint32_t umc32 = (const uint32_t)umcno; 90 const uint32_t reginst32 = (const uint32_t)reginst; 91 92 const uint32_t stride = (def.srd_stride == 0) ? 4 : def.srd_stride; 93 const uint32_t nents = (def.srd_nents == 0) ? 1 : 94 (const uint32_t)def.srd_nents; 95 96 ASSERT3S(def.srd_unit, ==, SMN_UNIT_UMC); 97 ASSERT0(def.srd_reg & APERTURE_MASK); 98 ASSERT3U(umc32, <, 12); 99 ASSERT3U(nents, >, reginst32); 100 101 const uint32_t aperture_off = umc32 << 20; 102 ASSERT3U(aperture_off, <=, UINT32_MAX - APERTURE_BASE); 103 104 const uint32_t aperture = APERTURE_BASE + aperture_off; 105 ASSERT0(aperture & ~APERTURE_MASK); 106 107 const uint32_t reg = def.srd_reg + reginst32 * stride; 108 ASSERT0(reg & APERTURE_MASK); 109 110 return (SMN_MAKE_REG(aperture + reg)); 111 } 112 113 /* 114 * UMC::CH::BaseAddr, UMC::CH::BaseAddrSec -- determines the base address used 115 * to match a chip select. Instances 0/1 always refer to DIMM 0, while 116 * instances 2/3 always refer to DIMM 1. 117 */ 118 /*CSTYLED*/ 119 #define D_UMC_BASE (const smn_reg_def_t){ \ 120 .srd_unit = SMN_UNIT_UMC, \ 121 .srd_reg = 0x00, \ 122 .srd_nents = 4 \ 123 } 124 /*CSTYLED*/ 125 #define D_UMC_BASE_SEC (const smn_reg_def_t){ \ 126 .srd_unit = SMN_UNIT_UMC, \ 127 .srd_reg = 0x10, \ 128 .srd_nents = 4 \ 129 } 130 #define UMC_BASE(u, i) amdzen_umc_smn_reg(u, D_UMC_BASE, i) 131 #define UMC_BASE_SEC(u, i) amdzen_umc_smn_reg(u, D_UMC_BASE_SEC, i) 132 #define UMC_BASE_GET_ADDR(r) bitx32(r, 31, 1) 133 #define UMC_BASE_ADDR_SHIFT 9 134 #define UMC_BASE_GET_EN(r) bitx32(r, 0, 0) 135 136 /* 137 * UMC::BaseAddrExt, UMC::BaseAddrSecExt -- The first of several extensions to 138 * registers that allow more address bits. Note, only present in some DDR5 139 * capable SoCs. 140 */ 141 /*CSTYLED*/ 142 #define D_UMC_BASE_EXT_DDR5 (const smn_reg_def_t){ \ 143 .srd_unit = SMN_UNIT_UMC, \ 144 .srd_reg = 0xb00, \ 145 .srd_nents = 4 \ 146 } 147 /*CSTYLED*/ 148 #define D_UMC_BASE_EXT_SEC_DDR5 (const smn_reg_def_t){ \ 149 .srd_unit = SMN_UNIT_UMC, \ 150 .srd_reg = 0xb10, \ 151 .srd_nents = 4 \ 152 } 153 #define UMC_BASE_EXT_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_BASE_EXT_DDR5, i) 154 #define UMC_BASE_EXT_SEC_DDR5(u, i) \ 155 amdzen_umc_smn_reg(u, D_UMC_BASE_EXT_SEC_DDR5, i) 156 #define UMC_BASE_EXT_GET_ADDR(r) bitx32(r, 7, 0) 157 #define UMC_BASE_EXT_ADDR_SHIFT 40 158 159 160 /* 161 * UMC::CH::AddrMask, UMC::CH::AddrMaskSec -- This register is used to compare 162 * the incoming address to see it matches the base. Tweaking what is used for 163 * match is often part of the interleaving strategy. 164 */ 165 /*CSTYLED*/ 166 #define D_UMC_MASK_DDR4 (const smn_reg_def_t){ \ 167 .srd_unit = SMN_UNIT_UMC, \ 168 .srd_reg = 0x20, \ 169 .srd_nents = 2 \ 170 } 171 /*CSTYLED*/ 172 #define D_UMC_MASK_SEC_DDR4 (const smn_reg_def_t){ \ 173 .srd_unit = SMN_UNIT_UMC, \ 174 .srd_reg = 0x28, \ 175 .srd_nents = 2 \ 176 } 177 /*CSTYLED*/ 178 #define D_UMC_MASK_DDR5 (const smn_reg_def_t){ \ 179 .srd_unit = SMN_UNIT_UMC, \ 180 .srd_reg = 0x20, \ 181 .srd_nents = 4 \ 182 } 183 /*CSTYLED*/ 184 #define D_UMC_MASK_SEC_DDR5 (const smn_reg_def_t){ \ 185 .srd_unit = SMN_UNIT_UMC, \ 186 .srd_reg = 0x30, \ 187 .srd_nents = 4 \ 188 } 189 #define UMC_MASK_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_DDR4, i) 190 #define UMC_MASK_SEC_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_SEC_DDR4, i) 191 #define UMC_MASK_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_DDR5, i) 192 #define UMC_MASK_SEC_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_SEC_DDR5, i) 193 #define UMC_MASK_GET_ADDR(r) bitx32(r, 31, 1) 194 #define UMC_MASK_ADDR_SHIFT 9 195 196 /* 197 * UMC::AddrMaskExt, UMC::AddrMaskSecExt -- Extended mask addresses. 198 */ 199 /*CSTYLED*/ 200 #define D_UMC_MASK_EXT_DDR5 (const smn_reg_def_t){ \ 201 .srd_unit = SMN_UNIT_UMC, \ 202 .srd_reg = 0xb20, \ 203 .srd_nents = 4 \ 204 } 205 /*CSTYLED*/ 206 #define D_UMC_MASK_EXT_SEC_DDR5 (const smn_reg_def_t){ \ 207 .srd_unit = SMN_UNIT_UMC, \ 208 .srd_reg = 0xb30, \ 209 .srd_nents = 4 \ 210 } 211 #define UMC_MASK_EXT_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_MASK_EXT_DDR5, i) 212 #define UMC_MASK_EXT_SEC_DDR5(u, i) \ 213 amdzen_umc_smn_reg(u, D_UMC_MASK_EXT_SEC_DDR5, i) 214 #define UMC_MASK_EXT_GET_ADDR(r) bitx32(r, 7, 0) 215 #define UMC_MASK_EXT_ADDR_SHIFT 40 216 217 /* 218 * UMC::CH::AddrCfg -- This register contains a number of bits that describe how 219 * the address is actually used, one per DIMM. Note, not all members are valid 220 * for all classes of DIMMs. It's worth calling out that the total number of 221 * banks value here describes the total number of banks on the entire chip, e.g. 222 * it is bank groups * banks/groups. Therefore to determine the number of 223 * banks/group you must subtract the number of bank group bits from the total 224 * number of bank bits. 225 */ 226 /*CSTYLED*/ 227 #define D_UMC_ADDRCFG_DDR4 (const smn_reg_def_t){ \ 228 .srd_unit = SMN_UNIT_UMC, \ 229 .srd_reg = 0x30, \ 230 .srd_nents = 2 \ 231 } 232 /*CSTYLED*/ 233 #define D_UMC_ADDRCFG_DDR5 (const smn_reg_def_t){ \ 234 .srd_unit = SMN_UNIT_UMC, \ 235 .srd_reg = 0x40, \ 236 .srd_nents = 4 \ 237 } 238 #define UMC_ADDRCFG_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_ADDRCFG_DDR4, i) 239 #define UMC_ADDRCFG_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_ADDRCFG_DDR5, i) 240 #define UMC_ADDRCFG_GET_NBANK_BITS(r) bitx32(r, 21, 20) 241 #define UMC_ADDRCFG_NBANK_BITS_BASE 3 242 #define UMC_ADDRCFG_GET_NCOL_BITS(r) bitx32(r, 19, 16) 243 #define UMC_ADDRCFG_NCOL_BITS_BASE 5 244 #define UMC_ADDRCFG_GET_NROW_BITS_LO(r) bitx32(r, 11, 8) 245 #define UMC_ADDRCFG_NROW_BITS_LO_BASE 10 246 #define UMC_ADDRCFG_GET_NBANKGRP_BITS(r) bitx32(r, 3, 2) 247 248 #define UMC_ADDRCFG_DDR4_GET_NROW_BITS_HI(r) bitx32(r, 15, 12) 249 #define UMC_ADDRCFG_DDR4_GET_NRM_BITS(r) bitx32(r, 5, 4) 250 #define UMC_ADDRCFG_DDR5_GET_CSXOR(r) bitx32(r, 31, 30) 251 #define UMC_ADDRCFG_DDR5_GET_NRM_BITS(r) bitx32(r, 6, 4) 252 253 /* 254 * UMC::CH::AddrSel -- This register is used to program how the actual bits in 255 * the normalized address map to the row and bank. While the bank can select 256 * which bits in the normalized address are used to construct the bank number, 257 * row bits are contiguous from the starting number. 258 */ 259 /*CSTYLED*/ 260 #define D_UMC_ADDRSEL_DDR4 (const smn_reg_def_t){ \ 261 .srd_unit = SMN_UNIT_UMC, \ 262 .srd_reg = 0x40, \ 263 .srd_nents = 2 \ 264 } 265 /*CSTYLED*/ 266 #define D_UMC_ADDRSEL_DDR5 (const smn_reg_def_t){ \ 267 .srd_unit = SMN_UNIT_UMC, \ 268 .srd_reg = 0x50, \ 269 .srd_nents = 4 \ 270 } 271 #define UMC_ADDRSEL_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_ADDRSEL_DDR4, i) 272 #define UMC_ADDRSEL_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_ADDRSEL_DDR5, i) 273 #define UMC_ADDRSEL_GET_ROW_LO(r) bitx32(r, 27, 24) 274 #define UMC_ADDRSEL_ROW_LO_BASE 12 275 #define UMC_ADDRSEL_GET_BANK4(r) bitx32(r, 19, 16) 276 #define UMC_ADDRSEL_GET_BANK3(r) bitx32(r, 15, 12) 277 #define UMC_ADDRSEL_GET_BANK2(r) bitx32(r, 11, 8) 278 #define UMC_ADDRSEL_GET_BANK1(r) bitx32(r, 7, 4) 279 #define UMC_ADDRSEL_GET_BANK0(r) bitx32(r, 3, 0) 280 #define UMC_ADDRSEL_BANK_BASE 5 281 282 #define UMC_ADDRSEL_DDR4_GET_ROW_HI(r) bitx32(r, 31, 28) 283 #define UMC_ADDRSEL_DDR4_ROW_HI_BASE 24 284 285 /* 286 * UMC::CH::ColSelLo, UMC::CH::ColSelHi -- This register selects which address 287 * bits map to the various column select bits. These registers interleave so in 288 * the case of DDR4, it's 0x50, 0x54 for DIMM 0 lo, hi. Then 0x58, 0x5c for 289 * DIMM1. DDR5 based entries do something similar; however, instead of being 290 * per-DIMM, there is one of these for each CS. 291 */ 292 /*CSTYLED*/ 293 #define D_UMC_COLSEL_LO_DDR4 (const smn_reg_def_t){ \ 294 .srd_unit = SMN_UNIT_UMC, \ 295 .srd_reg = 0x50, \ 296 .srd_nents = 2, \ 297 .srd_stride = 8 \ 298 } 299 /*CSTYLED*/ 300 #define D_UMC_COLSEL_HI_DDR4 (const smn_reg_def_t){ \ 301 .srd_unit = SMN_UNIT_UMC, \ 302 .srd_reg = 0x54, \ 303 .srd_nents = 2, \ 304 .srd_stride = 8 \ 305 } 306 /*CSTYLED*/ 307 #define D_UMC_COLSEL_LO_DDR5 (const smn_reg_def_t){ \ 308 .srd_unit = SMN_UNIT_UMC, \ 309 .srd_reg = 0x60, \ 310 .srd_nents = 4, \ 311 .srd_stride = 8 \ 312 } 313 /*CSTYLED*/ 314 #define D_UMC_COLSEL_HI_DDR5 (const smn_reg_def_t){ \ 315 .srd_unit = SMN_UNIT_UMC, \ 316 .srd_reg = 0x64, \ 317 .srd_nents = 4, \ 318 .srd_stride = 8 \ 319 } 320 #define UMC_COLSEL_LO_DDR4(u, i) \ 321 amdzen_umc_smn_reg(u, D_UMC_COLSEL_LO_DDR4, i) 322 #define UMC_COLSEL_HI_DDR4(u, i) \ 323 amdzen_umc_smn_reg(u, D_UMC_COLSEL_HI_DDR4, i) 324 #define UMC_COLSEL_LO_DDR5(u, i) \ 325 amdzen_umc_smn_reg(u, D_UMC_COLSEL_LO_DDR5, i) 326 #define UMC_COLSEL_HI_DDR5(u, i) \ 327 amdzen_umc_smn_reg(u, D_UMC_COLSEL_HI_DDR5, i) 328 329 #define UMC_COLSEL_REMAP_GET_COL(r, x) bitx32(r, (3 + (4 * (x))), (4 * ((x)))) 330 #define UMC_COLSEL_LO_BASE 2 331 #define UMC_COLSEL_HI_BASE 8 332 333 /* 334 * UMC::CH::RmSel -- This register contains the bits that determine how the rank 335 * is determined. Which fields of this are valid vary a lot in the different 336 * parts. The DDR4 and DDR5 versions are different enough that we use totally 337 * disjoint definitions. It's also worth noting that DDR5 doesn't have a 338 * secondary version of this as it is included in the main register. 339 * 340 * In general, APUs have some of the MSBS (most significant bit swap) related 341 * fields; however, they do not have rank multiplication bits. 342 */ 343 /*CSTYLED*/ 344 #define D_UMC_RMSEL_DDR4 (const smn_reg_def_t){ \ 345 .srd_unit = SMN_UNIT_UMC, \ 346 .srd_reg = 0x70, \ 347 .srd_nents = 2 \ 348 } 349 /*CSTYLED*/ 350 #define D_UMC_RMSEL_SEC_DDR4 (const smn_reg_def_t){ \ 351 .srd_unit = SMN_UNIT_UMC, \ 352 .srd_reg = 0x78, \ 353 .srd_nents = 2 \ 354 } 355 #define UMC_RMSEL_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_RMSEL_DDR4, i) 356 #define UMC_RMSEL_SEC_DDR4(u, i) \ 357 amdzen_umc_smn_reg(u, D_UMC_RMSEL_SEC_DDR4, i) 358 #define UMC_RMSEL_DDR4_GET_INV_MSBO(r) bitx32(r, 19, 18) 359 #define UMC_RMSEL_DDR4_GET_INV_MSBE(r) bitx32(r, 17, 16) 360 #define UMC_RMSEL_DDR4_GET_RM2(r) bitx32(r, 11, 8) 361 #define UMC_RMSEL_DDR4_GET_RM1(r) bitx32(r, 7, 4) 362 #define UMC_RMSEL_DDR4_GET_RM0(r) bitx32(r, 3, 0) 363 #define UMC_RMSEL_BASE 12 364 365 /*CSTYLED*/ 366 #define D_UMC_RMSEL_DDR5 (const smn_reg_def_t){ \ 367 .srd_unit = SMN_UNIT_UMC, \ 368 .srd_reg = 0x80, \ 369 .srd_nents = 4 \ 370 } 371 #define UMC_RMSEL_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_RMSEL_DDR5, i) 372 #define UMC_RMSEL_DDR5_GET_INV_MSBS_SEC(r) bitx32(r, 31, 30) 373 #define UMC_RMSEL_DDR5_GET_INV_MSBS(r) bitx32(r, 29, 28) 374 #define UMC_RMSEL_DDR5_GET_SUBCHAN(r) bitx32(r, 19, 16) 375 #define UMC_RMSEL_DDR5_SUBCHAN_BASE 5 376 #define UMC_RMSEL_DDR5_GET_RM3(r) bitx32(r, 15, 12) 377 #define UMC_RMSEL_DDR5_GET_RM2(r) bitx32(r, 11, 8) 378 #define UMC_RMSEL_DDR5_GET_RM1(r) bitx32(r, 7, 4) 379 #define UMC_RMSEL_DDR5_GET_RM0(r) bitx32(r, 3, 0) 380 381 382 /* 383 * UMC::CH::DimmCfg -- This describes several properties of the DIMM that is 384 * installed, such as its overall width or type. 385 */ 386 /*CSTYLED*/ 387 #define D_UMC_DIMMCFG_DDR4 (const smn_reg_def_t){ \ 388 .srd_unit = SMN_UNIT_UMC, \ 389 .srd_reg = 0x80, \ 390 .srd_nents = 2 \ 391 } 392 /*CSTYLED*/ 393 #define D_UMC_DIMMCFG_DDR5 (const smn_reg_def_t){ \ 394 .srd_unit = SMN_UNIT_UMC, \ 395 .srd_reg = 0x90, \ 396 .srd_nents = 2 \ 397 } 398 #define UMC_DIMMCFG_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_DIMMCFG_DDR4, i) 399 #define UMC_DIMMCFG_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_DIMMCFG_DDR5, i) 400 #define UMC_DIMMCFG_GET_PKG_RALIGN(r) bitx32(r, 10, 10) 401 #define UMC_DIMMCFG_GET_REFRESH_DIS(r) bitx32(r, 9, 9) 402 #define UMC_DIMMCFG_GET_DQ_SWAP_DIS(r) bitx32(r, 8, 8) 403 #define UMC_DIMMCFG_GET_X16(r) bitx32(r, 7, 7) 404 #define UMC_DIMMCFG_GET_X4(r) bitx32(r, 6, 6) 405 #define UMC_DIMMCFG_GET_LRDIMM(r) bitx32(r, 5, 5) 406 #define UMC_DIMMCFG_GET_RDIMM(r) bitx32(r, 4, 4) 407 #define UMC_DIMMCFG_GET_CISCS(r) bitx32(r, 3, 3) 408 #define UMC_DIMMCFG_GET_3DS(r) bitx32(r, 2, 2) 409 410 #define UMC_DIMMCFG_DDR4_GET_NVDIMMP(r) bitx32(r, 12, 12) 411 #define UMC_DIMMCFG_DDR4_GET_DDR4e(r) bitx32(r, 11, 11) 412 #define UMC_DIMMCFG_DDR5_GET_RALIGN(r) bitx32(r, 13, 12) 413 #define UMC_DIMMCFG_DDR5_GET_ASYM(r) bitx32(r, 11, 11) 414 415 #define UMC_DIMMCFG_DDR4_GET_OUTPUT_INV(r) bitx32(r, 1, 1) 416 #define UMC_DIMMCFG_DDR4_GET_MRS_MIRROR(r) bitx32(r, 0, 0) 417 418 /* 419 * UMC::CH::AddrHashBank -- These registers contain various instructions about 420 * how to hash an address across a bank to influence which bank is used. 421 */ 422 /*CSTYLED*/ 423 #define D_UMC_BANK_HASH_DDR4 (const smn_reg_def_t){ \ 424 .srd_unit = SMN_UNIT_UMC, \ 425 .srd_reg = 0xc8, \ 426 .srd_nents = 5 \ 427 } 428 /*CSTYLED*/ 429 #define D_UMC_BANK_HASH_DDR5 (const smn_reg_def_t){ \ 430 .srd_unit = SMN_UNIT_UMC, \ 431 .srd_reg = 0x98, \ 432 .srd_nents = 5 \ 433 } 434 #define UMC_BANK_HASH_DDR4(u, i) \ 435 amdzen_umc_smn_reg(u, D_UMC_BANK_HASH_DDR4, i) 436 #define UMC_BANK_HASH_DDR5(u, i) \ 437 amdzen_umc_smn_reg(u, D_UMC_BANK_HASH_DDR5, i) 438 #define UMC_BANK_HASH_GET_ROW(r) bitx32(r, 31, 14) 439 #define UMC_BANK_HASH_GET_COL(r) bitx32(r, 13, 1) 440 #define UMC_BANK_HASH_GET_EN(r) bitx32(r, 0, 0) 441 442 /* 443 * UMC::CH::AddrHashRM -- This hash register describes how to transform a UMC 444 * address when trying to do rank hashing. Note, instance 3 is is reserved in 445 * DDR5 modes. 446 */ 447 /*CSTYLED*/ 448 #define D_UMC_RANK_HASH_DDR4 (const smn_reg_def_t){ \ 449 .srd_unit = SMN_UNIT_UMC, \ 450 .srd_reg = 0xdc, \ 451 .srd_nents = 3 \ 452 } 453 /*CSTYLED*/ 454 #define D_UMC_RANK_HASH_DDR5 (const smn_reg_def_t){ \ 455 .srd_unit = SMN_UNIT_UMC, \ 456 .srd_reg = 0xb0, \ 457 .srd_nents = 4 \ 458 } 459 #define UMC_RANK_HASH_DDR4(u, i) \ 460 amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_DDR4, i) 461 #define UMC_RANK_HASH_DDR5(u, i) \ 462 amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_DDR5, i) 463 #define UMC_RANK_HASH_GET_ADDR(r) bitx32(r, 31, 1) 464 #define UMC_RANK_HASH_SHIFT 9 465 #define UMC_RANK_HASH_GET_EN(r) bitx32(r, 0, 0) 466 467 /* 468 * UMC::AddrHashRMExt -- Extended rank hash addresses. 469 */ 470 /*CSTYLED*/ 471 #define D_UMC_RANK_HASH_EXT_DDR5 (const smn_reg_def_t){ \ 472 .srd_unit = SMN_UNIT_UMC, \ 473 .srd_reg = 0xbb0, \ 474 .srd_nents = 4 \ 475 } 476 #define UMC_RANK_HASH_EXT_DDR5(u, i) \ 477 amdzen_umc_smn_reg(u, D_UMC_RANK_HASH_EXT_DDR5, i) 478 #define UMC_RANK_HASH_EXT_GET_ADDR(r) bitx32(r, 7, 0) 479 #define UMC_RANK_HASH_EXT_ADDR_SHIFT 40 480 481 /* 482 * UMC::CH::AddrHashPC, UMC::CH::AddrHashPC2 -- These registers describe a hash 483 * to use for the DDR5 sub-channel. Note, in the DDR4 case this is actually the 484 * upper two rank hash registers defined above because on the systems where this 485 * occurs for DDR4, they only have up to one rank hash. 486 */ 487 /*CSTYLED*/ 488 #define D_UMC_PC_HASH_DDR5 (const smn_reg_def_t){ \ 489 .srd_unit = SMN_UNIT_UMC, \ 490 .srd_reg = 0xc0 \ 491 } 492 /*CSTYLED*/ 493 #define D_UMC_PC_HASH2_DDR5 (const smn_reg_def_t){ \ 494 .srd_unit = SMN_UNIT_UMC, \ 495 .srd_reg = 0xc4 \ 496 } 497 #define UMC_PC_HASH_DDR4(u) UMC_RANK_HASH_DDR4(u, 1) 498 #define UMC_PC_HASH2_DDR4(u) UMC_RANK_HASH_DDR4(u, 2) 499 #define UMC_PC_HASH_DDR5(u) amdzen_umc_smn_reg(u, D_UMC_PC_HASH_DDR5, 0) 500 #define UMC_PC_HASH2_DDR5(u) amdzen_umc_smn_reg(u, D_UMC_PC_HASH2_DDR5, 0) 501 #define UMC_PC_HASH_GET_ROW(r) bitx32(r, 31, 14) 502 #define UMC_PC_HASH_GET_COL(r) bitx32(r, 13, 1) 503 #define UMC_PC_HASH_GET_EN(r) bitx32(r, 0, 0) 504 #define UMC_PC_HASH2_GET_BANK(r) bitx32(r, 4, 0) 505 506 /* 507 * UMC::CH::AddrHashCS -- Hashing: chip-select edition. Note, these can 508 * ultimately cause you to change which DIMM is being actually accessed. 509 */ 510 /*CSTYLED*/ 511 #define D_UMC_CS_HASH_DDR4 (const smn_reg_def_t){ \ 512 .srd_unit = SMN_UNIT_UMC, \ 513 .srd_reg = 0xe8, \ 514 .srd_nents = 2 \ 515 } 516 /*CSTYLED*/ 517 #define D_UMC_CS_HASH_DDR5 (const smn_reg_def_t){ \ 518 .srd_unit = SMN_UNIT_UMC, \ 519 .srd_reg = 0xc8, \ 520 .srd_nents = 2 \ 521 } 522 #define UMC_CS_HASH_DDR4(u, i) amdzen_umc_smn_reg(u, D_UMC_CS_HASH_DDR4, i) 523 #define UMC_CS_HASH_DDR5(u, i) amdzen_umc_smn_reg(u, D_UMC_CS_HASH_DDR5, i) 524 #define UMC_CS_HASH_GET_ADDR(r) bitx32(r, 31, 1) 525 #define UMC_CS_HASH_SHIFT 9 526 #define UMC_CS_HASH_GET_EN(r) bitx32(r, 0, 0) 527 528 /* 529 * UMC::AddrHashExtCS -- Extended chip-select hash addresses. 530 */ 531 /*CSTYLED*/ 532 #define D_UMC_CS_HASH_EXT_DDR5 (const smn_reg_def_t){ \ 533 .srd_unit = SMN_UNIT_UMC, \ 534 .srd_reg = 0xbc8, \ 535 .srd_nents = 2 \ 536 } 537 #define UMC_CS_HASH_EXT_DDR5(u, i) \ 538 amdzen_umc_smn_reg(u, D_UMC_CS_HASH_EXT_DDR5, i) 539 #define UMC_CS_HASH_EXT_GET_ADDR(r) bitx32(r, 7, 0) 540 #define UMC_CS_HASH_EXT_ADDR_SHIFT 40 541 542 /* 543 * UMC::CH::UmcConfig -- This register controls various features of the device. 544 * For our purposes we mostly care about seeing if ECC is enabled and a DIMM 545 * type. 546 */ 547 /*CSTYLED*/ 548 #define D_UMC_UMCCFG (const smn_reg_def_t){ \ 549 .srd_unit = SMN_UNIT_UMC, \ 550 .srd_reg = 0x100 \ 551 } 552 #define UMC_UMCCFG(u) amdzen_umc_smn_reg(u, D_UMC_UMCCFG, 0) 553 #define UMC_UMCCFG_GET_READY(r) bitx32(r, 31, 31) 554 #define UMC_UMCCFG_GET_ECC_EN(r) bitx32(r, 12, 12) 555 #define UMC_UMCCFG_GET_BURST_CTL(r) bitx32(r, 11, 10) 556 #define UMC_UMCCFG_GET_BURST_LEN(r) bitx32(r, 9, 8) 557 #define UMC_UMCCFG_GET_DDR_TYPE(r) bitx32(r, 2, 0) 558 #define UMC_UMCCFG_DDR4_T_DDR4 0 559 #define UMC_UMCCFG_DDR4_T_LPDDR4 5 560 561 #define UMC_UMCCFG_DDR5_T_DDR4 0 562 #define UMC_UMCCFG_DDR5_T_DDR5 1 563 #define UMC_UMCCFG_DDR5_T_LPDDR4 5 564 #define UMC_UMCCFG_DDR5_T_LPDDR5 6 565 566 /* 567 * UMC::CH::DataCtrl -- Various settings around whether data encryption or 568 * scrambling is enabled. Note, this register really changes a bunch from family 569 * to family. 570 */ 571 /*CSTYLED*/ 572 #define D_UMC_DATACTL (const smn_reg_def_t){ \ 573 .srd_unit = SMN_UNIT_UMC, \ 574 .srd_reg = 0x144 \ 575 } 576 #define UMC_DATACTL(u) amdzen_umc_smn_reg(u, D_UMC_DATACTL, 0) 577 #define UMC_DATACTL_GET_ENCR_EN(r) bitx32(r, 8, 8) 578 #define UMC_DATACTL_GET_SCRAM_EN(r) bitx32(r, 0, 0) 579 580 #define UMC_DATACTL_DDR4_GET_TWEAK(r) bitx32(r, 19, 16) 581 #define UMC_DATACTL_DDR4_GET_VMG2M(r) bitx32(r, 12, 12) 582 #define UMC_DATACTL_DDR4_GET_FORCE_ENCR(r) bitx32(r, 11, 11) 583 584 #define UMC_DATACTL_DDR5_GET_TWEAK(r) bitx32(r, 16, 16) 585 #define UMC_DATACTL_DDR5_GET_XTS(r) bitx32(r, 14, 14) 586 #define UMC_DATACTL_DDR5_GET_AES256(r) bitx32(r, 13, 13) 587 588 /* 589 * UMC::CH:EccCtrl -- Various settings around how ECC operates. 590 */ 591 /*CSTYLED*/ 592 #define D_UMC_ECCCTL (const smn_reg_def_t){ \ 593 .srd_unit = SMN_UNIT_UMC, \ 594 .srd_reg = 0x14c \ 595 } 596 #define UMC_ECCCTL(u) amdzen_umc_smn_reg(u, D_UMC_ECCCTL, 0) 597 #define UMC_ECCCTL_GET_RD_EN(r) bitx32(x, 10, 10) 598 #define UMC_ECCCTL_GET_X16(r) bitx32(x, 9, 9) 599 #define UMC_ECCCTL_GET_UC_FATAL(r) bitx32(x, 8, 8) 600 #define UMC_ECCCTL_GET_SYM_SIZE(r) bitx32(x, 7, 7) 601 #define UMC_ECCCTL_GET_BIT_IL(r) bitx32(x, 6, 6) 602 #define UMC_ECCCTL_GET_HIST_EN(r) bitx32(x, 5, 5) 603 #define UMC_ECCCTL_GET_SW_SYM_EN(r) bitx32(x, 4, 4) 604 #define UMC_ECCCTL_GET_WR_EN(r) bitx32(x, 0, 0) 605 606 /* 607 * Note, while this group appears generic and is the same in both DDR4/DDR5 608 * systems, this is not always present on every SoC and seems to depend on 609 * something else inside the chip. 610 */ 611 #define UMC_ECCCTL_DDR_GET_PI(r) bitx32(r, 13, 13) 612 #define UMC_ECCCTL_DDR_GET_PF_DIS(r) bitx32(r, 12, 12) 613 #define UMC_ECCCTL_DDR_GET_SDP_OVR(r) bitx32(x, 11, 11) 614 #define UMC_ECCCTL_DDR_GET_REPLAY_EN(r) bitx32(x, 1, 1) 615 616 #define UMC_ECCCTL_DDR5_GET_PIN_RED(r) bitx32(r, 14, 14) 617 618 /* 619 * UMC::Ch::UmcCap, UMC::CH::UmcCapHi -- Various capability registers and 620 * feature disables. We mostly just record these for future us for debugging 621 * purposes. They aren't used as part of memory decoding. 622 */ 623 /*CSTYLED*/ 624 #define D_UMC_UMCCAP (const smn_reg_def_t){ \ 625 .srd_unit = SMN_UNIT_UMC, \ 626 .srd_reg = 0xdf0 \ 627 } 628 /*CSTYLED*/ 629 #define D_UMC_UMCCAP_HI (const smn_reg_def_t){ \ 630 .srd_unit = SMN_UNIT_UMC, \ 631 .srd_reg = 0xdf4 \ 632 } 633 #define UMC_UMCCAP(u) amdzen_umc_smn_reg(u, D_UMC_UMCCAP, 0) 634 #define UMC_UMCCAP_HI(u) amdzen_umc_smn_reg(u, D_UMC_UMCCAP_HI, 0) 635 636 #ifdef __cplusplus 637 } 638 #endif 639 640 #endif /* _SYS_UMC_H */ 641