171815ce7SRobert Mustacchi /* 271815ce7SRobert Mustacchi * This file and its contents are supplied under the terms of the 371815ce7SRobert Mustacchi * Common Development and Distribution License ("CDDL"), version 1.0. 471815ce7SRobert Mustacchi * You may only use this file in accordance with the terms of version 571815ce7SRobert Mustacchi * 1.0 of the CDDL. 671815ce7SRobert Mustacchi * 771815ce7SRobert Mustacchi * A full copy of the text of the CDDL should have accompanied this 871815ce7SRobert Mustacchi * source. A copy of the CDDL is also available via the Internet at 971815ce7SRobert Mustacchi * http://www.illumos.org/license/CDDL. 1071815ce7SRobert Mustacchi */ 1171815ce7SRobert Mustacchi 1271815ce7SRobert Mustacchi /* 13019df03dSRobert Mustacchi * Copyright 2024 Oxide Computer Company 1471815ce7SRobert Mustacchi */ 1571815ce7SRobert Mustacchi 1671815ce7SRobert Mustacchi #ifndef _SYS_AMDZEN_DF_H 1771815ce7SRobert Mustacchi #define _SYS_AMDZEN_DF_H 1871815ce7SRobert Mustacchi 1971815ce7SRobert Mustacchi /* 2071815ce7SRobert Mustacchi * This file contains definitions for the registers that appears in the AMD Zen 2171815ce7SRobert Mustacchi * Data Fabric. The data fabric is the main component which routes transactions 2271815ce7SRobert Mustacchi * between entities (e.g. CPUS, DRAM, PCIe, etc.) in the system. The data fabric 2371815ce7SRobert Mustacchi * itself is made up of up to 8 PCI functions. There can be multiple instances 2471815ce7SRobert Mustacchi * of the data fabric. There is one instance per die. In most AMD processors 2571815ce7SRobert Mustacchi * after Zen 1, there is only a single die per socket, for more background see 2671815ce7SRobert Mustacchi * the uts/i86pc/os/cpuid.c big theory statement. All data fabric instances 2771815ce7SRobert Mustacchi * appear on PCI bus 0. The first instance shows up on device 0x18. Subsequent 2871815ce7SRobert Mustacchi * instances simply increment that number by one. 2971815ce7SRobert Mustacchi * 3071815ce7SRobert Mustacchi * There are currently four major revisions of the data fabric that are 3171815ce7SRobert Mustacchi * supported here, which are v2 (Zen 1), v3 (Zen 2/3), v3.5 (Zen 2/3 with DDR5), 3271815ce7SRobert Mustacchi * and v4 (Zen 4). In many cases, while the same logical thing exists in 3371815ce7SRobert Mustacchi * different generations, they often have different shapes and sometimes things 34019df03dSRobert Mustacchi * with the same shape show up in different locations. As DFv4 has been extended 35019df03dSRobert Mustacchi * across several different lines, things haven't been quite as smooth as we'd 36019df03dSRobert Mustacchi * like in terms of DF representation. Certain things end up moving around much 37019df03dSRobert Mustacchi * more liberally while revving the minor version of the DF, though at least we 38019df03dSRobert Mustacchi * can still identify it as such. 39019df03dSRobert Mustacchi * 40019df03dSRobert Mustacchi * The major (relevant to us) distinction that we have found so far is that 41019df03dSRobert Mustacchi * starting in DF 4v2 and greater, the way that DRAM was structured and the 42019df03dSRobert Mustacchi * corresponding DRAM channel remap settings were moved. Because the DRAM base 43019df03dSRobert Mustacchi * address registers were moved to 0x200, we call this DF_REV_4D2. If this 44019df03dSRobert Mustacchi * gets much more nuanced, we should likely figure out if we want to encode 45019df03dSRobert Mustacchi * minor versions in these constants and offer function pointers to get common 46019df03dSRobert Mustacchi * things rather than forcing it onto clients. Note that this is very much a 47019df03dSRobert Mustacchi * rough approximation and not really great. There are many places where the 48019df03dSRobert Mustacchi * width of fields has changed slightly between minor revs, but are eating up 49019df03dSRobert Mustacchi * more reserved bits, or not using quite as many. 5071815ce7SRobert Mustacchi * 5171815ce7SRobert Mustacchi * To make things a little easier for clients, each register definition encodes 5271815ce7SRobert Mustacchi * enough information to also include which hardware generations it supports, 5371815ce7SRobert Mustacchi * the actual PCI function it appears upon, and the register offset. This is to 5471815ce7SRobert Mustacchi * make sure that consumers don't have to guess some of this information in the 5571815ce7SRobert Mustacchi * latter cases and we can try to guarantee we're not accessing an incorrect 5671815ce7SRobert Mustacchi * register for our platform (unfortunately at runtime). 5771815ce7SRobert Mustacchi * 5871815ce7SRobert Mustacchi * Register definitions have the following form: 5971815ce7SRobert Mustacchi * 6071815ce7SRobert Mustacchi * DF_<reg name>_<vers> 6171815ce7SRobert Mustacchi * 6271815ce7SRobert Mustacchi * Here <reg name> is something that describes the register. This may not be the 6371815ce7SRobert Mustacchi * exact same as the PPR (processor programming reference); however, the PPR 6471815ce7SRobert Mustacchi * name for the register will be included above it in a comment (though these 6571815ce7SRobert Mustacchi * have sometimes changed from time to time). For example, DF_DRAM_HOLE. If a 6671815ce7SRobert Mustacchi * given register is the same in all currently supported versions, then there is 6771815ce7SRobert Mustacchi * no version suffix appended. Otherwise, the first version it is supported in 6871815ce7SRobert Mustacchi * is appended. For example, DF_DRAM_BASE_V2, DF_DRAM_BASE_V3, DF_DRAM_BASE_V4, 6971815ce7SRobert Mustacchi * etc. or DF_FIDMASK0_V3P5, etc. If the register offset is the same in multiple 7071815ce7SRobert Mustacchi * versions, then there they share the earliest version. 7171815ce7SRobert Mustacchi * 7271815ce7SRobert Mustacchi * For fields there are currently macros to extract these or chain them together 7371815ce7SRobert Mustacchi * leveraging bitx32() and bitset32(). Fields have the forms: 7471815ce7SRobert Mustacchi * 7571815ce7SRobert Mustacchi * DF_<reg name>_<vers>_GET_<field> 7671815ce7SRobert Mustacchi * DF_<reg name>_<vers>_SET_<field> 7771815ce7SRobert Mustacchi * 7871815ce7SRobert Mustacchi * Like in the above, if there are cases where a single field is the same across 7971815ce7SRobert Mustacchi * all versions, then the <vers> portion will be elided. There are many cases 8071815ce7SRobert Mustacchi * where the register definition does not change, but the fields themselves do 8171815ce7SRobert Mustacchi * change with each version because each hardware rev opts to be slightly 8271815ce7SRobert Mustacchi * different. 8371815ce7SRobert Mustacchi * 8471815ce7SRobert Mustacchi * When adding support for a new chip, please look carefully through the 8571815ce7SRobert Mustacchi * requisite documentation to ensure that they match what we see here. There are 8671815ce7SRobert Mustacchi * often cases where there may be a subtle thing or you hit a case like V3P5 8771815ce7SRobert Mustacchi * that until you dig deeper just seem to be weird. 8871815ce7SRobert Mustacchi */ 8971815ce7SRobert Mustacchi 9071815ce7SRobert Mustacchi #include <sys/bitext.h> 9171815ce7SRobert Mustacchi 9271815ce7SRobert Mustacchi #ifdef __cplusplus 9371815ce7SRobert Mustacchi extern "C" { 9471815ce7SRobert Mustacchi #endif 9571815ce7SRobert Mustacchi 9671815ce7SRobert Mustacchi typedef enum df_rev { 9771815ce7SRobert Mustacchi DF_REV_UNKNOWN = 0, 9871815ce7SRobert Mustacchi DF_REV_2 = 1 << 0, 9971815ce7SRobert Mustacchi DF_REV_3 = 1 << 1, 10071815ce7SRobert Mustacchi DF_REV_3P5 = 1 << 2, 101019df03dSRobert Mustacchi DF_REV_4 = 1 << 3, 102019df03dSRobert Mustacchi /* 103019df03dSRobert Mustacchi * This is a synthetic revision we make up per the theory statement that 104019df03dSRobert Mustacchi * covers devices that have an updated DRAM layout. 105019df03dSRobert Mustacchi */ 106019df03dSRobert Mustacchi DF_REV_4D2 = 1 << 4 10771815ce7SRobert Mustacchi } df_rev_t; 10871815ce7SRobert Mustacchi 109dd23d762SRobert Mustacchi #define DF_REV_ALL_3 (DF_REV_3 | DF_REV_3P5) 110019df03dSRobert Mustacchi #define DF_REV_ALL_23 (DF_REV_2 | DF_REV_ALL_3) 111019df03dSRobert Mustacchi #define DF_REV_ALL_4 (DF_REV_4 | DF_REV_4D2) 112019df03dSRobert Mustacchi #define DF_REV_ALL (DF_REV_ALL_23 | DF_REV_ALL_4) 11371815ce7SRobert Mustacchi 11471815ce7SRobert Mustacchi typedef struct df_reg_def { 11571815ce7SRobert Mustacchi df_rev_t drd_gens; 11671815ce7SRobert Mustacchi uint8_t drd_func; 11771815ce7SRobert Mustacchi uint16_t drd_reg; 11871815ce7SRobert Mustacchi } df_reg_def_t; 11971815ce7SRobert Mustacchi 12071815ce7SRobert Mustacchi /* 12171815ce7SRobert Mustacchi * This set of registers provides us access to the count of instances in the 12271815ce7SRobert Mustacchi * data fabric and then a number of different pieces of information about them 12371815ce7SRobert Mustacchi * like their type. Note, these registers require indirect access because the 12471815ce7SRobert Mustacchi * information cannot be broadcast. 12571815ce7SRobert Mustacchi */ 12671815ce7SRobert Mustacchi 12771815ce7SRobert Mustacchi /* 12871815ce7SRobert Mustacchi * DF::FabricBlockInstanceCount -- Describes the number of instances in the data 12971815ce7SRobert Mustacchi * fabric. With v4, also includes versioning information. 13071815ce7SRobert Mustacchi */ 13171815ce7SRobert Mustacchi /*CSTYLED*/ 13271815ce7SRobert Mustacchi #define DF_FBICNT (df_reg_def_t){ .drd_gens = DF_REV_ALL, \ 13371815ce7SRobert Mustacchi .drd_func = 0, .drd_reg = 0x40 } 13471815ce7SRobert Mustacchi #define DF_FBICNT_V4_GET_MAJOR(r) bitx32(r, 27, 24) 13571815ce7SRobert Mustacchi #define DF_FBICNT_V4_GET_MINOR(r) bitx32(r, 23, 16) 13671815ce7SRobert Mustacchi #define DF_FBICNT_GET_COUNT(r) bitx32(r, 7, 0) 13771815ce7SRobert Mustacchi 13871815ce7SRobert Mustacchi /* 13971815ce7SRobert Mustacchi * DF::FabricBlockInstanceInformation0 -- get basic information about a fabric 14071815ce7SRobert Mustacchi * instance. 14171815ce7SRobert Mustacchi */ 14271815ce7SRobert Mustacchi /*CSTYLED*/ 14371815ce7SRobert Mustacchi #define DF_FBIINFO0 (df_reg_def_t){ .drd_gens = DF_REV_ALL, \ 14471815ce7SRobert Mustacchi .drd_func = 0, .drd_reg = 0x44 } 14571815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_SUBTYPE(r) bitx32(r, 26, 24) 14671815ce7SRobert Mustacchi #define DF_SUBTYPE_NONE 0 14771815ce7SRobert Mustacchi typedef enum { 14871815ce7SRobert Mustacchi DF_CAKE_SUBTYPE_GMI = 1, 14971815ce7SRobert Mustacchi DF_CAKE_SUBTYPE_xGMI = 2 15071815ce7SRobert Mustacchi } df_cake_subtype_t; 15171815ce7SRobert Mustacchi 15271815ce7SRobert Mustacchi typedef enum { 15371815ce7SRobert Mustacchi DF_IOM_SUBTYPE_IOHUB = 1, 15471815ce7SRobert Mustacchi } df_iom_subtype_t; 15571815ce7SRobert Mustacchi 15671815ce7SRobert Mustacchi typedef enum { 15771815ce7SRobert Mustacchi DF_CS_SUBTYPE_UMC = 1, 15871815ce7SRobert Mustacchi /* 15971815ce7SRobert Mustacchi * The subtype changed beginning in DFv4. Prior to DFv4, the secondary 16071815ce7SRobert Mustacchi * type was CCIX. Starting with DFv4, this is now CMP. It is unclear if 16171815ce7SRobert Mustacchi * these are the same thing or not. 16271815ce7SRobert Mustacchi */ 16371815ce7SRobert Mustacchi DF_CS_SUBTYPE_CCIX = 2, 16471815ce7SRobert Mustacchi DF_CS_SUBTYPE_CMP = 2 16571815ce7SRobert Mustacchi } df_cs_subtype_t; 16671815ce7SRobert Mustacchi 16771815ce7SRobert Mustacchi /* 168019df03dSRobert Mustacchi * Starting in DFv4 they introduced a CCM subtype; however, kept the CPU 169019df03dSRobert Mustacchi * compatible with prior DF revisions in v4.0. Starting with v4.1, they moved 170019df03dSRobert Mustacchi * this to a value of one and the less asked about the ACM the better. 171019df03dSRobert Mustacchi * Unfortunately this doesn't fit nicely with the major DF revisions which we 172019df03dSRobert Mustacchi * use for register access. 17371815ce7SRobert Mustacchi */ 17471815ce7SRobert Mustacchi typedef enum { 175019df03dSRobert Mustacchi DF_CCM_SUBTYPE_CPU_V2 = 0, 176019df03dSRobert Mustacchi DF_CCM_SUBTYPE_ACM_V4 = 1, 177019df03dSRobert Mustacchi DF_CCM_SUBTYPE_CPU_V4P1 = 1 17871815ce7SRobert Mustacchi } df_ccm_subtype_v4_t; 179019df03dSRobert Mustacchi 180019df03dSRobert Mustacchi typedef enum { 181019df03dSRobert Mustacchi DF_NCM_SUBTYPE_MMHUB = 1, 182019df03dSRobert Mustacchi DF_NCM_SUBTYPE_DCE = 2, 183019df03dSRobert Mustacchi DF_NCM_SUBTYPE_IOMMU = 4 184019df03dSRobert Mustacchi } df_ncm_subtype_t; 185019df03dSRobert Mustacchi 186019df03dSRobert Mustacchi 18771815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_HAS_MCA(r) bitx32(r, 23, 23) 18871815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_FTI_DCNT(r) bitx32(r, 21, 20) 18971815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_FTI_PCNT(r) bitx32(r, 18, 16) 19071815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_SDP_RESPCNT(r) bitx32(r, 14, 14) 19171815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_SDP_PCNT(r) bitx32(r, 13, 12) 19271815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_FTI_WIDTH(r) bitx32(r, 9, 8) 19371815ce7SRobert Mustacchi typedef enum { 19471815ce7SRobert Mustacchi DF_FTI_W_64 = 0, 19571815ce7SRobert Mustacchi DF_FTI_W_128, 19671815ce7SRobert Mustacchi DF_FTI_W_256, 19771815ce7SRobert Mustacchi DF_FTI_W_512 19871815ce7SRobert Mustacchi } df_fti_width_t; 19971815ce7SRobert Mustacchi #define DF_FBIINFO0_V3_GET_ENABLED(r) bitx32(r, 6, 6) 20071815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_SDP_WIDTH(r) bitx32(r, 5, 4) 20171815ce7SRobert Mustacchi typedef enum { 20271815ce7SRobert Mustacchi DF_SDP_W_64 = 0, 20371815ce7SRobert Mustacchi DF_SDP_W_128, 20471815ce7SRobert Mustacchi DF_SDP_W_256, 20571815ce7SRobert Mustacchi DF_SDP_W_512 20671815ce7SRobert Mustacchi } df_sdp_width_t; 20771815ce7SRobert Mustacchi #define DF_FBIINFO0_GET_TYPE(r) bitx32(r, 3, 0) 20871815ce7SRobert Mustacchi typedef enum { 20971815ce7SRobert Mustacchi DF_TYPE_CCM = 0, 21071815ce7SRobert Mustacchi DF_TYPE_GCM, 21171815ce7SRobert Mustacchi DF_TYPE_NCM, 21271815ce7SRobert Mustacchi DF_TYPE_IOMS, 21371815ce7SRobert Mustacchi DF_TYPE_CS, 21471815ce7SRobert Mustacchi DF_TYPE_NCS, 21571815ce7SRobert Mustacchi DF_TYPE_TCDX, 21671815ce7SRobert Mustacchi DF_TYPE_PIE, 21771815ce7SRobert Mustacchi DF_TYPE_SPF, 21871815ce7SRobert Mustacchi DF_TYPE_LLC, 21971815ce7SRobert Mustacchi DF_TYPE_CAKE, 220019df03dSRobert Mustacchi DF_TYPE_ICNG, 221019df03dSRobert Mustacchi DF_TYPE_PFX, 222019df03dSRobert Mustacchi DF_TYPE_CNLI 22371815ce7SRobert Mustacchi } df_type_t; 22471815ce7SRobert Mustacchi 22571815ce7SRobert Mustacchi /* 22671815ce7SRobert Mustacchi * DF::FabricBlockInstanceInformation1 -- get basic information about a fabric 227019df03dSRobert Mustacchi * instance. This appears to have been dropped starting in DF 4D2. 22871815ce7SRobert Mustacchi */ 22971815ce7SRobert Mustacchi /*CSTYLED*/ 230019df03dSRobert Mustacchi #define DF_FBIINFO1 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \ 231019df03dSRobert Mustacchi DF_REV_4, .drd_func = 0, .drd_reg = 0x48 } 23271815ce7SRobert Mustacchi #define DF_FBINFO1_GET_FTI3_NINSTID(r) bitx32(r, 31, 24) 23371815ce7SRobert Mustacchi #define DF_FBINFO1_GET_FTI2_NINSTID(r) bitx32(r, 23, 16) 23471815ce7SRobert Mustacchi #define DF_FBINFO1_GET_FTI1_NINSTID(r) bitx32(r, 15, 8) 23571815ce7SRobert Mustacchi #define DF_FBINFO1_GET_FTI0_NINSTID(r) bitx32(r, 7, 0) 23671815ce7SRobert Mustacchi 23771815ce7SRobert Mustacchi /* 23871815ce7SRobert Mustacchi * DF::FabricBlockInstanceInformation2 -- get basic information about a fabric 239019df03dSRobert Mustacchi * instance. This appears to have been dropped starting in DF 4D2. 24071815ce7SRobert Mustacchi */ 24171815ce7SRobert Mustacchi /*CSTYLED*/ 242019df03dSRobert Mustacchi #define DF_FBIINFO2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \ 243019df03dSRobert Mustacchi DF_REV_4, .drd_func = 0, .drd_reg = 0x4c } 24471815ce7SRobert Mustacchi #define DF_FBINFO2_GET_FTI5_NINSTID(r) bitx32(r, 15, 8) 24571815ce7SRobert Mustacchi #define DF_FBINFO2_GET_FTI4_NINSTID(r) bitx32(r, 7, 0) 24671815ce7SRobert Mustacchi 24771815ce7SRobert Mustacchi /* 24871815ce7SRobert Mustacchi * DF::FabricBlockInstanceInformation3 -- obtain the basic IDs for a given 24971815ce7SRobert Mustacchi * instance. 25071815ce7SRobert Mustacchi */ 25171815ce7SRobert Mustacchi /*CSTYLED*/ 25271815ce7SRobert Mustacchi #define DF_FBIINFO3 (df_reg_def_t){ .drd_gens = DF_REV_ALL, \ 25371815ce7SRobert Mustacchi .drd_func = 0, .drd_reg = 0x50 } 25471815ce7SRobert Mustacchi #define DF_FBIINFO3_V2_GET_BLOCKID(r) bitx32(r, 15, 8) 25571815ce7SRobert Mustacchi #define DF_FBIINFO3_V3_GET_BLOCKID(r) bitx32(r, 13, 8) 25671815ce7SRobert Mustacchi #define DF_FBIINFO3_V3P5_GET_BLOCKID(r) bitx32(r, 11, 8) 25771815ce7SRobert Mustacchi #define DF_FBIINFO3_V4_GET_BLOCKID(r) bitx32(r, 19, 8) 25871815ce7SRobert Mustacchi #define DF_FBIINFO3_GET_INSTID(r) bitx32(r, 7, 0) 25971815ce7SRobert Mustacchi 26071815ce7SRobert Mustacchi /* 261019df03dSRobert Mustacchi * DF::DfCapability -- Describes the capabilities that the DF has. 262019df03dSRobert Mustacchi */ 263019df03dSRobert Mustacchi /*CSTYLED*/ 264019df03dSRobert Mustacchi #define DF_CAPAB (df_reg_def_t){ .drd_gens = DF_REV_ALL, \ 265019df03dSRobert Mustacchi .drd_func = 0, .drd_reg = 0x90 } 266019df03dSRobert Mustacchi #define DF_CAPAB_GET_EXTCSREMAP(r) bitx32(r, 2, 2); 267019df03dSRobert Mustacchi #define DF_CAPAB_GET_SPF(r) bitx32(r, 1, 1); 268019df03dSRobert Mustacchi #define DF_CAPAB_GET_POISON(r) bitx32(r, 0, 0); 269019df03dSRobert Mustacchi 270019df03dSRobert Mustacchi /* 27171815ce7SRobert Mustacchi * DF::Skt0CsTargetRemap0, DF::Skt0CsTargetRemap1, DF::Skt1CsTargetRemap0, 27271815ce7SRobert Mustacchi * DF::Skt1CsTargetRemap1 -- The next set of registers provide access to 27371815ce7SRobert Mustacchi * chip-select remapping. Caution, while these have a documented DF generation 27471815ce7SRobert Mustacchi * that they are specific to, it seems they still aren't always implemented and 27571815ce7SRobert Mustacchi * are specific to Milan (v3) and Genoa (v4). The actual remap extraction is the 27671815ce7SRobert Mustacchi * same between both. 27771815ce7SRobert Mustacchi */ 27871815ce7SRobert Mustacchi #define DF_CS_REMAP_GET_CSX(r, x) bitx32(r, (3 + (4 * (x))), (4 * ((x)))) 27971815ce7SRobert Mustacchi /*CSTYLED*/ 28071815ce7SRobert Mustacchi #define DF_SKT0_CS_REMAP0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 28171815ce7SRobert Mustacchi .drd_func = 0, .drd_reg = 0x60 } 28271815ce7SRobert Mustacchi /*CSTYLED*/ 28371815ce7SRobert Mustacchi #define DF_SKT1_CS_REMAP0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 28471815ce7SRobert Mustacchi .drd_func = 0, .drd_reg = 0x68 } 28571815ce7SRobert Mustacchi /*CSTYLED*/ 28671815ce7SRobert Mustacchi #define DF_SKT0_CS_REMAP1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 28771815ce7SRobert Mustacchi .drd_func = 0, .drd_reg = 0x64 } 28871815ce7SRobert Mustacchi /*CSTYLED*/ 28971815ce7SRobert Mustacchi #define DF_SKT1_CS_REMAP1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 29071815ce7SRobert Mustacchi .drd_func = 0, .drd_reg = 0x6c } 29171815ce7SRobert Mustacchi /* 29271815ce7SRobert Mustacchi * DF::CsTargetRemap0A, DF::CsTargetRemap0B, etc. -- These registers contain the 29371815ce7SRobert Mustacchi * remap engines in DFv4. Note, that while v3 used 0/1 as REMAP[01], as 29471815ce7SRobert Mustacchi * referring to the same logical set of things, here [0-3] is used for different 295019df03dSRobert Mustacchi * things and A/B distinguish the different actual CS values. This was redone to 296019df03dSRobert Mustacchi * allow for a wider channel selection in the 4D2 parts, see the subsequent 297019df03dSRobert Mustacchi * section. 29871815ce7SRobert Mustacchi */ 29971815ce7SRobert Mustacchi /*CSTYLED*/ 30071815ce7SRobert Mustacchi #define DF_CS_REMAP0A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 30171815ce7SRobert Mustacchi .drd_func = 7, .drd_reg = 0x180 } 30271815ce7SRobert Mustacchi /*CSTYLED*/ 30371815ce7SRobert Mustacchi #define DF_CS_REMAP0B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 30471815ce7SRobert Mustacchi .drd_func = 7, .drd_reg = 0x184 } 30571815ce7SRobert Mustacchi /*CSTYLED*/ 30671815ce7SRobert Mustacchi #define DF_CS_REMAP1A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 30771815ce7SRobert Mustacchi .drd_func = 7, .drd_reg = 0x188 } 30871815ce7SRobert Mustacchi /*CSTYLED*/ 30971815ce7SRobert Mustacchi #define DF_CS_REMAP1B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 31071815ce7SRobert Mustacchi .drd_func = 7, .drd_reg = 0x18c } 31171815ce7SRobert Mustacchi /*CSTYLED*/ 31271815ce7SRobert Mustacchi #define DF_CS_REMAP2A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 31371815ce7SRobert Mustacchi .drd_func = 7, .drd_reg = 0x190 } 31471815ce7SRobert Mustacchi /*CSTYLED*/ 31571815ce7SRobert Mustacchi #define DF_CS_REMAP2B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 31671815ce7SRobert Mustacchi .drd_func = 7, .drd_reg = 0x194 } 31771815ce7SRobert Mustacchi /*CSTYLED*/ 31871815ce7SRobert Mustacchi #define DF_CS_REMAP3A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 31971815ce7SRobert Mustacchi .drd_func = 7, .drd_reg = 0x198 } 32071815ce7SRobert Mustacchi /*CSTYLED*/ 32171815ce7SRobert Mustacchi #define DF_CS_REMAP3B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 32271815ce7SRobert Mustacchi .drd_func = 7, .drd_reg = 0x19c } 323019df03dSRobert Mustacchi 324019df03dSRobert Mustacchi /* 325019df03dSRobert Mustacchi * DF::CsTargetRemap0A, DF::CsTargetRemap0B, etc. -- D42 edition. This has 326019df03dSRobert Mustacchi * changed the actual size of the remap values so that they are now 5 bits wide, 327019df03dSRobert Mustacchi * allowing for up to 32 channels. This is indicated by bit 2 (EXTCSREMAP) in 328019df03dSRobert Mustacchi * DF::DfCapability. As a result, there are now only 6 remaps per register, so 329019df03dSRobert Mustacchi * there are now 3 registers [ABC] per remap target [0123]. 330019df03dSRobert Mustacchi * changing around where the registers actually are. 331019df03dSRobert Mustacchi */ 332019df03dSRobert Mustacchi #define DF_CS_REMAP_GET_CSX_V4B(r, x) bitx32(r, (4 + (5 * (x))), (5 * ((x)))) 333019df03dSRobert Mustacchi /*CSTYLED*/ 334019df03dSRobert Mustacchi #define DF_CS_REMAP0A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 335019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x180 } 336019df03dSRobert Mustacchi /*CSTYLED*/ 337019df03dSRobert Mustacchi #define DF_CS_REMAP0B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 338019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x184 } 339019df03dSRobert Mustacchi /*CSTYLED*/ 340019df03dSRobert Mustacchi #define DF_CS_REMAP0C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 341019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x188 } 342019df03dSRobert Mustacchi /*CSTYLED*/ 343019df03dSRobert Mustacchi #define DF_CS_REMAP1A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 344019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x198 } 345019df03dSRobert Mustacchi /*CSTYLED*/ 346019df03dSRobert Mustacchi #define DF_CS_REMAP1B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 347019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x19c } 348019df03dSRobert Mustacchi /*CSTYLED*/ 349019df03dSRobert Mustacchi #define DF_CS_REMAP1C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 350019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x1a0 } 351019df03dSRobert Mustacchi /*CSTYLED*/ 352019df03dSRobert Mustacchi #define DF_CS_REMAP2A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 353019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x1b0 } 354019df03dSRobert Mustacchi /*CSTYLED*/ 355019df03dSRobert Mustacchi #define DF_CS_REMAP2B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 356019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x1b4 } 357019df03dSRobert Mustacchi /*CSTYLED*/ 358019df03dSRobert Mustacchi #define DF_CS_REMAP2C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 359019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x1b8 } 360019df03dSRobert Mustacchi /*CSTYLED*/ 361019df03dSRobert Mustacchi #define DF_CS_REMAP3A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 362019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x1c8 } 363019df03dSRobert Mustacchi /*CSTYLED*/ 364019df03dSRobert Mustacchi #define DF_CS_REMAP3B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 365019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x1cc } 366019df03dSRobert Mustacchi /*CSTYLED*/ 367019df03dSRobert Mustacchi #define DF_CS_REMAP3C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 368019df03dSRobert Mustacchi .drd_func = 7, .drd_reg = 0x1d0 } 369019df03dSRobert Mustacchi 37071815ce7SRobert Mustacchi /* 37171815ce7SRobert Mustacchi * DF::CfgAddressCntl -- This register contains the information about the 37271815ce7SRobert Mustacchi * configuration of PCIe buses. We care about finding which one has our BUS A, 37371815ce7SRobert Mustacchi * which is required to map it to the in-package northbridge instance. 37471815ce7SRobert Mustacchi */ 37571815ce7SRobert Mustacchi /*CSTYLED*/ 37671815ce7SRobert Mustacchi #define DF_CFG_ADDR_CTL_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 37771815ce7SRobert Mustacchi .drd_func = 0, \ 37871815ce7SRobert Mustacchi .drd_reg = 0x84 } 37971815ce7SRobert Mustacchi /*CSTYLED*/ 380019df03dSRobert Mustacchi #define DF_CFG_ADDR_CTL_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 38171815ce7SRobert Mustacchi .drd_func = 0, \ 38271815ce7SRobert Mustacchi .drd_reg = 0xc04 } 38371815ce7SRobert Mustacchi #define DF_CFG_ADDR_CTL_GET_BUS_NUM(r) bitx32(r, 7, 0) 38471815ce7SRobert Mustacchi 38571815ce7SRobert Mustacchi /* 38671815ce7SRobert Mustacchi * DF::CfgAddressMap -- This next set of registers covers PCI Bus configuration 38771815ce7SRobert Mustacchi * address maps. The layout here changes at v4. This routes a given PCI bus to a 38871815ce7SRobert Mustacchi * device. 38971815ce7SRobert Mustacchi */ 39071815ce7SRobert Mustacchi /*CSTYLED*/ 39171815ce7SRobert Mustacchi #define DF_CFGMAP_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 39271815ce7SRobert Mustacchi .drd_func = 0, \ 39371815ce7SRobert Mustacchi .drd_reg = 0xa0 + ((x) * 4) } 39471815ce7SRobert Mustacchi #define DF_MAX_CFGMAP 8 395019df03dSRobert Mustacchi #define DF_MAX_CFGMAP_TURIN 16 39671815ce7SRobert Mustacchi #define DF_CFGMAP_V2_GET_BUS_LIMIT(r) bitx32(r, 31, 24) 39771815ce7SRobert Mustacchi #define DF_CFGMAP_V2_GET_BUS_BASE(r) bitx32(r, 23, 16) 39871815ce7SRobert Mustacchi #define DF_CFGMAP_V2_GET_DEST_ID(r) bitx32(r, 11, 4) 39971815ce7SRobert Mustacchi #define DF_CFGMAP_V3_GET_DEST_ID(r) bitx32(r, 13, 4) 40071815ce7SRobert Mustacchi #define DF_CFGMAP_V3P5_GET_DEST_ID(r) bitx32(r, 7, 4) 40171815ce7SRobert Mustacchi #define DF_CFGMAP_V2_GET_WE(r) bitx32(r, 1, 1) 40271815ce7SRobert Mustacchi #define DF_CFGMAP_V2_GET_RE(r) bitx32(r, 0, 0) 40371815ce7SRobert Mustacchi 40471815ce7SRobert Mustacchi /* 40571815ce7SRobert Mustacchi * DF::CfgBaseAddress, DF::CfgLimitAddress -- DFv4 variants of the above now in 40671815ce7SRobert Mustacchi * two registers and more possible entries! 40771815ce7SRobert Mustacchi */ 40871815ce7SRobert Mustacchi /*CSTYLED*/ 409019df03dSRobert Mustacchi #define DF_CFGMAP_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 41071815ce7SRobert Mustacchi .drd_func = 0, \ 41171815ce7SRobert Mustacchi .drd_reg = 0xc80 + ((x) * 8) } 41271815ce7SRobert Mustacchi /*CSTYLED*/ 413019df03dSRobert Mustacchi #define DF_CFGMAP_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 41471815ce7SRobert Mustacchi .drd_func = 0, \ 41571815ce7SRobert Mustacchi .drd_reg = 0xc84 + ((x) * 8) } 41671815ce7SRobert Mustacchi #define DF_CFGMAP_BASE_V4_GET_BASE(r) bitx32(r, 23, 16) 41771815ce7SRobert Mustacchi #define DF_CFGMAP_BASE_V4_GET_SEG(r) bitx32(r, 15, 8) 41871815ce7SRobert Mustacchi #define DF_CFGMAP_BASE_V4_GET_WE(r) bitx32(r, 1, 1) 41971815ce7SRobert Mustacchi #define DF_CFGMAP_BASE_V4_GET_RE(r) bitx32(r, 0, 0) 42071815ce7SRobert Mustacchi #define DF_CFGMAP_LIMIT_V4_GET_LIMIT(r) bitx32(r, 23, 16) 42171815ce7SRobert Mustacchi #define DF_CFGMAP_LIMIT_V4_GET_DEST_ID(r) bitx32(r, 11, 0) 42271815ce7SRobert Mustacchi 42371815ce7SRobert Mustacchi /* 42471815ce7SRobert Mustacchi * DF::X86IOBaseAddress, DF::X86IOLimitAddress -- Base and limit registers for 425019df03dSRobert Mustacchi * routing I/O space. These are fairly similar prior to DFv4. The number of 426019df03dSRobert Mustacchi * these was increased in Turin. We expect this'll hold true for future server 427019df03dSRobert Mustacchi * parts. 42871815ce7SRobert Mustacchi */ 42971815ce7SRobert Mustacchi /*CSTYLED*/ 43071815ce7SRobert Mustacchi #define DF_IO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 43171815ce7SRobert Mustacchi .drd_func = 0, \ 43271815ce7SRobert Mustacchi .drd_reg = 0xc0 + ((x) * 8) } 43371815ce7SRobert Mustacchi /*CSTYLED*/ 43471815ce7SRobert Mustacchi #define DF_IO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 43571815ce7SRobert Mustacchi .drd_func = 0, \ 43671815ce7SRobert Mustacchi .drd_reg = 0xd00 + ((x) * 8) } 43771815ce7SRobert Mustacchi #define DF_MAX_IO_RULES 8 438019df03dSRobert Mustacchi #define DF_MAX_IO_RULES_TURIN 16 43971815ce7SRobert Mustacchi #define DF_IO_BASE_SHIFT 12 44071815ce7SRobert Mustacchi #define DF_IO_BASE_V2_GET_BASE(r) bitx32(r, 24, 12) 44171815ce7SRobert Mustacchi #define DF_IO_BASE_V2_GET_IE(r) bitx32(r, 5, 5) 44271815ce7SRobert Mustacchi #define DF_IO_BASE_V2_GET_WE(r) bitx32(r, 1, 1) 44371815ce7SRobert Mustacchi #define DF_IO_BASE_V2_GET_RE(r) bitx32(r, 0, 0) 44471815ce7SRobert Mustacchi #define DF_IO_BASE_V2_SET_BASE(r, v) bitset32(r, 24, 12, v) 44571815ce7SRobert Mustacchi #define DF_IO_BASE_V2_SET_IE(r, v) bitset32(r, 5, 5, v) 44671815ce7SRobert Mustacchi #define DF_IO_BASE_V2_SET_WE(r, v) bitset32(r, 1, 1, v) 44771815ce7SRobert Mustacchi #define DF_IO_BASE_V2_SET_RE(r, v) bitset32(r, 0, 0, v) 44871815ce7SRobert Mustacchi 44971815ce7SRobert Mustacchi #define DF_IO_BASE_V4_GET_BASE(r) bitx32(r, 28, 16) 45071815ce7SRobert Mustacchi #define DF_IO_BASE_V4_GET_IE(r) bitx32(r, 5, 5) 45171815ce7SRobert Mustacchi #define DF_IO_BASE_V4_GET_WE(r) bitx32(r, 1, 1) 45271815ce7SRobert Mustacchi #define DF_IO_BASE_V4_GET_RE(r) bitx32(r, 0, 0) 45371815ce7SRobert Mustacchi #define DF_IO_BASE_V4_SET_BASE(r, v) bitset32(r, 28, 16, v) 45471815ce7SRobert Mustacchi #define DF_IO_BASE_V4_SET_IE(r, v) bitset32(r, 5, 5, v) 45571815ce7SRobert Mustacchi #define DF_IO_BASE_V4_SET_WE(r, v) bitset32(r, 1, 1, v) 45671815ce7SRobert Mustacchi #define DF_IO_BASE_V4_SET_RE(r, v) bitset32(r, 0, 0, v) 45771815ce7SRobert Mustacchi 45871815ce7SRobert Mustacchi /*CSTYLED*/ 45971815ce7SRobert Mustacchi #define DF_IO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 46071815ce7SRobert Mustacchi .drd_func = 0, \ 46171815ce7SRobert Mustacchi .drd_reg = 0xc4 + ((x) * 8) } 46271815ce7SRobert Mustacchi /*CSTYLED*/ 46371815ce7SRobert Mustacchi #define DF_IO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 46471815ce7SRobert Mustacchi .drd_func = 0, \ 46571815ce7SRobert Mustacchi .drd_reg = 0xd04 + ((x) * 8) } 46671815ce7SRobert Mustacchi #define DF_MAX_IO_LIMIT ((1 << 24) - 1) 46771815ce7SRobert Mustacchi #define DF_IO_LIMIT_SHIFT 12 46871815ce7SRobert Mustacchi #define DF_IO_LIMIT_EXCL (1 << DF_IO_LIMIT_SHIFT) 46971815ce7SRobert Mustacchi #define DF_IO_LIMIT_V2_GET_LIMIT(r) bitx32(r, 24, 12) 47071815ce7SRobert Mustacchi #define DF_IO_LIMIT_V2_GET_DEST_ID(r) bitx32(r, 7, 0) 47171815ce7SRobert Mustacchi #define DF_IO_LIMIT_V3_GET_DEST_ID(r) bitx32(r, 9, 0) 47271815ce7SRobert Mustacchi #define DF_IO_LIMIT_V3P5_GET_DEST_ID(r) bitx32(r, 3, 0) 47371815ce7SRobert Mustacchi #define DF_IO_LIMIT_V2_SET_LIMIT(r, v) bitset32(r, 24, 12, v) 47471815ce7SRobert Mustacchi #define DF_IO_LIMIT_V2_SET_DEST_ID(r, v) bitset32(r, 7, 0, v) 47571815ce7SRobert Mustacchi #define DF_IO_LIMIT_V3_SET_DEST_ID(r, v) bitset32(r, 9, 0, v) 47671815ce7SRobert Mustacchi #define DF_IO_LIMIT_V3P5_SET_DEST_ID(r, v) bitset32(r, 3, 0, v) 47771815ce7SRobert Mustacchi 47871815ce7SRobert Mustacchi #define DF_IO_LIMIT_V4_GET_LIMIT(r) bitx32(r, 28, 16) 47971815ce7SRobert Mustacchi #define DF_IO_LIMIT_V4_GET_DEST_ID(r) bitx32(r, 11, 0) 48071815ce7SRobert Mustacchi #define DF_IO_LIMIT_V4_SET_LIMIT(r, v) bitset32(r, 28, 16, v) 48171815ce7SRobert Mustacchi #define DF_IO_LIMIT_V4_SET_DEST_ID(r, v) bitset32(r, 11, 0, v) 48271815ce7SRobert Mustacchi 48371815ce7SRobert Mustacchi /* 48471815ce7SRobert Mustacchi * DF::DramHoleControl -- This controls MMIO below 4 GiB. Note, both this and 48571815ce7SRobert Mustacchi * the Top of Memory (TOM) need to be set consistently. 48671815ce7SRobert Mustacchi */ 48771815ce7SRobert Mustacchi /*CSTYLED*/ 48871815ce7SRobert Mustacchi #define DF_DRAM_HOLE_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 48971815ce7SRobert Mustacchi .drd_func = 0, \ 49071815ce7SRobert Mustacchi .drd_reg = 0x104 } 49171815ce7SRobert Mustacchi /*CSTYLED*/ 492019df03dSRobert Mustacchi #define DF_DRAM_HOLE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 49371815ce7SRobert Mustacchi .drd_func = 7, \ 49471815ce7SRobert Mustacchi .drd_reg = 0x104 } 49571815ce7SRobert Mustacchi #define DF_DRAM_HOLE_GET_BASE(r) bitx32(r, 31, 24) 49671815ce7SRobert Mustacchi #define DF_DRAM_HOLE_BASE_SHIFT 24 49771815ce7SRobert Mustacchi #define DF_DRAM_HOLE_GET_VALID(r) bitx32(r, 0, 0) 49871815ce7SRobert Mustacchi 49971815ce7SRobert Mustacchi /* 50071815ce7SRobert Mustacchi * DF::DramBaseAddress, DF::DramLimitAddress -- DRAM rules, these are split into 50171815ce7SRobert Mustacchi * a base and limit. While DFv2, 3, and 3.5 all have the same addresses, they 50271815ce7SRobert Mustacchi * have different bit patterns entirely. DFv4 is in a different location and 50371815ce7SRobert Mustacchi * further splits this into four registers. We do all of the pre-DFv4 stuff and 50471815ce7SRobert Mustacchi * follow with DFv4. In DFv2-3.5 the actual values of the bits (e.g. the meaning 50571815ce7SRobert Mustacchi * of the channel interleave value) are the same, even though where those bits 50671815ce7SRobert Mustacchi * are in the register changes. 50771815ce7SRobert Mustacchi * 50871815ce7SRobert Mustacchi * In DF v2, v3, and v3.5 the set of constants for interleave values are the 50971815ce7SRobert Mustacchi * same, so we define them once at the v2 version. 51071815ce7SRobert Mustacchi */ 51171815ce7SRobert Mustacchi /*CSTYLED*/ 51271815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 51371815ce7SRobert Mustacchi .drd_func = 0, \ 51471815ce7SRobert Mustacchi .drd_reg = 0x110 + ((r) * 8) } 51571815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_GET_BASE(r) bitx32(r, 31, 12) 51671815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_BASE_SHIFT 28 51771815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_GET_ILV_ADDR(r) bitx32(r, 10, 8) 51871815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_GET_ILV_CHAN(r) bitx32(r, 7, 4) 51971815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_ILV_CHAN_1 0x0 52071815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_ILV_CHAN_2 0x1 52171815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_ILV_CHAN_4 0x3 52271815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_ILV_CHAN_8 0x5 52371815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_ILV_CHAN_6 0x6 52471815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_ILV_CHAN_COD4_2 0xc 52571815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_ILV_CHAN_COD2_4 0xd 52671815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_ILV_CHAN_COD1_8 0xe 52771815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_GET_HOLE_EN(r) bitx32(r, 1, 1) 52871815ce7SRobert Mustacchi #define DF_DRAM_BASE_V2_GET_VALID(r) bitx32(r, 0, 0) 52971815ce7SRobert Mustacchi 53071815ce7SRobert Mustacchi #define DF_DRAM_BASE_V3_GET_ILV_ADDR(r) bitx32(r, 11, 9) 53171815ce7SRobert Mustacchi #define DF_DRAM_BASE_V3_GET_ILV_SOCK(r) bitx32(r, 8, 8) 53271815ce7SRobert Mustacchi #define DF_DRAM_BASE_V3_GET_ILV_DIE(r) bitx32(r, 7, 6) 53371815ce7SRobert Mustacchi #define DF_DRAM_BASE_V3_GET_ILV_CHAN(r) bitx32(r, 5, 2) 53471815ce7SRobert Mustacchi 53571815ce7SRobert Mustacchi #define DF_DRAM_BASE_V3P5_GET_ILV_ADDR(r) bitx32(r, 11, 9) 53671815ce7SRobert Mustacchi #define DF_DRAM_BASE_V3P5_GET_ILV_SOCK(r) bitx32(r, 8, 8) 53771815ce7SRobert Mustacchi #define DF_DRAM_BASE_V3P5_GET_ILV_DIE(r) bitx32(r, 7, 7) 53871815ce7SRobert Mustacchi #define DF_DRAM_BASE_V3P5_GET_ILV_CHAN(r) bitx32(r, 6, 2) 53971815ce7SRobert Mustacchi 54071815ce7SRobert Mustacchi /* 54171815ce7SRobert Mustacchi * Shared definitions for the DF DRAM interleaving address start bits. While the 54271815ce7SRobert Mustacchi * bitfield / register definition is different between DFv2/3/3.5 and DFv4, the 54371815ce7SRobert Mustacchi * actual contents of the base address register and the base are shared. 54471815ce7SRobert Mustacchi */ 54571815ce7SRobert Mustacchi #define DF_DRAM_ILV_ADDR_8 0 54671815ce7SRobert Mustacchi #define DF_DRAM_ILV_ADDR_9 1 54771815ce7SRobert Mustacchi #define DF_DRAM_ILV_ADDR_10 2 54871815ce7SRobert Mustacchi #define DF_DRAM_ILV_ADDR_11 3 54971815ce7SRobert Mustacchi #define DF_DRAM_ILV_ADDR_12 4 55071815ce7SRobert Mustacchi #define DF_DRAM_ILV_ADDR_BASE 8 55171815ce7SRobert Mustacchi 55271815ce7SRobert Mustacchi /*CSTYLED*/ 55371815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 55471815ce7SRobert Mustacchi .drd_func = 0, \ 55571815ce7SRobert Mustacchi .drd_reg = 0x114 + ((r) * 8) } 55671815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V2_GET_LIMIT(r) bitx32(r, 31, 12) 55771815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V2_LIMIT_SHIFT 28 55871815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V2_LIMIT_EXCL (1 << 28) 55971815ce7SRobert Mustacchi /* These are in the base register for v3, v3.5 */ 56071815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V2_GET_ILV_DIE(r) bitx32(r, 11, 10) 56171815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V2_GET_ILV_SOCK(r) bitx32(r, 8, 8) 56271815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V2_GET_DEST_ID(r) bitx32(r, 7, 0) 56371815ce7SRobert Mustacchi 56471815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V3_GET_BUS_BREAK(r) bitx32(r, 10, 10) 56571815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V3_GET_DEST_ID(r) bitx32(r, 9, 0) 56671815ce7SRobert Mustacchi 56771815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V3P5_GET_DEST_ID(r) bitx32(r, 3, 0) 56871815ce7SRobert Mustacchi 56971815ce7SRobert Mustacchi /* 57071815ce7SRobert Mustacchi * DF::DramBaseAddress, DF::DramLimitAddress, DF::DramAddressCtl, 57171815ce7SRobert Mustacchi * DF::DramAddressIntlv -- DFv4 edition. Here all the controls around the 57271815ce7SRobert Mustacchi * target, interleaving, hashing, and more is split out from the base and limit 57371815ce7SRobert Mustacchi * registers and put into dedicated control and interleave registers. 574019df03dSRobert Mustacchi * 575019df03dSRobert Mustacchi * In the 4D2 variant, the base and limit are the same, just at different 576019df03dSRobert Mustacchi * addresses. The control register is subtly different with additional 577019df03dSRobert Mustacchi * interleave options. 57871815ce7SRobert Mustacchi */ 57971815ce7SRobert Mustacchi /*CSTYLED*/ 58071815ce7SRobert Mustacchi #define DF_DRAM_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 58171815ce7SRobert Mustacchi .drd_func = 7, \ 58271815ce7SRobert Mustacchi .drd_reg = 0xe00 + ((x) * 0x10) } 583019df03dSRobert Mustacchi /*CSTYLED*/ 584019df03dSRobert Mustacchi #define DF_DRAM_BASE_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 585019df03dSRobert Mustacchi .drd_func = 7, \ 586019df03dSRobert Mustacchi .drd_reg = 0x200 + ((x) * 0x10) } 58771815ce7SRobert Mustacchi #define DF_DRAM_BASE_V4_GET_ADDR(r) bitx32(r, 27, 0) 58871815ce7SRobert Mustacchi #define DF_DRAM_BASE_V4_BASE_SHIFT 28 58971815ce7SRobert Mustacchi /*CSTYLED*/ 59071815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 59171815ce7SRobert Mustacchi .drd_func = 7, \ 59271815ce7SRobert Mustacchi .drd_reg = 0xe04 + ((x) * 0x10) } 593019df03dSRobert Mustacchi /*CSTYLED*/ 594019df03dSRobert Mustacchi #define DF_DRAM_LIMIT_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 595019df03dSRobert Mustacchi .drd_func = 7, \ 596019df03dSRobert Mustacchi .drd_reg = 0x204 + ((x) * 0x10) } 59771815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V4_GET_ADDR(r) bitx32(r, 27, 0) 59871815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V4_LIMIT_SHIFT 28 59971815ce7SRobert Mustacchi #define DF_DRAM_LIMIT_V4_LIMIT_EXCL (1 << 28) 60071815ce7SRobert Mustacchi 60171815ce7SRobert Mustacchi /*CSTYLED*/ 60271815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 60371815ce7SRobert Mustacchi .drd_func = 7, \ 60471815ce7SRobert Mustacchi .drd_reg = 0xe08 + ((x) * 0x10) } 605019df03dSRobert Mustacchi /*CSTYLED*/ 606019df03dSRobert Mustacchi #define DF_DRAM_CTL_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 607019df03dSRobert Mustacchi .drd_func = 7, \ 608019df03dSRobert Mustacchi .drd_reg = 0208 + ((x) * 0x10) } 60971815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_DEST_ID(r) bitx32(r, 27, 16) 610019df03dSRobert Mustacchi #define DF_DRAM_CTL_V4D2_GET_HASH_1T(r) bitx32(r, 15, 15) 611019df03dSRobert Mustacchi /* 612019df03dSRobert Mustacchi * It seems that this was added in DF V4.1 (no relation to 4D2). It was reserved 613019df03dSRobert Mustacchi * prior to this, so we leave it without a version suffix for now. 614019df03dSRobert Mustacchi */ 615019df03dSRobert Mustacchi #define DF_DRAM_CTL_V4_GET_COL_SWIZ(r) bitx32(r, 11, 11) 61671815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_HASH_1G(r) bitx32(r, 10, 10) 61771815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_HASH_2M(r) bitx32(r, 9, 9) 61871815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_HASH_64K(r) bitx32(r, 8, 8) 619019df03dSRobert Mustacchi #define DF_DRAM_CTL_V4D2_GET_HASH_4K(r) bitx32(r, 7, 7) 62071815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_REMAP_SEL(r) bitx32(r, 7, 5) 621019df03dSRobert Mustacchi #define DF_DRAM_CTL_V4D2_GET_REMAP_SEL(r) bitx32(r, 6, 5) 62271815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_REMAP_EN(r) bitx32(r, 4, 4) 62371815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_SCM(r) bitx32(r, 2, 2) 62471815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_HOLE_EN(r) bitx32(r, 1, 1) 62571815ce7SRobert Mustacchi #define DF_DRAM_CTL_V4_GET_VALID(r) bitx32(r, 0, 0) 62671815ce7SRobert Mustacchi 62771815ce7SRobert Mustacchi /*CSTYLED*/ 62871815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 62971815ce7SRobert Mustacchi .drd_func = 7, \ 63071815ce7SRobert Mustacchi .drd_reg = 0xe0c + ((x) * 0x10) } 631019df03dSRobert Mustacchi /*CSTYLED*/ 632019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 633019df03dSRobert Mustacchi .drd_func = 7, \ 634019df03dSRobert Mustacchi .drd_reg = 0x20c + ((x) * 0x10) } 63571815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_GET_SOCK(r) bitx32(r, 18, 18) 63671815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_GET_DIE(r) bitx32(r, 13, 12) 637019df03dSRobert Mustacchi /* 638019df03dSRobert Mustacchi * We're cheating a bit here. We combine the various different non-overlapping 639019df03dSRobert Mustacchi * values in the 4D2 variants. In particular, most client parts stick to the 640019df03dSRobert Mustacchi * first few values while the rest are sometimes used in the moniker "DF 4.5". 641019df03dSRobert Mustacchi */ 642019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_GET_CHAN(r) bitx32(r, 9, 4) 643019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_1 0x0 644019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_2 0x1 645019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_4 0x3 646019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS1_16S8CH_1K 0xc 647019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS0_24CH_1K 0xe 648019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS4_2CH_1K 0x10 649019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS2_4CH_1K 0x11 650019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS1_8S4CH_1K 0x12 651019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS4_3CH_1K 0x13 652019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS2_6CH_1K 0x14 653019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS1_12CH_1K 0x15 654019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS2_5CH_1K 0x16 655019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS1_10CH_1K 0x17 656019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS4_2CH_2K 0x20 657019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS2_4CH_2K 0x21 658019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS1_8S4CH_2K 0x22 659019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS1_16S8CH_2K 0x23 660019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS4_3CH_2K 0x24 661019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS2_6CH_2K 0x25 662019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS1_12CH_2K 0x26 663019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS0_24CH_2K 0x27 664019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS2_5CH_2K 0x28 665019df03dSRobert Mustacchi #define DF_DRAM_ILV_V4D2_CHAN_NPS2_10CH_2K 0x29 66671815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_GET_CHAN(r) bitx32(r, 8, 4) 66771815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_1 0x0 66871815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_2 0x1 66971815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_4 0x3 67071815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_8 0x5 67171815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_16 0x7 67271815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_32 0x8 67371815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_NPS4_2CH 0x10 67471815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_NPS2_4CH 0x11 67571815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_NPS1_8CH 0x12 67671815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_NPS4_3CH 0x13 67771815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_NPS2_6CH 0x14 67871815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_NPS1_12CH 0x15 67971815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_NPS2_5CH 0x16 68071815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_CHAN_NPS1_10CH 0x17 68171815ce7SRobert Mustacchi #define DF_DRAM_ILV_V4_GET_ADDR(r) bitx32(r, 2, 0) 68271815ce7SRobert Mustacchi 68371815ce7SRobert Mustacchi /* 68471815ce7SRobert Mustacchi * DF::DramOffset -- These exist only for CS entries, e.g. a UMC. There is 68571815ce7SRobert Mustacchi * generally only one of these in Zen 1-3. This register changes in Zen 4 and 68671815ce7SRobert Mustacchi * there are up to 3 instances there. This register corresponds to each DRAM 68771815ce7SRobert Mustacchi * rule that the UMC has starting at the second one. This is because the first 68871815ce7SRobert Mustacchi * DRAM rule in a channel always is defined to start at offset 0, so there is no 68971815ce7SRobert Mustacchi * entry here. 69071815ce7SRobert Mustacchi */ 69171815ce7SRobert Mustacchi /*CSTYLED*/ 69271815ce7SRobert Mustacchi #define DF_DRAM_OFFSET_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 69371815ce7SRobert Mustacchi .drd_func = 0, \ 69471815ce7SRobert Mustacchi .drd_reg = 0x1b4 } 69571815ce7SRobert Mustacchi /*CSTYLED*/ 696019df03dSRobert Mustacchi #define DF_DRAM_OFFSET_V4(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 69771815ce7SRobert Mustacchi .drd_func = 7, \ 6987a7820a2SRobert Mustacchi .drd_reg = 0x140 + ((r) * 4) } 69971815ce7SRobert Mustacchi #define DF_DRAM_OFFSET_V2_GET_OFFSET(r) bitx32(r, 31, 20) 70071815ce7SRobert Mustacchi #define DF_DRAM_OFFSET_V3_GET_OFFSET(r) bitx32(r, 31, 12) 70171815ce7SRobert Mustacchi #define DF_DRAM_OFFSET_V4_GET_OFFSET(r) bitx32(r, 24, 1) 70271815ce7SRobert Mustacchi #define DF_DRAM_OFFSET_SHIFT 28 70371815ce7SRobert Mustacchi #define DF_DRAM_OFFSET_GET_EN(r) bitx32(r, 0, 0) 70471815ce7SRobert Mustacchi 70571815ce7SRobert Mustacchi /* 706019df03dSRobert Mustacchi * DF::VGAEn -- This controls whether or not the historical x86 VGA 707019df03dSRobert Mustacchi * compatibility region is enabled or not. 708019df03dSRobert Mustacchi */ 709019df03dSRobert Mustacchi /*CSTYLED*/ 710019df03dSRobert Mustacchi #define DF_VGA_EN_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 711019df03dSRobert Mustacchi .drd_func = 0, \ 712019df03dSRobert Mustacchi .drd_reg = 0x80 } 713019df03dSRobert Mustacchi /*CSTYLED*/ 714019df03dSRobert Mustacchi #define DF_VGA_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 715019df03dSRobert Mustacchi .drd_func = 0, \ 716019df03dSRobert Mustacchi .drd_reg = 0xc08 } 717019df03dSRobert Mustacchi 718019df03dSRobert Mustacchi #define DF_VGA_EN_GET_FABID(r) bitx32(r, 15, 4) 719019df03dSRobert Mustacchi #define DF_VGA_EN_GET_CPUDIS(r) bitx32(r, 2, 2) 720019df03dSRobert Mustacchi #define DF_VGA_EN_GET_NP(r) bitx32(r, 1, 1) 721019df03dSRobert Mustacchi #define DF_VGA_EN_GET_EN(r) bitx32(r, 0, 0) 722019df03dSRobert Mustacchi 723019df03dSRobert Mustacchi /* 724019df03dSRobert Mustacchi * DF::MmioPciCfgBaseAddr, DF::MmioPciCfgBaseAddrExt, DF::MmioPciCfgLimitAddr, 725019df03dSRobert Mustacchi * DF::MmioPciCfgLimitAddrExt -- These are DFv4 additions that control where PCI 726019df03dSRobert Mustacchi * extended configuration space is and whether or not the DF honors this. This 727019df03dSRobert Mustacchi * must match the values programmed into the CPU. Prior to DFv4, there was not a 728019df03dSRobert Mustacchi * DF setting for this. The encoded values of the base and limit are the same. 729019df03dSRobert Mustacchi */ 730019df03dSRobert Mustacchi /*CSTYLED*/ 731019df03dSRobert Mustacchi #define DF_ECAM_BASE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 732019df03dSRobert Mustacchi .drd_func = 0, \ 733019df03dSRobert Mustacchi .drd_reg = 0xc10 } 734019df03dSRobert Mustacchi /*CSTYLED*/ 735019df03dSRobert Mustacchi #define DF_ECAM_BASE_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 736019df03dSRobert Mustacchi .drd_func = 0, \ 737019df03dSRobert Mustacchi .drd_reg = 0xc14 } 738019df03dSRobert Mustacchi /*CSTYLED*/ 739019df03dSRobert Mustacchi #define DF_ECAM_LIMIT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 740019df03dSRobert Mustacchi .drd_func = 0, \ 741019df03dSRobert Mustacchi .drd_reg = 0xc18 } 742019df03dSRobert Mustacchi /*CSTYLED*/ 743019df03dSRobert Mustacchi #define DF_ECAM_LIMIT_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 744019df03dSRobert Mustacchi .drd_func = 0, \ 745019df03dSRobert Mustacchi .drd_reg = 0xc1c } 746019df03dSRobert Mustacchi #define DF_ECAM_V4_GET_ADDR(r) bitx32(r, 31, 20) 747019df03dSRobert Mustacchi #define DF_ECAM_V4_ADDR_SHIFT 20 748019df03dSRobert Mustacchi #define DF_ECAM_LIMIT_EXCL (1 << DF_ECAM_V4_ADDR_SHIFT) 749019df03dSRobert Mustacchi #define DF_ECAM_BASE_V4_GET_EN(r) bitx32(r, 0, 0) 750019df03dSRobert Mustacchi #define DF_ECAM_EXT_V4_GET_ADDR(r) bitx32(r, 23, 0) 751019df03dSRobert Mustacchi #define DF_ECAM_EXT_V4_ADDR_SHIFT 32 752019df03dSRobert Mustacchi 753019df03dSRobert Mustacchi /* 75471815ce7SRobert Mustacchi * DF::MmioBaseAddress, DF::MmioLimitAddress, DF::MmioAddressControl -- These 75571815ce7SRobert Mustacchi * control the various MMIO rules for a given system. 75671815ce7SRobert Mustacchi */ 75771815ce7SRobert Mustacchi /*CSTYLED*/ 75871815ce7SRobert Mustacchi #define DF_MMIO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 75971815ce7SRobert Mustacchi .drd_func = 0, \ 76071815ce7SRobert Mustacchi .drd_reg = 0x200 + ((x) * 0x10) } 76171815ce7SRobert Mustacchi /*CSTYLED*/ 76271815ce7SRobert Mustacchi #define DF_MMIO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 76371815ce7SRobert Mustacchi .drd_func = 0, \ 76471815ce7SRobert Mustacchi .drd_reg = 0x204 + ((x) * 0x10) } 76571815ce7SRobert Mustacchi /*CSTYLED*/ 766019df03dSRobert Mustacchi #define DF_MMIO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 76771815ce7SRobert Mustacchi .drd_func = 0, \ 76871815ce7SRobert Mustacchi .drd_reg = 0xd80 + ((x) * 0x10) } 76971815ce7SRobert Mustacchi /*CSTYLED*/ 770019df03dSRobert Mustacchi #define DF_MMIO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 77171815ce7SRobert Mustacchi .drd_func = 0, \ 77271815ce7SRobert Mustacchi .drd_reg = 0xd84 + ((x) * 0x10) } 77371815ce7SRobert Mustacchi #define DF_MMIO_SHIFT 16 77471815ce7SRobert Mustacchi #define DF_MMIO_LIMIT_EXCL (1 << DF_MMIO_SHIFT) 77571815ce7SRobert Mustacchi #define DF_MAX_MMIO_RULES 16 776019df03dSRobert Mustacchi #define DF_MAX_MMIO_RULES_TURIN 32 77771815ce7SRobert Mustacchi /*CSTYLED*/ 77871815ce7SRobert Mustacchi #define DF_MMIO_CTL_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 77971815ce7SRobert Mustacchi .drd_func = 0, \ 78071815ce7SRobert Mustacchi .drd_reg = 0x208 + ((x) * 0x10) } 78171815ce7SRobert Mustacchi /*CSTYLED*/ 782019df03dSRobert Mustacchi #define DF_MMIO_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 78371815ce7SRobert Mustacchi .drd_func = 0, \ 78471815ce7SRobert Mustacchi .drd_reg = 0xd88 + ((x) * 0x10) } 78571815ce7SRobert Mustacchi #define DF_MMIO_CTL_V2_GET_NP(r) bitx32(r, 12, 12) 78671815ce7SRobert Mustacchi #define DF_MMIO_CTL_V2_GET_DEST_ID(r) bitx32(r, 11, 4) 78771815ce7SRobert Mustacchi #define DF_MMIO_CTL_V2_SET_NP(r, v) bitset32(r, 12, 12, v) 78871815ce7SRobert Mustacchi #define DF_MMIO_CTL_V2_SET_DEST_ID(r, v) bitset32(r, 11, 4, v) 78971815ce7SRobert Mustacchi 79071815ce7SRobert Mustacchi #define DF_MMIO_CTL_V3_GET_NP(r) bitx32(r, 16, 16) 79171815ce7SRobert Mustacchi #define DF_MMIO_CTL_V3_GET_DEST_ID(r) bitx32(r, 13, 4) 79271815ce7SRobert Mustacchi #define DF_MMIO_CTL_V3P5_GET_DEST_ID(r) bitx32(r, 7, 4) 79371815ce7SRobert Mustacchi #define DF_MMIO_CTL_V3_SET_NP(r, v) bitset32(r, 16, 16, v) 79471815ce7SRobert Mustacchi #define DF_MMIO_CTL_V3_SET_DEST_ID(r, v) bitset32(r, 13, 4, v) 79571815ce7SRobert Mustacchi #define DF_MMIO_CTL_V3P5_SET_DEST_ID(r, v) bitset32(r, 7, 4, v) 79671815ce7SRobert Mustacchi 79771815ce7SRobert Mustacchi #define DF_MMIO_CTL_V4_GET_DEST_ID(r) bitx32(r, 27, 16) 79871815ce7SRobert Mustacchi #define DF_MMIO_CTL_V4_GET_NP(r) bitx32(r, 3, 3) 79971815ce7SRobert Mustacchi #define DF_MMIO_CTL_V4_SET_DEST_ID(r, v) bitset32(r, 27, 16, v) 80071815ce7SRobert Mustacchi #define DF_MMIO_CTL_V4_SET_NP(r, v) bitset32(r, 3, 3, v) 80171815ce7SRobert Mustacchi 80271815ce7SRobert Mustacchi #define DF_MMIO_CTL_GET_CPU_DIS(r) bitx32(r, 2, 2) 80371815ce7SRobert Mustacchi #define DF_MMIO_CTL_GET_WE(r) bitx32(r, 1, 1) 80471815ce7SRobert Mustacchi #define DF_MMIO_CTL_GET_RE(r) bitx32(r, 0, 0) 80571815ce7SRobert Mustacchi #define DF_MMIO_CTL_SET_CPU_DIS(r, v) bitset32(r, 2, 2, v) 80671815ce7SRobert Mustacchi #define DF_MMIO_CTL_SET_WE(r, v) bitset32(r, 1, 1, v) 80771815ce7SRobert Mustacchi #define DF_MMIO_CTL_SET_RE(r, v) bitset32(r, 0, 0, v) 80871815ce7SRobert Mustacchi 80971815ce7SRobert Mustacchi /* 81071815ce7SRobert Mustacchi * DF::MmioExtAddress -- New in DFv4, this allows extending the number of bits 81171815ce7SRobert Mustacchi * used for MMIO. 81271815ce7SRobert Mustacchi */ 81371815ce7SRobert Mustacchi /*CSTYLED*/ 814019df03dSRobert Mustacchi #define DF_MMIO_EXT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 81571815ce7SRobert Mustacchi .drd_func = 0, \ 81671815ce7SRobert Mustacchi .drd_reg = 0xd8c + ((x) * 0x10) } 81771815ce7SRobert Mustacchi #define DF_MMIO_EXT_V4_GET_LIMIT(r) bitx32(r, 23, 16) 81871815ce7SRobert Mustacchi #define DF_MMIO_EXT_V4_GET_BASE(r) bitx32(r, 7, 0) 81971815ce7SRobert Mustacchi #define DF_MMIO_EXT_V4_SET_LIMIT(r) bitset32(r, 23, 16) 82071815ce7SRobert Mustacchi #define DF_MMIO_EXT_V4_SET_BASE(r) bitset32(r, 7, 0) 821*9e3944acSLuqman Aden #define DF_MMIO_EXT_SHIFT 48 82271815ce7SRobert Mustacchi 82371815ce7SRobert Mustacchi /* 82471815ce7SRobert Mustacchi * DF::DfGlobalCtrl -- This register we generally only care about in the 82571815ce7SRobert Mustacchi * DFv3/3.5 timeframe when it has the actual hash controls, hence its current 82671815ce7SRobert Mustacchi * definition. It technically exists in DFv2/v4, but is not relevant. 82771815ce7SRobert Mustacchi */ 82871815ce7SRobert Mustacchi /*CSTYLED*/ 829dd23d762SRobert Mustacchi #define DF_GLOB_CTL_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \ 83071815ce7SRobert Mustacchi .drd_func = 0, \ 83171815ce7SRobert Mustacchi .drd_reg = 0x3F8 } 83271815ce7SRobert Mustacchi #define DF_GLOB_CTL_V3_GET_HASH_1G(r) bitx32(r, 22, 22) 83371815ce7SRobert Mustacchi #define DF_GLOB_CTL_V3_GET_HASH_2M(r) bitx32(r, 21, 21) 83471815ce7SRobert Mustacchi #define DF_GLOB_CTL_V3_GET_HASH_64K(r) bitx32(r, 20, 20) 83571815ce7SRobert Mustacchi 83671815ce7SRobert Mustacchi /* 83771815ce7SRobert Mustacchi * DF::SystemCfg -- This register describes the basic information about the data 83871815ce7SRobert Mustacchi * fabric that we're talking to. Don't worry, this is different in every 83971815ce7SRobert Mustacchi * generation, even when the address is the same. Somehow despite all these 84071815ce7SRobert Mustacchi * differences the actual things like defined types are somehow the same. 84171815ce7SRobert Mustacchi */ 84271815ce7SRobert Mustacchi typedef enum { 84371815ce7SRobert Mustacchi DF_DIE_TYPE_CPU = 0, 84471815ce7SRobert Mustacchi DF_DIE_TYPE_APU, 84571815ce7SRobert Mustacchi DF_DIE_TYPE_dGPU 84671815ce7SRobert Mustacchi } df_die_type_t; 84771815ce7SRobert Mustacchi 84871815ce7SRobert Mustacchi /*CSTYLED*/ 84971815ce7SRobert Mustacchi #define DF_SYSCFG_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \ 85071815ce7SRobert Mustacchi .drd_func = 1, \ 85171815ce7SRobert Mustacchi .drd_reg = 0x200 } 85271815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_SOCK_ID(r) bitx32(r, 27, 27) 85371815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_DIE_ID(r) bitx32(r, 25, 24) 85471815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_MY_TYPE(r) bitx32(r, 22, 21) 85571815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_LOCAL_IS_ME(r) bitx32(r, 19, 16) 85671815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_LOCAL_TYPE3(r) bitx32(r, 13, 12) 85771815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_LOCAL_TYPE2(r) bitx32(r, 11, 10) 85871815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_LOCAL_TYPE1(r) bitx32(r, 9, 8) 85971815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_LOCAL_TYPE0(r) bitx32(r, 7, 6) 86071815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_OTHER_SOCK(r) bitx32(r, 5, 5) 86171815ce7SRobert Mustacchi #define DF_SYSCFG_V2_GET_DIE_PRESENT(r) bitx32(r, 4, 0) 86271815ce7SRobert Mustacchi #define DF_SYSCFG_V2_DIE_PRESENT(x) bitx32(r, 3, 0) 86371815ce7SRobert Mustacchi 86471815ce7SRobert Mustacchi /*CSTYLED*/ 86571815ce7SRobert Mustacchi #define DF_SYSCFG_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 86671815ce7SRobert Mustacchi .drd_func = 1, \ 86771815ce7SRobert Mustacchi .drd_reg = 0x200 } 86871815ce7SRobert Mustacchi #define DF_SYSCFG_V3_GET_NODE_ID(r) bitx32(r, 30, 28) 86971815ce7SRobert Mustacchi #define DF_SYSCFG_V3_GET_OTHER_SOCK(r) bitx32(r, 27, 27) 87071815ce7SRobert Mustacchi #define DF_SYSCFG_V3_GET_OTHER_TYPE(r) bitx32(r, 26, 25) 87171815ce7SRobert Mustacchi #define DF_SYSCFG_V3_GET_MY_TYPE(r) bitx32(r, 24, 23) 87271815ce7SRobert Mustacchi #define DF_SYSCFG_V3_GET_DIE_TYPE(r) bitx32(r, 18, 11) 87371815ce7SRobert Mustacchi #define DF_SYSCFG_V3_GET_DIE_PRESENT(r) bitx32(r, 7, 0) 87471815ce7SRobert Mustacchi 87571815ce7SRobert Mustacchi /*CSTYLED*/ 87671815ce7SRobert Mustacchi #define DF_SYSCFG_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \ 87771815ce7SRobert Mustacchi .drd_func = 1, \ 87871815ce7SRobert Mustacchi .drd_reg = 0x140 } 87971815ce7SRobert Mustacchi #define DF_SYSCFG_V3P5_GET_NODE_ID(r) bitx32(r, 19, 16) 88071815ce7SRobert Mustacchi #define DF_SYSCFG_V3P5_GET_OTHER_SOCK(r) bitx32(r, 8, 8) 88171815ce7SRobert Mustacchi #define DF_SYSCFG_V3P5_GET_NODE_MAP(r) bitx32(r, 4, 4) 88271815ce7SRobert Mustacchi #define DF_SYSCFG_V3P5_GET_OTHER_TYPE(r) bitx32(r, 3, 2) 88371815ce7SRobert Mustacchi #define DF_SYSCFG_V3P5_GET_MY_TYPE(r) bitx32(r, 1, 0) 88471815ce7SRobert Mustacchi 88571815ce7SRobert Mustacchi /*CSTYLED*/ 886019df03dSRobert Mustacchi #define DF_SYSCFG_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 88771815ce7SRobert Mustacchi .drd_func = 4, \ 88871815ce7SRobert Mustacchi .drd_reg = 0x180 } 88971815ce7SRobert Mustacchi #define DF_SYSCFG_V4_GET_NODE_ID(r) bitx32(r, 27, 16) 89071815ce7SRobert Mustacchi #define DF_SYSCFG_V4_GET_OTHER_SOCK(r) bitx32(r, 8, 8) 89171815ce7SRobert Mustacchi #define DF_SYSCFG_V4_GET_NODE_MAP(r) bitx32(r, 4, 4) 89271815ce7SRobert Mustacchi #define DF_SYSCFG_V4_GET_OTHER_TYPE(r) bitx32(r, 3, 2) 89371815ce7SRobert Mustacchi #define DF_SYSCFG_V4_GET_MY_TYPE(r) bitx32(r, 1, 0) 89471815ce7SRobert Mustacchi 89571815ce7SRobert Mustacchi /* 89671815ce7SRobert Mustacchi * DF::SystemComponentCnt -- Has a count of how many things are here. However, 89771815ce7SRobert Mustacchi * this does not seem defined for DFv3.5 89871815ce7SRobert Mustacchi */ 89971815ce7SRobert Mustacchi /*CSTYLED*/ 900019df03dSRobert Mustacchi #define DF_COMPCNT_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 90171815ce7SRobert Mustacchi .drd_func = 1, \ 90271815ce7SRobert Mustacchi .drd_reg = 0x204 } 90371815ce7SRobert Mustacchi #define DF_COMPCNT_V2_GET_IOMS(r) bitx32(r, 23, 16) 90471815ce7SRobert Mustacchi #define DF_COMPCNT_V2_GET_GCM(r) bitx32(r, 15, 8) 90571815ce7SRobert Mustacchi #define DF_COMPCNT_V2_GET_PIE(r) bitx32(r, 7, 0) 90671815ce7SRobert Mustacchi 90771815ce7SRobert Mustacchi /*CSTYLED*/ 908019df03dSRobert Mustacchi #define DF_COMPCNT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 90971815ce7SRobert Mustacchi .drd_func = 4, \ 91071815ce7SRobert Mustacchi .drd_reg = 0x184 } 91171815ce7SRobert Mustacchi #define DF_COMPCNT_V4_GET_IOS(r) bitx32(r, 31, 26) 91271815ce7SRobert Mustacchi #define DF_COMPCNT_V4_GET_GCM(r) bitx32(r, 25, 16) 91371815ce7SRobert Mustacchi #define DF_COMPCNT_V4_GET_IOM(r) bitx32(r, 15, 8) 91471815ce7SRobert Mustacchi #define DF_COMPCNT_V4_GET_PIE(r) bitx32(r, 7, 0) 91571815ce7SRobert Mustacchi 91671815ce7SRobert Mustacchi /* 91771815ce7SRobert Mustacchi * This next section contains a bunch of register definitions for how to take 91871815ce7SRobert Mustacchi * apart ID masks. The register names and sets have changed across every DF 91971815ce7SRobert Mustacchi * revision. This will be done in chunks that define all DFv2, then v3, etc. 92071815ce7SRobert Mustacchi */ 92171815ce7SRobert Mustacchi 92271815ce7SRobert Mustacchi /* 92371815ce7SRobert Mustacchi * DF::SystemFabricIdMask -- DFv2 style breakdowns of IDs. Note, unlike others 92471815ce7SRobert Mustacchi * the socket and die shifts are not relative to a node mask, but are global. 92571815ce7SRobert Mustacchi */ 92671815ce7SRobert Mustacchi /*CSTYLED*/ 92771815ce7SRobert Mustacchi #define DF_FIDMASK_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \ 92871815ce7SRobert Mustacchi .drd_func = 1, \ 92971815ce7SRobert Mustacchi .drd_reg = 0x208 } 93071815ce7SRobert Mustacchi #define DF_FIDMASK_V2_GET_SOCK_SHIFT(r) bitx32(r, 31, 28) 93171815ce7SRobert Mustacchi #define DF_FIDMASK_V2_GET_DIE_SHIFT(r) bitx32(r, 27, 24) 93271815ce7SRobert Mustacchi #define DF_FIDMASK_V2_GET_SOCK_MASK(r) bitx32(r, 23, 16) 93371815ce7SRobert Mustacchi #define DF_FIDMASK_V2_GET_DIE_MASK(r) bitx32(r, 15, 8) 93471815ce7SRobert Mustacchi 93571815ce7SRobert Mustacchi /* 93671815ce7SRobert Mustacchi * DF::SystemFabricIdMask0, DF::SystemFabricIdMask1 -- The DFv3 variant of 93771815ce7SRobert Mustacchi * breaking down an ID into bits and shifts. Unlike in DFv2, the socket and die 93871815ce7SRobert Mustacchi * are relative to a node ID. For more, see amdzen_determine_fabric_decomp() in 93971815ce7SRobert Mustacchi * uts/intel/io/amdzen/amdzen.c. 94071815ce7SRobert Mustacchi */ 94171815ce7SRobert Mustacchi /*CSTYLED*/ 94271815ce7SRobert Mustacchi #define DF_FIDMASK0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 94371815ce7SRobert Mustacchi .drd_func = 1, \ 94471815ce7SRobert Mustacchi .drd_reg = 0x208 } 94571815ce7SRobert Mustacchi #define DF_FIDMASK0_V3_GET_NODE_MASK(r) bitx32(r, 25, 16) 94671815ce7SRobert Mustacchi #define DF_FIDMASK0_V3_GET_COMP_MASK(r) bitx32(r, 9, 0) 94771815ce7SRobert Mustacchi /*CSTYLED*/ 94871815ce7SRobert Mustacchi #define DF_FIDMASK1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 94971815ce7SRobert Mustacchi .drd_func = 1, \ 95071815ce7SRobert Mustacchi .drd_reg = 0x20c } 95171815ce7SRobert Mustacchi #define DF_FIDMASK1_V3_GET_SOCK_MASK(r) bitx32(r, 26, 24) 95271815ce7SRobert Mustacchi #define DF_FIDMASK1_V3_GET_DIE_MASK(r) bitx32(r, 18, 16) 95371815ce7SRobert Mustacchi #define DF_FIDMASK1_V3_GET_SOCK_SHIFT(r) bitx32(r, 9, 8) 95471815ce7SRobert Mustacchi #define DF_FIDMASK1_V3_GET_NODE_SHIFT(r) bitx32(r, 3, 0) 95571815ce7SRobert Mustacchi 95671815ce7SRobert Mustacchi /* 95771815ce7SRobert Mustacchi * DF::SystemFabricIdMask0, DF::SystemFabricIdMask1, DF::SystemFabricIdMask2 -- 95871815ce7SRobert Mustacchi * DFv3.5 and DFv4 have the same format here, but in different registers. 95971815ce7SRobert Mustacchi */ 96071815ce7SRobert Mustacchi /*CSTYLED*/ 96171815ce7SRobert Mustacchi #define DF_FIDMASK0_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \ 96271815ce7SRobert Mustacchi .drd_func = 1, \ 96371815ce7SRobert Mustacchi .drd_reg = 0x150 } 96471815ce7SRobert Mustacchi /*CSTYLED*/ 965019df03dSRobert Mustacchi #define DF_FIDMASK0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 96671815ce7SRobert Mustacchi .drd_func = 4, \ 96771815ce7SRobert Mustacchi .drd_reg = 0x1b0 } 96871815ce7SRobert Mustacchi #define DF_FIDMASK0_V3P5_GET_NODE_MASK(r) bitx32(r, 31, 16) 96971815ce7SRobert Mustacchi #define DF_FIDMASK0_V3P5_GET_COMP_MASK(r) bitx32(r, 15, 0) 97071815ce7SRobert Mustacchi /*CSTYLED*/ 97171815ce7SRobert Mustacchi #define DF_FIDMASK1_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \ 97271815ce7SRobert Mustacchi .drd_func = 1, \ 97371815ce7SRobert Mustacchi .drd_reg = 0x154 } 97471815ce7SRobert Mustacchi /*CSTYLED*/ 975019df03dSRobert Mustacchi #define DF_FIDMASK1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 97671815ce7SRobert Mustacchi .drd_func = 4, \ 97771815ce7SRobert Mustacchi .drd_reg = 0x1b4 } 97871815ce7SRobert Mustacchi #define DF_FIDMASK1_V3P5_GET_SOCK_SHIFT(r) bitx32(r, 11, 8) 97971815ce7SRobert Mustacchi #define DF_FIDMASK1_V3P5_GET_NODE_SHIFT(r) bitx32(r, 3, 0) 98071815ce7SRobert Mustacchi /*CSTYLED*/ 98171815ce7SRobert Mustacchi #define DF_FIDMASK2_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \ 98271815ce7SRobert Mustacchi .drd_func = 1, \ 98371815ce7SRobert Mustacchi .drd_reg = 0x158 } 98471815ce7SRobert Mustacchi /*CSTYLED*/ 985019df03dSRobert Mustacchi #define DF_FIDMASK2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 98671815ce7SRobert Mustacchi .drd_func = 4, \ 98771815ce7SRobert Mustacchi .drd_reg = 0x1b8 } 98871815ce7SRobert Mustacchi #define DF_FIDMASK2_V3P5_GET_SOCK_MASK(r) bitx32(r, 31, 16) 98971815ce7SRobert Mustacchi #define DF_FIDMASK2_V3P5_GET_DIE_MASK(r) bitx32(r, 15, 0) 99071815ce7SRobert Mustacchi 99171815ce7SRobert Mustacchi /* 99271815ce7SRobert Mustacchi * DF::DieFabricIdMask -- This is a Zeppelin, DFv2 special. There are a couple 99371815ce7SRobert Mustacchi * instances of this for different types of devices; however, this is where the 99471815ce7SRobert Mustacchi * component mask is actually stored. This is replicated for a CPU, APU, and 99571815ce7SRobert Mustacchi * dGPU, each with slightly different values. We need to look at DF_SYSCFG_V2 to 99671815ce7SRobert Mustacchi * determine which type of die we have and use the appropriate one when looking 99771815ce7SRobert Mustacchi * at this. This makes the Zen 1 CPUs and APUs have explicitly different set up 99871815ce7SRobert Mustacchi * here. Look, it got better in DFv3. 99971815ce7SRobert Mustacchi */ 100071815ce7SRobert Mustacchi /*CSTYLED*/ 100171815ce7SRobert Mustacchi #define DF_DIEMASK_CPU_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \ 100271815ce7SRobert Mustacchi .drd_func = 1, \ 100371815ce7SRobert Mustacchi .drd_reg = 0x22c } 100471815ce7SRobert Mustacchi /*CSTYLED*/ 100571815ce7SRobert Mustacchi #define DF_DIEMASK_APU_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \ 100671815ce7SRobert Mustacchi .drd_func = 1, \ 100771815ce7SRobert Mustacchi .drd_reg = 0x24c } 100871815ce7SRobert Mustacchi #define DF_DIEMASK_V2_GET_SOCK_SHIFT(r) bitx32(r, 31, 28) 100971815ce7SRobert Mustacchi #define DF_DIEMASK_V2_GET_DIE_SHIFT(r) bitx32(r, 27, 24) 101071815ce7SRobert Mustacchi #define DF_DIEMASK_V2_GET_SOCK_MASK(r) bitx32(r, 23, 16) 101171815ce7SRobert Mustacchi #define DF_DIEMASK_V2_GET_DIE_MASK(r) bitx32(r, 15, 8) 101271815ce7SRobert Mustacchi #define DF_DIEMASK_V2_GET_COMP_MASK(r) bitx32(r, 7, 0) 101371815ce7SRobert Mustacchi 1014dd23d762SRobert Mustacchi /* 1015dd23d762SRobert Mustacchi * DF::CCDEnable -- This register is present for CCMs and ACMs. Despite its 1016dd23d762SRobert Mustacchi * name, the interpretation is not quite straightforward. That is, it only 1017dd23d762SRobert Mustacchi * indirectly tells us about whether or not there are two CCDs or not. A CCM 1018dd23d762SRobert Mustacchi * port can be in wide mode where its two SDPs (Scalable Data Ports) are in fact 1019dd23d762SRobert Mustacchi * instead connected to a single CCD. If wide mode is enabled in DF::CCMConfig4, 1020dd23d762SRobert Mustacchi * then a value of 0x3 just indicates that both SDP ports are connected to a 1021dd23d762SRobert Mustacchi * single CCD. 1022dd23d762SRobert Mustacchi * 1023dd23d762SRobert Mustacchi * The CCX related fields are only valid when the dense mode is enabled in the 1024019df03dSRobert Mustacchi * global DF controls. If a CPU doesn't support that, then that field is 1025019df03dSRobert Mustacchi * reserved. We don't generally recommend this as a way of determining if 1026019df03dSRobert Mustacchi * multiple CCX units are present on the CCD because it is tied to DFv4. 1027dd23d762SRobert Mustacchi */ 1028dd23d762SRobert Mustacchi #define DF_MAX_CCDS_PER_CCM 2 1029dd23d762SRobert Mustacchi /*CSTYLED*/ 1030019df03dSRobert Mustacchi #define DF_CCD_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1031dd23d762SRobert Mustacchi .drd_func = 1, \ 1032dd23d762SRobert Mustacchi .drd_reg = 0x104 } 1033dd23d762SRobert Mustacchi #define DF_CCD_EN_V4_GET_CCX_EN(r) bitx32(r, 17, 16) 1034dd23d762SRobert Mustacchi #define DF_CCD_EN_V4_GET_CCD_EN(r) bitx32(r, 1, 0) 1035dd23d762SRobert Mustacchi 103671815ce7SRobert Mustacchi 103771815ce7SRobert Mustacchi /* 103871815ce7SRobert Mustacchi * DF::PhysicalCoreEnable0, etc. -- These registers can be used to tell us which 1039dd23d762SRobert Mustacchi * cores are actually enabled. This appears to have been introduced in DFv3. 1040019df03dSRobert Mustacchi * DFv4 expanded this from two registers to several more. The number that are 1041019df03dSRobert Mustacchi * valid vary based upon the CPU family. 104271815ce7SRobert Mustacchi */ 104371815ce7SRobert Mustacchi /*CSTYLED*/ 1044dd23d762SRobert Mustacchi #define DF_PHYS_CORE_EN0_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \ 104571815ce7SRobert Mustacchi .drd_func = 1, \ 104671815ce7SRobert Mustacchi .drd_reg = 0x300 } 104771815ce7SRobert Mustacchi /*CSTYLED*/ 1048dd23d762SRobert Mustacchi #define DF_PHYS_CORE_EN1_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \ 104971815ce7SRobert Mustacchi .drd_func = 1, \ 105071815ce7SRobert Mustacchi .drd_reg = 0x304 } 105171815ce7SRobert Mustacchi /*CSTYLED*/ 1052019df03dSRobert Mustacchi #define DF_PHYS_CORE_EN0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 105371815ce7SRobert Mustacchi .drd_func = 1, \ 105471815ce7SRobert Mustacchi .drd_reg = 0x140 } 105571815ce7SRobert Mustacchi /*CSTYLED*/ 1056019df03dSRobert Mustacchi #define DF_PHYS_CORE_EN1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 105771815ce7SRobert Mustacchi .drd_func = 1, \ 105871815ce7SRobert Mustacchi .drd_reg = 0x144 } 105971815ce7SRobert Mustacchi /*CSTYLED*/ 1060019df03dSRobert Mustacchi #define DF_PHYS_CORE_EN2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 106171815ce7SRobert Mustacchi .drd_func = 1, \ 106271815ce7SRobert Mustacchi .drd_reg = 0x148 } 1063dd23d762SRobert Mustacchi /*CSTYLED*/ 1064019df03dSRobert Mustacchi #define DF_PHYS_CORE_EN3_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1065dd23d762SRobert Mustacchi .drd_func = 1, \ 1066dd23d762SRobert Mustacchi .drd_reg = 0x14c } 1067019df03dSRobert Mustacchi /*CSTYLED*/ 1068019df03dSRobert Mustacchi #define DF_PHYS_CORE_EN4_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1069019df03dSRobert Mustacchi .drd_func = 1, \ 1070019df03dSRobert Mustacchi .drd_reg = 0x150 } 1071019df03dSRobert Mustacchi /*CSTYLED*/ 1072019df03dSRobert Mustacchi #define DF_PHYS_CORE_EN5_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1073019df03dSRobert Mustacchi .drd_func = 1, \ 1074019df03dSRobert Mustacchi .drd_reg = 0x154 } 107571815ce7SRobert Mustacchi 107671815ce7SRobert Mustacchi /* 107771815ce7SRobert Mustacchi * DF::Np2ChannelConfig -- This is used in Milan to contain information about 107871815ce7SRobert Mustacchi * how non-power of 2 based channel configuration works. Note, we only know that 107971815ce7SRobert Mustacchi * this exists in Milan (and its ThreadRipper equivalent). We don't believe it 108071815ce7SRobert Mustacchi * is in other DFv3 products like Rome, Matisse, Vermeer, or the APUs. 108171815ce7SRobert Mustacchi */ 108271815ce7SRobert Mustacchi /*CSTYLED*/ 108371815ce7SRobert Mustacchi #define DF_NP2_CONFIG_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 108471815ce7SRobert Mustacchi .drd_func = 2, \ 108571815ce7SRobert Mustacchi .drd_reg = 0x90 } 108671815ce7SRobert Mustacchi #define DF_NP2_CONFIG_V3_GET_SPACE1(r) bitx32(r, 13, 8) 108771815ce7SRobert Mustacchi #define DF_NP2_CONFIG_V3_GET_SPACE0(r) bitx32(r, 5, 0) 108871815ce7SRobert Mustacchi 1089dd23d762SRobert Mustacchi /* 1090dd23d762SRobert Mustacchi * DF::CCMConfig4 -- This is one of several CCM configuration related registers. 1091dd23d762SRobert Mustacchi * This varies in each DF revision. That is, while we've found it does exist in 1092dd23d762SRobert Mustacchi * DFv3, it is at a different address and the bits have rather different 1093dd23d762SRobert Mustacchi * meanings. A subset of the bits are defined below based upon our needs. 1094dd23d762SRobert Mustacchi */ 1095dd23d762SRobert Mustacchi /*CSTYLED*/ 1096019df03dSRobert Mustacchi #define DF_CCMCFG4_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1097dd23d762SRobert Mustacchi .drd_func = 3, \ 1098dd23d762SRobert Mustacchi .drd_reg = 0x510 } 1099dd23d762SRobert Mustacchi #define DF_CCMCFG4_V4_GET_WIDE_EN(r) bitx32(r, 26, 26) 110071815ce7SRobert Mustacchi 110171815ce7SRobert Mustacchi /* 110271815ce7SRobert Mustacchi * DF::FabricIndirectConfigAccessAddress, DF::FabricIndirectConfigAccessDataLo, 110371815ce7SRobert Mustacchi * DF::FabricIndirectConfigAccessDataHi -- These registers are used to define 110471815ce7SRobert Mustacchi * Indirect Access, commonly known as FICAA and FICAD for the system. While 110571815ce7SRobert Mustacchi * there are multiple copies of the indirect access registers in device 4, we're 110671815ce7SRobert Mustacchi * only allowed access to one set of those (which are the ones present here). 110771815ce7SRobert Mustacchi * Specifically the OS is given access to set 3. 110871815ce7SRobert Mustacchi */ 110971815ce7SRobert Mustacchi /*CSTYLED*/ 111071815ce7SRobert Mustacchi #define DF_FICAA_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 111171815ce7SRobert Mustacchi .drd_func = 4, \ 111271815ce7SRobert Mustacchi .drd_reg = 0x5c } 111371815ce7SRobert Mustacchi /*CSTYLED*/ 1114019df03dSRobert Mustacchi #define DF_FICAA_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 111571815ce7SRobert Mustacchi .drd_func = 4, \ 111671815ce7SRobert Mustacchi .drd_reg = 0x8c } 111771815ce7SRobert Mustacchi #define DF_FICAA_V2_SET_INST(r, v) bitset32(r, 23, 16, v) 111871815ce7SRobert Mustacchi #define DF_FICAA_V2_SET_64B(r, v) bitset32(r, 14, 14, v) 111971815ce7SRobert Mustacchi #define DF_FICAA_V2_SET_FUNC(r, v) bitset32(r, 13, 11, v) 112071815ce7SRobert Mustacchi #define DF_FICAA_V2_SET_REG(r, v) bitset32(r, 10, 2, v) 112171815ce7SRobert Mustacchi #define DF_FICAA_V2_SET_TARG_INST(r, v) bitset32(r, 0, 0, v) 112271815ce7SRobert Mustacchi 112371815ce7SRobert Mustacchi #define DF_FICAA_V4_SET_REG(r, v) bitset32(r, 10, 1, v) 112471815ce7SRobert Mustacchi 112571815ce7SRobert Mustacchi /*CSTYLED*/ 112671815ce7SRobert Mustacchi #define DF_FICAD_LO_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 112771815ce7SRobert Mustacchi .drd_func = 4, \ 112871815ce7SRobert Mustacchi .drd_reg = 0x98} 112971815ce7SRobert Mustacchi /*CSTYLED*/ 113071815ce7SRobert Mustacchi #define DF_FICAD_HI_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 113171815ce7SRobert Mustacchi .drd_func = 4, \ 113271815ce7SRobert Mustacchi .drd_reg = 0x9c} 113371815ce7SRobert Mustacchi /*CSTYLED*/ 1134019df03dSRobert Mustacchi #define DF_FICAD_LO_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 113571815ce7SRobert Mustacchi .drd_func = 4, \ 113671815ce7SRobert Mustacchi .drd_reg = 0xb8} 113771815ce7SRobert Mustacchi /*CSTYLED*/ 1138019df03dSRobert Mustacchi #define DF_FICAD_HI_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 113971815ce7SRobert Mustacchi .drd_func = 4, \ 114071815ce7SRobert Mustacchi .drd_reg = 0xbc} 114171815ce7SRobert Mustacchi 114271815ce7SRobert Mustacchi #ifdef __cplusplus 114371815ce7SRobert Mustacchi } 114471815ce7SRobert Mustacchi #endif 114571815ce7SRobert Mustacchi 114671815ce7SRobert Mustacchi #endif /* _SYS_AMDZEN_DF_H */ 1147