1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 * 26 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 27 */ 28 29 /* 30 * Portions Copyright 2009 Advanced Micro Devices, Inc. 31 */ 32 33 /* 34 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 35 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 36 * Copyright 2019 Joyent, Inc. 37 * Copyright 2023 Oxide Computer Company 38 */ 39 40 /* 41 * Support functions that interpret CPUID and similar information. 42 * These should not be used from anywhere other than cpuid.c and 43 * cmi_hw.c - as such we will not list them in any header file 44 * such as x86_archext.h. 45 * 46 * In cpuid.c we process CPUID information for each cpu_t instance 47 * we're presented with, and stash this raw information and material 48 * derived from it in per-cpu_t structures. 49 * 50 * If we are virtualized then the CPUID information derived from CPUID 51 * instructions executed in the guest is based on whatever the hypervisor 52 * wanted to make things look like, and the cpu_t are not necessarily in 1:1 53 * or fixed correspondence with real processor execution resources. In cmi_hw.c 54 * we are interested in the native properties of a processor - for fault 55 * management (and potentially other, such as power management) purposes; 56 * it will tunnel through to real hardware information, and use the 57 * functionality provided in this file to process it. 58 */ 59 60 #include <sys/types.h> 61 #include <sys/systm.h> 62 #include <sys/bitmap.h> 63 #include <sys/x86_archext.h> 64 #include <sys/pci_cfgspace.h> 65 #include <sys/sysmacros.h> 66 #ifdef __xpv 67 #include <sys/hypervisor.h> 68 #endif 69 70 /* 71 * AMD socket types. 72 * First index defines a processor family; see notes inline. The second index 73 * selects the socket type by either (model & 0x3) for family 0fh or the CPUID 74 * pkg bits (Fn8000_0001_EBX[31:28]) for later families. 75 */ 76 static uint32_t amd_skts[][8] = { 77 /* 78 * Family 0xf revisions B through E 79 */ 80 #define A_SKTS_0 0 81 { 82 X86_SOCKET_754, /* 0b000 */ 83 X86_SOCKET_940, /* 0b001 */ 84 X86_SOCKET_754, /* 0b010 */ 85 X86_SOCKET_939, /* 0b011 */ 86 X86_SOCKET_UNKNOWN, /* 0b100 */ 87 X86_SOCKET_UNKNOWN, /* 0b101 */ 88 X86_SOCKET_UNKNOWN, /* 0b110 */ 89 X86_SOCKET_UNKNOWN /* 0b111 */ 90 }, 91 /* 92 * Family 0xf revisions F and G 93 */ 94 #define A_SKTS_1 1 95 { 96 X86_SOCKET_S1g1, /* 0b000 */ 97 X86_SOCKET_F1207, /* 0b001 */ 98 X86_SOCKET_UNKNOWN, /* 0b010 */ 99 X86_SOCKET_AM2, /* 0b011 */ 100 X86_SOCKET_UNKNOWN, /* 0b100 */ 101 X86_SOCKET_UNKNOWN, /* 0b101 */ 102 X86_SOCKET_UNKNOWN, /* 0b110 */ 103 X86_SOCKET_UNKNOWN /* 0b111 */ 104 }, 105 /* 106 * Family 0x10 107 */ 108 #define A_SKTS_2 2 109 { 110 X86_SOCKET_F1207, /* 0b000 */ 111 X86_SOCKET_AM2R2, /* 0b001 */ 112 X86_SOCKET_S1g3, /* 0b010 */ 113 X86_SOCKET_G34, /* 0b011 */ 114 X86_SOCKET_ASB2, /* 0b100 */ 115 X86_SOCKET_C32, /* 0b101 */ 116 X86_SOCKET_UNKNOWN, /* 0b110 */ 117 X86_SOCKET_UNKNOWN /* 0b111 */ 118 }, 119 120 /* 121 * Family 0x11 122 */ 123 #define A_SKTS_3 3 124 { 125 X86_SOCKET_UNKNOWN, /* 0b000 */ 126 X86_SOCKET_UNKNOWN, /* 0b001 */ 127 X86_SOCKET_S1g2, /* 0b010 */ 128 X86_SOCKET_UNKNOWN, /* 0b011 */ 129 X86_SOCKET_UNKNOWN, /* 0b100 */ 130 X86_SOCKET_UNKNOWN, /* 0b101 */ 131 X86_SOCKET_UNKNOWN, /* 0b110 */ 132 X86_SOCKET_UNKNOWN /* 0b111 */ 133 }, 134 135 /* 136 * Family 0x12 137 */ 138 #define A_SKTS_4 4 139 { 140 X86_SOCKET_UNKNOWN, /* 0b000 */ 141 X86_SOCKET_FS1, /* 0b001 */ 142 X86_SOCKET_FM1, /* 0b010 */ 143 X86_SOCKET_UNKNOWN, /* 0b011 */ 144 X86_SOCKET_UNKNOWN, /* 0b100 */ 145 X86_SOCKET_UNKNOWN, /* 0b101 */ 146 X86_SOCKET_UNKNOWN, /* 0b110 */ 147 X86_SOCKET_UNKNOWN /* 0b111 */ 148 }, 149 150 /* 151 * Family 0x14 152 */ 153 #define A_SKTS_5 5 154 { 155 X86_SOCKET_FT1, /* 0b000 */ 156 X86_SOCKET_UNKNOWN, /* 0b001 */ 157 X86_SOCKET_UNKNOWN, /* 0b010 */ 158 X86_SOCKET_UNKNOWN, /* 0b011 */ 159 X86_SOCKET_UNKNOWN, /* 0b100 */ 160 X86_SOCKET_UNKNOWN, /* 0b101 */ 161 X86_SOCKET_UNKNOWN, /* 0b110 */ 162 X86_SOCKET_UNKNOWN /* 0b111 */ 163 }, 164 165 /* 166 * Family 0x15 models 00 - 0f 167 */ 168 #define A_SKTS_6 6 169 { 170 X86_SOCKET_UNKNOWN, /* 0b000 */ 171 X86_SOCKET_AM3R2, /* 0b001 */ 172 X86_SOCKET_UNKNOWN, /* 0b010 */ 173 X86_SOCKET_G34, /* 0b011 */ 174 X86_SOCKET_UNKNOWN, /* 0b100 */ 175 X86_SOCKET_C32, /* 0b101 */ 176 X86_SOCKET_UNKNOWN, /* 0b110 */ 177 X86_SOCKET_UNKNOWN /* 0b111 */ 178 }, 179 180 /* 181 * Family 0x15 models 10 - 1f 182 */ 183 #define A_SKTS_7 7 184 { 185 X86_SOCKET_FP2, /* 0b000 */ 186 X86_SOCKET_FS1R2, /* 0b001 */ 187 X86_SOCKET_FM2, /* 0b010 */ 188 X86_SOCKET_UNKNOWN, /* 0b011 */ 189 X86_SOCKET_UNKNOWN, /* 0b100 */ 190 X86_SOCKET_UNKNOWN, /* 0b101 */ 191 X86_SOCKET_UNKNOWN, /* 0b110 */ 192 X86_SOCKET_UNKNOWN /* 0b111 */ 193 }, 194 195 /* 196 * Family 0x15 models 30-3f 197 */ 198 #define A_SKTS_8 8 199 { 200 X86_SOCKET_FP3, /* 0b000 */ 201 X86_SOCKET_FM2R2, /* 0b001 */ 202 X86_SOCKET_UNKNOWN, /* 0b010 */ 203 X86_SOCKET_UNKNOWN, /* 0b011 */ 204 X86_SOCKET_UNKNOWN, /* 0b100 */ 205 X86_SOCKET_UNKNOWN, /* 0b101 */ 206 X86_SOCKET_UNKNOWN, /* 0b110 */ 207 X86_SOCKET_UNKNOWN /* 0b111 */ 208 }, 209 210 /* 211 * Family 0x15 models 60-6f 212 */ 213 #define A_SKTS_9 9 214 { 215 X86_SOCKET_FP4, /* 0b000 */ 216 X86_SOCKET_UNKNOWN, /* 0b001 */ 217 X86_SOCKET_AM4, /* 0b010 */ 218 X86_SOCKET_FM2R2, /* 0b011 */ 219 X86_SOCKET_UNKNOWN, /* 0b100 */ 220 X86_SOCKET_UNKNOWN, /* 0b101 */ 221 X86_SOCKET_UNKNOWN, /* 0b110 */ 222 X86_SOCKET_UNKNOWN /* 0b111 */ 223 }, 224 225 /* 226 * Family 0x15 models 70-7f 227 */ 228 #define A_SKTS_10 10 229 { 230 X86_SOCKET_FP4, /* 0b000 */ 231 X86_SOCKET_UNKNOWN, /* 0b001 */ 232 X86_SOCKET_AM4, /* 0b010 */ 233 X86_SOCKET_UNKNOWN, /* 0b011 */ 234 X86_SOCKET_FT4, /* 0b100 */ 235 X86_SOCKET_UNKNOWN, /* 0b101 */ 236 X86_SOCKET_UNKNOWN, /* 0b110 */ 237 X86_SOCKET_UNKNOWN /* 0b111 */ 238 }, 239 240 /* 241 * Family 0x16 models 00-0f 242 */ 243 #define A_SKTS_11 11 244 { 245 X86_SOCKET_FT3, /* 0b000 */ 246 X86_SOCKET_FS1B, /* 0b001 */ 247 X86_SOCKET_UNKNOWN, /* 0b010 */ 248 X86_SOCKET_UNKNOWN, /* 0b011 */ 249 X86_SOCKET_UNKNOWN, /* 0b100 */ 250 X86_SOCKET_UNKNOWN, /* 0b101 */ 251 X86_SOCKET_UNKNOWN, /* 0b110 */ 252 X86_SOCKET_UNKNOWN /* 0b111 */ 253 }, 254 255 /* 256 * Family 0x16 models 30-3f 257 */ 258 #define A_SKTS_12 12 259 { 260 X86_SOCKET_FT3B, /* 0b000 */ 261 X86_SOCKET_UNKNOWN, /* 0b001 */ 262 X86_SOCKET_UNKNOWN, /* 0b010 */ 263 X86_SOCKET_FP4, /* 0b011 */ 264 X86_SOCKET_UNKNOWN, /* 0b100 */ 265 X86_SOCKET_UNKNOWN, /* 0b101 */ 266 X86_SOCKET_UNKNOWN, /* 0b110 */ 267 X86_SOCKET_UNKNOWN /* 0b111 */ 268 }, 269 270 /* 271 * Family 0x17 models 00-0f (Zen 1 - Naples, Ryzen) 272 */ 273 #define A_SKTS_13 13 274 { 275 X86_SOCKET_UNKNOWN, /* 0b000 */ 276 X86_SOCKET_UNKNOWN, /* 0b001 */ 277 X86_SOCKET_AM4, /* 0b010 */ 278 X86_SOCKET_UNKNOWN, /* 0b011 */ 279 X86_SOCKET_SP3, /* 0b100 */ 280 X86_SOCKET_UNKNOWN, /* 0b101 */ 281 X86_SOCKET_UNKNOWN, /* 0b110 */ 282 X86_SOCKET_SP3R2 /* 0b111 */ 283 }, 284 285 /* 286 * Family 0x17 models 10-2f (Zen 1 - APU: Raven Ridge) 287 * (Zen 1 - APU: Banded Kestrel) 288 * (Zen 1 - APU: Dali) 289 */ 290 #define A_SKTS_14 14 291 { 292 X86_SOCKET_FP5, /* 0b000 */ 293 X86_SOCKET_UNKNOWN, /* 0b001 */ 294 X86_SOCKET_AM4, /* 0b010 */ 295 X86_SOCKET_UNKNOWN, /* 0b011 */ 296 X86_SOCKET_UNKNOWN, /* 0b100 */ 297 X86_SOCKET_UNKNOWN, /* 0b101 */ 298 X86_SOCKET_UNKNOWN, /* 0b110 */ 299 X86_SOCKET_UNKNOWN /* 0b111 */ 300 }, 301 302 /* 303 * Family 0x17 models 30-3f (Zen 2 - Rome) 304 */ 305 #define A_SKTS_15 15 306 { 307 X86_SOCKET_UNKNOWN, /* 0b000 */ 308 X86_SOCKET_UNKNOWN, /* 0b001 */ 309 X86_SOCKET_UNKNOWN, /* 0b010 */ 310 X86_SOCKET_UNKNOWN, /* 0b011 */ 311 X86_SOCKET_SP3, /* 0b100 */ 312 X86_SOCKET_UNKNOWN, /* 0b101 */ 313 X86_SOCKET_UNKNOWN, /* 0b110 */ 314 X86_SOCKET_SP3R2 /* 0b111 */ 315 }, 316 317 /* 318 * Family 0x17 models 60-6f (Zen 2 - Renoir) 319 */ 320 #define A_SKTS_16 16 321 { 322 X86_SOCKET_FP6, /* 0b000 */ 323 X86_SOCKET_UNKNOWN, /* 0b001 */ 324 X86_SOCKET_AM4, /* 0b010 */ 325 X86_SOCKET_UNKNOWN, /* 0b011 */ 326 X86_SOCKET_UNKNOWN, /* 0b100 */ 327 X86_SOCKET_UNKNOWN, /* 0b101 */ 328 X86_SOCKET_UNKNOWN, /* 0b110 */ 329 X86_SOCKET_UNKNOWN /* 0b111 */ 330 }, 331 332 /* 333 * Family 0x17 models 70-7f (Zen 2 - Matisse) 334 */ 335 #define A_SKTS_17 17 336 { 337 X86_SOCKET_UNKNOWN, /* 0b000 */ 338 X86_SOCKET_UNKNOWN, /* 0b001 */ 339 X86_SOCKET_AM4, /* 0b010 */ 340 X86_SOCKET_UNKNOWN, /* 0b011 */ 341 X86_SOCKET_UNKNOWN, /* 0b100 */ 342 X86_SOCKET_UNKNOWN, /* 0b101 */ 343 X86_SOCKET_UNKNOWN, /* 0b110 */ 344 X86_SOCKET_UNKNOWN /* 0b111 */ 345 }, 346 347 /* 348 * Family 0x18 models 00-0f (Dhyana) 349 */ 350 #define A_SKTS_18 18 351 { 352 X86_SOCKET_UNKNOWN, /* 0b000 */ 353 X86_SOCKET_UNKNOWN, /* 0b001 */ 354 X86_SOCKET_UNKNOWN, /* 0b010 */ 355 X86_SOCKET_UNKNOWN, /* 0b011 */ 356 X86_SOCKET_SL1, /* 0b100 */ 357 X86_SOCKET_UNKNOWN, /* 0b101 */ 358 X86_SOCKET_DM1, /* 0b110 */ 359 X86_SOCKET_SL1R2 /* 0b111 */ 360 }, 361 362 /* 363 * Family 0x19 models 00-0f (Zen 3 - Milan) 364 */ 365 #define A_SKTS_19 19 366 { 367 X86_SOCKET_UNKNOWN, /* 0b000 */ 368 X86_SOCKET_UNKNOWN, /* 0b001 */ 369 X86_SOCKET_UNKNOWN, /* 0b010 */ 370 X86_SOCKET_UNKNOWN, /* 0b011 */ 371 X86_SOCKET_SP3, /* 0b100 */ 372 X86_SOCKET_UNKNOWN, /* 0b101 */ 373 X86_SOCKET_UNKNOWN, /* 0b110 */ 374 X86_SOCKET_STRX4 /* 0b111 */ 375 }, 376 377 /* 378 * Family 0x19 models 20-2f (Zen 3 - Vermeer) 379 */ 380 #define A_SKTS_20 20 381 { 382 X86_SOCKET_UNKNOWN, /* 0b000 */ 383 X86_SOCKET_UNKNOWN, /* 0b001 */ 384 X86_SOCKET_AM4, /* 0b010 */ 385 X86_SOCKET_UNKNOWN, /* 0b011 */ 386 X86_SOCKET_UNKNOWN, /* 0b100 */ 387 X86_SOCKET_UNKNOWN, /* 0b101 */ 388 X86_SOCKET_UNKNOWN, /* 0b110 */ 389 X86_SOCKET_UNKNOWN /* 0b111 */ 390 }, 391 392 /* 393 * Family 0x19 models 50-5f (Zen 3 - Cezanne) 394 */ 395 #define A_SKTS_21 21 396 { 397 X86_SOCKET_FP6, /* 0b000 */ 398 X86_SOCKET_UNKNOWN, /* 0b001 */ 399 X86_SOCKET_AM4, /* 0b010 */ 400 X86_SOCKET_UNKNOWN, /* 0b011 */ 401 X86_SOCKET_UNKNOWN, /* 0b100 */ 402 X86_SOCKET_UNKNOWN, /* 0b101 */ 403 X86_SOCKET_UNKNOWN, /* 0b110 */ 404 X86_SOCKET_UNKNOWN /* 0b111 */ 405 }, 406 407 /* 408 * Family 0x19 models 10-1f (Zen 4 - Genoa) 409 * Family 0x19 models a0-af (Zen 4 - Bergamo) 410 */ 411 #define A_SKTS_22 22 412 { 413 X86_SOCKET_UNKNOWN, /* 0b000 */ 414 X86_SOCKET_UNKNOWN, /* 0b001 */ 415 X86_SOCKET_UNKNOWN, /* 0b010 */ 416 X86_SOCKET_UNKNOWN, /* 0b011 */ 417 X86_SOCKET_SP5, /* 0b100 */ 418 X86_SOCKET_UNKNOWN, /* 0b101 */ 419 X86_SOCKET_UNKNOWN, /* 0b110 */ 420 X86_SOCKET_UNKNOWN /* 0b111 */ 421 }, 422 423 /* 424 * Family 0x19 models 40-4f (Zen 3 - Rembrandt) 425 */ 426 #define A_SKTS_23 23 427 { 428 X86_SOCKET_AM5, /* 0b000 */ 429 X86_SOCKET_FP7, /* 0b001 */ 430 X86_SOCKET_FP7R2, /* 0b010 */ 431 X86_SOCKET_UNKNOWN, /* 0b011 */ 432 X86_SOCKET_UNKNOWN, /* 0b100 */ 433 X86_SOCKET_UNKNOWN, /* 0b101 */ 434 X86_SOCKET_UNKNOWN, /* 0b110 */ 435 X86_SOCKET_UNKNOWN /* 0b111 */ 436 }, 437 438 /* 439 * Family 0x19 models 60-6f (Zen 4 - Raphael) 440 */ 441 #define A_SKTS_24 24 442 { 443 X86_SOCKET_AM5, /* 0b000 */ 444 X86_SOCKET_FL1, /* 0b001 */ 445 X86_SOCKET_UNKNOWN, /* 0b010 */ 446 X86_SOCKET_UNKNOWN, /* 0b011 */ 447 X86_SOCKET_UNKNOWN, /* 0b100 */ 448 X86_SOCKET_UNKNOWN, /* 0b101 */ 449 X86_SOCKET_UNKNOWN, /* 0b110 */ 450 X86_SOCKET_UNKNOWN /* 0b111 */ 451 }, 452 453 /* 454 * The always-unknown socket group, used for undocumented parts. It 455 * need not be last; the position is arbitrary. 456 */ 457 #define A_SKTS_UNKNOWN 25 458 { 459 X86_SOCKET_UNKNOWN, /* 0b000 */ 460 X86_SOCKET_UNKNOWN, /* 0b001 */ 461 X86_SOCKET_UNKNOWN, /* 0b010 */ 462 X86_SOCKET_UNKNOWN, /* 0b011 */ 463 X86_SOCKET_UNKNOWN, /* 0b100 */ 464 X86_SOCKET_UNKNOWN, /* 0b101 */ 465 X86_SOCKET_UNKNOWN, /* 0b110 */ 466 X86_SOCKET_UNKNOWN /* 0b111 */ 467 }, 468 /* 469 * Family 0x17 models 90-97 (Zen 2 - Van Gogh) 470 */ 471 #define A_SKTS_26 26 472 { 473 X86_SOCKET_UNKNOWN, /* 0b000 */ 474 X86_SOCKET_UNKNOWN, /* 0b001 */ 475 X86_SOCKET_UNKNOWN, /* 0b010 */ 476 X86_SOCKET_FF3, /* 0b011 */ 477 X86_SOCKET_UNKNOWN, /* 0b100 */ 478 X86_SOCKET_UNKNOWN, /* 0b101 */ 479 X86_SOCKET_UNKNOWN, /* 0b110 */ 480 X86_SOCKET_UNKNOWN /* 0b111 */ 481 }, 482 /* 483 * Family 0x17 models a0-af (Zen 2 - Mendocino) 484 */ 485 #define A_SKTS_27 27 486 { 487 X86_SOCKET_UNKNOWN, /* 0b000 */ 488 X86_SOCKET_FT6, /* 0b001 */ 489 X86_SOCKET_UNKNOWN, /* 0b010 */ 490 X86_SOCKET_UNKNOWN, /* 0b011 */ 491 X86_SOCKET_UNKNOWN, /* 0b100 */ 492 X86_SOCKET_UNKNOWN, /* 0b101 */ 493 X86_SOCKET_UNKNOWN, /* 0b110 */ 494 X86_SOCKET_UNKNOWN /* 0b111 */ 495 }, 496 497 /* 498 * Family 0x19 models 70-7f (Zen 4 - Phoenix) 499 */ 500 #define A_SKTS_28 28 501 { 502 X86_SOCKET_AM5, /* 0b000 */ 503 X86_SOCKET_FP8, /* 0b001 */ 504 X86_SOCKET_UNKNOWN, /* 0b010 */ 505 X86_SOCKET_UNKNOWN, /* 0b011 */ 506 X86_SOCKET_FP7, /* 0b100 */ 507 X86_SOCKET_FP7R2, /* 0b101 */ 508 X86_SOCKET_UNKNOWN, /* 0b110 */ 509 X86_SOCKET_UNKNOWN /* 0b111 */ 510 } 511 }; 512 513 struct amd_sktmap_s { 514 uint32_t skt_code; 515 char sktstr[16]; 516 }; 517 static struct amd_sktmap_s amd_sktmap_strs[] = { 518 { X86_SOCKET_754, "754" }, 519 { X86_SOCKET_939, "939" }, 520 { X86_SOCKET_940, "940" }, 521 { X86_SOCKET_S1g1, "S1g1" }, 522 { X86_SOCKET_AM2, "AM2" }, 523 { X86_SOCKET_F1207, "F(1207)" }, 524 { X86_SOCKET_S1g2, "S1g2" }, 525 { X86_SOCKET_S1g3, "S1g3" }, 526 { X86_SOCKET_AM, "AM" }, 527 { X86_SOCKET_AM2R2, "AM2r2" }, 528 { X86_SOCKET_AM3, "AM3" }, 529 { X86_SOCKET_G34, "G34" }, 530 { X86_SOCKET_ASB2, "ASB2" }, 531 { X86_SOCKET_C32, "C32" }, 532 { X86_SOCKET_S1g4, "S1g4" }, 533 { X86_SOCKET_FT1, "FT1" }, 534 { X86_SOCKET_FM1, "FM1" }, 535 { X86_SOCKET_FS1, "FS1" }, 536 { X86_SOCKET_AM3R2, "AM3r2" }, 537 { X86_SOCKET_FP2, "FP2" }, 538 { X86_SOCKET_FS1R2, "FS1r2" }, 539 { X86_SOCKET_FM2, "FM2" }, 540 { X86_SOCKET_FP3, "FP3" }, 541 { X86_SOCKET_FM2R2, "FM2r2" }, 542 { X86_SOCKET_FP4, "FP4" }, 543 { X86_SOCKET_AM4, "AM4" }, 544 { X86_SOCKET_FT3, "FT3" }, 545 { X86_SOCKET_FT4, "FT4" }, 546 { X86_SOCKET_FS1B, "FS1b" }, 547 { X86_SOCKET_FT3B, "FT3b" }, 548 { X86_SOCKET_SP3, "SP3" }, 549 { X86_SOCKET_SP3R2, "SP3r2" }, 550 { X86_SOCKET_FP5, "FP5" }, 551 { X86_SOCKET_FP6, "FP6" }, 552 { X86_SOCKET_STRX4, "sTRX4" }, 553 { X86_SOCKET_SL1, "SL1" }, 554 { X86_SOCKET_SL1R2, "SL1R2" }, 555 { X86_SOCKET_DM1, "DM1" }, 556 { X86_SOCKET_SP5, "SP5" }, 557 { X86_SOCKET_AM5, "AM5" }, 558 { X86_SOCKET_FP7, "FP7" }, 559 { X86_SOCKET_FP7R2, "FP7r2" }, 560 { X86_SOCKET_FF3, "FF3" }, 561 { X86_SOCKET_FT6, "FT6" }, 562 { X86_SOCKET_FP8, "FP8" }, 563 { X86_SOCKET_FL1, "FL1" }, 564 { X86_SOCKET_UNKNOWN, "Unknown" } /* Must be last! */ 565 }; 566 567 /* Keep the array above in sync with the definitions in x86_archext.h. */ 568 CTASSERT(ARRAY_SIZE(amd_sktmap_strs) == X86_NUM_SOCKETS + 1); 569 570 /* 571 * Table for mapping AMD family/model/stepping ranges onto three derived items: 572 * 573 * * The "chiprev" and associated string, which is generally the AMD silicon 574 * revision along with a symbolic representation of the marketing (not cpuid) 575 * family. In line with the overall cpuid usage, we refer to this as a 576 * processor family. 577 * * The uarch, which is analogous to the chiprev and provides the 578 * microarchitecture/core generation and silicon revision. Note that this is 579 * distinct from the package-level silicon/product revision and is often common 580 * to multiple product lines offered at a given time. 581 * * The socket map selector, used to translate this collection of products' 582 * last 4 model bits (for family 0xf only) or Fn8000_0001_EBX[30:28] into a 583 * socket ID. 584 * 585 * The first member of this array that matches a given family, extended model 586 * plus model range, and stepping range will be considered a match. This allows 587 * us to end each cpuid family and/or processor family with a catchall that 588 * while less specific than we might like still allows us to provide a fair 589 * amount of detail to both other kernel consumers and userland. 590 */ 591 static const struct amd_rev_mapent { 592 uint_t rm_family; 593 uint_t rm_modello; 594 uint_t rm_modelhi; 595 uint_t rm_steplo; 596 uint_t rm_stephi; 597 x86_chiprev_t rm_chiprev; 598 const char *rm_chiprevstr; 599 x86_uarchrev_t rm_uarchrev; 600 uint_t rm_sktidx; 601 } amd_revmap[] = { 602 /* 603 * =============== AuthenticAMD Family 0xf =============== 604 */ 605 606 /* 607 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 608 */ 609 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_LEGACY_F_REV_B, "B", 610 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 611 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_LEGACY_F_REV_B, "B", 612 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 613 /* 614 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 615 */ 616 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_LEGACY_F_REV_C0, "C0", 617 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 618 /* 619 * Rev CG is the rest of extended model 0x0 - i.e., everything 620 * but the rev B and C0 combinations covered above. 621 */ 622 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_CG, "CG", 623 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 624 /* 625 * Rev D has extended model 0x1. 626 */ 627 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_D, "D", 628 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 629 /* 630 * Rev E has extended model 0x2. 631 * Extended model 0x3 is unused but available to grow into. 632 */ 633 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_E, "E", 634 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 635 /* 636 * Rev F has extended models 0x4 and 0x5. 637 */ 638 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_F, "F", 639 X86_UARCHREV_AMD_LEGACY, A_SKTS_1 }, 640 /* 641 * Rev G has extended model 0x6. 642 */ 643 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_G, "G", 644 X86_UARCHREV_AMD_LEGACY, A_SKTS_1 }, 645 646 /* 647 * =============== AuthenticAMD Family 0x10 =============== 648 */ 649 650 /* 651 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}. 652 * Give all of model 0 stepping range to rev A. 653 */ 654 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_LEGACY_10_REV_A, "A", 655 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 656 657 /* 658 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}. 659 * Give all of model 2 stepping range to rev B. 660 */ 661 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_B, "B", 662 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 663 664 /* 665 * Rev C has models 4-6 (depending on L3 cache configuration) 666 * Give all of models 4-6 stepping range 0-2 to rev C2. 667 */ 668 { 0x10, 0x4, 0x6, 0x0, 0x2, X86_CHIPREV_AMD_LEGACY_10_REV_C2, "C2", 669 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 670 671 /* 672 * Rev C has models 4-6 (depending on L3 cache configuration) 673 * Give all of models 4-6 stepping range >= 3 to rev C3. 674 */ 675 { 0x10, 0x4, 0x6, 0x3, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_C3, "C3", 676 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 677 678 /* 679 * Rev D has models 8 and 9 680 * Give all of model 8 and 9 stepping 0 to rev D0. 681 */ 682 { 0x10, 0x8, 0x9, 0x0, 0x0, X86_CHIPREV_AMD_LEGACY_10_REV_D0, "D0", 683 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 684 685 /* 686 * Rev D has models 8 and 9 687 * Give all of model 8 and 9 stepping range >= 1 to rev D1. 688 */ 689 { 0x10, 0x8, 0x9, 0x1, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_D1, "D1", 690 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 691 692 /* 693 * Rev E has models A and stepping 0 694 * Give all of model A stepping range to rev E. 695 */ 696 { 0x10, 0xA, 0xA, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_E, "E", 697 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 698 699 { 0x10, 0x0, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_UNKNOWN, "??", 700 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 701 702 /* 703 * =============== AuthenticAMD Family 0x11 =============== 704 */ 705 { 0x11, 0x03, 0x03, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_11_REV_B, "B", 706 X86_UARCHREV_AMD_LEGACY, A_SKTS_3 }, 707 { 0x11, 0x00, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_11_UNKNOWN, "??", 708 X86_UARCHREV_AMD_LEGACY, A_SKTS_3 }, 709 710 /* 711 * =============== AuthenticAMD Family 0x12 =============== 712 */ 713 { 0x12, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_12_REV_B, "B", 714 X86_UARCHREV_AMD_LEGACY, A_SKTS_4 }, 715 { 0x12, 0x00, 0x00, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_12_UNKNOWN, "??", 716 X86_UARCHREV_AMD_LEGACY, A_SKTS_4 }, 717 718 /* 719 * =============== AuthenticAMD Family 0x14 =============== 720 */ 721 { 0x14, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_REV_B, "B", 722 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 }, 723 { 0x14, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_REV_C, "C", 724 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 }, 725 { 0x14, 0x00, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_UNKNOWN, "??", 726 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 }, 727 728 /* 729 * =============== AuthenticAMD Family 0x15 =============== 730 */ 731 { 0x15, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_OROCHI_REV_B2, "OR-B2", 732 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 }, 733 { 0x15, 0x02, 0x02, 0x0, 0x0, X86_CHIPREV_AMD_OROCHI_REV_C0, "OR-C0", 734 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 }, 735 { 0x15, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_OROCHI_UNKNOWN, "OR-??", 736 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 }, 737 738 { 0x15, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_TRINITY_REV_A1, "TN-A1", 739 X86_UARCHREV_AMD_LEGACY, A_SKTS_7 }, 740 { 0x15, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_TRINITY_UNKNOWN, "TN-??", 741 X86_UARCHREV_AMD_LEGACY, A_SKTS_7 }, 742 743 { 0x15, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_KAVERI_REV_A1, "KV-A1", 744 X86_UARCHREV_AMD_LEGACY, A_SKTS_8 }, 745 { 0x15, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_KAVERI_UNKNOWN, "KV-??", 746 X86_UARCHREV_AMD_LEGACY, A_SKTS_8 }, 747 748 /* 749 * The Carrizo rev guide mentions A0 as having an ID of "00600F00h" but 750 * this appears to be a typo as elsewhere it's given as "00660F00h". We 751 * assume the latter is correct. 752 */ 753 { 0x15, 0x60, 0x60, 0x0, 0x0, X86_CHIPREV_AMD_CARRIZO_REV_A0, "CZ-A0", 754 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 }, 755 { 0x15, 0x60, 0x60, 0x1, 0x1, X86_CHIPREV_AMD_CARRIZO_REV_A1, "CZ-A1", 756 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 }, 757 /* 758 * CZ-DDR4 and BR-A1 are indistinguishable via cpuid; the rev guide 759 * indicates that they should be distinguished by the contents of the 760 * OSVW MSR, but this register is just a software scratch space which 761 * means the actual method of distinguishing the two is not documented 762 * and on PCs will be done by a BIOS. In the extremely unlikely event 763 * it becomes necessary to distinguish these, an OSVW-driven fixup can 764 * be added. 765 */ 766 { 0x15, 0x65, 0x65, 0x1, 0x1, X86_CHIPREV_AMD_CARRIZO_REV_DDR4, 767 "CZ-DDR4", X86_UARCHREV_AMD_LEGACY, A_SKTS_9 }, 768 { 0x15, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_CARRIZO_UNKNOWN, "CZ-??", 769 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 }, 770 771 { 0x15, 0x70, 0x70, 0x0, 0x0, X86_CHIPREV_AMD_STONEY_RIDGE_REV_A0, 772 "ST-A0", X86_UARCHREV_AMD_LEGACY, A_SKTS_10 }, 773 { 0x15, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_STONEY_RIDGE_UNKNOWN, 774 "ST-??", X86_UARCHREV_AMD_LEGACY, A_SKTS_10 }, 775 776 /* 777 * =============== AuthenticAMD Family 0x16 =============== 778 */ 779 { 0x16, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_AMD_KABINI_A1, "KB-A1", 780 X86_UARCHREV_AMD_LEGACY, A_SKTS_11 }, 781 { 0x16, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_KABINI_UNKNOWN, "KB-??", 782 X86_UARCHREV_AMD_LEGACY, A_SKTS_11 }, 783 784 { 0x16, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_MULLINS_A1, "ML-A1", 785 X86_UARCHREV_AMD_LEGACY, A_SKTS_12 }, 786 { 0x16, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_MULLINS_UNKNOWN, "ML-??", 787 X86_UARCHREV_AMD_LEGACY, A_SKTS_12 }, 788 789 /* 790 * =============== AuthenticAMD Family 0x17 =============== 791 */ 792 /* Naples == Zeppelin == ZP */ 793 { 0x17, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_NAPLES_A0, "ZP-A0", 794 X86_UARCHREV_AMD_ZEN1, A_SKTS_13 }, 795 { 0x17, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_NAPLES_B1, "ZP-B1", 796 X86_UARCHREV_AMD_ZEN1, A_SKTS_13 }, 797 { 0x17, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_NAPLES_B2, "ZP-B2", 798 X86_UARCHREV_AMD_ZEN1, A_SKTS_13 }, 799 { 0x17, 0x00, 0x07, 0x0, 0xf, X86_CHIPREV_AMD_NAPLES_UNKNOWN, "ZP-??", 800 X86_UARCHREV_AMD_ZEN1, A_SKTS_13 }, 801 { 0x17, 0x08, 0x08, 0x2, 0x2, X86_CHIPREV_AMD_PINNACLE_RIDGE_B2, 802 "PiR-B2", X86_UARCHREV_AMD_ZENPLUS, A_SKTS_13 }, 803 { 0x17, 0x08, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_PINNACLE_RIDGE_UNKNOWN, 804 "PiR-??", X86_UARCHREV_AMD_ZENPLUS, A_SKTS_13 }, 805 806 { 0x17, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_RAVEN_RIDGE_B0, 807 "RV-B0", X86_UARCHREV_AMD_ZEN1, A_SKTS_14 }, 808 { 0x17, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_RAVEN_RIDGE_B1, 809 "RV-B1", X86_UARCHREV_AMD_ZEN1, A_SKTS_14 }, 810 { 0x17, 0x10, 0x17, 0x0, 0xf, X86_CHIPREV_AMD_RAVEN_RIDGE_UNKNOWN, 811 "RV-??", X86_UARCHREV_AMD_ZEN1, A_SKTS_14 }, 812 { 0x17, 0x18, 0x18, 0x1, 0x1, X86_CHIPREV_AMD_PICASSO_B1, "PCO-B1", 813 X86_UARCHREV_AMD_ZENPLUS, A_SKTS_14 }, 814 { 0x17, 0x18, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_PICASSO_UNKNOWN, "PCO-??", 815 X86_UARCHREV_AMD_ZENPLUS, A_SKTS_14 }, 816 817 { 0x17, 0x20, 0x20, 0x1, 0x1, X86_CHIPREV_AMD_DALI_A1, "RV2X-A1", 818 X86_UARCHREV_AMD_ZEN1, A_SKTS_14 }, 819 { 0x17, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_DALI_UNKNOWN, "RV2X-??", 820 X86_UARCHREV_AMD_ZEN1, A_SKTS_14 }, 821 822 /* Rome == Starship == SSP */ 823 { 0x17, 0x30, 0x30, 0x0, 0x0, X86_CHIPREV_AMD_ROME_A0, "SSP-A0", 824 X86_UARCHREV_AMD_ZEN2_A0, A_SKTS_15 }, 825 { 0x17, 0x31, 0x31, 0x0, 0x0, X86_CHIPREV_AMD_ROME_B0, "SSP-B0", 826 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_15 }, 827 { 0x17, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_ROME_UNKNOWN, "SSP-??", 828 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_15 }, 829 830 { 0x17, 0x60, 0x60, 0x1, 0x1, X86_CHIPREV_AMD_RENOIR_A1, "RN-A1", 831 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_16 }, 832 { 0x17, 0x60, 0x67, 0x0, 0xf, X86_CHIPREV_AMD_RENOIR_UNKNOWN, "RN-??", 833 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_16 }, 834 { 0x17, 0x68, 0x68, 0x1, 0x1, X86_CHIPREV_AMD_RENOIR_LCN_A1, "LCN-A1", 835 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_16 }, 836 { 0x17, 0x68, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_RENOIR_UNKNOWN, "LCN-??", 837 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_16 }, 838 839 { 0x17, 0x71, 0x71, 0x0, 0x0, X86_CHIPREV_AMD_MATISSE_B0, "MTS-B0", 840 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_17 }, 841 { 0x17, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_MATISSE_UNKNOWN, "MTS-??", 842 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_17 }, 843 844 { 0x17, 0x90, 0x97, 0x0, 0xf, X86_CHIPREV_AMD_VAN_GOGH_UNKNOWN, "??", 845 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_26 }, 846 { 0x17, 0x98, 0x9f, 0x0, 0xf, X86_CHIPREV_AMD_VAN_GOGH_UNKNOWN, "??", 847 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_UNKNOWN }, 848 849 { 0x17, 0xa0, 0xaf, 0x0, 0xf, X86_CHIPREV_AMD_MENDOCINO_UNKNOWN, "??", 850 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_27 }, 851 852 /* 853 * =============== HygonGenuine Family 0x18 =============== 854 */ 855 { 0x18, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_HYGON_DHYANA_A1, "DN_A1", 856 X86_UARCHREV_AMD_ZEN1, A_SKTS_18 }, 857 { 0x18, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_HYGON_DHYANA_UNKNOWN, "DN_??", 858 X86_UARCHREV_AMD_ZEN1, A_SKTS_18 }, 859 860 /* 861 * =============== AuthenticAMD Family 0x19 =============== 862 */ 863 /* Milan == Genesis == GN */ 864 { 0x19, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_MILAN_A0, "GN-A0", 865 X86_UARCHREV_AMD_ZEN3_A0, A_SKTS_19 }, 866 { 0x19, 0x01, 0x01, 0x0, 0x0, X86_CHIPREV_AMD_MILAN_B0, "GN-B0", 867 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_19 }, 868 { 0x19, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_MILAN_B1, "GN-B1", 869 X86_UARCHREV_AMD_ZEN3_B1, A_SKTS_19 }, 870 /* Marketed as Milan-X but still GN */ 871 { 0x19, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_MILAN_B2, "GN-B2", 872 X86_UARCHREV_AMD_ZEN3_B2, A_SKTS_19 }, 873 { 0x19, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_MILAN_UNKNOWN, "GN-??", 874 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_19 }, 875 876 /* Genoa == Stones == RS */ 877 { 0x19, 0x10, 0x10, 0x0, 0x0, X86_CHIPREV_AMD_GENOA_A0, "RS-A0", 878 X86_UARCHREV_AMD_ZEN4, A_SKTS_22 }, 879 { 0x19, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_GENOA_A1, "RS-A1", 880 X86_UARCHREV_AMD_ZEN4, A_SKTS_22 }, 881 { 0x19, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_GENOA_B0, "RS-B0", 882 X86_UARCHREV_AMD_ZEN4, A_SKTS_22 }, 883 { 0x19, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_GENOA_B1, "RS-B1", 884 X86_UARCHREV_AMD_ZEN4, A_SKTS_22 }, 885 { 0x19, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_GENOA_UNKNOWN, "RS-??", 886 X86_UARCHREV_AMD_ZEN4, A_SKTS_22 }, 887 888 { 0x19, 0x20, 0x20, 0x0, 0x0, X86_CHIPREV_AMD_VERMEER_A0, "VMR-A0", 889 X86_UARCHREV_AMD_ZEN3_A0, A_SKTS_20 }, 890 { 0x19, 0x21, 0x21, 0x0, 0x0, X86_CHIPREV_AMD_VERMEER_B0, "VMR-B0", 891 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_20 }, 892 { 0x19, 0x21, 0x21, 0x2, 0x2, X86_CHIPREV_AMD_VERMEER_B2, "VMR-B2", 893 X86_UARCHREV_AMD_ZEN3_B2, A_SKTS_20 }, 894 { 0x19, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_VERMEER_UNKNOWN, "VMR-??", 895 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_20 }, 896 897 /* Rev guide is missing AM5 information, including A0 and B0 */ 898 { 0x19, 0x40, 0x40, 0x0, 0x0, X86_CHIPREV_AMD_REMBRANDT_A0, "RMB-A0", 899 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_23 }, 900 { 0x19, 0x44, 0x44, 0x0, 0x0, X86_CHIPREV_AMD_REMBRANDT_B0, "RMB-B0", 901 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_23 }, 902 { 0x19, 0x44, 0x44, 0x1, 0x1, X86_CHIPREV_AMD_REMBRANDT_B1, "RMB-B1", 903 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_23 }, 904 { 0x19, 0x40, 0x4f, 0x0, 0xf, X86_CHIPREV_AMD_REMBRANDT_UNKNOWN, 905 "RMB-??", X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_23 }, 906 907 /* Cezanne */ 908 { 0x19, 0x50, 0x50, 0x0, 0x0, X86_CHIPREV_AMD_CEZANNE_A0, "CZN-A0", 909 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_21 }, 910 { 0x19, 0x50, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_CEZANNE_UNKNOWN, "CZN-??", 911 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_21 }, 912 913 /* Raphael */ 914 { 0x19, 0x61, 0x61, 0x2, 0x2, X86_CHIPREV_AMD_RAPHAEL_B2, "RPL-B2", 915 X86_UARCHREV_AMD_ZEN4, A_SKTS_24 }, 916 { 0x19, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_RAPHAEL_UNKNOWN, "RPL-??", 917 X86_UARCHREV_AMD_ZEN4, A_SKTS_24 }, 918 919 /* Phoenix */ 920 { 0x19, 0x74, 0x74, 0x1, 0x1, X86_CHIPREV_AMD_PHOENIX_A1, "PHX-A1", 921 X86_UARCHREV_AMD_ZEN4, A_SKTS_28 }, 922 { 0x19, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_PHOENIX_UNKNOWN, "PHX-??", 923 X86_UARCHREV_AMD_ZEN4, A_SKTS_28 }, 924 925 /* Bergamo */ 926 { 0x19, 0xa0, 0xaf, 0x0, 0xf, X86_CHIPREV_AMD_BERGAMO_UNKNOWN, "???", 927 X86_UARCHREV_AMD_ZEN4, A_SKTS_22 } 928 }; 929 930 /* 931 * AMD keeps the socket type in CPUID Fn8000_0001_EBX, bits 31:28. 932 */ 933 static uint32_t 934 synth_amd_skt_cpuid(uint_t family, uint_t sktid) 935 { 936 struct cpuid_regs cp; 937 uint_t idx; 938 939 cp.cp_eax = 0x80000001; 940 (void) __cpuid_insn(&cp); 941 942 /* PkgType bits */ 943 idx = BITX(cp.cp_ebx, 31, 28); 944 945 if (idx > 7) { 946 return (X86_SOCKET_UNKNOWN); 947 } 948 949 if (family == 0x10) { 950 uint32_t val; 951 952 val = pci_getl_func(0, 24, 2, 0x94); 953 if (BITX(val, 8, 8)) { 954 if (amd_skts[sktid][idx] == X86_SOCKET_AM2R2) { 955 return (X86_SOCKET_AM3); 956 } else if (amd_skts[sktid][idx] == X86_SOCKET_S1g3) { 957 return (X86_SOCKET_S1g4); 958 } 959 } 960 } 961 962 return (amd_skts[sktid][idx]); 963 } 964 965 static void 966 synth_amd_info(uint_t family, uint_t model, uint_t step, 967 uint32_t *skt_p, x86_chiprev_t *chiprev_p, const char **chiprevstr_p, 968 x86_uarchrev_t *uarchrev_p) 969 { 970 const struct amd_rev_mapent *rmp; 971 int found = 0; 972 int i; 973 974 if (family < 0xf) 975 return; 976 977 for (i = 0, rmp = amd_revmap; i < ARRAY_SIZE(amd_revmap); i++, rmp++) { 978 if (family == rmp->rm_family && 979 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 980 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 981 found = 1; 982 break; 983 } 984 } 985 986 if (found) { 987 if (chiprev_p != NULL) 988 *chiprev_p = rmp->rm_chiprev; 989 if (chiprevstr_p != NULL) 990 *chiprevstr_p = rmp->rm_chiprevstr; 991 if (uarchrev_p != NULL) 992 *uarchrev_p = rmp->rm_uarchrev; 993 } 994 995 if (skt_p != NULL) { 996 int platform; 997 998 #ifdef __xpv 999 /* PV guest */ 1000 if (!is_controldom()) { 1001 *skt_p = X86_SOCKET_UNKNOWN; 1002 return; 1003 } 1004 #endif 1005 platform = get_hwenv(); 1006 1007 if ((platform & HW_VIRTUAL) != 0) { 1008 *skt_p = X86_SOCKET_UNKNOWN; 1009 return; 1010 } 1011 1012 if (!found) 1013 return; 1014 1015 if (family == 0xf) { 1016 *skt_p = amd_skts[rmp->rm_sktidx][model & 0x3]; 1017 } else { 1018 *skt_p = synth_amd_skt_cpuid(family, rmp->rm_sktidx); 1019 } 1020 } 1021 } 1022 1023 uint32_t 1024 _cpuid_skt(uint_t vendor, uint_t family, uint_t model, uint_t step) 1025 { 1026 uint32_t skt = X86_SOCKET_UNKNOWN; 1027 1028 switch (vendor) { 1029 case X86_VENDOR_AMD: 1030 case X86_VENDOR_HYGON: 1031 synth_amd_info(family, model, step, &skt, NULL, NULL, NULL); 1032 break; 1033 1034 default: 1035 break; 1036 1037 } 1038 1039 return (skt); 1040 } 1041 1042 const char * 1043 _cpuid_sktstr(uint_t vendor, uint_t family, uint_t model, uint_t step) 1044 { 1045 const char *sktstr = "Unknown"; 1046 struct amd_sktmap_s *sktmapp; 1047 uint32_t skt = X86_SOCKET_UNKNOWN; 1048 1049 switch (vendor) { 1050 case X86_VENDOR_AMD: 1051 case X86_VENDOR_HYGON: 1052 synth_amd_info(family, model, step, &skt, NULL, NULL, NULL); 1053 1054 sktmapp = amd_sktmap_strs; 1055 while (sktmapp->skt_code != X86_SOCKET_UNKNOWN) { 1056 if (sktmapp->skt_code == skt) 1057 break; 1058 sktmapp++; 1059 } 1060 sktstr = sktmapp->sktstr; 1061 break; 1062 1063 default: 1064 break; 1065 1066 } 1067 1068 return (sktstr); 1069 } 1070 1071 x86_chiprev_t 1072 _cpuid_chiprev(uint_t vendor, uint_t family, uint_t model, uint_t step) 1073 { 1074 x86_chiprev_t chiprev = X86_CHIPREV_UNKNOWN; 1075 1076 switch (vendor) { 1077 case X86_VENDOR_AMD: 1078 case X86_VENDOR_HYGON: 1079 synth_amd_info(family, model, step, NULL, &chiprev, NULL, NULL); 1080 break; 1081 1082 default: 1083 break; 1084 1085 } 1086 1087 return (chiprev); 1088 } 1089 1090 x86_uarchrev_t 1091 _cpuid_uarchrev(uint_t vendor, uint_t family, uint_t model, uint_t step) 1092 { 1093 x86_uarchrev_t uarchrev = X86_UARCHREV_UNKNOWN; 1094 1095 switch (vendor) { 1096 case X86_VENDOR_AMD: 1097 case X86_VENDOR_HYGON: 1098 synth_amd_info(family, model, step, NULL, NULL, NULL, 1099 &uarchrev); 1100 break; 1101 1102 default: 1103 break; 1104 1105 } 1106 1107 return (uarchrev); 1108 } 1109 1110 const char * 1111 _cpuid_chiprevstr(uint_t vendor, uint_t family, uint_t model, uint_t step) 1112 { 1113 const char *revstr = "Unknown"; 1114 1115 switch (vendor) { 1116 case X86_VENDOR_AMD: 1117 case X86_VENDOR_HYGON: 1118 synth_amd_info(family, model, step, NULL, NULL, &revstr, NULL); 1119 break; 1120 1121 default: 1122 break; 1123 1124 } 1125 1126 return (revstr); 1127 1128 } 1129 1130 /* 1131 * Map the vendor string to a type code 1132 */ 1133 uint_t 1134 _cpuid_vendorstr_to_vendorcode(char *vendorstr) 1135 { 1136 if (strcmp(vendorstr, X86_VENDORSTR_Intel) == 0) 1137 return (X86_VENDOR_Intel); 1138 else if (strcmp(vendorstr, X86_VENDORSTR_AMD) == 0) 1139 return (X86_VENDOR_AMD); 1140 else if (strcmp(vendorstr, X86_VENDORSTR_HYGON) == 0) 1141 return (X86_VENDOR_HYGON); 1142 else if (strcmp(vendorstr, X86_VENDORSTR_TM) == 0) 1143 return (X86_VENDOR_TM); 1144 else if (strcmp(vendorstr, X86_VENDORSTR_CYRIX) == 0) 1145 return (X86_VENDOR_Cyrix); 1146 else if (strcmp(vendorstr, X86_VENDORSTR_UMC) == 0) 1147 return (X86_VENDOR_UMC); 1148 else if (strcmp(vendorstr, X86_VENDORSTR_NexGen) == 0) 1149 return (X86_VENDOR_NexGen); 1150 else if (strcmp(vendorstr, X86_VENDORSTR_Centaur) == 0) 1151 return (X86_VENDOR_Centaur); 1152 else if (strcmp(vendorstr, X86_VENDORSTR_Rise) == 0) 1153 return (X86_VENDOR_Rise); 1154 else if (strcmp(vendorstr, X86_VENDORSTR_SiS) == 0) 1155 return (X86_VENDOR_SiS); 1156 else if (strcmp(vendorstr, X86_VENDORSTR_NSC) == 0) 1157 return (X86_VENDOR_NSC); 1158 else 1159 return (X86_VENDOR_IntelClone); 1160 } 1161