1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 * 26 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 27 */ 28 29 /* 30 * Portions Copyright 2009 Advanced Micro Devices, Inc. 31 */ 32 33 /* 34 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> 35 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 36 * Copyright 2019 Joyent, Inc. 37 * Copyright 2023 Oxide Computer Company 38 */ 39 40 /* 41 * Support functions that interpret CPUID and similar information. 42 * These should not be used from anywhere other than cpuid.c and 43 * cmi_hw.c - as such we will not list them in any header file 44 * such as x86_archext.h. 45 * 46 * In cpuid.c we process CPUID information for each cpu_t instance 47 * we're presented with, and stash this raw information and material 48 * derived from it in per-cpu_t structures. 49 * 50 * If we are virtualized then the CPUID information derived from CPUID 51 * instructions executed in the guest is based on whatever the hypervisor 52 * wanted to make things look like, and the cpu_t are not necessarily in 1:1 53 * or fixed correspondence with real processor execution resources. In cmi_hw.c 54 * we are interested in the native properties of a processor - for fault 55 * management (and potentially other, such as power management) purposes; 56 * it will tunnel through to real hardware information, and use the 57 * functionality provided in this file to process it. 58 */ 59 60 #include <sys/types.h> 61 #include <sys/systm.h> 62 #include <sys/bitmap.h> 63 #include <sys/x86_archext.h> 64 #include <sys/pci_cfgspace.h> 65 #include <sys/sysmacros.h> 66 #ifdef __xpv 67 #include <sys/hypervisor.h> 68 #endif 69 70 /* 71 * AMD socket types. 72 * First index defines a processor family; see notes inline. The second index 73 * selects the socket type by either (model & 0x3) for family 0fh or the CPUID 74 * pkg bits (Fn8000_0001_EBX[31:28]) for later families. 75 */ 76 static uint32_t amd_skts[][16] = { 77 /* 78 * Family 0xf revisions B through E 79 */ 80 #define A_SKTS_0 0 81 { 82 [0] = X86_SOCKET_754, 83 [1] = X86_SOCKET_940, 84 [2] = X86_SOCKET_754, 85 [3] = X86_SOCKET_939, 86 }, 87 /* 88 * Family 0xf revisions F and G 89 */ 90 #define A_SKTS_1 1 91 { 92 [0] = X86_SOCKET_S1g1, 93 [1] = X86_SOCKET_F1207, 94 [3] = X86_SOCKET_AM2 95 }, 96 /* 97 * Family 0x10 98 */ 99 #define A_SKTS_2 2 100 { 101 [0] = X86_SOCKET_F1207, 102 [1] = X86_SOCKET_AM2R2, 103 [2] = X86_SOCKET_S1g3, 104 [3] = X86_SOCKET_G34, 105 [4] = X86_SOCKET_ASB2, 106 [5] = X86_SOCKET_C32 107 }, 108 109 /* 110 * Family 0x11 111 */ 112 #define A_SKTS_3 3 113 { 114 [2] = X86_SOCKET_S1g2 115 }, 116 117 /* 118 * Family 0x12 119 */ 120 #define A_SKTS_4 4 121 { 122 [1] = X86_SOCKET_FS1, 123 [2] = X86_SOCKET_FM1 124 }, 125 126 /* 127 * Family 0x14 128 */ 129 #define A_SKTS_5 5 130 { 131 [0] = X86_SOCKET_FT1 132 }, 133 134 /* 135 * Family 0x15 models 00 - 0f 136 */ 137 #define A_SKTS_6 6 138 { 139 [1] = X86_SOCKET_AM3R2, 140 [3] = X86_SOCKET_G34, 141 [5] = X86_SOCKET_C32 142 }, 143 144 /* 145 * Family 0x15 models 10 - 1f 146 */ 147 #define A_SKTS_7 7 148 { 149 [0] = X86_SOCKET_FP2, 150 [1] = X86_SOCKET_FS1R2, 151 [2] = X86_SOCKET_FM2 152 }, 153 154 /* 155 * Family 0x15 models 30-3f 156 */ 157 #define A_SKTS_8 8 158 { 159 [0] = X86_SOCKET_FP3, 160 [1] = X86_SOCKET_FM2R2 161 }, 162 163 /* 164 * Family 0x15 models 60-6f 165 */ 166 #define A_SKTS_9 9 167 { 168 [0] = X86_SOCKET_FP4, 169 [2] = X86_SOCKET_AM4, 170 [3] = X86_SOCKET_FM2R2 171 }, 172 173 /* 174 * Family 0x15 models 70-7f 175 */ 176 #define A_SKTS_10 10 177 { 178 [0] = X86_SOCKET_FP4, 179 [2] = X86_SOCKET_AM4, 180 [4] = X86_SOCKET_FT4 181 }, 182 183 /* 184 * Family 0x16 models 00-0f 185 */ 186 #define A_SKTS_11 11 187 { 188 [0] = X86_SOCKET_FT3, 189 [1] = X86_SOCKET_FS1B 190 }, 191 192 /* 193 * Family 0x16 models 30-3f 194 */ 195 #define A_SKTS_12 12 196 { 197 [0] = X86_SOCKET_FT3B, 198 [3] = X86_SOCKET_FP4 199 }, 200 201 /* 202 * Family 0x17 models 00-0f (Zen 1 - Naples, Ryzen) 203 */ 204 #define A_SKTS_NAPLES 13 205 { 206 [2] = X86_SOCKET_AM4, 207 [4] = X86_SOCKET_SP3, 208 [7] = X86_SOCKET_SP3R2 209 }, 210 211 /* 212 * Family 0x17 models 10-2f (Zen 1 - APU: Raven Ridge) 213 * (Zen 1 - APU: Banded Kestrel) 214 * (Zen 1 - APU: Dali) 215 */ 216 #define A_SKTS_RAVEN 14 217 { 218 [0] = X86_SOCKET_FP5, 219 [2] = X86_SOCKET_AM4 220 }, 221 222 /* 223 * Family 0x17 models 30-3f (Zen 2 - Rome) 224 */ 225 #define A_SKTS_ROME 15 226 { 227 [4] = X86_SOCKET_SP3, 228 [7] = X86_SOCKET_SP3R2 229 }, 230 231 /* 232 * Family 0x17 models 60-6f (Zen 2 - Renoir) 233 */ 234 #define A_SKTS_RENOIR 16 235 { 236 [0] = X86_SOCKET_FP6, 237 [2] = X86_SOCKET_AM4 238 }, 239 240 /* 241 * Family 0x17 models 70-7f (Zen 2 - Matisse) 242 */ 243 #define A_SKTS_MATISSE 17 244 { 245 [2] = X86_SOCKET_AM4, 246 }, 247 248 /* 249 * Family 0x18 models 00-0f (Dhyana) 250 */ 251 #define A_SKTS_DHYANA 18 252 { 253 [4] = X86_SOCKET_SL1, 254 [6] = X86_SOCKET_DM1, 255 [7] = X86_SOCKET_SL1R2 256 }, 257 258 /* 259 * Family 0x19 models 00-0f (Zen 3 - Milan) 260 */ 261 #define A_SKTS_MILAN 19 262 { 263 [4] = X86_SOCKET_SP3, 264 [7] = X86_SOCKET_STRX4 265 }, 266 267 /* 268 * Family 0x19 models 20-2f (Zen 3 - Vermeer) 269 */ 270 #define A_SKTS_VERMEER 20 271 { 272 [2] = X86_SOCKET_AM4, 273 }, 274 275 /* 276 * Family 0x19 models 50-5f (Zen 3 - Cezanne) 277 */ 278 #define A_SKTS_CEZANNE 21 279 { 280 [0] = X86_SOCKET_FP6, 281 [2] = X86_SOCKET_AM4 282 }, 283 284 /* 285 * Family 0x19 models 10-1f (Zen 4 - Genoa) 286 */ 287 #define A_SKTS_GENOA 22 288 { 289 [4] = X86_SOCKET_SP5, 290 [8] = X86_SOCKET_TR5 291 }, 292 293 /* 294 * Family 0x19 models 40-4f (Zen 3 - Rembrandt) 295 */ 296 #define A_SKTS_REMBRANDT 23 297 { 298 [0] = X86_SOCKET_AM5, 299 [1] = X86_SOCKET_FP7, 300 [2] = X86_SOCKET_FP7R2 301 }, 302 303 /* 304 * Family 0x19 models 60-6f (Zen 4 - Raphael) 305 */ 306 #define A_SKTS_RAPHAEL 24 307 { 308 [0] = X86_SOCKET_AM5, 309 [1] = X86_SOCKET_FL1 310 }, 311 312 /* 313 * The always-unknown socket group, used for undocumented parts. It 314 * need not be last; the position is arbitrary. The default initializer 315 * for this is zero which is x86 socket unknown. 316 */ 317 #define A_SKTS_UNKNOWN 25 318 { 319 }, 320 /* 321 * Family 0x17 models 90-97 (Zen 2 - Van Gogh) 322 */ 323 #define A_SKTS_VANGOGH 26 324 { 325 [3] = X86_SOCKET_FF3 326 }, 327 /* 328 * Family 0x17 models a0-af (Zen 2 - Mendocino) 329 */ 330 #define A_SKTS_MENDOCINO 27 331 { 332 [1] = X86_SOCKET_FT6 333 }, 334 335 /* 336 * Family 0x19 models 70-7f (Zen 4 - Phoenix) 337 */ 338 #define A_SKTS_PHOENIX 28 339 { 340 [0] = X86_SOCKET_AM5, 341 [1] = X86_SOCKET_FP8, 342 [4] = X86_SOCKET_FP7, 343 [5] = X86_SOCKET_FP7R2, 344 }, 345 346 /* 347 * Family 0x19 models a0-af (Zen 4c - Bergamo/Siena) 348 */ 349 #define A_SKTS_BERGAMO 29 350 { 351 [4] = X86_SOCKET_SP5, 352 [8] = X86_SOCKET_SP6 353 } 354 }; 355 356 struct amd_sktmap_s { 357 uint32_t skt_code; 358 char sktstr[16]; 359 }; 360 static struct amd_sktmap_s amd_sktmap_strs[] = { 361 { X86_SOCKET_754, "754" }, 362 { X86_SOCKET_939, "939" }, 363 { X86_SOCKET_940, "940" }, 364 { X86_SOCKET_S1g1, "S1g1" }, 365 { X86_SOCKET_AM2, "AM2" }, 366 { X86_SOCKET_F1207, "F(1207)" }, 367 { X86_SOCKET_S1g2, "S1g2" }, 368 { X86_SOCKET_S1g3, "S1g3" }, 369 { X86_SOCKET_AM, "AM" }, 370 { X86_SOCKET_AM2R2, "AM2r2" }, 371 { X86_SOCKET_AM3, "AM3" }, 372 { X86_SOCKET_G34, "G34" }, 373 { X86_SOCKET_ASB2, "ASB2" }, 374 { X86_SOCKET_C32, "C32" }, 375 { X86_SOCKET_S1g4, "S1g4" }, 376 { X86_SOCKET_FT1, "FT1" }, 377 { X86_SOCKET_FM1, "FM1" }, 378 { X86_SOCKET_FS1, "FS1" }, 379 { X86_SOCKET_AM3R2, "AM3r2" }, 380 { X86_SOCKET_FP2, "FP2" }, 381 { X86_SOCKET_FS1R2, "FS1r2" }, 382 { X86_SOCKET_FM2, "FM2" }, 383 { X86_SOCKET_FP3, "FP3" }, 384 { X86_SOCKET_FM2R2, "FM2r2" }, 385 { X86_SOCKET_FP4, "FP4" }, 386 { X86_SOCKET_AM4, "AM4" }, 387 { X86_SOCKET_FT3, "FT3" }, 388 { X86_SOCKET_FT4, "FT4" }, 389 { X86_SOCKET_FS1B, "FS1b" }, 390 { X86_SOCKET_FT3B, "FT3b" }, 391 { X86_SOCKET_SP3, "SP3" }, 392 { X86_SOCKET_SP3R2, "SP3r2" }, 393 { X86_SOCKET_FP5, "FP5" }, 394 { X86_SOCKET_FP6, "FP6" }, 395 { X86_SOCKET_STRX4, "sTRX4" }, 396 { X86_SOCKET_SL1, "SL1" }, 397 { X86_SOCKET_SL1R2, "SL1R2" }, 398 { X86_SOCKET_DM1, "DM1" }, 399 { X86_SOCKET_SP5, "SP5" }, 400 { X86_SOCKET_AM5, "AM5" }, 401 { X86_SOCKET_FP7, "FP7" }, 402 { X86_SOCKET_FP7R2, "FP7r2" }, 403 { X86_SOCKET_FF3, "FF3" }, 404 { X86_SOCKET_FT6, "FT6" }, 405 { X86_SOCKET_FP8, "FP8" }, 406 { X86_SOCKET_FL1, "FL1" }, 407 { X86_SOCKET_SP6, "SP6" }, 408 { X86_SOCKET_TR5, "TR5" }, 409 { X86_SOCKET_UNKNOWN, "Unknown" } /* Must be last! */ 410 }; 411 412 /* Keep the array above in sync with the definitions in x86_archext.h. */ 413 CTASSERT(ARRAY_SIZE(amd_sktmap_strs) == X86_NUM_SOCKETS + 1); 414 415 /* 416 * Table for mapping AMD family/model/stepping ranges onto three derived items: 417 * 418 * * The "chiprev" and associated string, which is generally the AMD silicon 419 * revision along with a symbolic representation of the marketing (not cpuid) 420 * family. In line with the overall cpuid usage, we refer to this as a 421 * processor family. 422 * * The uarch, which is analogous to the chiprev and provides the 423 * microarchitecture/core generation and silicon revision. Note that this is 424 * distinct from the package-level silicon/product revision and is often common 425 * to multiple product lines offered at a given time. 426 * * The socket map selector, used to translate this collection of products' 427 * last 4 model bits (for family 0xf only) or Fn8000_0001_EBX[30:28] into a 428 * socket ID. 429 * 430 * The first member of this array that matches a given family, extended model 431 * plus model range, and stepping range will be considered a match. This allows 432 * us to end each cpuid family and/or processor family with a catchall that 433 * while less specific than we might like still allows us to provide a fair 434 * amount of detail to both other kernel consumers and userland. 435 */ 436 static const struct amd_rev_mapent { 437 uint_t rm_family; 438 uint_t rm_modello; 439 uint_t rm_modelhi; 440 uint_t rm_steplo; 441 uint_t rm_stephi; 442 x86_chiprev_t rm_chiprev; 443 const char *rm_chiprevstr; 444 x86_uarchrev_t rm_uarchrev; 445 uint_t rm_sktidx; 446 } amd_revmap[] = { 447 /* 448 * =============== AuthenticAMD Family 0xf =============== 449 */ 450 451 /* 452 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1. 453 */ 454 { 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_LEGACY_F_REV_B, "B", 455 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 456 { 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_LEGACY_F_REV_B, "B", 457 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 458 /* 459 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8 460 */ 461 { 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_LEGACY_F_REV_C0, "C0", 462 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 463 /* 464 * Rev CG is the rest of extended model 0x0 - i.e., everything 465 * but the rev B and C0 combinations covered above. 466 */ 467 { 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_CG, "CG", 468 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 469 /* 470 * Rev D has extended model 0x1. 471 */ 472 { 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_D, "D", 473 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 474 /* 475 * Rev E has extended model 0x2. 476 * Extended model 0x3 is unused but available to grow into. 477 */ 478 { 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_E, "E", 479 X86_UARCHREV_AMD_LEGACY, A_SKTS_0 }, 480 /* 481 * Rev F has extended models 0x4 and 0x5. 482 */ 483 { 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_F, "F", 484 X86_UARCHREV_AMD_LEGACY, A_SKTS_1 }, 485 /* 486 * Rev G has extended model 0x6. 487 */ 488 { 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_F_REV_G, "G", 489 X86_UARCHREV_AMD_LEGACY, A_SKTS_1 }, 490 491 /* 492 * =============== AuthenticAMD Family 0x10 =============== 493 */ 494 495 /* 496 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}. 497 * Give all of model 0 stepping range to rev A. 498 */ 499 { 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_LEGACY_10_REV_A, "A", 500 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 501 502 /* 503 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}. 504 * Give all of model 2 stepping range to rev B. 505 */ 506 { 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_B, "B", 507 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 508 509 /* 510 * Rev C has models 4-6 (depending on L3 cache configuration) 511 * Give all of models 4-6 stepping range 0-2 to rev C2. 512 */ 513 { 0x10, 0x4, 0x6, 0x0, 0x2, X86_CHIPREV_AMD_LEGACY_10_REV_C2, "C2", 514 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 515 516 /* 517 * Rev C has models 4-6 (depending on L3 cache configuration) 518 * Give all of models 4-6 stepping range >= 3 to rev C3. 519 */ 520 { 0x10, 0x4, 0x6, 0x3, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_C3, "C3", 521 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 522 523 /* 524 * Rev D has models 8 and 9 525 * Give all of model 8 and 9 stepping 0 to rev D0. 526 */ 527 { 0x10, 0x8, 0x9, 0x0, 0x0, X86_CHIPREV_AMD_LEGACY_10_REV_D0, "D0", 528 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 529 530 /* 531 * Rev D has models 8 and 9 532 * Give all of model 8 and 9 stepping range >= 1 to rev D1. 533 */ 534 { 0x10, 0x8, 0x9, 0x1, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_D1, "D1", 535 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 536 537 /* 538 * Rev E has models A and stepping 0 539 * Give all of model A stepping range to rev E. 540 */ 541 { 0x10, 0xA, 0xA, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_REV_E, "E", 542 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 543 544 { 0x10, 0x0, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_10_UNKNOWN, "??", 545 X86_UARCHREV_AMD_LEGACY, A_SKTS_2 }, 546 547 /* 548 * =============== AuthenticAMD Family 0x11 =============== 549 */ 550 { 0x11, 0x03, 0x03, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_11_REV_B, "B", 551 X86_UARCHREV_AMD_LEGACY, A_SKTS_3 }, 552 { 0x11, 0x00, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_11_UNKNOWN, "??", 553 X86_UARCHREV_AMD_LEGACY, A_SKTS_3 }, 554 555 /* 556 * =============== AuthenticAMD Family 0x12 =============== 557 */ 558 { 0x12, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_12_REV_B, "B", 559 X86_UARCHREV_AMD_LEGACY, A_SKTS_4 }, 560 { 0x12, 0x00, 0x00, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_12_UNKNOWN, "??", 561 X86_UARCHREV_AMD_LEGACY, A_SKTS_4 }, 562 563 /* 564 * =============== AuthenticAMD Family 0x14 =============== 565 */ 566 { 0x14, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_REV_B, "B", 567 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 }, 568 { 0x14, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_REV_C, "C", 569 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 }, 570 { 0x14, 0x00, 0xff, 0x0, 0xf, X86_CHIPREV_AMD_LEGACY_14_UNKNOWN, "??", 571 X86_UARCHREV_AMD_LEGACY, A_SKTS_5 }, 572 573 /* 574 * =============== AuthenticAMD Family 0x15 =============== 575 */ 576 { 0x15, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_OROCHI_REV_B2, "OR-B2", 577 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 }, 578 { 0x15, 0x02, 0x02, 0x0, 0x0, X86_CHIPREV_AMD_OROCHI_REV_C0, "OR-C0", 579 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 }, 580 { 0x15, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_OROCHI_UNKNOWN, "OR-??", 581 X86_UARCHREV_AMD_LEGACY, A_SKTS_6 }, 582 583 { 0x15, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_TRINITY_REV_A1, "TN-A1", 584 X86_UARCHREV_AMD_LEGACY, A_SKTS_7 }, 585 { 0x15, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_TRINITY_UNKNOWN, "TN-??", 586 X86_UARCHREV_AMD_LEGACY, A_SKTS_7 }, 587 588 { 0x15, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_KAVERI_REV_A1, "KV-A1", 589 X86_UARCHREV_AMD_LEGACY, A_SKTS_8 }, 590 { 0x15, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_KAVERI_UNKNOWN, "KV-??", 591 X86_UARCHREV_AMD_LEGACY, A_SKTS_8 }, 592 593 /* 594 * The Carrizo rev guide mentions A0 as having an ID of "00600F00h" but 595 * this appears to be a typo as elsewhere it's given as "00660F00h". We 596 * assume the latter is correct. 597 */ 598 { 0x15, 0x60, 0x60, 0x0, 0x0, X86_CHIPREV_AMD_CARRIZO_REV_A0, "CZ-A0", 599 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 }, 600 { 0x15, 0x60, 0x60, 0x1, 0x1, X86_CHIPREV_AMD_CARRIZO_REV_A1, "CZ-A1", 601 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 }, 602 /* 603 * CZ-DDR4 and BR-A1 are indistinguishable via cpuid; the rev guide 604 * indicates that they should be distinguished by the contents of the 605 * OSVW MSR, but this register is just a software scratch space which 606 * means the actual method of distinguishing the two is not documented 607 * and on PCs will be done by a BIOS. In the extremely unlikely event 608 * it becomes necessary to distinguish these, an OSVW-driven fixup can 609 * be added. 610 */ 611 { 0x15, 0x65, 0x65, 0x1, 0x1, X86_CHIPREV_AMD_CARRIZO_REV_DDR4, 612 "CZ-DDR4", X86_UARCHREV_AMD_LEGACY, A_SKTS_9 }, 613 { 0x15, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_CARRIZO_UNKNOWN, "CZ-??", 614 X86_UARCHREV_AMD_LEGACY, A_SKTS_9 }, 615 616 { 0x15, 0x70, 0x70, 0x0, 0x0, X86_CHIPREV_AMD_STONEY_RIDGE_REV_A0, 617 "ST-A0", X86_UARCHREV_AMD_LEGACY, A_SKTS_10 }, 618 { 0x15, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_STONEY_RIDGE_UNKNOWN, 619 "ST-??", X86_UARCHREV_AMD_LEGACY, A_SKTS_10 }, 620 621 /* 622 * =============== AuthenticAMD Family 0x16 =============== 623 */ 624 { 0x16, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_AMD_KABINI_A1, "KB-A1", 625 X86_UARCHREV_AMD_LEGACY, A_SKTS_11 }, 626 { 0x16, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_KABINI_UNKNOWN, "KB-??", 627 X86_UARCHREV_AMD_LEGACY, A_SKTS_11 }, 628 629 { 0x16, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_MULLINS_A1, "ML-A1", 630 X86_UARCHREV_AMD_LEGACY, A_SKTS_12 }, 631 { 0x16, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_MULLINS_UNKNOWN, "ML-??", 632 X86_UARCHREV_AMD_LEGACY, A_SKTS_12 }, 633 634 /* 635 * =============== AuthenticAMD Family 0x17 =============== 636 */ 637 /* Naples == Zeppelin == ZP */ 638 { 0x17, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_NAPLES_A0, "ZP-A0", 639 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES }, 640 { 0x17, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_NAPLES_B1, "ZP-B1", 641 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES }, 642 { 0x17, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_NAPLES_B2, "ZP-B2", 643 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES }, 644 { 0x17, 0x00, 0x07, 0x0, 0xf, X86_CHIPREV_AMD_NAPLES_UNKNOWN, "ZP-??", 645 X86_UARCHREV_AMD_ZEN1, A_SKTS_NAPLES }, 646 { 0x17, 0x08, 0x08, 0x2, 0x2, X86_CHIPREV_AMD_PINNACLE_RIDGE_B2, 647 "PiR-B2", X86_UARCHREV_AMD_ZENPLUS, A_SKTS_NAPLES }, 648 { 0x17, 0x08, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_PINNACLE_RIDGE_UNKNOWN, 649 "PiR-??", X86_UARCHREV_AMD_ZENPLUS, A_SKTS_NAPLES }, 650 651 { 0x17, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_RAVEN_RIDGE_B0, 652 "RV-B0", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN }, 653 { 0x17, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_RAVEN_RIDGE_B1, 654 "RV-B1", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN }, 655 { 0x17, 0x10, 0x17, 0x0, 0xf, X86_CHIPREV_AMD_RAVEN_RIDGE_UNKNOWN, 656 "RV-??", X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN }, 657 { 0x17, 0x18, 0x18, 0x1, 0x1, X86_CHIPREV_AMD_PICASSO_B1, "PCO-B1", 658 X86_UARCHREV_AMD_ZENPLUS, A_SKTS_RAVEN }, 659 { 0x17, 0x18, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_PICASSO_UNKNOWN, "PCO-??", 660 X86_UARCHREV_AMD_ZENPLUS, A_SKTS_RAVEN }, 661 662 { 0x17, 0x20, 0x20, 0x1, 0x1, X86_CHIPREV_AMD_DALI_A1, "RV2X-A1", 663 X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN }, 664 { 0x17, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_DALI_UNKNOWN, "RV2X-??", 665 X86_UARCHREV_AMD_ZEN1, A_SKTS_RAVEN }, 666 667 /* Rome == Starship == SSP */ 668 { 0x17, 0x30, 0x30, 0x0, 0x0, X86_CHIPREV_AMD_ROME_A0, "SSP-A0", 669 X86_UARCHREV_AMD_ZEN2_A0, A_SKTS_ROME }, 670 { 0x17, 0x31, 0x31, 0x0, 0x0, X86_CHIPREV_AMD_ROME_B0, "SSP-B0", 671 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_ROME }, 672 { 0x17, 0x30, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_ROME_UNKNOWN, "SSP-??", 673 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_ROME }, 674 675 { 0x17, 0x60, 0x60, 0x1, 0x1, X86_CHIPREV_AMD_RENOIR_A1, "RN-A1", 676 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_RENOIR }, 677 { 0x17, 0x60, 0x67, 0x0, 0xf, X86_CHIPREV_AMD_RENOIR_UNKNOWN, "RN-??", 678 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_RENOIR }, 679 { 0x17, 0x68, 0x68, 0x1, 0x1, X86_CHIPREV_AMD_RENOIR_LCN_A1, "LCN-A1", 680 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_RENOIR }, 681 { 0x17, 0x68, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_RENOIR_UNKNOWN, "LCN-??", 682 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_RENOIR }, 683 684 { 0x17, 0x71, 0x71, 0x0, 0x0, X86_CHIPREV_AMD_MATISSE_B0, "MTS-B0", 685 X86_UARCHREV_AMD_ZEN2_B0, A_SKTS_MATISSE }, 686 { 0x17, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_MATISSE_UNKNOWN, "MTS-??", 687 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_MATISSE }, 688 689 { 0x17, 0x90, 0x97, 0x0, 0xf, X86_CHIPREV_AMD_VAN_GOGH_UNKNOWN, "??", 690 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_VANGOGH }, 691 { 0x17, 0x98, 0x9f, 0x0, 0xf, X86_CHIPREV_AMD_VAN_GOGH_UNKNOWN, "??", 692 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_UNKNOWN }, 693 694 { 0x17, 0xa0, 0xaf, 0x0, 0xf, X86_CHIPREV_AMD_MENDOCINO_UNKNOWN, "??", 695 X86_UARCHREV_AMD_ZEN2_UNKNOWN, A_SKTS_MENDOCINO }, 696 697 /* 698 * =============== HygonGenuine Family 0x18 =============== 699 */ 700 { 0x18, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_HYGON_DHYANA_A1, "DN_A1", 701 X86_UARCHREV_AMD_ZEN1, A_SKTS_DHYANA }, 702 { 0x18, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_HYGON_DHYANA_UNKNOWN, "DN_??", 703 X86_UARCHREV_AMD_ZEN1, A_SKTS_DHYANA }, 704 705 /* 706 * =============== AuthenticAMD Family 0x19 =============== 707 */ 708 /* Milan == Genesis == GN */ 709 { 0x19, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_MILAN_A0, "GN-A0", 710 X86_UARCHREV_AMD_ZEN3_A0, A_SKTS_MILAN }, 711 { 0x19, 0x01, 0x01, 0x0, 0x0, X86_CHIPREV_AMD_MILAN_B0, "GN-B0", 712 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_MILAN }, 713 { 0x19, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_MILAN_B1, "GN-B1", 714 X86_UARCHREV_AMD_ZEN3_B1, A_SKTS_MILAN }, 715 /* Marketed as Milan-X but still GN */ 716 { 0x19, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_MILAN_B2, "GN-B2", 717 X86_UARCHREV_AMD_ZEN3_B2, A_SKTS_MILAN }, 718 { 0x19, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_MILAN_UNKNOWN, "GN-??", 719 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_MILAN }, 720 721 /* Genoa == Stones == RS */ 722 { 0x19, 0x10, 0x10, 0x0, 0x0, X86_CHIPREV_AMD_GENOA_A0, "RS-A0", 723 X86_UARCHREV_AMD_ZEN4, A_SKTS_GENOA }, 724 { 0x19, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_GENOA_A1, "RS-A1", 725 X86_UARCHREV_AMD_ZEN4, A_SKTS_GENOA }, 726 { 0x19, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_GENOA_B0, "RS-B0", 727 X86_UARCHREV_AMD_ZEN4, A_SKTS_GENOA }, 728 { 0x19, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_GENOA_B1, "RS-B1", 729 X86_UARCHREV_AMD_ZEN4, A_SKTS_GENOA }, 730 { 0x19, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_GENOA_UNKNOWN, "RS-??", 731 X86_UARCHREV_AMD_ZEN4, A_SKTS_GENOA }, 732 733 { 0x19, 0x20, 0x20, 0x0, 0x0, X86_CHIPREV_AMD_VERMEER_A0, "VMR-A0", 734 X86_UARCHREV_AMD_ZEN3_A0, A_SKTS_VERMEER }, 735 { 0x19, 0x21, 0x21, 0x0, 0x0, X86_CHIPREV_AMD_VERMEER_B0, "VMR-B0", 736 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_VERMEER }, 737 { 0x19, 0x21, 0x21, 0x2, 0x2, X86_CHIPREV_AMD_VERMEER_B2, "VMR-B2", 738 X86_UARCHREV_AMD_ZEN3_B2, A_SKTS_VERMEER }, 739 { 0x19, 0x20, 0x2f, 0x0, 0xf, X86_CHIPREV_AMD_VERMEER_UNKNOWN, "VMR-??", 740 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_VERMEER }, 741 742 /* Rev guide is missing AM5 information, including A0 and B0 */ 743 { 0x19, 0x40, 0x40, 0x0, 0x0, X86_CHIPREV_AMD_REMBRANDT_A0, "RMB-A0", 744 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT }, 745 { 0x19, 0x44, 0x44, 0x0, 0x0, X86_CHIPREV_AMD_REMBRANDT_B0, "RMB-B0", 746 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT }, 747 { 0x19, 0x44, 0x44, 0x1, 0x1, X86_CHIPREV_AMD_REMBRANDT_B1, "RMB-B1", 748 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_REMBRANDT }, 749 { 0x19, 0x40, 0x4f, 0x0, 0xf, X86_CHIPREV_AMD_REMBRANDT_UNKNOWN, 750 "RMB-??", X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_REMBRANDT }, 751 752 /* Cezanne */ 753 { 0x19, 0x50, 0x50, 0x0, 0x0, X86_CHIPREV_AMD_CEZANNE_A0, "CZN-A0", 754 X86_UARCHREV_AMD_ZEN3_B0, A_SKTS_CEZANNE }, 755 { 0x19, 0x50, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_CEZANNE_UNKNOWN, "CZN-??", 756 X86_UARCHREV_AMD_ZEN3_UNKNOWN, A_SKTS_CEZANNE }, 757 758 /* Raphael */ 759 { 0x19, 0x61, 0x61, 0x2, 0x2, X86_CHIPREV_AMD_RAPHAEL_B2, "RPL-B2", 760 X86_UARCHREV_AMD_ZEN4, A_SKTS_RAPHAEL }, 761 { 0x19, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_RAPHAEL_UNKNOWN, "RPL-??", 762 X86_UARCHREV_AMD_ZEN4, A_SKTS_RAPHAEL }, 763 764 /* Phoenix */ 765 { 0x19, 0x74, 0x74, 0x1, 0x1, X86_CHIPREV_AMD_PHOENIX_A1, "PHX-A1", 766 X86_UARCHREV_AMD_ZEN4, A_SKTS_PHOENIX }, 767 { 0x19, 0x70, 0x7f, 0x0, 0xf, X86_CHIPREV_AMD_PHOENIX_UNKNOWN, "PHX-??", 768 X86_UARCHREV_AMD_ZEN4, A_SKTS_PHOENIX }, 769 770 /* Bergamo / Siena */ 771 { 0x19, 0xa0, 0xaf, 0x0, 0x0, X86_CHIPREV_AMD_BERGAMO_A0, "RSDN-A0", 772 X86_UARCHREV_AMD_ZEN4, A_SKTS_BERGAMO }, 773 { 0x19, 0xa0, 0xaf, 0x1, 0x1, X86_CHIPREV_AMD_BERGAMO_A1, "RSDN-A1", 774 X86_UARCHREV_AMD_ZEN4, A_SKTS_BERGAMO }, 775 { 0x19, 0xa0, 0xaf, 0x2, 0x2, X86_CHIPREV_AMD_BERGAMO_A2, "RSDN-A2", 776 X86_UARCHREV_AMD_ZEN4, A_SKTS_BERGAMO }, 777 { 0x19, 0xa0, 0xaf, 0x0, 0xf, X86_CHIPREV_AMD_BERGAMO_UNKNOWN, "???", 778 X86_UARCHREV_AMD_ZEN4, A_SKTS_BERGAMO } 779 }; 780 781 /* 782 * AMD keeps the socket type in CPUID Fn8000_0001_EBX, bits 31:28. 783 */ 784 static uint32_t 785 synth_amd_skt_cpuid(uint_t family, uint_t sktid) 786 { 787 struct cpuid_regs cp; 788 uint_t idx; 789 790 cp.cp_eax = 0x80000001; 791 (void) __cpuid_insn(&cp); 792 793 /* PkgType bits */ 794 idx = BITX(cp.cp_ebx, 31, 28); 795 796 if (family == 0x10) { 797 uint32_t val; 798 799 val = pci_getl_func(0, 24, 2, 0x94); 800 if (BITX(val, 8, 8)) { 801 if (amd_skts[sktid][idx] == X86_SOCKET_AM2R2) { 802 return (X86_SOCKET_AM3); 803 } else if (amd_skts[sktid][idx] == X86_SOCKET_S1g3) { 804 return (X86_SOCKET_S1g4); 805 } 806 } 807 } 808 809 return (amd_skts[sktid][idx]); 810 } 811 812 static void 813 synth_amd_info(uint_t family, uint_t model, uint_t step, 814 uint32_t *skt_p, x86_chiprev_t *chiprev_p, const char **chiprevstr_p, 815 x86_uarchrev_t *uarchrev_p) 816 { 817 const struct amd_rev_mapent *rmp; 818 int found = 0; 819 int i; 820 821 if (family < 0xf) 822 return; 823 824 for (i = 0, rmp = amd_revmap; i < ARRAY_SIZE(amd_revmap); i++, rmp++) { 825 if (family == rmp->rm_family && 826 model >= rmp->rm_modello && model <= rmp->rm_modelhi && 827 step >= rmp->rm_steplo && step <= rmp->rm_stephi) { 828 found = 1; 829 break; 830 } 831 } 832 833 if (found) { 834 if (chiprev_p != NULL) 835 *chiprev_p = rmp->rm_chiprev; 836 if (chiprevstr_p != NULL) 837 *chiprevstr_p = rmp->rm_chiprevstr; 838 if (uarchrev_p != NULL) 839 *uarchrev_p = rmp->rm_uarchrev; 840 } 841 842 if (skt_p != NULL) { 843 int platform; 844 845 #ifdef __xpv 846 /* PV guest */ 847 if (!is_controldom()) { 848 *skt_p = X86_SOCKET_UNKNOWN; 849 return; 850 } 851 #endif 852 platform = get_hwenv(); 853 854 if ((platform & HW_VIRTUAL) != 0) { 855 *skt_p = X86_SOCKET_UNKNOWN; 856 return; 857 } 858 859 if (!found) 860 return; 861 862 if (family == 0xf) { 863 *skt_p = amd_skts[rmp->rm_sktidx][model & 0x3]; 864 } else { 865 *skt_p = synth_amd_skt_cpuid(family, rmp->rm_sktidx); 866 } 867 } 868 } 869 870 uint32_t 871 _cpuid_skt(uint_t vendor, uint_t family, uint_t model, uint_t step) 872 { 873 uint32_t skt = X86_SOCKET_UNKNOWN; 874 875 switch (vendor) { 876 case X86_VENDOR_AMD: 877 case X86_VENDOR_HYGON: 878 synth_amd_info(family, model, step, &skt, NULL, NULL, NULL); 879 break; 880 881 default: 882 break; 883 884 } 885 886 return (skt); 887 } 888 889 const char * 890 _cpuid_sktstr(uint_t vendor, uint_t family, uint_t model, uint_t step) 891 { 892 const char *sktstr = "Unknown"; 893 struct amd_sktmap_s *sktmapp; 894 uint32_t skt = X86_SOCKET_UNKNOWN; 895 896 switch (vendor) { 897 case X86_VENDOR_AMD: 898 case X86_VENDOR_HYGON: 899 synth_amd_info(family, model, step, &skt, NULL, NULL, NULL); 900 901 sktmapp = amd_sktmap_strs; 902 while (sktmapp->skt_code != X86_SOCKET_UNKNOWN) { 903 if (sktmapp->skt_code == skt) 904 break; 905 sktmapp++; 906 } 907 sktstr = sktmapp->sktstr; 908 break; 909 910 default: 911 break; 912 913 } 914 915 return (sktstr); 916 } 917 918 x86_chiprev_t 919 _cpuid_chiprev(uint_t vendor, uint_t family, uint_t model, uint_t step) 920 { 921 x86_chiprev_t chiprev = X86_CHIPREV_UNKNOWN; 922 923 switch (vendor) { 924 case X86_VENDOR_AMD: 925 case X86_VENDOR_HYGON: 926 synth_amd_info(family, model, step, NULL, &chiprev, NULL, NULL); 927 break; 928 929 default: 930 break; 931 932 } 933 934 return (chiprev); 935 } 936 937 x86_uarchrev_t 938 _cpuid_uarchrev(uint_t vendor, uint_t family, uint_t model, uint_t step) 939 { 940 x86_uarchrev_t uarchrev = X86_UARCHREV_UNKNOWN; 941 942 switch (vendor) { 943 case X86_VENDOR_AMD: 944 case X86_VENDOR_HYGON: 945 synth_amd_info(family, model, step, NULL, NULL, NULL, 946 &uarchrev); 947 break; 948 949 default: 950 break; 951 952 } 953 954 return (uarchrev); 955 } 956 957 const char * 958 _cpuid_chiprevstr(uint_t vendor, uint_t family, uint_t model, uint_t step) 959 { 960 const char *revstr = "Unknown"; 961 962 switch (vendor) { 963 case X86_VENDOR_AMD: 964 case X86_VENDOR_HYGON: 965 synth_amd_info(family, model, step, NULL, NULL, &revstr, NULL); 966 break; 967 968 default: 969 break; 970 971 } 972 973 return (revstr); 974 975 } 976 977 /* 978 * Map the vendor string to a type code 979 */ 980 uint_t 981 _cpuid_vendorstr_to_vendorcode(char *vendorstr) 982 { 983 if (strcmp(vendorstr, X86_VENDORSTR_Intel) == 0) 984 return (X86_VENDOR_Intel); 985 else if (strcmp(vendorstr, X86_VENDORSTR_AMD) == 0) 986 return (X86_VENDOR_AMD); 987 else if (strcmp(vendorstr, X86_VENDORSTR_HYGON) == 0) 988 return (X86_VENDOR_HYGON); 989 else if (strcmp(vendorstr, X86_VENDORSTR_TM) == 0) 990 return (X86_VENDOR_TM); 991 else if (strcmp(vendorstr, X86_VENDORSTR_CYRIX) == 0) 992 return (X86_VENDOR_Cyrix); 993 else if (strcmp(vendorstr, X86_VENDORSTR_UMC) == 0) 994 return (X86_VENDOR_UMC); 995 else if (strcmp(vendorstr, X86_VENDORSTR_NexGen) == 0) 996 return (X86_VENDOR_NexGen); 997 else if (strcmp(vendorstr, X86_VENDORSTR_Centaur) == 0) 998 return (X86_VENDOR_Centaur); 999 else if (strcmp(vendorstr, X86_VENDORSTR_Rise) == 0) 1000 return (X86_VENDOR_Rise); 1001 else if (strcmp(vendorstr, X86_VENDORSTR_SiS) == 0) 1002 return (X86_VENDOR_SiS); 1003 else if (strcmp(vendorstr, X86_VENDORSTR_NSC) == 0) 1004 return (X86_VENDOR_NSC); 1005 else 1006 return (X86_VENDOR_IntelClone); 1007 } 1008