1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2018 Joyent, Inc. 42 * Copyright 2020 Oxide Computer Company 43 */ 44 45 #include <sys/cdefs.h> 46 __FBSDID("$FreeBSD$"); 47 48 #include <sys/param.h> 49 #include <sys/pcpu.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/x86_archext.h> 53 54 #include <machine/clock.h> 55 #include <machine/cpufunc.h> 56 #include <machine/md_var.h> 57 #include <machine/segments.h> 58 #include <machine/specialreg.h> 59 60 #include <machine/vmm.h> 61 62 #include "vmm_host.h" 63 #include "vmm_util.h" 64 #include "x86.h" 65 66 SYSCTL_DECL(_hw_vmm); 67 68 #define CPUID_VM_HIGH 0x40000000 69 70 static const char bhyve_id[12] = "bhyve bhyve "; 71 72 /* Number of times an unknown cpuid leaf was accessed */ 73 static uint64_t bhyve_xcpuids; 74 75 static int cpuid_leaf_b = 1; 76 77 /* 78 * Force exposition of the invariant TSC capability, regardless of whether the 79 * host CPU reports having it. 80 */ 81 static int vmm_force_invariant_tsc = 0; 82 83 /* 84 * Round up to the next power of two, if necessary, and then take log2. 85 * Returns -1 if argument is zero. 86 */ 87 static __inline int 88 log2(uint_t x) 89 { 90 91 return (fls(x << (1 - powerof2(x))) - 1); 92 } 93 94 int 95 x86_emulate_cpuid(struct vm *vm, int vcpu_id, uint64_t *rax, uint64_t *rbx, 96 uint64_t *rcx, uint64_t *rdx) 97 { 98 const struct xsave_limits *limits; 99 uint64_t cr4; 100 int error, enable_invpcid, level, width = 0, x2apic_id = 0; 101 unsigned int func, regs[4], logical_cpus = 0, param; 102 enum x2apic_state x2apic_state; 103 uint16_t cores, maxcpus, sockets, threads; 104 105 /* 106 * The function of CPUID is controlled through the provided value of 107 * %eax (and secondarily %ecx, for certain leaf data). 108 */ 109 func = (uint32_t)*rax; 110 param = (uint32_t)*rcx; 111 112 /* 113 * Requests for invalid CPUID levels should map to the highest 114 * available level instead. 115 */ 116 if (cpu_exthigh != 0 && func >= 0x80000000) { 117 if (func > cpu_exthigh) 118 func = cpu_exthigh; 119 } else if (func >= 0x40000000) { 120 if (func > CPUID_VM_HIGH) 121 func = CPUID_VM_HIGH; 122 } else if (func > cpu_high) { 123 func = cpu_high; 124 } 125 126 /* 127 * In general the approach used for CPU topology is to 128 * advertise a flat topology where all CPUs are packages with 129 * no multi-core or SMT. 130 */ 131 switch (func) { 132 /* 133 * Pass these through to the guest 134 */ 135 case CPUID_0000_0000: 136 case CPUID_0000_0002: 137 case CPUID_0000_0003: 138 case CPUID_8000_0000: 139 case CPUID_8000_0002: 140 case CPUID_8000_0003: 141 case CPUID_8000_0004: 142 case CPUID_8000_0006: 143 cpuid_count(func, param, regs); 144 break; 145 case CPUID_8000_0008: 146 cpuid_count(func, param, regs); 147 if (vmm_is_svm()) { 148 /* 149 * As on Intel (0000_0007:0, EDX), mask out 150 * unsupported or unsafe AMD extended features 151 * (8000_0008 EBX). 152 */ 153 regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF | 154 AMDFEID_XSAVEERPTR); 155 156 vm_get_topology(vm, &sockets, &cores, &threads, 157 &maxcpus); 158 /* 159 * Here, width is ApicIdCoreIdSize, present on 160 * at least Family 15h and newer. It 161 * represents the "number of bits in the 162 * initial apicid that indicate thread id 163 * within a package." 164 * 165 * Our topo_probe_amd() uses it for 166 * pkg_id_shift and other OSes may rely on it. 167 */ 168 width = MIN(0xF, log2(threads * cores)); 169 if (width < 0x4) 170 width = 0; 171 logical_cpus = MIN(0xFF, threads * cores - 1); 172 regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | 173 logical_cpus; 174 } 175 break; 176 177 case CPUID_8000_0001: 178 cpuid_count(func, param, regs); 179 180 /* 181 * Hide SVM from guest. 182 */ 183 regs[2] &= ~AMDID2_SVM; 184 185 /* 186 * Don't advertise extended performance counter MSRs 187 * to the guest. 188 */ 189 regs[2] &= ~AMDID2_PCXC; 190 regs[2] &= ~AMDID2_PNXC; 191 regs[2] &= ~AMDID2_PTSCEL2I; 192 193 /* 194 * Don't advertise Instruction Based Sampling feature. 195 */ 196 regs[2] &= ~AMDID2_IBS; 197 198 /* NodeID MSR not available */ 199 regs[2] &= ~AMDID2_NODE_ID; 200 201 /* Don't advertise the OS visible workaround feature */ 202 regs[2] &= ~AMDID2_OSVW; 203 204 /* Hide mwaitx/monitorx capability from the guest */ 205 regs[2] &= ~AMDID2_MWAITX; 206 207 #ifndef __FreeBSD__ 208 /* 209 * Detection routines for TCE and FFXSR are missing 210 * from our vm_cpuid_capability() detection logic 211 * today. Mask them out until that is remedied. 212 * They do not appear to be in common usage, so their 213 * absence should not cause undue trouble. 214 */ 215 regs[2] &= ~AMDID2_TCE; 216 regs[3] &= ~AMDID_FFXSR; 217 #endif 218 219 /* 220 * Hide rdtscp/ia32_tsc_aux until we know how 221 * to deal with them. 222 */ 223 regs[3] &= ~AMDID_RDTSCP; 224 break; 225 226 case CPUID_8000_0007: 227 cpuid_count(func, param, regs); 228 /* 229 * AMD uses this leaf to advertise the processor's 230 * power monitoring and RAS capabilities. These 231 * features are hardware-specific and exposing 232 * them to a guest doesn't make a lot of sense. 233 * 234 * Intel uses this leaf only to advertise the 235 * "Invariant TSC" feature with all other bits 236 * being reserved (set to zero). 237 */ 238 regs[0] = 0; 239 regs[1] = 0; 240 regs[2] = 0; 241 242 /* 243 * If the host system possesses an invariant TSC, then 244 * it is safe to expose to the guest. 245 * 246 * If there is measured skew between host TSCs, it will 247 * be properly offset so guests do not observe any 248 * change between CPU migrations. 249 */ 250 regs[3] &= AMDPM_TSC_INVARIANT; 251 252 /* 253 * Since illumos avoids deep C-states on CPUs which do 254 * not support an invariant TSC, it may be safe (and 255 * desired) to unconditionally expose that capability to 256 * the guest. 257 */ 258 if (vmm_force_invariant_tsc != 0) { 259 regs[3] |= AMDPM_TSC_INVARIANT; 260 } 261 break; 262 263 case CPUID_8000_001D: 264 /* AMD Cache topology, like 0000_0004 for Intel. */ 265 if (!vmm_is_svm()) 266 goto default_leaf; 267 268 /* 269 * Similar to Intel, generate a ficticious cache 270 * topology for the guest with L3 shared by the 271 * package, and L1 and L2 local to a core. 272 */ 273 vm_get_topology(vm, &sockets, &cores, &threads, 274 &maxcpus); 275 switch (param) { 276 case 0: 277 logical_cpus = threads; 278 level = 1; 279 func = 1; /* data cache */ 280 break; 281 case 1: 282 logical_cpus = threads; 283 level = 2; 284 func = 3; /* unified cache */ 285 break; 286 case 2: 287 logical_cpus = threads * cores; 288 level = 3; 289 func = 3; /* unified cache */ 290 break; 291 default: 292 logical_cpus = 0; 293 level = 0; 294 func = 0; 295 break; 296 } 297 298 logical_cpus = MIN(0xfff, logical_cpus - 1); 299 regs[0] = (logical_cpus << 14) | (1 << 8) | 300 (level << 5) | func; 301 regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0; 302 regs[2] = 0; 303 regs[3] = 0; 304 break; 305 306 case CPUID_8000_001E: 307 /* 308 * AMD Family 16h+ and Hygon Family 18h additional 309 * identifiers. 310 */ 311 if (!vmm_is_svm() || CPUID_TO_FAMILY(cpu_id) < 0x16) 312 goto default_leaf; 313 314 vm_get_topology(vm, &sockets, &cores, &threads, 315 &maxcpus); 316 regs[0] = vcpu_id; 317 threads = MIN(0xFF, threads - 1); 318 regs[1] = (threads << 8) | 319 (vcpu_id >> log2(threads + 1)); 320 /* 321 * XXX Bhyve topology cannot yet represent >1 node per 322 * processor. 323 */ 324 regs[2] = 0; 325 regs[3] = 0; 326 break; 327 328 case CPUID_0000_0001: 329 do_cpuid(1, regs); 330 331 error = vm_get_x2apic_state(vm, vcpu_id, &x2apic_state); 332 if (error) { 333 panic("x86_emulate_cpuid: error %d " 334 "fetching x2apic state", error); 335 } 336 337 /* 338 * Override the APIC ID only in ebx 339 */ 340 regs[1] &= ~(CPUID_LOCAL_APIC_ID); 341 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT); 342 343 /* 344 * Don't expose VMX, SpeedStep, TME or SMX capability. 345 * Advertise x2APIC capability and Hypervisor guest. 346 */ 347 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2); 348 regs[2] &= ~(CPUID2_SMX); 349 350 regs[2] |= CPUID2_HV; 351 352 if (x2apic_state != X2APIC_DISABLED) 353 regs[2] |= CPUID2_X2APIC; 354 else 355 regs[2] &= ~CPUID2_X2APIC; 356 357 /* 358 * Only advertise CPUID2_XSAVE in the guest if 359 * the host is using XSAVE. 360 */ 361 if (!(regs[2] & CPUID2_OSXSAVE)) 362 regs[2] &= ~CPUID2_XSAVE; 363 364 /* 365 * If CPUID2_XSAVE is being advertised and the 366 * guest has set CR4_XSAVE, set 367 * CPUID2_OSXSAVE. 368 */ 369 regs[2] &= ~CPUID2_OSXSAVE; 370 if (regs[2] & CPUID2_XSAVE) { 371 error = vm_get_register(vm, vcpu_id, 372 VM_REG_GUEST_CR4, &cr4); 373 if (error) 374 panic("x86_emulate_cpuid: error %d " 375 "fetching %%cr4", error); 376 if (cr4 & CR4_XSAVE) 377 regs[2] |= CPUID2_OSXSAVE; 378 } 379 380 /* 381 * Hide monitor/mwait until we know how to deal with 382 * these instructions. 383 */ 384 regs[2] &= ~CPUID2_MON; 385 386 /* 387 * Hide the performance and debug features. 388 */ 389 regs[2] &= ~CPUID2_PDCM; 390 391 /* 392 * No TSC deadline support in the APIC yet 393 */ 394 regs[2] &= ~CPUID2_TSCDLT; 395 396 /* 397 * Hide thermal monitoring 398 */ 399 regs[3] &= ~(CPUID_ACPI | CPUID_TM); 400 401 /* 402 * Hide the debug store capability. 403 */ 404 regs[3] &= ~CPUID_DS; 405 406 /* 407 * Advertise the Machine Check and MTRR capability. 408 * 409 * Some guest OSes (e.g. Windows) will not boot if 410 * these features are absent. 411 */ 412 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR); 413 414 vm_get_topology(vm, &sockets, &cores, &threads, 415 &maxcpus); 416 logical_cpus = threads * cores; 417 regs[1] &= ~CPUID_HTT_CORES; 418 regs[1] |= (logical_cpus & 0xff) << 16; 419 regs[3] |= CPUID_HTT; 420 break; 421 422 case CPUID_0000_0004: 423 cpuid_count(func, param, regs); 424 425 if (regs[0] || regs[1] || regs[2] || regs[3]) { 426 vm_get_topology(vm, &sockets, &cores, &threads, 427 &maxcpus); 428 regs[0] &= 0x3ff; 429 regs[0] |= (cores - 1) << 26; 430 /* 431 * Cache topology: 432 * - L1 and L2 are shared only by the logical 433 * processors in a single core. 434 * - L3 and above are shared by all logical 435 * processors in the package. 436 */ 437 logical_cpus = threads; 438 level = (regs[0] >> 5) & 0x7; 439 if (level >= 3) 440 logical_cpus *= cores; 441 regs[0] |= (logical_cpus - 1) << 14; 442 } 443 break; 444 445 case CPUID_0000_0007: 446 regs[0] = 0; 447 regs[1] = 0; 448 regs[2] = 0; 449 regs[3] = 0; 450 451 /* leaf 0 */ 452 if (param == 0) { 453 cpuid_count(func, param, regs); 454 455 /* Only leaf 0 is supported */ 456 regs[0] = 0; 457 458 /* 459 * Expose known-safe features. 460 */ 461 regs[1] &= (CPUID_STDEXT_FSGSBASE | 462 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE | 463 CPUID_STDEXT_AVX2 | CPUID_STDEXT_SMEP | 464 CPUID_STDEXT_BMI2 | 465 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM | 466 CPUID_STDEXT_AVX512F | 467 CPUID_STDEXT_RDSEED | 468 CPUID_STDEXT_SMAP | 469 CPUID_STDEXT_AVX512PF | 470 CPUID_STDEXT_AVX512ER | 471 CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA); 472 regs[2] = 0; 473 regs[3] &= CPUID_STDEXT3_MD_CLEAR; 474 475 /* Advertise INVPCID if it is enabled. */ 476 error = vm_get_capability(vm, vcpu_id, 477 VM_CAP_ENABLE_INVPCID, &enable_invpcid); 478 if (error == 0 && enable_invpcid) 479 regs[1] |= CPUID_STDEXT_INVPCID; 480 } 481 break; 482 483 case CPUID_0000_0006: 484 regs[0] = CPUTPM1_ARAT; 485 regs[1] = 0; 486 regs[2] = 0; 487 regs[3] = 0; 488 break; 489 490 case CPUID_0000_000A: 491 /* 492 * Handle the access, but report 0 for 493 * all options 494 */ 495 regs[0] = 0; 496 regs[1] = 0; 497 regs[2] = 0; 498 regs[3] = 0; 499 break; 500 501 case CPUID_0000_000B: 502 /* 503 * Intel processor topology enumeration 504 */ 505 if (vmm_is_intel()) { 506 vm_get_topology(vm, &sockets, &cores, &threads, 507 &maxcpus); 508 if (param == 0) { 509 logical_cpus = threads; 510 width = log2(logical_cpus); 511 level = CPUID_TYPE_SMT; 512 x2apic_id = vcpu_id; 513 } 514 515 if (param == 1) { 516 logical_cpus = threads * cores; 517 width = log2(logical_cpus); 518 level = CPUID_TYPE_CORE; 519 x2apic_id = vcpu_id; 520 } 521 522 if (!cpuid_leaf_b || param >= 2) { 523 width = 0; 524 logical_cpus = 0; 525 level = 0; 526 x2apic_id = 0; 527 } 528 529 regs[0] = width & 0x1f; 530 regs[1] = logical_cpus & 0xffff; 531 regs[2] = (level << 8) | (param & 0xff); 532 regs[3] = x2apic_id; 533 } else { 534 regs[0] = 0; 535 regs[1] = 0; 536 regs[2] = 0; 537 regs[3] = 0; 538 } 539 break; 540 541 case CPUID_0000_000D: 542 limits = vmm_get_xsave_limits(); 543 if (!limits->xsave_enabled) { 544 regs[0] = 0; 545 regs[1] = 0; 546 regs[2] = 0; 547 regs[3] = 0; 548 break; 549 } 550 551 cpuid_count(func, param, regs); 552 switch (param) { 553 case 0: 554 /* 555 * Only permit the guest to use bits 556 * that are active in the host in 557 * %xcr0. Also, claim that the 558 * maximum save area size is 559 * equivalent to the host's current 560 * save area size. Since this runs 561 * "inside" of vmrun(), it runs with 562 * the guest's xcr0, so the current 563 * save area size is correct as-is. 564 */ 565 regs[0] &= limits->xcr0_allowed; 566 regs[2] = limits->xsave_max_size; 567 regs[3] &= (limits->xcr0_allowed >> 32); 568 break; 569 case 1: 570 /* Only permit XSAVEOPT. */ 571 regs[0] &= CPUID_EXTSTATE_XSAVEOPT; 572 regs[1] = 0; 573 regs[2] = 0; 574 regs[3] = 0; 575 break; 576 default: 577 /* 578 * If the leaf is for a permitted feature, 579 * pass through as-is, otherwise return 580 * all zeroes. 581 */ 582 if (!(limits->xcr0_allowed & (1ul << param))) { 583 regs[0] = 0; 584 regs[1] = 0; 585 regs[2] = 0; 586 regs[3] = 0; 587 } 588 break; 589 } 590 break; 591 592 case CPUID_0000_000F: 593 case CPUID_0000_0010: 594 /* 595 * Do not report any Resource Director Technology 596 * capabilities. Exposing control of cache or memory 597 * controller resource partitioning to the guest is not 598 * at all sensible. 599 * 600 * This is already hidden at a high level by masking of 601 * leaf 0x7. Even still, a guest may look here for 602 * detailed capability information. 603 */ 604 regs[0] = 0; 605 regs[1] = 0; 606 regs[2] = 0; 607 regs[3] = 0; 608 break; 609 610 case CPUID_0000_0015: 611 /* 612 * Don't report CPU TSC/Crystal ratio and clock 613 * values since guests may use these to derive the 614 * local APIC frequency.. 615 */ 616 regs[0] = 0; 617 regs[1] = 0; 618 regs[2] = 0; 619 regs[3] = 0; 620 break; 621 622 case 0x40000000: 623 regs[0] = CPUID_VM_HIGH; 624 bcopy(bhyve_id, ®s[1], 4); 625 bcopy(bhyve_id + 4, ®s[2], 4); 626 bcopy(bhyve_id + 8, ®s[3], 4); 627 break; 628 629 default: 630 default_leaf: 631 /* 632 * The leaf value has already been clamped so 633 * simply pass this through, keeping count of 634 * how many unhandled leaf values have been seen. 635 */ 636 atomic_add_long(&bhyve_xcpuids, 1); 637 cpuid_count(func, param, regs); 638 break; 639 } 640 641 /* 642 * CPUID clears the upper 32-bits of the long-mode registers. 643 */ 644 *rax = regs[0]; 645 *rbx = regs[1]; 646 *rcx = regs[2]; 647 *rdx = regs[3]; 648 649 return (1); 650 } 651 652 bool 653 vm_cpuid_capability(struct vm *vm, int vcpuid, enum vm_cpuid_capability cap) 654 { 655 bool rv; 656 657 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d", 658 __func__, cap)); 659 660 /* 661 * Simply passthrough the capabilities of the host cpu for now. 662 */ 663 rv = false; 664 switch (cap) { 665 #ifdef __FreeBSD__ 666 case VCC_NO_EXECUTE: 667 if (amd_feature & AMDID_NX) 668 rv = true; 669 break; 670 case VCC_FFXSR: 671 if (amd_feature & AMDID_FFXSR) 672 rv = true; 673 break; 674 case VCC_TCE: 675 if (amd_feature2 & AMDID2_TCE) 676 rv = true; 677 break; 678 #else 679 case VCC_NO_EXECUTE: 680 if (is_x86_feature(x86_featureset, X86FSET_NX)) 681 rv = true; 682 break; 683 /* XXXJOY: No kernel detection for FFXR or TCE at present, so ignore */ 684 case VCC_FFXSR: 685 case VCC_TCE: 686 break; 687 #endif 688 default: 689 panic("%s: unknown vm_cpu_capability %d", __func__, cap); 690 } 691 return (rv); 692 } 693