1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2020 Oxide Computer Company 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/cpuset.h> 50 51 #include <x86/specialreg.h> 52 #include <x86/apicreg.h> 53 54 #include <machine/vmm.h> 55 #include "vmm_lapic.h" 56 #include "vlapic.h" 57 58 /* 59 * Some MSI message definitions 60 */ 61 #define MSI_X86_ADDR_MASK 0xfff00000 62 #define MSI_X86_ADDR_BASE 0xfee00000 63 #define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */ 64 #define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */ 65 66 int 67 lapic_set_intr(struct vm *vm, int cpu, int vector, bool level) 68 { 69 struct vlapic *vlapic; 70 vcpu_notify_t notify; 71 72 if (cpu < 0 || cpu >= vm_get_maxcpus(vm)) 73 return (EINVAL); 74 75 /* 76 * According to section "Maskable Hardware Interrupts" in Intel SDM 77 * vectors 16 through 255 can be delivered through the local APIC. 78 */ 79 if (vector < 16 || vector > 255) 80 return (EINVAL); 81 82 vlapic = vm_lapic(vm, cpu); 83 notify = vlapic_set_intr_ready(vlapic, vector, level); 84 vcpu_notify_event_type(vm, cpu, notify); 85 return (0); 86 } 87 88 int 89 lapic_set_local_intr(struct vm *vm, int cpu, int vector) 90 { 91 struct vlapic *vlapic; 92 cpuset_t dmask; 93 int error; 94 95 if (cpu < -1 || cpu >= vm_get_maxcpus(vm)) 96 return (EINVAL); 97 98 if (cpu == -1) 99 dmask = vm_active_cpus(vm); 100 else 101 CPU_SETOF(cpu, &dmask); 102 error = 0; 103 while ((cpu = CPU_FFS(&dmask)) != 0) { 104 cpu--; 105 CPU_CLR(cpu, &dmask); 106 vlapic = vm_lapic(vm, cpu); 107 error = vlapic_trigger_lvt(vlapic, vector); 108 if (error) 109 break; 110 } 111 112 return (error); 113 } 114 115 int 116 lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg) 117 { 118 int delmode, vec; 119 uint32_t dest; 120 bool phys; 121 122 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) { 123 /* Invalid MSI address */ 124 return (-1); 125 } 126 127 /* 128 * Extract the x86-specific fields from the MSI addr/msg params 129 * according to the Intel Arch spec, Vol3 Ch 10. 130 * 131 * The PCI specification does not support level triggered MSI/MSI-X so 132 * ignore trigger level in 'msg'. 133 * 134 * Certain kinds of interrupt broadcasts (physical or logical-clustered 135 * for destination 0xff) are prohibited when the redirection hint bit is 136 * set for a given message. Those edge cases are ignored for now. 137 */ 138 dest = (addr >> 12) & 0xff; 139 phys = (addr & MSI_X86_ADDR_LOG) == 0; 140 delmode = msg & APIC_DELMODE_MASK; 141 vec = msg & 0xff; 142 143 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec); 144 return (0); 145 } 146