1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2020 Oxide Computer Company 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/cpuset.h> 50 51 #include <x86/specialreg.h> 52 #include <x86/apicreg.h> 53 54 #include <machine/vmm.h> 55 #include "vmm_ktr.h" 56 #include "vmm_lapic.h" 57 #include "vlapic.h" 58 59 /* 60 * Some MSI message definitions 61 */ 62 #define MSI_X86_ADDR_MASK 0xfff00000 63 #define MSI_X86_ADDR_BASE 0xfee00000 64 #define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */ 65 #define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */ 66 67 int 68 lapic_set_intr(struct vm *vm, int cpu, int vector, bool level) 69 { 70 struct vlapic *vlapic; 71 vcpu_notify_t notify; 72 73 if (cpu < 0 || cpu >= vm_get_maxcpus(vm)) 74 return (EINVAL); 75 76 /* 77 * According to section "Maskable Hardware Interrupts" in Intel SDM 78 * vectors 16 through 255 can be delivered through the local APIC. 79 */ 80 if (vector < 16 || vector > 255) 81 return (EINVAL); 82 83 vlapic = vm_lapic(vm, cpu); 84 notify = vlapic_set_intr_ready(vlapic, vector, level); 85 vcpu_notify_event_type(vm, cpu, notify); 86 return (0); 87 } 88 89 int 90 lapic_set_local_intr(struct vm *vm, int cpu, int vector) 91 { 92 struct vlapic *vlapic; 93 cpuset_t dmask; 94 int error; 95 96 if (cpu < -1 || cpu >= vm_get_maxcpus(vm)) 97 return (EINVAL); 98 99 if (cpu == -1) 100 dmask = vm_active_cpus(vm); 101 else 102 CPU_SETOF(cpu, &dmask); 103 error = 0; 104 while ((cpu = CPU_FFS(&dmask)) != 0) { 105 cpu--; 106 CPU_CLR(cpu, &dmask); 107 vlapic = vm_lapic(vm, cpu); 108 error = vlapic_trigger_lvt(vlapic, vector); 109 if (error) 110 break; 111 } 112 113 return (error); 114 } 115 116 int 117 lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg) 118 { 119 int delmode, vec; 120 uint32_t dest; 121 bool phys; 122 123 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg); 124 125 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) { 126 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr); 127 return (-1); 128 } 129 130 /* 131 * Extract the x86-specific fields from the MSI addr/msg params 132 * according to the Intel Arch spec, Vol3 Ch 10. 133 * 134 * The PCI specification does not support level triggered MSI/MSI-X so 135 * ignore trigger level in 'msg'. 136 * 137 * Certain kinds of interrupt broadcasts (physical or logical-clustered 138 * for destination 0xff) are prohibited when the redirection hint bit is 139 * set for a given message. Those edge cases are ignored for now. 140 */ 141 dest = (addr >> 12) & 0xff; 142 phys = (addr & MSI_X86_ADDR_LOG) == 0; 143 delmode = msg & APIC_DELMODE_MASK; 144 vec = msg & 0xff; 145 146 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d", 147 phys ? "physical" : "logical", dest, vec); 148 149 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec); 150 return (0); 151 } 152